[ARM] mm: enable sparsemem on clps7500 and RiscPC

[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-clps7500 / include / mach / memory.h

diff --git a/arch/arm/mach-clps7500/include/mach/memory.h b/arch/arm/mach-clps7500/include/mach/memory.h
index 3326aa99d3eceda08e3ca78288e11ca110da6e82..87b32db470c812a10bd48563bb3c2cd71263cfa0 100644 (file)
--- a/arch/arm/mach-clps7500/include/mach/memory.h
+++ b/arch/arm/mach-clps7500/include/mach/memory.h
@@ -32,4 +32,12 @@
 #define FLUSH_BASE_PHYS                0x00000000
 #define FLUSH_BASE             0xdf000000
 
+/*
+ * Sparsemem support.  Each section is a maximum of 64MB.  The sections
+ * are offset by 128MB and can cover 128MB, so that gives us a maximum
+ * of 29 physmem bits.
+ */
+#define MAX_PHYSMEM_BITS       29
+#define SECTION_SIZE_BITS      26
+
 #endif