ARM: 7013/1: P2V: Remove ARM_PATCH_PHYS_VIRT_16BIT

[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / kernel / head.S

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 742b6108a00168b8ed8c391c6d8e8b1b9c438fc6..136abb610948461f00596edb4d658253b37e4faf 100644 (file)
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -488,13 +488,8 @@ __fixup_pv_table:
        add     r5, r5, r3      @ adjust table end address
        add     r7, r7, r3      @ adjust __pv_phys_offset address
        str     r8, [r7]        @ save computed PHYS_OFFSET to __pv_phys_offset
-#ifndef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
        mov     r6, r3, lsr #24 @ constant for add/sub instructions
        teq     r3, r6, lsl #24 @ must be 16MiB aligned
-#else
-       mov     r6, r3, lsr #16 @ constant for add/sub instructions
-       teq     r3, r6, lsl #16 @ must be 64kiB aligned
-#endif
 THUMB( it      ne              @ cross section branch )
        bne     __error
        str     r6, [r7, #4]    @ save to __pv_offset
@@ -510,20 +505,8 @@ ENDPROC(__fixup_pv_table)
        .text
 __fixup_a_pv_table:
 #ifdef CONFIG_THUMB2_KERNEL
-#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
-       lsls    r0, r6, #24
-       lsr     r6, #8
-       beq     1f
-       clz     r7, r0
-       lsr     r0, #24
-       lsl     r0, r7
-       bic     r0, 0x0080
-       lsrs    r7, #1
-       orrcs   r0, #0x0080
-       orr     r0, r0, r7, lsl #12
-#endif
-1:     lsls    r6, #24
-       beq     4f
+       lsls    r6, #24
+       beq     2f
        clz     r7, r6
        lsr     r6, #24
        lsl     r6, r7
@@ -532,43 +515,25 @@ __fixup_a_pv_table:
        orrcs   r6, #0x0080
        orr     r6, r6, r7, lsl #12
        orr     r6, #0x4000
-       b       4f
-2:     @ at this point the C flag is always clear
-       add     r7, r3
-#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
-       ldrh    ip, [r7]
-       tst     ip, 0x0400      @ the i bit tells us LS or MS byte
-       beq     3f
-       cmp     r0, #0          @ set C flag, and ...
-       biceq   ip, 0x0400      @ immediate zero value has a special encoding
-       streqh  ip, [r7]        @ that requires the i bit cleared
-#endif
-3:     ldrh    ip, [r7, #2]
+       b       2f
+1:     add     r7, r3
+       ldrh    ip, [r7, #2]
        and     ip, 0x8f00
-       orrcc   ip, r6  @ mask in offset bits 31-24
-       orrcs   ip, r0  @ mask in offset bits 23-16
+       orr     ip, r6  @ mask in offset bits 31-24
        strh    ip, [r7, #2]
-4:     cmp     r4, r5
+2:     cmp     r4, r5
        ldrcc   r7, [r4], #4    @ use branch for delay slot
-       bcc     2b
+       bcc     1b
        bx      lr
 #else
-#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
-       and     r0, r6, #255    @ offset bits 23-16
-       mov     r6, r6, lsr #8  @ offset bits 31-24
-#else
-       mov     r0, #0          @ just in case...
-#endif
-       b       3f
-2:     ldr     ip, [r7, r3]
+       b       2f
+1:     ldr     ip, [r7, r3]
        bic     ip, ip, #0x000000ff
-       tst     ip, #0x400      @ rotate shift tells us LS or MS byte
-       orrne   ip, ip, r6      @ mask in offset bits 31-24
-       orreq   ip, ip, r0      @ mask in offset bits 23-16
+       orr     ip, ip, r6      @ mask in offset bits 31-24
        str     ip, [r7, r3]
-3:     cmp     r4, r5
+2:     cmp     r4, r5
        ldrcc   r7, [r4], #4    @ use branch for delay slot
-       bcc     2b
+       bcc     1b
        mov     pc, lr
 #endif
 ENDPROC(__fixup_a_pv_table)