ARM: 7114/1: cache-l2x0: add resume entry for l2 in secure mode

[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / include / asm / outercache.h

diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h
index d8387437ec5aa8c49258d9ab9f3bbeca2b6bd189..53426c66352a1bde6f1b3fb510f404ea41ba3206 100644 (file)
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -34,6 +34,7 @@ struct outer_cache_fns {
        void (*sync)(void);
 #endif
        void (*set_debug)(unsigned long);
+       void (*resume)(void);
 };
 
 #ifdef CONFIG_OUTER_CACHE
@@ -74,6 +75,12 @@ static inline void outer_disable(void)
                outer_cache.disable();
 }
 
+static inline void outer_resume(void)
+{
+       if (outer_cache.resume)
+               outer_cache.resume();
+}
+
 #else
 
 static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)