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Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes...
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git]
/
drivers
/
pcmcia
/
cardbus.c
diff --git
a/drivers/pcmcia/cardbus.c
b/drivers/pcmcia/cardbus.c
index db77e1f3309a087a6c93c06d251284981df80311..a73b040ddbfb81102fffe2a6da4768155f7689e3 100644
(file)
--- a/
drivers/pcmcia/cardbus.c
+++ b/
drivers/pcmcia/cardbus.c
@@
-91,7
+91,7
@@
static u_int xlate_rom_addr(void __iomem *b, u_int addr)
static void cb_release_cis_mem(struct pcmcia_socket * s)
{
if (s->cb_cis_virt) {
static void cb_release_cis_mem(struct pcmcia_socket * s)
{
if (s->cb_cis_virt) {
-
cs_dbg(s, 1
, "cb_release_cis_mem()\n");
+
dev_dbg(&s->dev
, "cb_release_cis_mem()\n");
iounmap(s->cb_cis_virt);
s->cb_cis_virt = NULL;
s->cb_cis_res = NULL;
iounmap(s->cb_cis_virt);
s->cb_cis_virt = NULL;
s->cb_cis_res = NULL;
@@
-132,7
+132,7
@@
int read_cb_mem(struct pcmcia_socket * s, int space, u_int addr, u_int len, void
struct pci_dev *dev;
struct resource *res;
struct pci_dev *dev;
struct resource *res;
-
cs_dbg(s, 3
, "read_cb_mem(%d, %#x, %u)\n", space, addr, len);
+
dev_dbg(&s->dev
, "read_cb_mem(%d, %#x, %u)\n", space, addr, len);
dev = pci_get_slot(s->cb_dev->subordinate, 0);
if (!dev)
dev = pci_get_slot(s->cb_dev->subordinate, 0);
if (!dev)
@@
-184,26
+184,33
@@
fail:
=====================================================================*/
=====================================================================*/
-/*
- * Since there is only one interrupt available to CardBus
- * devices, all devices downstream of this device must
- * be using this IRQ.
- */
-static void cardbus_assign_irqs(struct pci_bus *bus, int irq)
+static void cardbus_config_irq_and_cls(struct pci_bus *bus, int irq)
{
struct pci_dev *dev;
list_for_each_entry(dev, &bus->devices, bus_list) {
u8 irq_pin;
{
struct pci_dev *dev;
list_for_each_entry(dev, &bus->devices, bus_list) {
u8 irq_pin;
+ /*
+ * Since there is only one interrupt available to
+ * CardBus devices, all devices downstream of this
+ * device must be using this IRQ.
+ */
pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq_pin);
if (irq_pin) {
dev->irq = irq;
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
}
pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq_pin);
if (irq_pin) {
dev->irq = irq;
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
}
+ /*
+ * Some controllers transfer very slowly with 0 CLS.
+ * Configure it. This may fail as CLS configuration
+ * is mandatory only for MWI.
+ */
+ pci_set_cacheline_size(dev);
+
if (dev->subordinate)
if (dev->subordinate)
- cardbus_
assign_irq
s(dev->subordinate, irq);
+ cardbus_
config_irq_and_cl
s(dev->subordinate, irq);
}
}
}
}
@@
-228,7
+235,7
@@
int __ref cb_alloc(struct pcmcia_socket * s)
*/
pci_bus_size_bridges(bus);
pci_bus_assign_resources(bus);
*/
pci_bus_size_bridges(bus);
pci_bus_assign_resources(bus);
- cardbus_
assign_irq
s(bus, s->pci_irq);
+ cardbus_
config_irq_and_cl
s(bus, s->pci_irq);
/* socket specific tune function */
if (s->tune_bridge)
/* socket specific tune function */
if (s->tune_bridge)