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xtensa: fix kernel register spilling
[GitHub/mt8127/android_kernel_alcatel_ttab.git]
/
arch
/
xtensa
/
include
/
asm
/
traps.h
diff --git
a/arch/xtensa/include/asm/traps.h
b/arch/xtensa/include/asm/traps.h
index f2faa58f9a43f3a591b41f9bf7f62b72bc8e6218..03d02df47b9a99dd7a62e196e1f87dd426d811c2 100644
(file)
--- a/
arch/xtensa/include/asm/traps.h
+++ b/
arch/xtensa/include/asm/traps.h
@@
-24,30
+24,39
@@
static inline void spill_registers(void)
{
#if XCHAL_NUM_AREGS > 16
__asm__ __volatile__ (
{
#if XCHAL_NUM_AREGS > 16
__asm__ __volatile__ (
- " call
12
1f\n"
+ " call
8
1f\n"
" _j 2f\n"
" retw\n"
" .align 4\n"
"1:\n"
" _j 2f\n"
" retw\n"
" .align 4\n"
"1:\n"
+#if XCHAL_NUM_AREGS == 32
+ " _entry a1, 32\n"
+ " addi a8, a0, 3\n"
+ " _entry a1, 16\n"
+ " mov a12, a12\n"
+ " retw\n"
+#else
" _entry a1, 48\n"
" _entry a1, 48\n"
- " addi a12, a0, 3\n"
-#if XCHAL_NUM_AREGS > 32
- " .rept (" __stringify(XCHAL_NUM_AREGS) " - 32) / 12\n"
+ " call12 1f\n"
+ " retw\n"
+ " .align 4\n"
+ "1:\n"
+ " .rept (" __stringify(XCHAL_NUM_AREGS) " - 16) / 12\n"
" _entry a1, 48\n"
" mov a12, a0\n"
" .endr\n"
" _entry a1, 48\n"
" mov a12, a0\n"
" .endr\n"
-#endif
- " _entry a1, 48\n"
+ " _entry a1, 16\n"
#if XCHAL_NUM_AREGS % 12 == 0
#if XCHAL_NUM_AREGS % 12 == 0
- " mov a8, a8\n"
-#elif XCHAL_NUM_AREGS % 12 == 4
" mov a12, a12\n"
" mov a12, a12\n"
-#elif XCHAL_NUM_AREGS % 12 ==
8
+#elif XCHAL_NUM_AREGS % 12 ==
4
" mov a4, a4\n"
" mov a4, a4\n"
+#elif XCHAL_NUM_AREGS % 12 == 8
+ " mov a8, a8\n"
#endif
" retw\n"
#endif
" retw\n"
+#endif
"2:\n"
"2:\n"
- : : : "a
12", "a13
", "memory");
+ : : : "a
8", "a9
", "memory");
#else
__asm__ __volatile__ (
" mov a12, a12\n"
#else
__asm__ __volatile__ (
" mov a12, a12\n"