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MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt)
[GitHub/mt8127/android_kernel_alcatel_ttab.git]
/
arch
/
mips
/
include
/
asm
/
cpu-features.h
diff --git
a/arch/mips/include/asm/cpu-features.h
b/arch/mips/include/asm/cpu-features.h
index ca400f7c3f594944d31a7b1341b6aa04d7e4c757..089125a6ae6a019bcfb051b957a9b4547aea4c0c 100644
(file)
--- a/
arch/mips/include/asm/cpu-features.h
+++ b/
arch/mips/include/asm/cpu-features.h
@@
-95,8
+95,8
@@
#ifndef cpu_has_smartmips
#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
#endif
#ifndef cpu_has_smartmips
#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
#endif
-#ifndef
kernel_uses_smartmip
s_rixi
-#define
kernel_uses_smartmips_rixi 0
+#ifndef
cpu_ha
s_rixi
+#define
cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
#endif
#ifndef cpu_has_vtag_icache
#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
#endif
#ifndef cpu_has_vtag_icache
#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
@@
-252,4
+252,8
@@
#define cpu_hwrena_impl_bits 0
#endif
#define cpu_hwrena_impl_bits 0
#endif
+#ifndef cpu_has_perf_cntr_intr_bit
+#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
+#endif
+
#endif /* __ASM_CPU_FEATURES_H */
#endif /* __ASM_CPU_FEATURES_H */