/* * arch/arm64/boot/dts/amlogic/mesonsm1.dtsi * * Copyright (C) 2017 Amlogic, Inc. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * */ #include #include #include #include #include #include #include #include #include #include #include #include "mesong12a-bifrost.dtsi" / { cpus:cpus { #address-cells = <2>; #size-cells = <0>; cpu-map { cluster0:cluster0 { core0 { cpu = <&CPU0>; }; core1 { cpu = <&CPU1>; }; core2 { cpu = <&CPU2>; }; core3 { cpu = <&CPU3>; }; }; }; CPU0:cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; //cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&clkc CLKID_CPU_CLK>, <&clkc CLKID_CPU_FCLK_P>, <&clkc CLKID_SYS_PLL>; clock-names = "core_clk", "low_freq_clk_parent", "high_freq_clk_parent"; operating-points-v2 = <&cpu_opp_table0>; cpu-supply = <&vddcpu0>; voltage-tolerance = <0>; clock-latency = <50000>; }; CPU1:cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; //cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&clkc CLKID_CPU_CLK>, <&clkc CLKID_CPU_FCLK_P>, <&clkc CLKID_SYS_PLL>; clock-names = "core_clk", "low_freq_clk_parent", "high_freq_clk_parent"; operating-points-v2 = <&cpu_opp_table0>; cpu-supply = <&vddcpu0>; voltage-tolerance = <0>; clock-latency = <50000>; }; CPU2:cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; //cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&clkc CLKID_CPU_CLK>, <&clkc CLKID_CPU_FCLK_P>, <&clkc CLKID_SYS_PLL>; clock-names = "core_clk", "low_freq_clk_parent", "high_freq_clk_parent"; operating-points-v2 = <&cpu_opp_table0>; cpu-supply = <&vddcpu0>; voltage-tolerance = <0>; clock-latency = <50000>; }; CPU3:cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&clkc CLKID_CPU_CLK>, <&clkc CLKID_CPU_FCLK_P>, <&clkc CLKID_SYS_PLL>, <&clkc CLKID_DSU_CLK>, <&clkc CLKID_DSU_PRE_CLK>; clock-names = "core_clk", "low_freq_clk_parent", "high_freq_clk_parent", "dsu_clk", "dsu_pre_parent"; operating-points-v2 = <&cpu_opp_table0>; cpu-supply = <&vddcpu0>; voltage-tolerance = <0>; clock-latency = <50000>; }; idle-states { entry-method = "arm,psci-0.2"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x0010000>; local-timer-stop; entry-latency-us = <4000>; exit-latency-us = <5000>; min-residency-us = <10000>; }; }; }; timer { compatible = "arm,armv8-timer"; interrupts = , , , ; }; timer_bc { compatible = "arm, meson-bc-timer"; reg= <0x0 0xffd0f190 0x0 0x4 0x0 0xffd0f194 0x0 0x4>; timer_name = "Meson TimerF"; clockevent-rating=<300>; clockevent-shift=<20>; clockevent-features=<0x23>; interrupts = <0 60 1>; bit_enable=<16>; bit_mode=<12>; bit_resolution=<0>; }; arm_pmu { compatible = "arm,armv8-pmuv3"; /* clusterb-enabled; */ interrupts = ; reg = <0x0 0xff634680 0x0 0x4>; cpumasks = <0xf>; /* default 10ms */ relax-timer-ns = <10000000>; /* default 10000us */ max-wait-cnt = <10000>; }; gic: interrupt-controller@2c001000 { compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; reg = <0x0 0xffc01000 0 0x1000>, <0x0 0xffc02000 0 0x0100>; interrupts = ; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; aml_pm { compatible = "amlogic, pm"; status = "okay"; device_name = "aml_pm"; debug_reg = <0xff8000a8>; exit_reg = <0xff80023c>; }; secmon { compatible = "amlogic, secmon"; memory-region = <&secmon_reserved>; in_base_func = <0x82000020>; out_base_func = <0x82000021>; reserve_mem_size = <0x00300000>; }; securitykey { compatible = "aml, securitykey"; storage_query = <0x82000060>; storage_read = <0x82000061>; storage_write = <0x82000062>; storage_tell = <0x82000063>; storage_verify = <0x82000064>; storage_status = <0x82000065>; storage_list = <0x82000067>; storage_remove = <0x82000068>; storage_in_func = <0x82000023>; storage_out_func = <0x82000024>; storage_block_func = <0x82000025>; storage_size_func = <0x82000027>; storage_set_enctype = <0x8200006A>; storage_get_enctype = <0x8200006B>; storage_version = <0x8200006C>; }; mailbox: mhu@c883c400 { compatible = "amlogic, meson_mhu"; reg = <0x0 0xff63c400 0x0 0x4c>, /* MHU registers */ <0x0 0xfffe7000 0x0 0x800>; /* Payload area */ interrupts = <0 209 1>, /* low priority interrupt */ <0 210 1>; /* b interrupt */ #mbox-cells = <1>; mbox-names = "cpu_to_scp_low", "cpu_to_scp_high"; mboxes = <&mailbox 0 &mailbox 1>; }; cpu_iomap { compatible = "amlogic, iomap"; #address-cells=<2>; #size-cells=<2>; ranges; io_cbus_base { reg = <0x0 0xffd00000 0x0 0x26fff>; }; io_apb_base { reg = <0x0 0xffe01000 0x0 0x7f000>; }; io_aobus_base { reg = <0x0 0xff800000 0x0 0xb000>; }; io_vapb_base { reg = <0x0 0xff900000 0x0 0x50000>; }; io_hiu_base { reg = <0x0 0xff63c000 0x0 0x2000>; }; }; xtal: xtal-clk { compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "xtal"; #clock-cells = <0>; }; rtc{ compatible = "amlogic, aml_vrtc"; alarm_reg_addr = <0xff8000a8>; timer_e_addr = <0xffd0f188>; init_date = "2015/01/01"; status = "okay"; }; cpu_info { compatible = "amlogic, cpuinfo"; status = "okay"; cpuinfo_cmd = <0x82000044>; }; aml_reboot{ compatible = "aml, reboot"; sys_reset = <0x84000009>; sys_poweroff = <0x84000008>; reboot_reason_addr = <0xff80023c>; }; vpu: vpu { compatible = "amlogic, vpu-sm1"; dev_name = "vpu"; status = "okay"; clocks = <&clkc CLKID_VAPB_MUX>, <&clkc CLKID_VPU_INTR>, <&clkc CLKID_VPU_P0_COMP>, <&clkc CLKID_VPU_P1_COMP>, <&clkc CLKID_VPU_MUX>; clock-names = "vapb_clk", "vpu_intr_gate", "vpu_clk0", "vpu_clk1", "vpu_clk"; clk_level = <7>; /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */ /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */ }; meson_uvm{ compatible = "amlogic, meson_uvm"; status = "okay"; }; meson_videotunnel{ compatible = "amlogic, meson_videotunnel"; status = "okay"; }; ethmac: ethernet@ff3f0000 { compatible = "amlogic, g12a-eth-dwmac","snps,dwmac"; reg = <0x0 0xff3f0000 0x0 0x10000 0x0 0xff634540 0x0 0x8 0x0 0xff64c000 0x0 0xa0 0x0 0xffd01008 0x0 0x4>; reg-names = "eth_base", "eth_cfg", "eth_pll", "eth_reset"; interrupts = <0 8 1>; interrupt-names = "macirq"; status = "disabled"; clocks = <&clkc CLKID_ETH_CORE>; clock-names = "ethclk81"; pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>; analog_val = <0x20200000 0x0000c000 0x00000023>; }; pinctrl_aobus: pinctrl@ff800014{ compatible = "amlogic,meson-g12a-aobus-pinctrl"; #address-cells = <2>; #size-cells = <2>; ranges; gpio_ao: ao-bank@ff800014{ reg = <0x0 0xff800014 0x0 0x8>, <0x0 0xff800024 0x0 0x14>, <0x0 0xff80001c 0x0 0x8>; reg-names = "mux","gpio", "drive-strength"; gpio-controller; #gpio-cells = <2>; }; }; pinctrl_periphs: pinctrl@ff634480{ compatible = "amlogic,meson-g12a-periphs-pinctrl"; #address-cells = <2>; #size-cells = <2>; ranges; gpio: banks@ff6346c0{ reg = <0x0 0xff6346c0 0x0 0x40>, <0x0 0xff6344e8 0x0 0x18>, <0x0 0xff634520 0x0 0x18>, <0x0 0xff634440 0x0 0x4c>, <0x0 0xff634740 0x0 0x1c>; reg-names = "mux", "pull", "pull-enable", "gpio", "drive-strength"; gpio-controller; #gpio-cells = <2>; }; }; audio_data: audio_data { compatible = "amlogic, audio_data"; query_licence_cmd = <0x82000050>; status = "disabled"; }; dwc3: dwc3@ff500000 { compatible = "synopsys, dwc3"; status = "disable"; reg = <0x0 0xff500000 0x0 0x100000>; interrupts = <0 30 4>; usb-phy = <&usb2_phy_v2>, <&usb3_phy_v2>; cpu-type = "gxl"; clock-src = "usb3.0"; clocks = <&clkc CLKID_USB_GENERAL>; clock-names = "dwc_general"; }; usb2_phy_v2: usb2phy@ffe09000 { compatible = "amlogic, amlogic-new-usb2-v2"; status = "disable"; reg = <0x0 0xffe09000 0x0 0x80 0x0 0xffd01008 0x0 0x100 0x0 0xff636000 0x0 0x2000 0x0 0xff63a000 0x0 0x2000>; pll-setting-1 = <0x09400414>; pll-setting-2 = <0x927E0000>; pll-setting-3 = <0xac5f69e5>; pll-setting-4 = <0xfe18>; pll-setting-5 = <0x8000fff>; pll-setting-6 = <0x78000>; pll-setting-7 = <0xe0004>; pll-setting-8 = <0xe000c>; version = <2>; pwr-ctl = <1>; u2-ctrl-sleep-shift = <17>; u2-hhi-mem-pd-shift = <30>; u2-hhi-mem-pd-mask = <0x3>; u2-ctrl-iso-shift = <17>; }; usb3_phy_v2: usb3phy@ffe09080 { compatible = "amlogic, amlogic-new-usb3-v2"; status = "disable"; reg = <0x0 0xffe09080 0x0 0x20 0x0 0xffd01008 0x0 0x100>; phy-reg = <0xff646000>; phy-reg-size = <0x2000>; usb2-phy-reg = <0xffe09000>; usb2-phy-reg-size = <0x80>; interrupts = <0 16 4>; clocks = <&clkc CLKID_PCIE_PLL>; clock-names = "pcie_refpll"; pwr-ctl = <1>; u3-ctrl-sleep-shift = <18>; u3-hhi-mem-pd-shift = <26>; u3-hhi-mem-pd-mask = <0xf>; u3-ctrl-iso-shift = <18>; }; dwc2_a: dwc2_a@ff400000 { compatible = "amlogic, dwc2"; status = "disable"; device_name = "dwc2_a"; reg = <0x0 0xff400000 0x0 0x40000>; interrupts = <0 31 4>; pl-periph-id = <0>; /** lm name */ clock-src = "usb0"; /** clock src */ port-id = <0>; /** ref to mach/usb.h */ port-type = <2>; /** 0: otg, 1: host, 2: slave */ port-speed = <0>; /** 0: default, high, 1: full */ port-config = <0>; /** 0: default */ /*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/ port-dma = <0>; port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ usb-fifo = <728>; cpu-type = "v2"; phy-reg = <0xffe09000>; phy-reg-size = <0xa0>; /** phy-interface: 0x0: amlogic phy, 0x1: synopsys phy **/ phy-interface = <0x2>; clocks = <&clkc CLKID_USB_GENERAL &clkc CLKID_USB1_TO_DDR>; clock-names = "usb_general", "usb1"; }; wdt: watchdog@0xffd0f0d0 { compatible = "amlogic, meson-wdt"; status = "okay"; default_timeout=<10>; reset_watchdog_method=<1>; /* 0:sysfs,1:kernel */ reset_watchdog_time=<2>; shutdown_timeout=<10>; firmware_timeout=<6>; suspend_timeout=<6>; reg = <0x0 0xffd0f0d0 0x0 0x10>; clock-names = "xtal"; clocks = <&xtal>; }; ram-dump { compatible = "amlogic, ram_dump"; status = "okay"; reg = <0x0 0xFF6345E0 0x0 4>; reg-names = "PREG_STICKY_REG8"; }; jtag { compatible = "amlogic, jtag"; status = "okay"; select = "disable"; /* disable/apao/apee */ pinctrl-names="jtag_apao_pins", "jtag_apee_pins"; pinctrl-0=<&jtag_apao_pins>; pinctrl-1=<&jtag_apee_pins>; }; saradc:saradc { compatible = "amlogic,meson-g12a-saradc"; status = "okay"; #io-channel-cells = <1>; clocks = <&xtal>, <&clkc CLKID_SARADC_GATE>; clock-names = "xtal", "saradc_clk"; interrupts = ; reg = <0x0 0xff809000 0x0 0x48>; }; power_ctrl: power_ctrl@ff8000e8 { compatible = "amlogic, sm1-powerctrl"; reg = <0x0 0xff8000e8 0x0 0x10>, <0x0 0xff63c100 0x0 0x10>; }; bl40: bl40 { compatible = "amlogic, bl40-bootup"; status = "okay"; }; soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; cbus: cbus@ffd00000 { compatible = "simple-bus"; reg = <0x0 0xffd00000 0x0 0x26000>; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x26000>; gpio_intc: interrupt-controller@f080 { compatible = "amlogic,meson-gpio-intc", "amlogic,meson-sm1-gpio-intc"; reg = <0x0 0xf080 0x0 0x10>; interrupt-controller; #interrupt-cells = <2>; amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; status = "okay"; }; meson_clk_msr { compatible = "amlogic, sm1-measure"; reg = <0x0 0x18004 0x0 0x4 0x0 0x1800c 0x0 0x4>; ringctrl = <0xff6345fc>; }; pwm_ab: pwm@1b000 { compatible = "amlogic,g12a-ee-pwm"; reg = <0x0 0x1b000 0x0 0x20>; #pwm-cells = <3>; clocks = <&xtal>, <&xtal>, <&xtal>, <&xtal>; clock-names = "clkin0", "clkin1", "clkin2", "clkin3"; /* default xtal 24m clkin0-clkin2 and * clkin1-clkin3 should be set the same */ status = "disabled"; }; pwm_cd: pwm@1a000 { compatible = "amlogic,g12a-ee-pwm"; reg = <0x0 0x1a000 0x0 0x20>; #pwm-cells = <3>; clocks = <&xtal>, <&xtal>, <&xtal>, <&xtal>; clock-names = "clkin0", "clkin1", "clkin2", "clkin3"; status = "disabled"; }; pwm_ef: pwm@19000 { compatible = "amlogic,g12a-ee-pwm"; reg = <0x0 0x19000 0x0 0x20>; #pwm-cells = <3>; clocks = <&xtal>, <&xtal>, <&xtal>, <&xtal>; clock-names = "clkin0", "clkin1", "clkin2", "clkin3"; status = "disabled"; }; i2c0: i2c@1f000 { compatible = "amlogic,meson-g12a-i2c"; status = "disabled"; reg = <0x0 0x1f000 0x0 0x20>; interrupts = , ; #address-cells = <1>; #size-cells = <0>; clocks = <&clkc CLKID_I2C>; clock-names = "clk_i2c"; }; i2c1: i2c@1e000 { compatible = "amlogic,meson-g12a-i2c"; status = "disabled"; reg = <0x0 0x1e000 0x0 0x20>; interrupts = , ; #address-cells = <1>; #size-cells = <0>; clocks = <&clkc CLKID_I2C>; clock-names = "clk_i2c"; }; i2c2: i2c@1d000 { compatible = "amlogic,meson-g12a-i2c"; status = "disabled"; reg = <0x0 0x1d000 0x0 0x20>; interrupts = , ; #address-cells = <1>; #size-cells = <0>; clocks = <&clkc CLKID_I2C>; clock-names = "clk_i2c"; }; i2c3: i2c@1c000 { compatible = "amlogic,meson-g12a-i2c"; status = "disabled"; reg = <0x0 0x1c000 0x0 0x20>; interrupts = , ; #address-cells = <1>; #size-cells = <0>; clocks = <&clkc CLKID_I2C>; clock-names = "clk_i2c"; }; spicc0: spi@13000 { compatible = "amlogic,meson-g12a-spicc"; reg = <0x0 0x13000 0x0 0x44>; interrupts = ; clocks = <&clkc CLKID_SPICC0>, <&clkc CLKID_SPICC0_COMP>; clock-names = "core", "comp"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spicc1: spi@15000 { compatible = "amlogic,meson-g12a-spicc"; reg = <0x0 0x15000 0x0 0x44>; interrupts = ; clocks = <&clkc CLKID_SPICC1>, <&clkc CLKID_SPICC1_COMP>; clock-names = "core", "comp"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; /* end of cbus */ aobus: aobus@ff800000 { compatible = "simple-bus"; reg = <0x0 0xff800000 0x0 0xb000>; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xff800000 0x0 0xb000>; cpu_version { reg=<0x0 0x220 0x0 0x4>; }; aoclkc: clock-controller@0 { compatible = "amlogic,sm1-aoclkc"; #clock-cells = <1>; reg = <0x0 0x0 0x0 0x3dc>; }; pwm_AO_ab: pwm@7000 { compatible = "amlogic,g12a-ao-pwm"; reg = <0x0 0x7000 0x0 0x20>; #pwm-cells = <3>; clocks = <&xtal>, <&xtal>, <&xtal>, <&xtal>; clock-names = "clkin0", "clkin1", "clkin2", "clkin3"; status = "disabled"; }; pwm_AO_cd: pwm@2000 { compatible = "amlogic,g12a-ao-pwm"; reg = <0x0 0x2000 0x0 0x20>; #pwm-cells = <3>; clocks = <&xtal>, <&xtal>, <&xtal>, <&xtal>; clock-names = "clkin0", "clkin1", "clkin2", "clkin3"; status = "disabled"; }; i2c_AO: i2c@5000 { compatible = "amlogic,meson-g12a-i2c"; status = "disabled"; reg = <0x0 0x05000 0x0 0x20>; interrupts = , ; #address-cells = <1>; #size-cells = <0>; clocks = <&clkc CLKID_I2C>; clock-names = "clk_i2c"; }; i2c_AO_slave:i2c_slave@6000 { compatible = "amlogic, meson-i2c-slave"; status = "disabled"; reg = <0x0 0x6000 0x0 0x20>; interrupts = <0 194 1>; pinctrl-names="default"; pinctrl-0=<&ao_i2c_slave_pins>; }; uart_AO: serial@3000 { compatible = "amlogic, meson-uart"; reg = <0x0 0x3000 0x0 0x18>; interrupts = <0 193 1>; status = "okay"; clocks = <&xtal>; clock-names = "clk_uart"; xtal_tick_en = <2>; fifosize = < 64 >; pinctrl-names = "default"; /*pinctrl-0 = <&ao_uart_pins>;*/ support-sysrq = <1>; /* 0 not support*/ }; uart_AO_B: serial@4000 { compatible = "amlogic, meson-uart"; reg = <0x0 0x4000 0x0 0x18>; interrupts = <0 197 1>; status = "disabled"; clocks = <&xtal>; clock-names = "clk_uart"; fifosize = < 64 >; pinctrl-names = "default"; pinctrl-0 = <&ao_b_uart_pins>; }; };/* end of aobus */ periphs: periphs@ff634400 { compatible = "simple-bus"; reg = <0x0 0xff634400 0x0 0x400>; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xff634400 0x0 0x400>; };/* end of periphs */ hiubus: hiubus@ff63c000 { compatible = "simple-bus"; reg = <0x0 0xff63c000 0x0 0x2000>; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x2000>; clkc: clock-controller@0 { compatible = "amlogic,sm1-clkc-1"; #clock-cells = <1>; reg = <0x0 0x0 0x0 0x3dc>; }; clkc_b: clock-controller@1 { compatible = "amlogic,sm1-clkc-2"; #clock-cells = <1>; reg = <0x0 0x0 0x0 0x3dc>; clocks = <&clkc CLKID_FCLK_DIV2>; clock-names = "clkin0"; }; };/* end of hiubus*/ ion_dev { compatible = "amlogic, ion_dev"; memory-region = <&ion_cma_reserved &ion_fb_reserved>; };/* end of ion_dev*/ audiobus: audiobus@0xFF660000 { compatible = "amlogic, audio-controller", "simple-bus"; reg = <0x0 0xFF660000 0x0 0x3000>; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xFF660000 0x0 0x3000>; clkaudio: audio_clocks { compatible = "amlogic, sm1-audio-clocks"; #clock-cells = <1>; reg = <0x0 0x0 0x0 0xb0>; }; ddr_manager { compatible = "amlogic, sm1-audio-ddr-manager"; interrupts = < GIC_SPI 148 IRQ_TYPE_EDGE_RISING GIC_SPI 149 IRQ_TYPE_EDGE_RISING GIC_SPI 150 IRQ_TYPE_EDGE_RISING GIC_SPI 49 IRQ_TYPE_EDGE_RISING GIC_SPI 152 IRQ_TYPE_EDGE_RISING GIC_SPI 153 IRQ_TYPE_EDGE_RISING GIC_SPI 154 IRQ_TYPE_EDGE_RISING GIC_SPI 50 IRQ_TYPE_EDGE_RISING >; interrupt-names = "toddr_a", "toddr_b", "toddr_c", "toddr_d", "frddr_a", "frddr_b", "frddr_c", "frddr_d"; }; };/* end of audiobus*/ /* eARC */ audio_earc: bus@ff663000 { compatible = "simple-bus"; reg = <0x0 0xff663000 0x0 0x1000>; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xff663000 0x0 0x1000>; earc: earc@0 { compatible = "amlogic, sm1-snd-earc"; #sound-dai-cells = <0>; status = "disabled"; reg = <0x0 0x800 0x0 0x400>, <0x0 0xc00 0x0 0x200>, <0x0 0xe00 0x0 0x200>; reg-names = "rx_cmdc", "rx_dmac", "rx_top"; clocks = < &clkaudio CLKID_EARCRX_CMDC &clkaudio CLKID_EARCRX_DMAC &clkc CLKID_FCLK_DIV4 &clkc CLKID_FCLK_DIV4 &clkaudio CLKID_EARCTX_CMDC &clkaudio CLKID_EARCTX_DMAC &clkc CLKID_FCLK_DIV4 &clkc CLKID_MPLL1 >; clock-names = "rx_cmdc", "rx_dmac", "rx_cmdc_srcpll", "rx_dmac_srcpll"; interrupts = < GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "earc_rx"; }; }; /* Sound iomap */ aml_snd_iomap { compatible = "amlogic, snd-iomap"; status = "okay"; #address-cells=<2>; #size-cells=<2>; ranges; pdm_bus { reg = <0x0 0xFF661000 0x0 0x400>; }; audiobus_base { reg = <0x0 0xFF660000 0x0 0x1000>; }; audiolocker_base { reg = <0x0 0xFF661400 0x0 0x400>; }; eqdrc_base { reg = <0x0 0xFF662000 0x0 0x1000>; }; reset_base { reg = <0x0 0xFFD01000 0x0 0x1000>; }; vad_base { reg = <0x0 0xFF661800 0x0 0x400>; }; }; }; /* end of soc*/ remote:rc@0xff808040 { compatible = "amlogic, aml_remote"; dev_name = "meson-remote"; reg = <0x0 0xff808040 0x00 0x44>, /*Multi-format IR controller*/ <0x0 0xff808000 0x00 0x20>; /*Legacy IR controller*/ status = "disabled"; protocol = ; led_blink = <1>; led_blink_frq = <100>; interrupts = <0 196 1>; pinctrl-names = "default"; pinctrl-0 = <&remote_pins>; map = <&custom_maps>; max_frame_time = <200>; /*set software decoder max frame time*/ }; custom_maps:custom_maps { mapnum = <3>; map0 = <&map_0>; map1 = <&map_1>; map2 = <&map_2>; map_0: map_0{ mapname = "amlogic-remote-1"; customcode = <0xfb04>; release_delay = <80>; size = <50>; /*keymap size*/ keymap = ; }; map_1: map_1{ mapname = "amlogic-remote-2"; customcode = <0xfe01>; release_delay = <80>; size = <53>; keymap = ; }; map_2: map_2{ mapname = "amlogic-remote-3"; customcode = <0xbd02>; release_delay = <80>; size = <17>; keymap = ; }; }; uart_A: serial@ffd24000 { compatible = "amlogic, meson-uart"; reg = <0x0 0xffd24000 0x0 0x18>; interrupts = <0 26 1>; status = "disabled"; clocks = <&xtal &clkc CLKID_UART0>; clock-names = "clk_uart", "clk_gate"; fifosize = < 128 >; pinctrl-names = "default"; pinctrl-0 = <&a_uart_pins>; }; uart_B: serial@ffd23000 { compatible = "amlogic, meson-uart"; reg = <0x0 0xffd23000 0x0 0x18>; interrupts = <0 75 1>; status = "disabled"; clocks = <&xtal &clkc CLKID_UART1>; clock-names = "clk_uart", "clk_gate"; fifosize = < 64 >; pinctrl-names = "default"; pinctrl-0 = <&b_uart_pins>; }; uart_C: serial@ffd22000 { compatible = "amlogic, meson-uart"; reg = <0x0 0xffd22000 0x0 0x18>; interrupts = <0 93 1>; status = "disabled"; clocks = <&xtal &clkc CLKID_UART1>; clock-names = "clk_uart", "clk_gate"; fifosize = < 64 >; pinctrl-names = "default"; pinctrl-0 = <&c_uart_pins>; }; pcie_A: pcieA@fc000000 { compatible = "amlogic, amlogic-pcie-v2", "snps,dw-pcie"; reg = <0x0 0xfc000000 0x0 0x400000 0x0 0xff648000 0x0 0x2000 0x0 0xfc400000 0x0 0x200000 0x0 0xff646000 0x0 0x2000 0x0 0xffd01080 0x0 0x10>; reg-names = "elbi", "cfg", "config", "phy", "reset"; interrupts = <0 221 0>; #interrupt-cells = <1>; bus-range = <0x0 0xff>; #address-cells = <3>; #size-cells = <2>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_EDGE_RISING>; device_type = "pci"; ranges = <0x81000000 0 0 0 0xfc600000 0x0 0x100000 /* downstream I/O */ 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; /* non-prefetchable memory */ num-lanes = <1>; pcie-num = <1>; clocks = <&clkc CLKID_PCIE_PLL &clkc CLKID_PCIE_COMB &clkc CLKID_PCIE_PHY>; clock-names = "pcie_refpll", "pcie", "pcie_phy"; /*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/ gpio-type = <2>; pcie-apb-rst-bit = <15>; pcie-phy-rst-bit = <14>; pcie-ctrl-a-rst-bit = <12>; pwr-ctl = <1>; pcie-ctrl-sleep-shift = <18>; pcie-hhi-mem-pd-shift = <26>; pcie-hhi-mem-pd-mask = <0xf>; pcie-ctrl-iso-shift = <18>; status = "disabled"; }; amhdmitx: amhdmitx{ compatible = "amlogic, amhdmitx"; dev_name = "amhdmitx"; status = "okay"; vend-data = <&vend_data>; pinctrl-names="default", "hdmitx_i2c"; pinctrl-0=<&hdmitx_hpd &hdmitx_ddc>; pinctrl-1=<&hdmitx_hpd_gpio &i2c3_master_pins1>; clocks = <&clkc CLKID_VCLK2_ENCI &clkc CLKID_VCLK2_VENCI0 &clkc CLKID_VCLK2_VENCI1 &clkc CLKID_VAPB_MUX &clkc CLKID_VPU_MUX>; clock-names = "venci_top_gate", "venci_0_gate", "venci_1_gate", "hdmi_vapb_clk", "hdmi_vpu_clk"; /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ interrupts = <0 57 1>; interrupt-names = "hdmitx_hpd"; /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD * 10:G12A 11:G12B 12:SM1 */ ic_type = <12>; cedst_en = <1>; vend_data: vend_data{ /* Should modified by Customer */ vendor_name = "Google"; /* Max Chars: 8 */ product_desc = "Chromecast"; /* Max Chars: 16 */ /* standards.ieee.org/develop/regauth/oui/oui.txt */ vendor_id = <0x001a11>; }; }; galcore { compatible = "amlogic, galcore"; dev_name = "galcore"; status = "okay"; clocks = <&clkc CLKID_VNANOQ_AXI_CLK_COMP>, <&clkc CLKID_VNANOQ_CORE_CLK_COMP>; clock-names = "cts_vipnanoq_axi_clk_composite", "cts_vipnanoq_core_clk_composite"; interrupts = <0 186 4>; interrupt-names = "galcore"; reg = <0x0 0xff100000 0x0 0x800 0x0 0xff000000 0x0 0x400000 0x0 0xff63c118 0x0 0x0 0x0 0xff63c11c 0x0 0x0 0x0 0xffd01088 0x0 0x0 0x0 0xff63c1c8 0x0 0x0 >; reg-names = "NN_REG","NN_SRAM","NN_MEM0", "NN_MEM1","NN_RESET","NN_CLK"; nn_power_version = <3>; nn_efuse = <0xff63003c 0x20>; }; aocec: aocec { compatible = "amlogic, aocec-sm1"; device_name = "aocec"; status = "okay"; vendor_name = "Google"; /* Max Chars: 8 */ /* Refer to the following URL at: * http://standards.ieee.org/develop/regauth/oui/oui.txt */ vendor_id = <0x001a11>; product_desc = "Chromecast"; /* Max Chars: 16 */ cec_osd_string = "Chromecast"; /* Max Chars: 14 */ cec_version = <5>;/*5:1.4;6:2.0*/ port_num = <1>; output = <1>; ee_cec; arc_port_mask = <0x2>; interrupts = <0 203 1 0 199 1>; /*0:snps 1:ts*/ interrupt-names = "hdmi_aocecb","hdmi_aocec"; pinctrl-names = "default","hdmitx_aocecb","cec_pin_sleep"; pinctrl-0=<&eecec_a>; pinctrl-1=<&eecec_b>; pinctrl-2=<&eecec_b>; reg = <0x0 0xFF80023c 0x0 0x4 0x0 0xFF800000 0x0 0x400 0x0 0xFF634400 0x0 0x70>; reg-names = "ao_exit","ao","periphs"; }; /*if you want to use vdin just modify status to "ok"*/ vdin0: vdin0 { compatible = "amlogic, vdin"; dev_name = "vdin0"; status = "disabled"; reserve-iomap = "true"; flag_cma = <0>;/*1:share with codec_mm;2:cma alone*/ /*MByte, if 10bit disable: 64M(YUV422), *if 10bit enable: 64*1.5 = 96M(YUV422) *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M */ /*cma_size = <16>;*/ interrupts = <0 83 1>; rdma-irq = <2>; /*clocks = <&clock CLK_FPLL_DIV5>, * <&clock CLK_VDIN_MEAS_CLK>; *clock-names = "fclk_div5", "cts_vdin_meas_clk"; */ vdin_id = <0>; }; vdin1: vdin1 { compatible = "amlogic, vdin"; dev_name = "vdin1"; status = "disabled"; reserve-iomap = "true"; flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ interrupts = <0 85 1>; rdma-irq = <4>; /*clocks = <&clock CLK_FPLL_DIV5>, * <&clock CLK_VDIN_MEAS_CLK>; *clock-names = "fclk_div5", "cts_vdin_meas_clk"; */ vdin_id = <1>; }; vout { compatible = "amlogic, vout"; dev_name = "vout"; status = "okay"; /* fr_policy: * 0: disable * 1: nearby (only for 60->59.94 and 30->29.97) * 2: force (60/50/30/24/59.94/23.97) */ fr_policy = <2>; }; vout2 { compatible = "amlogic, vout2"; dev_name = "vout"; status = "okay"; clocks = <&clkc CLKID_VPU_CLKC_P0_COMP>, <&clkc CLKID_VPU_CLKC_MUX>; clock-names = "vpu_clkc0", "vpu_clkc"; /* fr_policy: * 0: disable * 1: nearby (only for 60->59.94 and 30->29.97) * 2: force (60/50/30/24/59.94/23.97) */ fr_policy = <2>; }; dummy_venc: dummy_venc { compatible = "amlogic, dummy_venc"; status = "okay"; clocks = <&clkc CLKID_VCLK2_ENCP &clkc CLKID_VCLK2_VENCP0 &clkc CLKID_VCLK2_VENCP1 &clkc CLKID_VCLK2_ENCI &clkc CLKID_VCLK2_VENCI0 &clkc CLKID_VCLK2_VENCI1 &clkc CLKID_VCLK2_ENCL &clkc CLKID_VCLK2_VENCL>; clock-names = "encp_top_gate", "encp_int_gate0", "encp_int_gate1", "venci_top_gate", "enci_int_gate0", "enci_int_gate1", "encl_top_gate", "encl_int_gate"; }; vdac { compatible = "amlogic, vdac-sm1"; status = "okay"; }; canvas: canvas{ compatible = "amlogic, meson, canvas"; dev_name = "amlogic-canvas"; status = "okay"; reg = <0x0 0xff638000 0x0 0x2000>; }; ge2d { compatible = "amlogic, ge2d-sm1"; dev_name = "ge2d"; status = "okay"; interrupts = <0 146 1>; interrupt-names = "ge2d"; clocks = <&clkc CLKID_VAPB_MUX>, <&clkc CLKID_G2D>, <&clkc CLKID_GE2D_GATE>; clock-names = "clk_vapb_0", "clk_ge2d", "clk_ge2d_gate"; reg = <0x0 0xff940000 0x0 0x10000>; }; meson-amvideom { compatible = "amlogic, amvideom"; dev_name = "amvideom"; status = "okay"; interrupts = <0 3 1>; interrupt-names = "vsync"; }; codec_io: codec_io { compatible = "amlogic, codec_io"; status = "okay"; #address-cells=<2>; #size-cells=<2>; ranges; io_cbus_base{ reg = <0x0 0xffd00000 0x0 0x100000>; }; io_dos_base{ reg = <0x0 0xff620000 0x0 0x10000>; }; io_hiubus_base{ reg = <0x0 0xff63c000 0x0 0x2000>; }; io_aobus_base{ reg = <0x0 0xff800000 0x0 0x10000>; }; io_vcbus_base{ reg = <0x0 0xff900000 0x0 0x40000>; }; io_dmc_base{ reg = <0x0 0xff638000 0x0 0x2000>; }; io_efuse_base{ reg = <0x0 0xff630000 0x0 0x2000>; }; }; mesonstream { compatible = "amlogic, codec, streambuf"; dev_name = "mesonstream"; status = "okay"; clocks = <&clkc CLKID_DOS_PARSER &clkc CLKID_DEMUX &clkc CLKID_AHB_ARB0 &clkc CLKID_DOS &clkc CLKID_CLK81 &clkc CLKID_VDEC_MUX &clkc CLKID_HCODEC_MUX &clkc CLKID_HEVC_MUX &clkc CLKID_HEVCF_MUX>; clock-names = "parser_top", "demux", "ahbarb0", "vdec", "clk_81", "clk_vdec_mux", "clk_hcodec_mux", "clk_hevc_mux", "clk_hevcb_mux"; }; vdec { compatible = "amlogic, vdec"; dev_name = "vdec.0"; status = "okay"; interrupts = <0 3 1 0 23 1 0 32 1 0 43 1 0 44 1 0 45 1>; interrupt-names = "vsync", "demux", "parser", "mailbox_0", "mailbox_1", "mailbox_2"; }; vcodec_dec { compatible = "amlogic, vcodec-dec"; dev_name = "aml-vcodec-dec"; status = "okay"; }; video_composer { compatible = "amlogic, video_composer"; dev_name = "video_composer"; status = "okay"; }; amvenc_avc{ compatible = "amlogic, amvenc_avc"; dev_name = "amvenc_avc"; status = "okay"; interrupts = <0 45 1>; interrupt-names = "mailbox_2"; }; hevc_enc{ compatible = "cnm, HevcEnc"; //memory-region = <&hevc_enc_reserved>; dev_name = "HevcEnc"; status = "okay"; interrupts = <0 187 1>; interrupt-names = "wave420l_irq"; #address-cells=<2>; #size-cells=<2>; ranges; io_reg_base{ reg = <0x0 0xff610000 0x0 0x4000>; }; }; rdma{ compatible = "amlogic, meson, rdma"; dev_name = "amlogic-rdma"; status = "okay"; interrupts = <0 89 1>; interrupt-names = "rdma"; }; meson_fb: fb { compatible = "amlogic, meson-sm1"; memory-region = <&logo_reserved>; dev_name = "meson-fb"; status = "disable"; interrupts = <0 3 1 0 56 1 0 89 1>; interrupt-names = "viu-vsync", "viu2-vsync", "rdma"; /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ display_mode_default = "1080p60hz"; scale_mode = <1>; /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ display_size_default = <1920 1080 1920 2160 32>; /*1920*1080*4*3 = 0x17BB000*/ clocks = <&clkc CLKID_VPU_CLKC_MUX>; clock-names = "vpu_clkc"; }; irblaster: meson-irblaster { compatible = "amlogic, meson_irblaster"; reg = <0x0 0xff80014c 0x0 0x10>, <0x0 0xff800040 0x0 0x4>; pinctrl-names = "default"; pinctrl-0 = <&irblaster_pins>; interrupts = <0 198 1>; status = "okay"; }; sd_emmc_c: emmc@ffe07000 { status = "disabled"; compatible = "amlogic, meson-mmc-sm1"; reg = <0x0 0xffe07000 0x0 0x800>; interrupts = <0 191 1>; pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; pinctrl-0 = <&emmc_clk_cmd_pins>; pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; clocks = <&clkc CLKID_SD_EMMC_C>, <&clkc CLKID_SD_EMMC_C_P0_COMP>, <&clkc CLKID_FCLK_DIV2>, <&clkc CLKID_FCLK_DIV2P5>, <&xtal>; clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; bus-width = <8>; cap-sd-highspeed; cap-mmc-highspeed; /* mmc-ddr-1_8v; */ /* mmc-hs200-1_8v; */ max-frequency = <200000000>; non-removable; disable-wp; emmc { pinname = "emmc"; ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ /*caps defined in dts*/ tx_delay = <0x13>; co_phase = <3>; max_req_size = <0x20000>; /**128KB*/ gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; hw_reset = <&gpio BOOT_12 GPIO_ACTIVE_HIGH>; card_type = <1>; /* 1:mmc card(include eMMC), * 2:sd card(include tSD) */ }; }; sd_emmc_b:sd@ffe05000 { status = "disabled"; compatible = "amlogic, meson-mmc-sm1"; reg = <0x0 0xffe05000 0x0 0x800>; interrupts = <0 190 1>; pinctrl-names = "sd_all_pins", "sd_clk_cmd_pins", "sd_1bit_pins", "sd_clk_cmd_uart_pins", "sd_1bit_uart_pins", "sd_to_ao_uart_pins", "ao_to_sd_uart_pins", "sd_to_ao_jtag_pins", "ao_to_sd_jtag_pins"; pinctrl-0 = <&sd_all_pins>; pinctrl-1 = <&sd_clk_cmd_pins>; pinctrl-2 = <&sd_1bit_pins>; pinctrl-3 = <&sd_to_ao_uart_clr_pins &sd_clk_cmd_pins &ao_to_sd_uart_pins>; pinctrl-4 = <&sd_to_ao_uart_clr_pins &sd_1bit_pins &ao_to_sd_uart_pins>; pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; pinctrl-7 = <&sd_all_pins &sd_to_ao_uart_pins>; pinctrl-8 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; clocks = <&clkc CLKID_SD_EMMC_B>, <&clkc CLKID_SD_EMMC_B_P0_COMP>, <&clkc CLKID_FCLK_DIV2>, <&clkc CLKID_FCLK_DIV5>, <&xtal>; clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <100000000>; disable-wp; sd { pinname = "sd"; ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ max_req_size = <0x20000>; /**128KB*/ gpio_dat3 = <&gpio GPIOC_3 GPIO_ACTIVE_HIGH>; jtag_pin = <&gpio GPIOC_0 GPIO_ACTIVE_HIGH>; gpio_cd = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; card_type = <5>; /* 3:sdio device(ie:sdio-wifi), * 4:SD combo (IO+mem) card */ }; }; sd_emmc_a:sdio@ffe03000 { status = "disabled"; compatible = "amlogic, meson-mmc-sm1"; reg = <0x0 0xffe03000 0x0 0x800>; interrupts = <0 189 4>; pinctrl-names = "sdio_all_pins", "sdio_clk_cmd_pins"; pinctrl-0 = <&sdio_all_pins>; pinctrl-1 = <&sdio_clk_cmd_pins>; clocks = <&clkc CLKID_SD_EMMC_A>, <&clkc CLKID_SD_EMMC_A_P0_COMP>, <&clkc CLKID_FCLK_DIV2>, <&clkc CLKID_FCLK_DIV5>, <&xtal>; clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <100000000>; disable-wp; sdio { pinname = "sdio"; ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ max_req_size = <0x20000>; /**128KB*/ card_type = <3>; /* 3:sdio device(ie:sdio-wifi), * 4:SD combo (IO+mem) card */ }; }; nand: nfc@0 { compatible = "amlogic, aml_mtd_nand"; dev_name = "mtdnand"; status = "disabled"; reg = <0x0 0xFFE07800 0x0 0x200>; interrupts = <0 34 1>; pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; pinctrl-0 = <&all_nand_pins>; pinctrl-1 = <&all_nand_pins>; pinctrl-2 = <&nand_cs_pins>; device_id = <0>; clocks = <&clkc CLKID_SD_EMMC_C>, <&clkc CLKID_FCLK_DIV2>; clock-names = "gate", "fdiv2pll"; bl_mode = <1>; fip_copies = <4>; fip_size = <0x200000>; nand_clk_ctrl = <0xFFE07000>; }; vddcpu0: pwmao_d-regulator { compatible = "pwm-regulator"; pwms = <&pwm_AO_cd MESON_PWM_1 1500 0>; regulator-name = "vddcpu0"; regulator-min-microvolt = <690000>; regulator-max-microvolt = <1050000>; regulator-always-on; max-duty-cycle = <1500>; /* Voltage Duty-Cycle */ voltage-table = <1050000 0>, <1040000 3>, <1030000 6>, <1020000 8>, <1010000 11>, <1000000 14>, <990000 17>, <980000 20>, <970000 23>, <960000 26>, <950000 29>, <940000 31>, <930000 34>, <920000 37>, <910000 40>, <900000 43>, <890000 45>, <880000 48>, <870000 51>, <860000 54>, <850000 56>, <840000 59>, <830000 62>, <820000 65>, <810000 68>, <800000 70>, <790000 73>, <780000 76>, <770000 79>, <760000 81>, <750000 84>, <740000 87>, <730000 89>, <720000 92>, <710000 95>, <700000 98>, <690000 100>; status = "okay"; }; ddr_bandwidth { compatible = "amlogic, ddr-bandwidth"; status = "okay"; reg = <0x0 0xff638000 0x0 0x100 0x0 0xff638c00 0x0 0x100>; sec_base = <0xff639000>; interrupts = <0 52 1>; interrupt-names = "ddr_bandwidth"; }; dmc_monitor { compatible = "amlogic, dmc_monitor"; status = "okay"; reg_base = <0xff639000>; interrupts = <0 51 1>; }; defendkey: defendkey { compatible = "amlogic, defendkey"; reg = <0x0 0xff630218 0x0 0x4>; /*RNG_USR_DATA*/ mem_size = <0x0 0x100000>; status = "okay"; }; aml_dma { compatible = "amlogic,aml_txlx_dma"; reg = <0x0 0xff63e000 0x0 0x48>; interrupts = <0 180 1>; aml_aes { compatible = "amlogic,aes_g12a_dma"; dev_name = "aml_aes_dma"; status = "okay"; }; aml_sha { compatible = "amlogic,sha_dma"; dev_name = "aml_sha_dma"; status = "okay"; }; }; rng { compatible = "amlogic,meson-rng"; status = "okay"; #address-cells = <2>; #size-cells = <2>; reg = <0x0 0xff630218 0x0 0x4>; quality = /bits/ 16 <1000>; }; efuse: efuse{ compatible = "amlogic, efuse"; read_cmd = <0x82000030>; write_cmd = <0x82000031>; get_max_cmd = <0x82000033>; key = <&efusekey>; clocks = <&clkc CLKID_EFUSE>; clock-names = "efuse_clk"; status = "disabled"; }; cpu_ver_name { compatible = "amlogic, cpu-major-id-sm1"; }; p_tsensor: p_tsensor@ff634800 { compatible = "amlogic, r1p1-tsensor"; device_name = "meson-pthermal"; status = "okay"; reg = <0x0 0xff634800 0x0 0x50>, <0x0 0xff800268 0x0 0x4>; cal_type = <0x1>; cal_a = <324>; cal_b = <424>; cal_c = <3159>; cal_d = <9411>; rtemp = <115000>; interrupts = <0 35 0>; clocks = <&clkc CLKID_TS_COMP>; /* CLKID_TS_COMP>;*/ clock-names = "ts_comp"; #thermal-sensor-cells = <1>; }; d_tsensor: d_tsensor@ff634c00 { compatible = "amlogic, r1p1-tsensor"; device_name = "meson-dthermal"; status = "okay"; reg = <0x0 0xff634c00 0x0 0x50>, <0x0 0xff800230 0x0 0x4>; cal_type = <0x1>; cal_a = <324>; cal_b = <424>; cal_c = <3159>; cal_d = <9411>; rtemp = <115000>; interrupts = <0 36 0>; clocks = <&clkc CLKID_TS_COMP>; /* CLKID_TS_COMP>;*/ clock-names = "ts_comp"; #thermal-sensor-cells = <1>; }; meson_cooldev: meson-cooldev@0 { status = "okay"; compatible = "amlogic, meson-cooldev"; device_name = "mcooldev"; cooling_devices { cpufreq_cool_cluster0 { min_state = <1000000>; dyn_coeff = <125>; gpu_pp = <2>; cluster_id = <0>; node_name = "cpufreq_cool0"; device_type = "cpufreq"; }; cpucore_cool_cluster0 { min_state = <1>; dyn_coeff = <0>; gpu_pp = <2>; cluster_id = <0>; node_name = "cpucore_cool0"; device_type = "cpucore"; }; gpufreq_cool { min_state = <500>; dyn_coeff = <215>; gpu_pp = <2>; cluster_id = <0>; node_name = "gpufreq_cool0"; device_type = "gpufreq"; }; gpucore_cool { min_state = <1>; dyn_coeff = <0>; gpu_pp = <2>; cluster_id = <0>; node_name = "gpucore_cool0"; device_type = "gpucore"; }; }; cpufreq_cool0:cpufreq_cool0 { #cooling-cells = <2>; /* min followed by max */ }; cpucore_cool0:cpucore_cool0 { #cooling-cells = <2>; /* min followed by max */ }; gpufreq_cool0:gpufreq_cool0 { #cooling-cells = <2>; /* min followed by max */ }; gpucore_cool0:gpucore_cool0 { #cooling-cells = <2>; /* min followed by max */ }; }; /*meson cooling devices end*/ thermal-zones { soc_thermal: soc_thermal { polling-delay = <1000>; polling-delay-passive = <100>; sustainable-power = <1410>; thermal-sensors = <&p_tsensor 0>; trips { pswitch_on: trip-point@0 { temperature = <60000>; hysteresis = <5000>; type = "passive"; }; pcontrol: trip-point@1 { temperature = <75000>; hysteresis = <5000>; type = "passive"; }; phot: trip-point@2 { temperature = <85000>; hysteresis = <5000>; type = "hot"; }; pcritical: trip-point@3 { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { cpufreq_cooling_map { trip = <&pcontrol>; cooling-device = <&cpufreq_cool0 0 4>; contribution = <1024>; }; cpucore_cooling_map { trip = <&pcontrol>; cooling-device = <&cpucore_cool0 0 3>; contribution = <1024>; }; gpufreq_cooling_map { trip = <&pcontrol>; cooling-device = <&gpufreq_cool0 0 3>; contribution = <1024>; }; gpucore_cooling_map { trip = <&pcontrol>; cooling-device = <&gpucore_cool0 0 2>; contribution = <1024>; }; }; }; ddr_thermal: ddr_thermal { polling-delay = <2000>; polling-delay-passive = <1000>; sustainable-power = <1410>; thermal-sensors = <&d_tsensor 1>; trips { dswitch_on: trip-point@0 { temperature = <60000>; hysteresis = <5000>; type = "passive"; }; dcontrol: trip-point@1 { temperature = <75000>; hysteresis = <5000>; type = "passive"; }; dhot: trip-point@2 { temperature = <85000>; hysteresis = <5000>; type = "hot"; }; dcritical: trip-point@3 { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; };/*thermal zone end*/ };/* end of / */ &pinctrl_aobus { sd_to_ao_uart_clr_pins:sd_to_ao_uart_clr_pins { mux { groups = "GPIOAO_0", "GPIOAO_1"; function = "gpio_aobus"; }; }; sd_to_ao_uart_pins:sd_to_ao_uart_pins { mux { groups = "uart_ao_tx_a", "uart_ao_rx_a"; function = "uart_ao_a"; bias-pull-up; input-enable; }; }; ao_uart_pins:ao_uart { mux { groups = "uart_ao_tx_a", "uart_ao_rx_a"; function = "uart_ao_a"; }; }; ao_b_uart_pins:ao_b_uart { mux { groups = "uart_ao_tx_b_2", "uart_ao_rx_b_3"; function = "uart_ao_b"; }; }; ao_i2c_master_pins1:ao_i2c_pins1 { mux { groups = "i2c_ao_sck", "i2c_ao_sda"; function = "i2c_ao"; drive-strength = <2>; }; }; ao_i2c_master_pins2:ao_i2c_pins2 { mux { groups = "i2c_ao_sck_e", "i2c_ao_sda_e"; function = "i2c_ao"; drive-strength = <2>; }; }; ao_i2c_slave_pins:ao_i2c_slave_pins { mux { groups = "i2c_ao_slave_sck", "i2c_ao_slave_sda"; function = "i2c_ao_slave"; }; }; pwm_ao_a_pins: pwm_ao_a { mux { groups = "pwm_ao_a"; function = "pwm_ao_a"; }; }; pwm_ao_a_hiz_pins: pwm_ao_a_hiz { mux { groups = "pwm_ao_a_hiz"; function = "pwm_ao_a"; }; }; pwm_ao_b_pins: pwm_ao_b { mux { groups = "pwm_ao_b"; function = "pwm_ao_b"; }; }; pwm_ao_c_pins1: pwm_ao_c_pins1 { mux { groups = "pwm_ao_c_4"; function = "pwm_ao_c"; }; }; pwm_ao_c_pins2: pwm_ao_c_pins2 { mux { groups = "pwm_ao_c_6"; function = "pwm_ao_c"; }; }; pwm_ao_c_hiz_pins: pwm_ao_c_hiz { mux { groups = "pwm_ao_c_hiz_4"; function = "pwm_ao_c"; }; }; pwm_ao_d_pins1: pwm_ao_d_pins1 { mux { groups = "pwm_ao_d_5"; function = "pwm_ao_d"; }; }; pwm_ao_d_pins2: pwm_ao_d_pins2 { mux { groups = "pwm_ao_d_10"; function = "pwm_ao_d"; }; }; pwm_ao_d_pins3: pwm_ao_d_pins3 { mux { groups = "pwm_ao_d_e"; function = "pwm_ao_d"; }; }; aocec_a: ao_ceca { mux { groups = "cec_ao_a"; function = "cec_ao"; }; }; aocec_b: ao_cecb { mux { groups = "cec_ao_b"; function = "cec_ao"; }; }; jtag_apao_pins:jtag_apao_pin { mux { groups = "jtag_a_tdi", "jtag_a_tdo", "jtag_a_clk", "jtag_a_tms"; function = "jtag_a"; }; }; }; &pinctrl_periphs { /* sdemmc portC */ emmc_clk_cmd_pins:emmc_clk_cmd_pins { mux { groups = "emmc_clk", "emmc_cmd"; function = "emmc"; input-enable; bias-pull-up; drive-strength = <3>; }; }; emmc_conf_pull_up:emmc_conf_pull_up { mux { groups = "emmc_nand_d7", "emmc_nand_d6", "emmc_nand_d5", "emmc_nand_d4", "emmc_nand_d3", "emmc_nand_d2", "emmc_nand_d1", "emmc_nand_d0", "emmc_clk", "emmc_cmd"; function = "emmc"; input-enable; bias-pull-up; drive-strength = <3>; }; }; emmc_conf_pull_done:emmc_conf_pull_done { mux { groups = "emmc_nand_ds"; function = "emmc"; input-enable; bias-pull-down; drive-strength = <3>; }; }; /* sdemmc portB */ sd_clk_cmd_pins:sd_clk_cmd_pins { mux { groups = "sdcard_cmd_c"; function = "sdcard"; input-enable; bias-pull-up; drive-strength = <3>; }; mux1 { groups = "sdcard_clk_c"; function = "sdcard"; bias-pull-up; output-high; drive-strength = <3>; }; }; sd_all_pins:sd_all_pins { mux { groups = "sdcard_d0_c", "sdcard_d1_c", "sdcard_d2_c", "sdcard_d3_c", "sdcard_cmd_c"; function = "sdcard"; input-enable; bias-pull-up; drive-strength = <3>; }; mux1 { groups = "sdcard_clk_c"; function = "sdcard"; bias-pull-up; output-high; drive-strength = <3>; }; }; sd_1bit_pins:sd_1bit_pins { mux { groups = "sdcard_d0_c", "sdcard_cmd_c"; function = "sdcard"; input-enable; bias-pull-up; drive-strength = <3>; }; mux1 { groups = "sdcard_clk_c"; function = "sdcard"; bias-pull-up; output-high; drive-strength = <3>; }; }; sd_clr_all_pins:sd_clr_all_pins { mux { groups = "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_5"; function = "gpio_periphs"; output-high; }; mux1 { groups = "GPIOC_4"; function = "gpio_periphs"; output-low; }; }; sd_clr_noall_pins:sd_clr_noall_pins { mux { groups = "GPIOC_0", "GPIOC_1", "GPIOC_4", "GPIOC_5"; function = "gpio_periphs"; output-high; }; }; ao_to_sd_uart_pins:ao_to_sd_uart_pins { mux { groups = "uart_ao_tx_a_c3", "uart_ao_rx_a_c2"; function = "uart_ao_a_ee"; bias-pull-up; input-enable; }; }; /* sdemmc portA */ sdio_clk_cmd_pins:sdio_clk_cmd_pins { mux { groups = "sdio_clk", "sdio_cmd"; function = "sdio"; input-enable; bias-pull-up; drive-strength = <3>; }; }; sdio_all_pins:sdio_all_pins { mux { groups = "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", "sdio_clk", "sdio_cmd"; function = "sdio"; input-enable; bias-pull-up; drive-strength = <3>; }; }; sdio_x_clk_cmd_pins:sdio_x_clk_cmd_pins { mux { groups = "GPIOX_5"; function = "gpio_periphs"; input-enable; bias-pull-up; drive-strength = <3>; }; mux1 { groups = "GPIOX_4"; function = "gpio_periphs"; bias-pull-up; output-high; drive-strength = <3>; }; }; sdio_x_all_pins:sdio_x_all_pins { mux { groups = "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_5"; function = "gpio_periphs"; input-enable; bias-pull-up; drive-strength = <3>; }; mux1 { groups = "GPIOX_4"; function = "gpio_periphs"; bias-pull-up; output-high; drive-strength = <3>; }; }; sdio_x_en_pins:sdio_x_en_pins { mux { groups = "sdio_dummy"; function = "sdio"; bias-pull-up; output-high; }; }; sdio_x_clr_pins:sdio_x_clr_pins { mux { groups = "GPIOV_0"; function = "gpio_periphs"; bias-pull-up; output-low; }; mux1 { groups = "GPIOX_4"; function = "gpio_periphs"; output-low; }; }; all_nand_pins: all_nand_pins { mux { groups = "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", "nand_ce0", "nand_ale", "nand_cle", "nand_wen_clk", "nand_ren_wr", "nand_rb0"; function = "nand"; input-enable; }; }; nand_cs_pins: nand_cs { mux { groups = "nand_ce0"; function = "nand"; }; }; i2c0_master_pins1:i2c0_pins1 { mux { groups = "i2c0_sda_c", "i2c0_sck_c"; function = "i2c0"; drive-strength = <2>; }; }; i2c0_master_pins2:i2c0_pins2 { mux { groups = "i2c0_sda_z0", "i2c0_sck_z1"; function = "i2c0"; drive-strength = <2>; }; }; i2c0_master_pins3:i2c0_pins3 { mux { groups = "i2c0_sda_z7", "i2c0_sck_z8"; function = "i2c0"; drive-strength = <2>; }; }; i2c1_master_pins1:i2c1_pins1 { mux { groups = "i2c1_sda_x", "i2c1_sck_x"; function = "i2c1"; drive-strength = <2>; }; }; i2c1_master_pins2:i2c1_pins2 { mux { groups = "i2c1_sda_h2", "i2c1_sck_h3"; function = "i2c1"; drive-strength = <2>; }; }; i2c1_master_pins3:i2c1_pins3 { mux { groups = "i2c1_sda_h6", "i2c1_sck_h7"; function = "i2c1"; drive-strength = <2>; }; }; i2c2_master_pins1:i2c2_pins1 { mux { groups = "i2c2_sda_x", "i2c2_sck_x"; function = "i2c2"; drive-strength = <2>; }; }; i2c2_master_pins2:i2c2_pins2 { mux { groups = "i2c2_sda_z", "i2c2_sck_z"; function = "i2c2"; drive-strength = <2>; }; }; i2c2_master_pins3:i2c2_pins3 { mux { groups = "i2c2_sda_z10", "i2c2_sck_z11"; function = "i2c2"; drive-strength = <2>; }; }; i2c3_master_pins1:i2c3_pins1 { mux { groups = "i2c3_sda_h", "i2c3_sck_h"; function = "i2c3"; drive-strength = <2>; }; }; i2c3_master_pins2:i2c3_pins2 { mux { groups = "i2c3_sda_a", "i2c3_sck_a"; function = "i2c3"; drive-strength = <2>; }; }; /*dvb_p_ts1_pins: dvb_p_ts1_pins { * tsin_b { * groups = "tsin_b_sop_z", * "tsin_b_valid_z", * "tsin_b_clk_z", * "tsin_b_din0_z", * "tsin_b_din1", * "tsin_b_din2", * "tsin_b_din3", * "tsin_b_din4", * "tsin_b_din5", * "tsin_b_din6", * "tsin_b_din7"; * function = "tsin_b"; * }; *}; */ pwm_a_pins: pwm_a { mux { groups = "pwm_a"; function = "pwm_a"; }; }; pwm_b_pins1: pwm_b_pins1 { mux { groups = "pwm_b_x7"; function = "pwm_b"; }; }; pwm_b_pins2: pwm_b_pins2 { mux { groups = "pwm_b_x19"; function = "pwm_b"; }; }; pwm_c_pins1: pwm_c_pins1 { mux { groups = "pwm_c_c4"; function = "pwm_c"; }; }; pwm_c_pins2: pwm_c_pins2 { mux { groups = "pwm_c_x5"; function = "pwm_c"; }; }; pwm_c_pins3: pwm_c_pins3 { mux { groups = "pwm_c_x8"; function = "pwm_c"; }; }; pwm_d_pins1: pwm_d_pins1 { mux { groups = "pwm_d_x3"; function = "pwm_d"; }; }; pwm_d_pins2: pwm_d_pins2 { mux { groups = "pwm_d_x6"; function = "pwm_d"; }; }; pwm_e_pins: pwm_e { mux { groups = "pwm_e"; function = "pwm_e"; drive-strength = <0>; }; }; pwm_f_pins1: pwm_f_pins1 { mux { groups = "pwm_f_x"; function = "pwm_f"; }; }; pwm_f_pins2: pwm_f_pins2 { mux { groups = "pwm_f_h"; function = "pwm_f"; }; }; spicc0_pins_x: spicc0_pins_x { mux { groups = "spi0_mosi_x", "spi0_miso_x", //"spi0_ss0_x", "spi0_clk_x"; function = "spi0"; drive-strength = <1>; }; }; spicc0_pins_c: spicc0_pins_c { mux { groups = "spi0_mosi_c", "spi0_miso_c", "spi0_ss0_c", "spi0_clk_c"; function = "spi0"; drive-strength = <1>; }; }; spicc1_pins: spicc1_pins { mux { groups = "spi1_mosi", "spi1_miso", //"spi1_ss0", "spi1_clk"; function = "spi1"; drive-strength = <1>; }; }; a_uart_pins:a_uart { mux { groups = "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a"; function = "uart_a"; }; }; b_uart_pins:b_uart { mux { groups = "uart_tx_b", "uart_rx_b"; function = "uart_b"; }; }; c_uart_pins:c_uart { mux { groups = "uart_tx_c", "uart_rx_c"; function = "uart_c"; }; }; hdmitx_hpd: hdmitx_hpd { mux { groups = "hdmitx_hpd_in"; function = "hdmitx"; bias-disable; }; }; hdmitx_hpd_gpio: hdmitx_hpd_gpio { mux { groups = "GPIOH_1"; function = "gpio_periphs"; bias-disable; }; }; hdmitx_ddc: hdmitx_ddc { mux { groups = "hdmitx_sda", "hdmitx_sck"; function = "hdmitx"; bias-disable; drive-strength = <3>; }; }; eecec_a: ee_ceca { mux { groups = "cec_ao_a_ee"; function = "cec_ao_ee"; }; }; eecec_b: ee_cecb { mux { groups = "cec_ao_b_ee"; function = "cec_ao_ee"; }; }; internal_eth_pins: internal_eth_pins { mux { groups = "eth_link_led", "eth_act_led"; function = "eth"; }; }; internal_gpio_pins: internal_gpio_pins { mux { groups = "GPIOZ_14", "GPIOZ_15"; function = "gpio_periphs"; bias-disable; input-enable; }; }; external_eth_pins: external_eth_pins { mux { groups = "eth_mdio", "eth_mdc", "eth_rgmii_rx_clk", "eth_rx_dv", "eth_rxd0", "eth_rxd1", "eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk", "eth_txen", "eth_txd0", "eth_txd1", "eth_txd2_rgmii", "eth_txd3_rgmii"; function = "eth"; drive-strength = <3>; }; }; jtag_apee_pins:jtag_apee_pin { mux { groups = "jtag_b_tdi", "jtag_b_tdo", "jtag_b_clk", "jtag_b_tms"; function = "jtag_b"; }; }; }; &pinctrl_aobus { remote_pins:remote_pin { mux { groups = "remote_input_ao"; function = "remote_input_ao"; }; }; irblaster_pins:irblaster_pin { mux { groups = "remote_out_ao"; function = "remote_out_ao"; }; }; }; /* end of pinctrl_aobus */