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[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] /
1 /*
2 OMAP3430 ZOOM MDK astoria interface defs(cyasmemmap.h)
3 ## ===========================
4 ## Copyright (C) 2010 Cypress Semiconductor
5 ##
6 ## This program is free software; you can redistribute it and/or
7 ## modify it under the terms of the GNU General Public License
8 ## as published by the Free Software Foundation; either version 2
9 ## of the License, or (at your option) any later version.
10 ##
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
15 ##
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin Street, Fifth Floor
19 ## Boston, MA 02110-1301, USA.
20 ## ===========================
21 */
22 /* include does not seem to work
23 * moving for patch submission
24 #include <mach/gpmc.h>
25 #include <mach/mux.h>
26 */
27 #include <linux/../../arch/arm/plat-omap/include/plat/gpmc.h>
28 #include <linux/../../arch/arm/plat-omap/include/plat/mux.h>
29
30 #ifndef _INCLUDED_CYASMEMMAP_H_
31 #define _INCLUDED_CYASMEMMAP_H_
32
33 /* defines copied from OMAP kernel branch */
34 #define OMAP34XX_MUX_MODE0 0
35 #define OMAP34XX_MUX_MODE4 4
36 #define OMAP3_INPUT_EN (1 << 8)
37 #define OMAP34XX_PIN_INPUT_PULLUP (OMAP2_PULL_ENA | OMAP3_INPUT_EN \
38 | OMAP2_PULL_UP)
39
40 /*
41 * for OMAP3430 <-> astoria : ADmux mode, 8 bit data path
42 * WB Signal- OMAP3430 signal COMMENTS
43 * --------------------------- --------------------
44 * CS_L -GPMC_nCS4_GPIO_53 ZOOM I SOM board
45 * signal: up_nCS_A_EXT
46 * AD[7:0]-upD[7:0] buffered on the
47 * transposer board
48 * GPMC_ADDR
49 * [A8:A1]->upD[7:0]
50 * INT# -GPMC_nWP_GPIO_62
51 * DACK -N/C not conected
52 * WAKEUP-GPIO_167
53 * RESET-GPIO_126
54 * R/B -GPMC_WAIT2_GPIO_64
55 * -------------------------------------------
56 * The address range for nCS1B is 0x06000000 - 0x07FF FFFF.
57 */
58
59 /*
60 *OMAP_ZOOM LEDS
61 */
62 #define LED_0 156
63 #define LED_1 128
64 #define LED_2 64
65 #define LED_3 60
66
67 #define HIGH 1
68 #define LOW 1
69
70 /*
71 *omap GPIO number
72 */
73 #define AST_WAKEUP 167
74 #define AST_RESET 126
75 #define AST__rn_b 64
76
77 /*
78 * NOTE THIS PIN IS USED AS WP for OMAP NAND
79 */
80 #define AST_INT 62
81
82 /*
83 * as an I/O, it is actually controlled by GPMC
84 */
85 #define AST_CS 55
86
87
88 /*
89 *GPMC prefetch engine
90 */
91
92 /* register and its bit fields */
93 #define GPMC_PREFETCH_CONFIG1 0x01E0
94
95 /*32 bytes for 16 bit pnand mode*/
96 #define PFE_THRESHOLD 31
97
98 /*
99 * bit fields
100 * PF_ACCESSMODE - 0 - read mode, 1 - write mode
101 * PF_DMAMODE - 0 - default only intr line signal will be generated
102 * PF_SYNCHROMODE - default 0 - engin will start access as soon as
103 * ctrl re STARTENGINE is set
104 * PF_WAITPINSEL - FOR synchro mode selects WAIT pin whch edge
105 * will be monitored
106 * PF_EN_ENGINE - 1- ENABLES ENGINE, but it needs to be started after
107 * that C ctrl reg bit 0
108 * PF_FIFO_THRESHOLD - FIFO threshhold in number of BUS(8 or 16) words
109 * PF_WEIGHTED_PRIO - NUM of cycles granted to PFE if RND_ROBIN
110 * prioritization is enabled
111 * PF_ROUND_ROBIN - if enabled, gives priority to other CS, but
112 * reserves NUM of cycles for PFE's turn
113 * PF_ENGIN_CS_SEL - GPMC CS assotiated with PFE function
114 */
115 #define PF_ACCESSMODE (0 << 0)
116 #define PF_DMAMODE (0 << 2)
117 #define PF_SYNCHROMODE (0 << 3)
118 #define PF_WAITPINSEL (0x0 << 4)
119 #define PF_EN_ENGINE (1 << 7)
120 #define PF_FIFO_THRESHOLD (PFE_THRESHOLD << 8)
121 #define PF_WEIGHTED_PRIO (0x0 << 16)
122 #define PF_ROUND_ROBIN (0 << 23)
123 #define PF_ENGIN_CS_SEL (AST_GPMC_CS << 24)
124 #define PF_EN_OPTIM_ACC (0 << 27)
125 #define PF_CYCLEOPTIM (0x0 << 28)
126
127 #define GPMC_PREFETCH_CONFIG1_VAL (PF_ACCESSMODE | \
128 PF_DMAMODE | PF_SYNCHROMODE | \
129 PF_WAITPINSEL | PF_EN_ENGINE | \
130 PF_FIFO_THRESHOLD | PF_FIFO_THRESHOLD | \
131 PF_WEIGHTED_PRIO | PF_ROUND_ROBIN | \
132 PF_ENGIN_CS_SEL | PF_EN_OPTIM_ACC | \
133 PF_CYCLEOPTIM)
134
135 /* register and its bit fields */
136 #define GPMC_PREFETCH_CONFIG2 0x01E4
137 /*
138 * bit fields
139 * 14 bit field NOTE this counts is also
140 * is in number of BUS(8 or 16) words
141 */
142 #define PF_TRANSFERCOUNT (0x000)
143
144
145 /* register and its bit fields */
146 #define GPMC_PREFETCH_CONTROL 0x01EC
147 /*
148 * bit fields , ONLY BIT 0 is implemented
149 * PFWE engin must be programmed with this bit = 0
150 */
151 #define PFPW_STARTENGINE (1 << 0)
152
153 /* register and its bit fields */
154 #define GPMC_PREFETCH_STATUS 0x01F0
155
156 /* */
157 #define PFE_FIFO_THRESHOLD (1 << 16)
158
159 /*
160 * GPMC posted write/prefetch engine end
161 */
162
163
164 /*
165 * chip select number on GPMC ( 0..7 )
166 */
167 #define AST_GPMC_CS 4
168
169 /*
170 * not connected
171 */
172 #define AST_DACK 00
173
174
175 /*
176 * Physical address above the NAND flash
177 * we use CS For mapping in OMAP3430 RAM space use 0x0600 0000
178 */
179 #define CYAS_DEV_BASE_ADDR (0x20000000)
180
181 #define CYAS_DEV_MAX_ADDR (0xFF)
182 #define CYAS_DEV_ADDR_RANGE (CYAS_DEV_MAX_ADDR << 1)
183
184 #ifdef p_s_r_a_m_INTERFACE
185 /* in CRAM or PSRAM mode OMAP A1..An wires-> Astoria, there is no A0 line */
186 #define CYAS_DEV_CALC_ADDR(cyas_addr) (cyas_addr << 1)
187 #define CYAS_DEV_CALC_EP_ADDR(ep) (ep << 1)
188 #else
189 /*
190 * For pNAND interface it depends on NAND emulation mode
191 * SBD/LBD etc we use NON-LNA_LBD mode, so it goes like this:
192 * forlbd <CMD><CA0,CA1,RA0,RA1,RA2> <CMD>,
193 * where CA1 address must have bits 2,3 = "11"
194 * ep is mapped into RA1 bits {4:0}
195 */
196 #define CYAS_DEV_CALC_ADDR(cyas_addr) (cyas_addr | 0x0c00)
197 #define CYAS_DEV_CALC_EP_ADDR(ep) ep
198 #endif
199
200 /*
201 *OMAP3430 i/o access macros
202 */
203 #define IORD32(addr) (*(volatile u32 *)(addr))
204 #define IOWR32(addr, val) (*(volatile u32 *)(addr) = val)
205
206 #define IORD16(addr) (*(volatile u16 *)(addr))
207 #define IOWR16(addr, val) (*(volatile u16 *)(addr) = val)
208
209 #define IORD8(addr) (*(volatile u8 *)(addr))
210 #define IOWR8(addr, val) (*(volatile u8 *)(addr) = val)
211
212 /*
213 * local defines for accessing to OMAP GPIO ***
214 */
215 #define CTLPADCONF_BASE_ADDR 0x48002000
216 #define CTLPADCONF_SIZE 0x1000
217
218 #define GPIO1_BASE_ADDR 0x48310000
219 #define GPIO2_BASE_ADDR 0x49050000
220 #define GPIO3_BASE_ADDR 0x49052000
221 #define GPIO4_BASE_ADDR 0x49054000
222 #define GPIO5_BASE_ADDR 0x49056000
223 #define GPIO6_BASE_ADDR 0x49058000
224 #define GPIO_SPACE_SIZE 0x1000
225
226
227 /*
228 * OMAP3430 GPMC timing for pNAND interface
229 */
230 #define GPMC_BASE 0x6E000000
231 #define GPMC_REGION_SIZE 0x1000
232 #define GPMC_CONFIG_REG (0x50)
233
234 /*
235 * bit 0 in the GPMC_CONFIG_REG
236 */
237 #define NAND_FORCE_POSTED_WRITE_B 1
238
239 /*
240 * WAIT2STATUS, must be (1 << 10)
241 */
242 #define AS_WAIT_PIN_MASK (1 << 10)
243
244
245 /*
246 * GPMC_CONFIG(reg number [1..7] [for chip sel CS[0..7])
247 */
248 #define GPMC_CFG_REG(N, CS) ((0x60 + (4*(N-1))) + (0x30*CS))
249
250 /*
251 *gpmc nand registers for CS4
252 */
253 #define GPMC_NAND_CMD (0x7c + (0x30*AST_GPMC_CS))
254 #define GPMC_NAND_ADDR (0x80 + (0x30*AST_GPMC_CS))
255 #define GPMC_NAND_DATA (0x84 + (0x30*AST_GPMC_CS))
256
257 #define GPMC_STAT_REG (0x54)
258 #define GPMC_ERR_TYPE (0x48)
259
260 /*
261 * we get "gpmc_base" from kernel
262 */
263 #define GPMC_VMA(offset) (gpmc_base + offset)
264
265 /*
266 * GPMC CS space VMA start address
267 */
268 #define GPMC_CS_VMA(offset) (gpmc_data_vma + offset)
269
270 /*
271 * PAD_CFG mux space VMA
272 */
273 #define PADCFG_VMA(offset) (iomux_vma + offset)
274
275 /*
276 * CONFIG1: by default, sngle access, async r/w RD_MULTIPLE[30]
277 * WR_MULTIPLE[28]; GPMC_FCL_DIV[1:0]
278 */
279 #define GPMC_FCLK_DIV ((0) << 0)
280
281 /*
282 * ADDITIONAL DIVIDER FOR ALL TIMING PARAMS
283 */
284 #define TIME_GRAN_SCALE ((0) << 4)
285
286 /*
287 * for use by gpmc_set_timings api, measured in ns, not clocks
288 */
289 #define WB_GPMC_BUSCYC_t (7 * 6)
290 #define WB_GPMC_CS_t_o_n (0)
291 #define WB_GPMC_ADV_t_o_n (0)
292 #define WB_GPMC_OE_t_o_n (0)
293 #define WB_GPMC_OE_t_o_f_f (5 * 6)
294 #define WB_GPMC_WE_t_o_n (1 * 6)
295 #define WB_GPMC_WE_t_o_f_f (5 * 6)
296 #define WB_GPMC_RDS_ADJ (2 * 6)
297 #define WB_GPMC_RD_t_a_c_c (WB_GPMC_OE_t_o_f_f + WB_GPMC_RDS_ADJ)
298 #define WB_GPMC_WR_t_a_c_c (WB_GPMC_BUSCYC_t)
299
300 #define DIR_OUT 0
301 #define DIR_INP 1
302 #define DRV_HI 1
303 #define DRV_LO 0
304
305 /*
306 * GPMC_CONFIG7[cs] register bit fields
307 * AS_CS_MASK - 3 bit mask for A26,A25,A24,
308 * AS_CS_BADDR - 6 BIT VALUE A29 ...A24
309 * CSVALID_B - CSVALID bit on GPMC_CONFIG7[cs] register
310 */
311 #define AS_CS_MASK (0X7 << 8)
312 #define AS_CS_BADDR 0x02
313 #define CSVALID_B (1 << 6)
314
315 /*
316 * DEFINE OMAP34XX GPIO OFFSETS (should have been defined in kernel /arch
317 * these are offsets from the BASE_ADDRESS of the GPIO BLOCK
318 */
319 #define GPIO_REVISION 0x000
320 #define GPIO_SYSCONFIG 0x010
321 #define GPIO_SYSSTATUS1 0x014
322 #define GPIO_IRQSTATUS1 0x018
323 #define GPIO_IRQENABLE1 0x01C
324 #define GPIO_IRQSTATUS2 0x028
325 #define GPIO_CTRL 0x030
326 #define GPIO_OE 0x034
327 #define GPIO_DATA_IN 0x038
328 #define GPIO_DATA_OUT 0x03C
329 #define GPIO_LEVELDETECT0 0x040
330 #define GPIO_LEVELDETECT1 0x044
331 #define GPIO_RISINGDETECT 0x048
332 #define GPIO_FALLINGDETECT 0x04c
333 #define GPIO_CLEAR_DATAOUT 0x090
334 #define GPIO_SET_DATAOUT 0x094
335
336 typedef struct {
337 char *name;
338 u32 phy_addr;
339 u32 virt_addr;
340 u32 size;
341 } io2vma_tab_t;
342
343 /*
344 * GPIO phy to translation VMA table
345 */
346 static io2vma_tab_t gpio_vma_tab[6] = {
347 {"GPIO1_BASE_ADDR", GPIO1_BASE_ADDR , 0 , GPIO_SPACE_SIZE},
348 {"GPIO2_BASE_ADDR", GPIO2_BASE_ADDR , 0 , GPIO_SPACE_SIZE},
349 {"GPIO3_BASE_ADDR", GPIO3_BASE_ADDR , 0 , GPIO_SPACE_SIZE},
350 {"GPIO4_BASE_ADDR", GPIO4_BASE_ADDR , 0 , GPIO_SPACE_SIZE},
351 {"GPIO5_BASE_ADDR", GPIO5_BASE_ADDR , 0 , GPIO_SPACE_SIZE},
352 {"GPIO6_BASE_ADDR", GPIO6_BASE_ADDR , 0 , GPIO_SPACE_SIZE}
353 };
354 /*
355 * name - USER signal name assigned to the pin ( for printks)
356 * mux_func - enum index NAME for the pad_cfg function
357 * pin_num - pin_number if mux_func is GPIO, if not a GPIO it is -1
358 * mux_ptr - pointer to the corresponding pad_cfg_reg
359 * (used for pad release )
360 * mux_save - preserve here original PAD_CNF value for this
361 * pin (used for pad release)
362 * dir - if GPIO: 0 - OUT , 1 - IN
363 * dir_save - save original pin direction
364 * drv - initial drive level "0" or "1"
365 * drv_save - save original pin drive level
366 * valid - 1 if successfuly configured
367 */
368 typedef struct {
369 char *name;
370 u32 mux_func;
371 int pin_num;
372 u16 *mux_ptr;
373 u16 mux_save;
374 u8 dir;
375 u8 dir_save;
376 u8 drv;
377 u8 drv_save;
378 u8 valid;
379 } user_pad_cfg_t;
380
381 /*
382 * need to ensure that enums are in sync with the
383 * omap_mux_pin_cfg table, these enums designate
384 * functions that OMAP pads can be configured to
385 */
386 enum {
387 B23_OMAP3430_GPIO_167,
388 D23_OMAP3430_GPIO_126,
389 H1_OMAP3430_GPIO_62,
390 H1_OMAP3430_GPMC_n_w_p,
391 T8_OMAP3430_GPMC_n_c_s4,
392 T8_OMAP3430_GPIO_55,
393 R25_OMAP3430_GPIO_156,
394 R27_OMAP3430_GPIO_128,
395 K8_OMAP3430_GPIO_64,
396 K8_GPMC_WAIT2,
397 G3_OMAP3430_GPIO_60,
398 G3_OMAP3430_n_b_e0_CLE,
399 C6_GPMC_WAIT3,
400 J1_OMAP3430_GPIO_61,
401 C6_OMAP3430_GPIO_65,
402
403 END_OF_TABLE
404 };
405
406 /*
407 * number of GPIOS we plan to grab
408 */
409 #define GPIO_SLOTS 8
410
411 /*
412 * user_pads_init() reads(and saves) from/to this table
413 * used in conjunction with omap_3430_mux_t table in .h file
414 * because the way it's done in the kernel code
415 * TODO: implement restore of the the original cfg and i/o regs
416 */
417
418 static user_pad_cfg_t user_pad_cfg[] = {
419 /*
420 * name,pad_func,pin_num, mux_ptr, mux_sav, dir,
421 * dir_sav, drv, drv_save, valid
422 */
423 {"AST_WAKEUP", B23_OMAP3430_GPIO_167, 167, NULL, 0,
424 DIR_OUT, 0, DRV_HI, 0, 0},
425 {"AST_RESET", D23_OMAP3430_GPIO_126, 126, NULL, 0,
426 DIR_OUT, 0, DRV_HI, 0, 0},
427 {"AST__rn_b", K8_GPMC_WAIT2, 64, NULL, 0,
428 DIR_INP, 0, 0, 0, 0},
429 {"AST_INTR", H1_OMAP3430_GPIO_62, 62, NULL, 0,
430 DIR_INP, 0, DRV_HI, 0, 0},
431 {"AST_CS", T8_OMAP3430_GPMC_n_c_s4, 55, NULL, 0,
432 DIR_OUT, 0, DRV_HI, 0, 0},
433 {"LED_0", R25_OMAP3430_GPIO_156, 156, NULL, 0,
434 DIR_OUT, 0, DRV_LO, 0, 0},
435 {"LED_1", R27_OMAP3430_GPIO_128, 128, NULL, 0,
436 DIR_OUT, 0, DRV_LO, 0, 0},
437 {"AST_CLE", G3_OMAP3430_n_b_e0_CLE , 60, NULL, 0,
438 DIR_OUT, 0, DRV_LO, 0, 0},
439 /*
440 * Z terminator, must always be present
441 * for sanity check, don't remove
442 */
443 {NULL}
444 };
445
446 #define GPIO_BANK(pin) (pin >> 5)
447 #define REG_WIDTH 32
448 #define GPIO_REG_VMA(pin_num, offset) \
449 (gpio_vma_tab[GPIO_BANK(pin_num)].virt_addr + offset)
450
451 /*
452 * OMAP GPIO_REG 32 BIT MASK for a bit or
453 * flag in gpio_No[0..191] apply it to a 32 bit
454 * location to set clear or check on a corresponding
455 * gpio bit or flag
456 */
457 #define GPIO_REG_MASK(pin_num) (1 << \
458 (pin_num - (GPIO_BANK(pin_num) * REG_WIDTH)))
459
460 /*
461 * OMAP GPIO registers bitwise access macros
462 */
463
464 #define OMAP_GPIO_BIT(pin_num, reg) \
465 ((*((u32 *)GPIO_REG_VMA(pin_num, reg)) \
466 & GPIO_REG_MASK(pin_num)) ? 1 : 0)
467
468 #define RD_OMAP_GPIO_BIT(pin_num, v) OMAP_GPIO_BIT(pin_num, reg)
469
470 /*
471 *these are superfast set/clr bitbang macro, 48ns cyc tyme
472 */
473 #define OMAP_SET_GPIO(pin_num) \
474 (*(u32 *)GPIO_REG_VMA(pin_num, GPIO_SET_DATAOUT) \
475 = GPIO_REG_MASK(pin_num))
476 #define OMAP_CLR_GPIO(pin_num) \
477 (*(u32 *)GPIO_REG_VMA(pin_num, GPIO_CLEAR_DATAOUT) \
478 = GPIO_REG_MASK(pin_num))
479
480 #define WR_OMAP_GPIO_BIT(pin_num, v) \
481 (v ? (*(u32 *)GPIO_REG_VMA(pin_num, \
482 GPIO_SET_DATAOUT) = GPIO_REG_MASK(pin_num)) \
483 : (*(u32 *)GPIO_REG_VMA(pin_num, \
484 GPIO_CLEAR_DATAOUT) = GPIO_REG_MASK(pin_num)))
485
486 /*
487 * Note this pin cfg mimicks similar implementation
488 * in linux kernel, which unfortunately doesn't allow
489 * us to dynamically insert new custom GPIO mux
490 * configurations all REG definitions used in this
491 * applications. to add a new pad_cfg function, insert
492 * a new ENUM and new pin_cfg entry in omap_mux_pin_cfg[]
493 * table below
494 *
495 * offset - note this is a word offset since the
496 * SCM regs are 16 bit packed in one 32 bit word
497 * mux_val - just enough to describe pins used
498 */
499 typedef struct {
500 char *name;
501 u16 offset;
502 u16 mux_val;
503 } omap_3430_mux_t;
504
505 /*
506 * "OUTIN" is configuration when DATA reg drives the
507 * pin but the level at the pin can be sensed
508 */
509 #define PAD_AS_OUTIN (OMAP34XX_MUX_MODE4 | \
510 OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_INPUT)
511
512 omap_3430_mux_t omap_mux_pin_cfg[] = {
513 /*
514 * B23_OMAP3430_GPIO_167 - GPIO func to PAD 167 WB wakeup
515 * D23_OMAP3430_GPIO_126 - drive GPIO_126 ( AST RESET)
516 * H1_OMAP3430_GPIO_62 - need a pullup on this pin
517 * H1_OMAP3430_GPMC_n_w_p - GPMC NAND CTRL n_w_p out
518 * T8_OMAP3430_GPMC_n_c_s4" - T8 is controlled b_y GPMC NAND ctrl
519 * R25_OMAP3430_GPIO_156 - OMAPZOOM drive LED_0
520 * R27_OMAP3430_GPIO_128 - OMAPZOOM drive LED_1
521 * K8_OMAP3430_GPIO_64 - OMAPZOOM drive LED_2
522 * K8_GPMC_WAIT2 - GPMC WAIT2 function on PAD K8
523 * G3_OMAP3430_GPIO_60 - OMAPZOOM drive LED_3
524 * G3_OMAP3430_n_b_e0_CLE -GPMC NAND ctrl CLE signal
525 */
526
527 {"B23_OMAP3430_GPIO_167", 0x0130, (OMAP34XX_MUX_MODE4)},
528 {"D23_OMAP3430_GPIO_126", 0x0132, (OMAP34XX_MUX_MODE4)},
529 {"H1_OMAP3430_GPIO_62", 0x00CA, (OMAP34XX_MUX_MODE4 |
530 OMAP3_INPUT_EN | OMAP34XX_PIN_INPUT_PULLUP) },
531 {"H1_OMAP3430_GPMC_n_w_p", 0x00CA, (OMAP34XX_MUX_MODE0)},
532 {"T8_OMAP3430_GPMC_n_c_s4", 0x00B6, (OMAP34XX_MUX_MODE0) },
533 {"T8_OMAP3430_GPIO_55", 0x00B6, (OMAP34XX_MUX_MODE4) },
534 {"R25_OMAP3430_GPIO_156", 0x018C, (OMAP34XX_MUX_MODE4) },
535 {"R27_OMAP3430_GPIO_128", 0x0154, (OMAP34XX_MUX_MODE4) },
536 {"K8_OMAP3430_GPIO_64", 0x00d0, (OMAP34XX_MUX_MODE4) },
537 {"K8_GPMC_WAIT2", 0x00d0, (OMAP34XX_MUX_MODE0) },
538 {"G3_OMAP3430_GPIO_60", 0x00C6, (OMAP34XX_MUX_MODE4 |
539 OMAP3_INPUT_EN)},
540 {"G3_OMAP3430_n_b_e0_CLE", 0x00C6, (OMAP34XX_MUX_MODE0)},
541 {"C6_GPMC_WAIT3", 0x00d2, (OMAP34XX_MUX_MODE0)},
542 {"C6_OMAP3430_GPIO_65", 0x00d2, (OMAP34XX_MUX_MODE4 |
543 OMAP3_INPUT_EN)},
544 {"J1_OMAP3430_GPIO_61", 0x00C8, (OMAP34XX_MUX_MODE4 |
545 OMAP3_INPUT_EN | OMAP34XX_PIN_INPUT_PULLUP)},
546 /*
547 * don't remove, used for sanity check.
548 */
549 {"END_OF_TABLE"}
550 };
551
552
553 #endif /* _INCLUDED_CYASMEMMAP_H_ */
554
555 /*[]*/