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1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 *
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/ptrace.h>
29 #include <linux/errno.h>
30 #include <linux/ioport.h>
31 #include <linux/slab.h>
32 #include <linux/interrupt.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/in.h>
38 #include <linux/ip.h>
39 #include <net/ip.h>
40 #include <net/tso.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/icmp.h>
44 #include <linux/spinlock.h>
45 #include <linux/workqueue.h>
46 #include <linux/bitops.h>
47 #include <linux/io.h>
48 #include <linux/irq.h>
49 #include <linux/clk.h>
50 #include <linux/platform_device.h>
51 #include <linux/mdio.h>
52 #include <linux/phy.h>
53 #include <linux/fec.h>
54 #include <linux/of.h>
55 #include <linux/of_device.h>
56 #include <linux/of_gpio.h>
57 #include <linux/of_mdio.h>
58 #include <linux/of_net.h>
59 #include <linux/regulator/consumer.h>
60 #include <linux/if_vlan.h>
61 #include <linux/pinctrl/consumer.h>
62 #include <linux/prefetch.h>
63
64 #include <asm/cacheflush.h>
65
66 #include "fec.h"
67
68 static void set_multicast_list(struct net_device *ndev);
69 static void fec_enet_itr_coal_init(struct net_device *ndev);
70
71 #define DRIVER_NAME "fec"
72
73 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
74
75 /* Pause frame feild and FIFO threshold */
76 #define FEC_ENET_FCE (1 << 5)
77 #define FEC_ENET_RSEM_V 0x84
78 #define FEC_ENET_RSFL_V 16
79 #define FEC_ENET_RAEM_V 0x8
80 #define FEC_ENET_RAFL_V 0x8
81 #define FEC_ENET_OPD_V 0xFFF0
82 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */
83
84 static struct platform_device_id fec_devtype[] = {
85 {
86 /* keep it for coldfire */
87 .name = DRIVER_NAME,
88 .driver_data = 0,
89 }, {
90 .name = "imx25-fec",
91 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_HAS_RACC,
92 }, {
93 .name = "imx27-fec",
94 .driver_data = FEC_QUIRK_HAS_RACC,
95 }, {
96 .name = "imx28-fec",
97 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
98 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC,
99 }, {
100 .name = "imx6q-fec",
101 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
102 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
103 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
104 FEC_QUIRK_HAS_RACC,
105 }, {
106 .name = "mvf600-fec",
107 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
108 }, {
109 .name = "imx6sx-fec",
110 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
111 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
112 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
113 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
114 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE,
115 }, {
116 .name = "imx6ul-fec",
117 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
118 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
119 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_BUG_CAPTURE |
120 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE,
121 }, {
122 /* sentinel */
123 }
124 };
125 MODULE_DEVICE_TABLE(platform, fec_devtype);
126
127 enum imx_fec_type {
128 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
129 IMX27_FEC, /* runs on i.mx27/35/51 */
130 IMX28_FEC,
131 IMX6Q_FEC,
132 MVF600_FEC,
133 IMX6SX_FEC,
134 IMX6UL_FEC,
135 };
136
137 static const struct of_device_id fec_dt_ids[] = {
138 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
139 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
140 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
141 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
142 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
143 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
144 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
145 { /* sentinel */ }
146 };
147 MODULE_DEVICE_TABLE(of, fec_dt_ids);
148
149 static unsigned char macaddr[ETH_ALEN];
150 module_param_array(macaddr, byte, NULL, 0);
151 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
152
153 #if defined(CONFIG_M5272)
154 /*
155 * Some hardware gets it MAC address out of local flash memory.
156 * if this is non-zero then assume it is the address to get MAC from.
157 */
158 #if defined(CONFIG_NETtel)
159 #define FEC_FLASHMAC 0xf0006006
160 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
161 #define FEC_FLASHMAC 0xf0006000
162 #elif defined(CONFIG_CANCam)
163 #define FEC_FLASHMAC 0xf0020000
164 #elif defined (CONFIG_M5272C3)
165 #define FEC_FLASHMAC (0xffe04000 + 4)
166 #elif defined(CONFIG_MOD5272)
167 #define FEC_FLASHMAC 0xffc0406b
168 #else
169 #define FEC_FLASHMAC 0
170 #endif
171 #endif /* CONFIG_M5272 */
172
173 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
174 */
175 #define PKT_MAXBUF_SIZE 1522
176 #define PKT_MINBUF_SIZE 64
177 #define PKT_MAXBLR_SIZE 1536
178
179 /* FEC receive acceleration */
180 #define FEC_RACC_IPDIS (1 << 1)
181 #define FEC_RACC_PRODIS (1 << 2)
182 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
183
184 /*
185 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
186 * size bits. Other FEC hardware does not, so we need to take that into
187 * account when setting it.
188 */
189 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
190 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
191 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
192 #else
193 #define OPT_FRAME_SIZE 0
194 #endif
195
196 /* FEC MII MMFR bits definition */
197 #define FEC_MMFR_ST (1 << 30)
198 #define FEC_MMFR_OP_READ (2 << 28)
199 #define FEC_MMFR_OP_WRITE (1 << 28)
200 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
201 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
202 #define FEC_MMFR_TA (2 << 16)
203 #define FEC_MMFR_DATA(v) (v & 0xffff)
204 /* FEC ECR bits definition */
205 #define FEC_ECR_MAGICEN (1 << 2)
206 #define FEC_ECR_SLEEP (1 << 3)
207
208 #define FEC_MII_TIMEOUT 30000 /* us */
209
210 /* Transmitter timeout */
211 #define TX_TIMEOUT (2 * HZ)
212
213 #define FEC_PAUSE_FLAG_AUTONEG 0x1
214 #define FEC_PAUSE_FLAG_ENABLE 0x2
215 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
216 #define FEC_WOL_FLAG_ENABLE (0x1 << 1)
217 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
218
219 #define COPYBREAK_DEFAULT 256
220
221 #define TSO_HEADER_SIZE 128
222 /* Max number of allowed TCP segments for software TSO */
223 #define FEC_MAX_TSO_SEGS 100
224 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
225
226 #define IS_TSO_HEADER(txq, addr) \
227 ((addr >= txq->tso_hdrs_dma) && \
228 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
229
230 static int mii_cnt;
231
232 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
233 struct bufdesc_prop *bd)
234 {
235 return (bdp >= bd->last) ? bd->base
236 : (struct bufdesc *)(((unsigned)bdp) + bd->dsize);
237 }
238
239 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
240 struct bufdesc_prop *bd)
241 {
242 return (bdp <= bd->base) ? bd->last
243 : (struct bufdesc *)(((unsigned)bdp) - bd->dsize);
244 }
245
246 static int fec_enet_get_bd_index(struct bufdesc *bdp,
247 struct bufdesc_prop *bd)
248 {
249 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
250 }
251
252 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
253 {
254 int entries;
255
256 entries = (((const char *)txq->dirty_tx -
257 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
258
259 return entries >= 0 ? entries : entries + txq->bd.ring_size;
260 }
261
262 static void swap_buffer(void *bufaddr, int len)
263 {
264 int i;
265 unsigned int *buf = bufaddr;
266
267 for (i = 0; i < len; i += 4, buf++)
268 swab32s(buf);
269 }
270
271 static void swap_buffer2(void *dst_buf, void *src_buf, int len)
272 {
273 int i;
274 unsigned int *src = src_buf;
275 unsigned int *dst = dst_buf;
276
277 for (i = 0; i < len; i += 4, src++, dst++)
278 *dst = swab32p(src);
279 }
280
281 static void fec_dump(struct net_device *ndev)
282 {
283 struct fec_enet_private *fep = netdev_priv(ndev);
284 struct bufdesc *bdp;
285 struct fec_enet_priv_tx_q *txq;
286 int index = 0;
287
288 netdev_info(ndev, "TX ring dump\n");
289 pr_info("Nr SC addr len SKB\n");
290
291 txq = fep->tx_queue[0];
292 bdp = txq->bd.base;
293
294 do {
295 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
296 index,
297 bdp == txq->bd.cur ? 'S' : ' ',
298 bdp == txq->dirty_tx ? 'H' : ' ',
299 fec16_to_cpu(bdp->cbd_sc),
300 fec32_to_cpu(bdp->cbd_bufaddr),
301 fec16_to_cpu(bdp->cbd_datlen),
302 txq->tx_skbuff[index]);
303 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
304 index++;
305 } while (bdp != txq->bd.base);
306 }
307
308 static inline bool is_ipv4_pkt(struct sk_buff *skb)
309 {
310 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
311 }
312
313 static int
314 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
315 {
316 /* Only run for packets requiring a checksum. */
317 if (skb->ip_summed != CHECKSUM_PARTIAL)
318 return 0;
319
320 if (unlikely(skb_cow_head(skb, 0)))
321 return -1;
322
323 if (is_ipv4_pkt(skb))
324 ip_hdr(skb)->check = 0;
325 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
326
327 return 0;
328 }
329
330 static struct bufdesc *
331 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
332 struct sk_buff *skb,
333 struct net_device *ndev)
334 {
335 struct fec_enet_private *fep = netdev_priv(ndev);
336 struct bufdesc *bdp = txq->bd.cur;
337 struct bufdesc_ex *ebdp;
338 int nr_frags = skb_shinfo(skb)->nr_frags;
339 int frag, frag_len;
340 unsigned short status;
341 unsigned int estatus = 0;
342 skb_frag_t *this_frag;
343 unsigned int index;
344 void *bufaddr;
345 dma_addr_t addr;
346 int i;
347
348 for (frag = 0; frag < nr_frags; frag++) {
349 this_frag = &skb_shinfo(skb)->frags[frag];
350 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
351 ebdp = (struct bufdesc_ex *)bdp;
352
353 status = fec16_to_cpu(bdp->cbd_sc);
354 status &= ~BD_ENET_TX_STATS;
355 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
356 frag_len = skb_shinfo(skb)->frags[frag].size;
357
358 /* Handle the last BD specially */
359 if (frag == nr_frags - 1) {
360 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
361 if (fep->bufdesc_ex) {
362 estatus |= BD_ENET_TX_INT;
363 if (unlikely(skb_shinfo(skb)->tx_flags &
364 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
365 estatus |= BD_ENET_TX_TS;
366 }
367 }
368
369 if (fep->bufdesc_ex) {
370 if (fep->quirks & FEC_QUIRK_HAS_AVB)
371 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
372 if (skb->ip_summed == CHECKSUM_PARTIAL)
373 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
374 ebdp->cbd_bdu = 0;
375 ebdp->cbd_esc = cpu_to_fec32(estatus);
376 }
377
378 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
379
380 index = fec_enet_get_bd_index(bdp, &txq->bd);
381 if (((unsigned long) bufaddr) & fep->tx_align ||
382 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
383 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
384 bufaddr = txq->tx_bounce[index];
385
386 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
387 swap_buffer(bufaddr, frag_len);
388 }
389
390 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
391 DMA_TO_DEVICE);
392 if (dma_mapping_error(&fep->pdev->dev, addr)) {
393 if (net_ratelimit())
394 netdev_err(ndev, "Tx DMA memory map failed\n");
395 goto dma_mapping_error;
396 }
397
398 bdp->cbd_bufaddr = cpu_to_fec32(addr);
399 bdp->cbd_datlen = cpu_to_fec16(frag_len);
400 /* Make sure the updates to rest of the descriptor are
401 * performed before transferring ownership.
402 */
403 wmb();
404 bdp->cbd_sc = cpu_to_fec16(status);
405 }
406
407 return bdp;
408 dma_mapping_error:
409 bdp = txq->bd.cur;
410 for (i = 0; i < frag; i++) {
411 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
412 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
413 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
414 }
415 return ERR_PTR(-ENOMEM);
416 }
417
418 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
419 struct sk_buff *skb, struct net_device *ndev)
420 {
421 struct fec_enet_private *fep = netdev_priv(ndev);
422 int nr_frags = skb_shinfo(skb)->nr_frags;
423 struct bufdesc *bdp, *last_bdp;
424 void *bufaddr;
425 dma_addr_t addr;
426 unsigned short status;
427 unsigned short buflen;
428 unsigned int estatus = 0;
429 unsigned int index;
430 int entries_free;
431
432 entries_free = fec_enet_get_free_txdesc_num(txq);
433 if (entries_free < MAX_SKB_FRAGS + 1) {
434 dev_kfree_skb_any(skb);
435 if (net_ratelimit())
436 netdev_err(ndev, "NOT enough BD for SG!\n");
437 return NETDEV_TX_OK;
438 }
439
440 /* Protocol checksum off-load for TCP and UDP. */
441 if (fec_enet_clear_csum(skb, ndev)) {
442 dev_kfree_skb_any(skb);
443 return NETDEV_TX_OK;
444 }
445
446 /* Fill in a Tx ring entry */
447 bdp = txq->bd.cur;
448 last_bdp = bdp;
449 status = fec16_to_cpu(bdp->cbd_sc);
450 status &= ~BD_ENET_TX_STATS;
451
452 /* Set buffer length and buffer pointer */
453 bufaddr = skb->data;
454 buflen = skb_headlen(skb);
455
456 index = fec_enet_get_bd_index(bdp, &txq->bd);
457 if (((unsigned long) bufaddr) & fep->tx_align ||
458 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
459 memcpy(txq->tx_bounce[index], skb->data, buflen);
460 bufaddr = txq->tx_bounce[index];
461
462 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
463 swap_buffer(bufaddr, buflen);
464 }
465
466 /* Push the data cache so the CPM does not get stale memory data. */
467 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
468 if (dma_mapping_error(&fep->pdev->dev, addr)) {
469 dev_kfree_skb_any(skb);
470 if (net_ratelimit())
471 netdev_err(ndev, "Tx DMA memory map failed\n");
472 return NETDEV_TX_OK;
473 }
474
475 if (nr_frags) {
476 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
477 if (IS_ERR(last_bdp)) {
478 dma_unmap_single(&fep->pdev->dev, addr,
479 buflen, DMA_TO_DEVICE);
480 dev_kfree_skb_any(skb);
481 return NETDEV_TX_OK;
482 }
483 } else {
484 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
485 if (fep->bufdesc_ex) {
486 estatus = BD_ENET_TX_INT;
487 if (unlikely(skb_shinfo(skb)->tx_flags &
488 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
489 estatus |= BD_ENET_TX_TS;
490 }
491 }
492 bdp->cbd_bufaddr = cpu_to_fec32(addr);
493 bdp->cbd_datlen = cpu_to_fec16(buflen);
494
495 if (fep->bufdesc_ex) {
496
497 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
498
499 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
500 fep->hwts_tx_en))
501 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
502
503 if (fep->quirks & FEC_QUIRK_HAS_AVB)
504 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
505
506 if (skb->ip_summed == CHECKSUM_PARTIAL)
507 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
508
509 ebdp->cbd_bdu = 0;
510 ebdp->cbd_esc = cpu_to_fec32(estatus);
511 }
512
513 index = fec_enet_get_bd_index(last_bdp, &txq->bd);
514 /* Save skb pointer */
515 txq->tx_skbuff[index] = skb;
516
517 /* Make sure the updates to rest of the descriptor are performed before
518 * transferring ownership.
519 */
520 wmb();
521
522 /* Send it on its way. Tell FEC it's ready, interrupt when done,
523 * it's the last BD of the frame, and to put the CRC on the end.
524 */
525 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
526 bdp->cbd_sc = cpu_to_fec16(status);
527
528 /* If this was the last BD in the ring, start at the beginning again. */
529 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
530
531 skb_tx_timestamp(skb);
532
533 /* Make sure the update to bdp and tx_skbuff are performed before
534 * txq->bd.cur.
535 */
536 wmb();
537 txq->bd.cur = bdp;
538
539 /* Trigger transmission start */
540 writel(0, txq->bd.reg_desc_active);
541
542 return 0;
543 }
544
545 static int
546 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
547 struct net_device *ndev,
548 struct bufdesc *bdp, int index, char *data,
549 int size, bool last_tcp, bool is_last)
550 {
551 struct fec_enet_private *fep = netdev_priv(ndev);
552 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
553 unsigned short status;
554 unsigned int estatus = 0;
555 dma_addr_t addr;
556
557 status = fec16_to_cpu(bdp->cbd_sc);
558 status &= ~BD_ENET_TX_STATS;
559
560 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
561
562 if (((unsigned long) data) & fep->tx_align ||
563 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
564 memcpy(txq->tx_bounce[index], data, size);
565 data = txq->tx_bounce[index];
566
567 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
568 swap_buffer(data, size);
569 }
570
571 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
572 if (dma_mapping_error(&fep->pdev->dev, addr)) {
573 dev_kfree_skb_any(skb);
574 if (net_ratelimit())
575 netdev_err(ndev, "Tx DMA memory map failed\n");
576 return NETDEV_TX_BUSY;
577 }
578
579 bdp->cbd_datlen = cpu_to_fec16(size);
580 bdp->cbd_bufaddr = cpu_to_fec32(addr);
581
582 if (fep->bufdesc_ex) {
583 if (fep->quirks & FEC_QUIRK_HAS_AVB)
584 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
585 if (skb->ip_summed == CHECKSUM_PARTIAL)
586 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
587 ebdp->cbd_bdu = 0;
588 ebdp->cbd_esc = cpu_to_fec32(estatus);
589 }
590
591 /* Handle the last BD specially */
592 if (last_tcp)
593 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
594 if (is_last) {
595 status |= BD_ENET_TX_INTR;
596 if (fep->bufdesc_ex)
597 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
598 }
599
600 bdp->cbd_sc = cpu_to_fec16(status);
601
602 return 0;
603 }
604
605 static int
606 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
607 struct sk_buff *skb, struct net_device *ndev,
608 struct bufdesc *bdp, int index)
609 {
610 struct fec_enet_private *fep = netdev_priv(ndev);
611 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
612 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
613 void *bufaddr;
614 unsigned long dmabuf;
615 unsigned short status;
616 unsigned int estatus = 0;
617
618 status = fec16_to_cpu(bdp->cbd_sc);
619 status &= ~BD_ENET_TX_STATS;
620 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
621
622 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
623 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
624 if (((unsigned long)bufaddr) & fep->tx_align ||
625 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
626 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
627 bufaddr = txq->tx_bounce[index];
628
629 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
630 swap_buffer(bufaddr, hdr_len);
631
632 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
633 hdr_len, DMA_TO_DEVICE);
634 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
635 dev_kfree_skb_any(skb);
636 if (net_ratelimit())
637 netdev_err(ndev, "Tx DMA memory map failed\n");
638 return NETDEV_TX_BUSY;
639 }
640 }
641
642 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
643 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
644
645 if (fep->bufdesc_ex) {
646 if (fep->quirks & FEC_QUIRK_HAS_AVB)
647 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
648 if (skb->ip_summed == CHECKSUM_PARTIAL)
649 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
650 ebdp->cbd_bdu = 0;
651 ebdp->cbd_esc = cpu_to_fec32(estatus);
652 }
653
654 bdp->cbd_sc = cpu_to_fec16(status);
655
656 return 0;
657 }
658
659 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
660 struct sk_buff *skb,
661 struct net_device *ndev)
662 {
663 struct fec_enet_private *fep = netdev_priv(ndev);
664 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
665 int total_len, data_left;
666 struct bufdesc *bdp = txq->bd.cur;
667 struct tso_t tso;
668 unsigned int index = 0;
669 int ret;
670
671 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
672 dev_kfree_skb_any(skb);
673 if (net_ratelimit())
674 netdev_err(ndev, "NOT enough BD for TSO!\n");
675 return NETDEV_TX_OK;
676 }
677
678 /* Protocol checksum off-load for TCP and UDP. */
679 if (fec_enet_clear_csum(skb, ndev)) {
680 dev_kfree_skb_any(skb);
681 return NETDEV_TX_OK;
682 }
683
684 /* Initialize the TSO handler, and prepare the first payload */
685 tso_start(skb, &tso);
686
687 total_len = skb->len - hdr_len;
688 while (total_len > 0) {
689 char *hdr;
690
691 index = fec_enet_get_bd_index(bdp, &txq->bd);
692 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
693 total_len -= data_left;
694
695 /* prepare packet headers: MAC + IP + TCP */
696 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
697 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
698 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
699 if (ret)
700 goto err_release;
701
702 while (data_left > 0) {
703 int size;
704
705 size = min_t(int, tso.size, data_left);
706 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
707 index = fec_enet_get_bd_index(bdp, &txq->bd);
708 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
709 bdp, index,
710 tso.data, size,
711 size == data_left,
712 total_len == 0);
713 if (ret)
714 goto err_release;
715
716 data_left -= size;
717 tso_build_data(skb, &tso, size);
718 }
719
720 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
721 }
722
723 /* Save skb pointer */
724 txq->tx_skbuff[index] = skb;
725
726 skb_tx_timestamp(skb);
727 txq->bd.cur = bdp;
728
729 /* Trigger transmission start */
730 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
731 !readl(txq->bd.reg_desc_active) ||
732 !readl(txq->bd.reg_desc_active) ||
733 !readl(txq->bd.reg_desc_active) ||
734 !readl(txq->bd.reg_desc_active))
735 writel(0, txq->bd.reg_desc_active);
736
737 return 0;
738
739 err_release:
740 /* TODO: Release all used data descriptors for TSO */
741 return ret;
742 }
743
744 static netdev_tx_t
745 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
746 {
747 struct fec_enet_private *fep = netdev_priv(ndev);
748 int entries_free;
749 unsigned short queue;
750 struct fec_enet_priv_tx_q *txq;
751 struct netdev_queue *nq;
752 int ret;
753
754 queue = skb_get_queue_mapping(skb);
755 txq = fep->tx_queue[queue];
756 nq = netdev_get_tx_queue(ndev, queue);
757
758 if (skb_is_gso(skb))
759 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
760 else
761 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
762 if (ret)
763 return ret;
764
765 entries_free = fec_enet_get_free_txdesc_num(txq);
766 if (entries_free <= txq->tx_stop_threshold)
767 netif_tx_stop_queue(nq);
768
769 return NETDEV_TX_OK;
770 }
771
772 /* Init RX & TX buffer descriptors
773 */
774 static void fec_enet_bd_init(struct net_device *dev)
775 {
776 struct fec_enet_private *fep = netdev_priv(dev);
777 struct fec_enet_priv_tx_q *txq;
778 struct fec_enet_priv_rx_q *rxq;
779 struct bufdesc *bdp;
780 unsigned int i;
781 unsigned int q;
782
783 for (q = 0; q < fep->num_rx_queues; q++) {
784 /* Initialize the receive buffer descriptors. */
785 rxq = fep->rx_queue[q];
786 bdp = rxq->bd.base;
787
788 for (i = 0; i < rxq->bd.ring_size; i++) {
789
790 /* Initialize the BD for every fragment in the page. */
791 if (bdp->cbd_bufaddr)
792 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
793 else
794 bdp->cbd_sc = cpu_to_fec16(0);
795 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
796 }
797
798 /* Set the last buffer to wrap */
799 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
800 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
801
802 rxq->bd.cur = rxq->bd.base;
803 }
804
805 for (q = 0; q < fep->num_tx_queues; q++) {
806 /* ...and the same for transmit */
807 txq = fep->tx_queue[q];
808 bdp = txq->bd.base;
809 txq->bd.cur = bdp;
810
811 for (i = 0; i < txq->bd.ring_size; i++) {
812 /* Initialize the BD for every fragment in the page. */
813 bdp->cbd_sc = cpu_to_fec16(0);
814 if (txq->tx_skbuff[i]) {
815 dev_kfree_skb_any(txq->tx_skbuff[i]);
816 txq->tx_skbuff[i] = NULL;
817 }
818 bdp->cbd_bufaddr = cpu_to_fec32(0);
819 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
820 }
821
822 /* Set the last buffer to wrap */
823 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
824 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
825 txq->dirty_tx = bdp;
826 }
827 }
828
829 static void fec_enet_active_rxring(struct net_device *ndev)
830 {
831 struct fec_enet_private *fep = netdev_priv(ndev);
832 int i;
833
834 for (i = 0; i < fep->num_rx_queues; i++)
835 writel(0, fep->rx_queue[i]->bd.reg_desc_active);
836 }
837
838 static void fec_enet_enable_ring(struct net_device *ndev)
839 {
840 struct fec_enet_private *fep = netdev_priv(ndev);
841 struct fec_enet_priv_tx_q *txq;
842 struct fec_enet_priv_rx_q *rxq;
843 int i;
844
845 for (i = 0; i < fep->num_rx_queues; i++) {
846 rxq = fep->rx_queue[i];
847 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
848 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
849
850 /* enable DMA1/2 */
851 if (i)
852 writel(RCMR_MATCHEN | RCMR_CMP(i),
853 fep->hwp + FEC_RCMR(i));
854 }
855
856 for (i = 0; i < fep->num_tx_queues; i++) {
857 txq = fep->tx_queue[i];
858 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
859
860 /* enable DMA1/2 */
861 if (i)
862 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
863 fep->hwp + FEC_DMA_CFG(i));
864 }
865 }
866
867 static void fec_enet_reset_skb(struct net_device *ndev)
868 {
869 struct fec_enet_private *fep = netdev_priv(ndev);
870 struct fec_enet_priv_tx_q *txq;
871 int i, j;
872
873 for (i = 0; i < fep->num_tx_queues; i++) {
874 txq = fep->tx_queue[i];
875
876 for (j = 0; j < txq->bd.ring_size; j++) {
877 if (txq->tx_skbuff[j]) {
878 dev_kfree_skb_any(txq->tx_skbuff[j]);
879 txq->tx_skbuff[j] = NULL;
880 }
881 }
882 }
883 }
884
885 /*
886 * This function is called to start or restart the FEC during a link
887 * change, transmit timeout, or to reconfigure the FEC. The network
888 * packet processing for this device must be stopped before this call.
889 */
890 static void
891 fec_restart(struct net_device *ndev)
892 {
893 struct fec_enet_private *fep = netdev_priv(ndev);
894 u32 val;
895 u32 temp_mac[2];
896 u32 rcntl = OPT_FRAME_SIZE | 0x04;
897 u32 ecntl = 0x2; /* ETHEREN */
898
899 /* Whack a reset. We should wait for this.
900 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
901 * instead of reset MAC itself.
902 */
903 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
904 writel(0, fep->hwp + FEC_ECNTRL);
905 } else {
906 writel(1, fep->hwp + FEC_ECNTRL);
907 udelay(10);
908 }
909
910 /*
911 * enet-mac reset will reset mac address registers too,
912 * so need to reconfigure it.
913 */
914 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
915 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
916 writel((__force u32)cpu_to_be32(temp_mac[0]),
917 fep->hwp + FEC_ADDR_LOW);
918 writel((__force u32)cpu_to_be32(temp_mac[1]),
919 fep->hwp + FEC_ADDR_HIGH);
920 }
921
922 /* Clear any outstanding interrupt. */
923 writel(0xffffffff, fep->hwp + FEC_IEVENT);
924
925 fec_enet_bd_init(ndev);
926
927 fec_enet_enable_ring(ndev);
928
929 /* Reset tx SKB buffers. */
930 fec_enet_reset_skb(ndev);
931
932 /* Enable MII mode */
933 if (fep->full_duplex == DUPLEX_FULL) {
934 /* FD enable */
935 writel(0x04, fep->hwp + FEC_X_CNTRL);
936 } else {
937 /* No Rcv on Xmit */
938 rcntl |= 0x02;
939 writel(0x0, fep->hwp + FEC_X_CNTRL);
940 }
941
942 /* Set MII speed */
943 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
944
945 #if !defined(CONFIG_M5272)
946 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
947 /* set RX checksum */
948 val = readl(fep->hwp + FEC_RACC);
949 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
950 val |= FEC_RACC_OPTIONS;
951 else
952 val &= ~FEC_RACC_OPTIONS;
953 writel(val, fep->hwp + FEC_RACC);
954 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
955 }
956 #endif
957
958 /*
959 * The phy interface and speed need to get configured
960 * differently on enet-mac.
961 */
962 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
963 /* Enable flow control and length check */
964 rcntl |= 0x40000000 | 0x00000020;
965
966 /* RGMII, RMII or MII */
967 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
968 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
969 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
970 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
971 rcntl |= (1 << 6);
972 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
973 rcntl |= (1 << 8);
974 else
975 rcntl &= ~(1 << 8);
976
977 /* 1G, 100M or 10M */
978 if (ndev->phydev) {
979 if (ndev->phydev->speed == SPEED_1000)
980 ecntl |= (1 << 5);
981 else if (ndev->phydev->speed == SPEED_100)
982 rcntl &= ~(1 << 9);
983 else
984 rcntl |= (1 << 9);
985 }
986 } else {
987 #ifdef FEC_MIIGSK_ENR
988 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
989 u32 cfgr;
990 /* disable the gasket and wait */
991 writel(0, fep->hwp + FEC_MIIGSK_ENR);
992 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
993 udelay(1);
994
995 /*
996 * configure the gasket:
997 * RMII, 50 MHz, no loopback, no echo
998 * MII, 25 MHz, no loopback, no echo
999 */
1000 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1001 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1002 if (ndev->phydev && ndev->phydev->speed == SPEED_10)
1003 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1004 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1005
1006 /* re-enable the gasket */
1007 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1008 }
1009 #endif
1010 }
1011
1012 #if !defined(CONFIG_M5272)
1013 /* enable pause frame*/
1014 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1015 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1016 ndev->phydev && ndev->phydev->pause)) {
1017 rcntl |= FEC_ENET_FCE;
1018
1019 /* set FIFO threshold parameter to reduce overrun */
1020 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1021 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1022 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1023 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1024
1025 /* OPD */
1026 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1027 } else {
1028 rcntl &= ~FEC_ENET_FCE;
1029 }
1030 #endif /* !defined(CONFIG_M5272) */
1031
1032 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1033
1034 /* Setup multicast filter. */
1035 set_multicast_list(ndev);
1036 #ifndef CONFIG_M5272
1037 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1038 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1039 #endif
1040
1041 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1042 /* enable ENET endian swap */
1043 ecntl |= (1 << 8);
1044 /* enable ENET store and forward mode */
1045 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1046 }
1047
1048 if (fep->bufdesc_ex)
1049 ecntl |= (1 << 4);
1050
1051 #ifndef CONFIG_M5272
1052 /* Enable the MIB statistic event counters */
1053 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1054 #endif
1055
1056 /* And last, enable the transmit and receive processing */
1057 writel(ecntl, fep->hwp + FEC_ECNTRL);
1058 fec_enet_active_rxring(ndev);
1059
1060 if (fep->bufdesc_ex)
1061 fec_ptp_start_cyclecounter(ndev);
1062
1063 /* Enable interrupts we wish to service */
1064 if (fep->link)
1065 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1066 else
1067 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1068
1069 /* Init the interrupt coalescing */
1070 fec_enet_itr_coal_init(ndev);
1071
1072 }
1073
1074 static void
1075 fec_stop(struct net_device *ndev)
1076 {
1077 struct fec_enet_private *fep = netdev_priv(ndev);
1078 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1079 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1080 u32 val;
1081
1082 /* We cannot expect a graceful transmit stop without link !!! */
1083 if (fep->link) {
1084 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1085 udelay(10);
1086 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1087 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1088 }
1089
1090 /* Whack a reset. We should wait for this.
1091 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1092 * instead of reset MAC itself.
1093 */
1094 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1095 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1096 writel(0, fep->hwp + FEC_ECNTRL);
1097 } else {
1098 writel(1, fep->hwp + FEC_ECNTRL);
1099 udelay(10);
1100 }
1101 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1102 } else {
1103 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1104 val = readl(fep->hwp + FEC_ECNTRL);
1105 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1106 writel(val, fep->hwp + FEC_ECNTRL);
1107
1108 if (pdata && pdata->sleep_mode_enable)
1109 pdata->sleep_mode_enable(true);
1110 }
1111 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1112
1113 /* We have to keep ENET enabled to have MII interrupt stay working */
1114 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1115 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1116 writel(2, fep->hwp + FEC_ECNTRL);
1117 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1118 }
1119 }
1120
1121
1122 static void
1123 fec_timeout(struct net_device *ndev)
1124 {
1125 struct fec_enet_private *fep = netdev_priv(ndev);
1126
1127 fec_dump(ndev);
1128
1129 ndev->stats.tx_errors++;
1130
1131 schedule_work(&fep->tx_timeout_work);
1132 }
1133
1134 static void fec_enet_timeout_work(struct work_struct *work)
1135 {
1136 struct fec_enet_private *fep =
1137 container_of(work, struct fec_enet_private, tx_timeout_work);
1138 struct net_device *ndev = fep->netdev;
1139
1140 rtnl_lock();
1141 if (netif_device_present(ndev) || netif_running(ndev)) {
1142 napi_disable(&fep->napi);
1143 netif_tx_lock_bh(ndev);
1144 fec_restart(ndev);
1145 netif_wake_queue(ndev);
1146 netif_tx_unlock_bh(ndev);
1147 napi_enable(&fep->napi);
1148 }
1149 rtnl_unlock();
1150 }
1151
1152 static void
1153 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1154 struct skb_shared_hwtstamps *hwtstamps)
1155 {
1156 unsigned long flags;
1157 u64 ns;
1158
1159 spin_lock_irqsave(&fep->tmreg_lock, flags);
1160 ns = timecounter_cyc2time(&fep->tc, ts);
1161 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1162
1163 memset(hwtstamps, 0, sizeof(*hwtstamps));
1164 hwtstamps->hwtstamp = ns_to_ktime(ns);
1165 }
1166
1167 static void
1168 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1169 {
1170 struct fec_enet_private *fep;
1171 struct bufdesc *bdp;
1172 unsigned short status;
1173 struct sk_buff *skb;
1174 struct fec_enet_priv_tx_q *txq;
1175 struct netdev_queue *nq;
1176 int index = 0;
1177 int entries_free;
1178
1179 fep = netdev_priv(ndev);
1180
1181 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1182
1183 txq = fep->tx_queue[queue_id];
1184 /* get next bdp of dirty_tx */
1185 nq = netdev_get_tx_queue(ndev, queue_id);
1186 bdp = txq->dirty_tx;
1187
1188 /* get next bdp of dirty_tx */
1189 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1190
1191 while (bdp != READ_ONCE(txq->bd.cur)) {
1192 /* Order the load of bd.cur and cbd_sc */
1193 rmb();
1194 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1195 if (status & BD_ENET_TX_READY)
1196 break;
1197
1198 index = fec_enet_get_bd_index(bdp, &txq->bd);
1199
1200 skb = txq->tx_skbuff[index];
1201 txq->tx_skbuff[index] = NULL;
1202 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1203 dma_unmap_single(&fep->pdev->dev,
1204 fec32_to_cpu(bdp->cbd_bufaddr),
1205 fec16_to_cpu(bdp->cbd_datlen),
1206 DMA_TO_DEVICE);
1207 bdp->cbd_bufaddr = cpu_to_fec32(0);
1208 if (!skb)
1209 goto skb_done;
1210
1211 /* Check for errors. */
1212 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1213 BD_ENET_TX_RL | BD_ENET_TX_UN |
1214 BD_ENET_TX_CSL)) {
1215 ndev->stats.tx_errors++;
1216 if (status & BD_ENET_TX_HB) /* No heartbeat */
1217 ndev->stats.tx_heartbeat_errors++;
1218 if (status & BD_ENET_TX_LC) /* Late collision */
1219 ndev->stats.tx_window_errors++;
1220 if (status & BD_ENET_TX_RL) /* Retrans limit */
1221 ndev->stats.tx_aborted_errors++;
1222 if (status & BD_ENET_TX_UN) /* Underrun */
1223 ndev->stats.tx_fifo_errors++;
1224 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1225 ndev->stats.tx_carrier_errors++;
1226 } else {
1227 ndev->stats.tx_packets++;
1228 ndev->stats.tx_bytes += skb->len;
1229 }
1230
1231 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1232 fep->bufdesc_ex) {
1233 struct skb_shared_hwtstamps shhwtstamps;
1234 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1235
1236 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1237 skb_tstamp_tx(skb, &shhwtstamps);
1238 }
1239
1240 /* Deferred means some collisions occurred during transmit,
1241 * but we eventually sent the packet OK.
1242 */
1243 if (status & BD_ENET_TX_DEF)
1244 ndev->stats.collisions++;
1245
1246 /* Free the sk buffer associated with this last transmit */
1247 dev_kfree_skb_any(skb);
1248 skb_done:
1249 /* Make sure the update to bdp and tx_skbuff are performed
1250 * before dirty_tx
1251 */
1252 wmb();
1253 txq->dirty_tx = bdp;
1254
1255 /* Update pointer to next buffer descriptor to be transmitted */
1256 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1257
1258 /* Since we have freed up a buffer, the ring is no longer full
1259 */
1260 if (netif_queue_stopped(ndev)) {
1261 entries_free = fec_enet_get_free_txdesc_num(txq);
1262 if (entries_free >= txq->tx_wake_threshold)
1263 netif_tx_wake_queue(nq);
1264 }
1265 }
1266
1267 /* ERR006538: Keep the transmitter going */
1268 if (bdp != txq->bd.cur &&
1269 readl(txq->bd.reg_desc_active) == 0)
1270 writel(0, txq->bd.reg_desc_active);
1271 }
1272
1273 static void
1274 fec_enet_tx(struct net_device *ndev)
1275 {
1276 struct fec_enet_private *fep = netdev_priv(ndev);
1277 u16 queue_id;
1278 /* First process class A queue, then Class B and Best Effort queue */
1279 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1280 clear_bit(queue_id, &fep->work_tx);
1281 fec_enet_tx_queue(ndev, queue_id);
1282 }
1283 return;
1284 }
1285
1286 static int
1287 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1288 {
1289 struct fec_enet_private *fep = netdev_priv(ndev);
1290 int off;
1291
1292 off = ((unsigned long)skb->data) & fep->rx_align;
1293 if (off)
1294 skb_reserve(skb, fep->rx_align + 1 - off);
1295
1296 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1297 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1298 if (net_ratelimit())
1299 netdev_err(ndev, "Rx DMA memory map failed\n");
1300 return -ENOMEM;
1301 }
1302
1303 return 0;
1304 }
1305
1306 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1307 struct bufdesc *bdp, u32 length, bool swap)
1308 {
1309 struct fec_enet_private *fep = netdev_priv(ndev);
1310 struct sk_buff *new_skb;
1311
1312 if (length > fep->rx_copybreak)
1313 return false;
1314
1315 new_skb = netdev_alloc_skb(ndev, length);
1316 if (!new_skb)
1317 return false;
1318
1319 dma_sync_single_for_cpu(&fep->pdev->dev,
1320 fec32_to_cpu(bdp->cbd_bufaddr),
1321 FEC_ENET_RX_FRSIZE - fep->rx_align,
1322 DMA_FROM_DEVICE);
1323 if (!swap)
1324 memcpy(new_skb->data, (*skb)->data, length);
1325 else
1326 swap_buffer2(new_skb->data, (*skb)->data, length);
1327 *skb = new_skb;
1328
1329 return true;
1330 }
1331
1332 /* During a receive, the bd_rx.cur points to the current incoming buffer.
1333 * When we update through the ring, if the next incoming buffer has
1334 * not been given to the system, we just set the empty indicator,
1335 * effectively tossing the packet.
1336 */
1337 static int
1338 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1339 {
1340 struct fec_enet_private *fep = netdev_priv(ndev);
1341 struct fec_enet_priv_rx_q *rxq;
1342 struct bufdesc *bdp;
1343 unsigned short status;
1344 struct sk_buff *skb_new = NULL;
1345 struct sk_buff *skb;
1346 ushort pkt_len;
1347 __u8 *data;
1348 int pkt_received = 0;
1349 struct bufdesc_ex *ebdp = NULL;
1350 bool vlan_packet_rcvd = false;
1351 u16 vlan_tag;
1352 int index = 0;
1353 bool is_copybreak;
1354 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1355
1356 #ifdef CONFIG_M532x
1357 flush_cache_all();
1358 #endif
1359 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1360 rxq = fep->rx_queue[queue_id];
1361
1362 /* First, grab all of the stats for the incoming packet.
1363 * These get messed up if we get called due to a busy condition.
1364 */
1365 bdp = rxq->bd.cur;
1366
1367 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1368
1369 if (pkt_received >= budget)
1370 break;
1371 pkt_received++;
1372
1373 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
1374
1375 /* Check for errors. */
1376 status ^= BD_ENET_RX_LAST;
1377 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1378 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1379 BD_ENET_RX_CL)) {
1380 ndev->stats.rx_errors++;
1381 if (status & BD_ENET_RX_OV) {
1382 /* FIFO overrun */
1383 ndev->stats.rx_fifo_errors++;
1384 goto rx_processing_done;
1385 }
1386 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1387 | BD_ENET_RX_LAST)) {
1388 /* Frame too long or too short. */
1389 ndev->stats.rx_length_errors++;
1390 if (status & BD_ENET_RX_LAST)
1391 netdev_err(ndev, "rcv is not +last\n");
1392 }
1393 if (status & BD_ENET_RX_CR) /* CRC Error */
1394 ndev->stats.rx_crc_errors++;
1395 /* Report late collisions as a frame error. */
1396 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1397 ndev->stats.rx_frame_errors++;
1398 goto rx_processing_done;
1399 }
1400
1401 /* Process the incoming frame. */
1402 ndev->stats.rx_packets++;
1403 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1404 ndev->stats.rx_bytes += pkt_len;
1405
1406 index = fec_enet_get_bd_index(bdp, &rxq->bd);
1407 skb = rxq->rx_skbuff[index];
1408
1409 /* The packet length includes FCS, but we don't want to
1410 * include that when passing upstream as it messes up
1411 * bridging applications.
1412 */
1413 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1414 need_swap);
1415 if (!is_copybreak) {
1416 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1417 if (unlikely(!skb_new)) {
1418 ndev->stats.rx_dropped++;
1419 goto rx_processing_done;
1420 }
1421 dma_unmap_single(&fep->pdev->dev,
1422 fec32_to_cpu(bdp->cbd_bufaddr),
1423 FEC_ENET_RX_FRSIZE - fep->rx_align,
1424 DMA_FROM_DEVICE);
1425 }
1426
1427 prefetch(skb->data - NET_IP_ALIGN);
1428 skb_put(skb, pkt_len - 4);
1429 data = skb->data;
1430 if (!is_copybreak && need_swap)
1431 swap_buffer(data, pkt_len);
1432
1433 /* Extract the enhanced buffer descriptor */
1434 ebdp = NULL;
1435 if (fep->bufdesc_ex)
1436 ebdp = (struct bufdesc_ex *)bdp;
1437
1438 /* If this is a VLAN packet remove the VLAN Tag */
1439 vlan_packet_rcvd = false;
1440 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1441 fep->bufdesc_ex &&
1442 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1443 /* Push and remove the vlan tag */
1444 struct vlan_hdr *vlan_header =
1445 (struct vlan_hdr *) (data + ETH_HLEN);
1446 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1447
1448 vlan_packet_rcvd = true;
1449
1450 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1451 skb_pull(skb, VLAN_HLEN);
1452 }
1453
1454 skb->protocol = eth_type_trans(skb, ndev);
1455
1456 /* Get receive timestamp from the skb */
1457 if (fep->hwts_rx_en && fep->bufdesc_ex)
1458 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1459 skb_hwtstamps(skb));
1460
1461 if (fep->bufdesc_ex &&
1462 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1463 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1464 /* don't check it */
1465 skb->ip_summed = CHECKSUM_UNNECESSARY;
1466 } else {
1467 skb_checksum_none_assert(skb);
1468 }
1469 }
1470
1471 /* Handle received VLAN packets */
1472 if (vlan_packet_rcvd)
1473 __vlan_hwaccel_put_tag(skb,
1474 htons(ETH_P_8021Q),
1475 vlan_tag);
1476
1477 napi_gro_receive(&fep->napi, skb);
1478
1479 if (is_copybreak) {
1480 dma_sync_single_for_device(&fep->pdev->dev,
1481 fec32_to_cpu(bdp->cbd_bufaddr),
1482 FEC_ENET_RX_FRSIZE - fep->rx_align,
1483 DMA_FROM_DEVICE);
1484 } else {
1485 rxq->rx_skbuff[index] = skb_new;
1486 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1487 }
1488
1489 rx_processing_done:
1490 /* Clear the status flags for this buffer */
1491 status &= ~BD_ENET_RX_STATS;
1492
1493 /* Mark the buffer empty */
1494 status |= BD_ENET_RX_EMPTY;
1495
1496 if (fep->bufdesc_ex) {
1497 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1498
1499 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1500 ebdp->cbd_prot = 0;
1501 ebdp->cbd_bdu = 0;
1502 }
1503 /* Make sure the updates to rest of the descriptor are
1504 * performed before transferring ownership.
1505 */
1506 wmb();
1507 bdp->cbd_sc = cpu_to_fec16(status);
1508
1509 /* Update BD pointer to next entry */
1510 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1511
1512 /* Doing this here will keep the FEC running while we process
1513 * incoming frames. On a heavily loaded network, we should be
1514 * able to keep up at the expense of system resources.
1515 */
1516 writel(0, rxq->bd.reg_desc_active);
1517 }
1518 rxq->bd.cur = bdp;
1519 return pkt_received;
1520 }
1521
1522 static int
1523 fec_enet_rx(struct net_device *ndev, int budget)
1524 {
1525 int pkt_received = 0;
1526 u16 queue_id;
1527 struct fec_enet_private *fep = netdev_priv(ndev);
1528
1529 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1530 int ret;
1531
1532 ret = fec_enet_rx_queue(ndev,
1533 budget - pkt_received, queue_id);
1534
1535 if (ret < budget - pkt_received)
1536 clear_bit(queue_id, &fep->work_rx);
1537
1538 pkt_received += ret;
1539 }
1540 return pkt_received;
1541 }
1542
1543 static bool
1544 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1545 {
1546 if (int_events == 0)
1547 return false;
1548
1549 if (int_events & FEC_ENET_RXF)
1550 fep->work_rx |= (1 << 2);
1551 if (int_events & FEC_ENET_RXF_1)
1552 fep->work_rx |= (1 << 0);
1553 if (int_events & FEC_ENET_RXF_2)
1554 fep->work_rx |= (1 << 1);
1555
1556 if (int_events & FEC_ENET_TXF)
1557 fep->work_tx |= (1 << 2);
1558 if (int_events & FEC_ENET_TXF_1)
1559 fep->work_tx |= (1 << 0);
1560 if (int_events & FEC_ENET_TXF_2)
1561 fep->work_tx |= (1 << 1);
1562
1563 return true;
1564 }
1565
1566 static irqreturn_t
1567 fec_enet_interrupt(int irq, void *dev_id)
1568 {
1569 struct net_device *ndev = dev_id;
1570 struct fec_enet_private *fep = netdev_priv(ndev);
1571 uint int_events;
1572 irqreturn_t ret = IRQ_NONE;
1573
1574 int_events = readl(fep->hwp + FEC_IEVENT);
1575 writel(int_events, fep->hwp + FEC_IEVENT);
1576 fec_enet_collect_events(fep, int_events);
1577
1578 if ((fep->work_tx || fep->work_rx) && fep->link) {
1579 ret = IRQ_HANDLED;
1580
1581 if (napi_schedule_prep(&fep->napi)) {
1582 /* Disable the NAPI interrupts */
1583 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK);
1584 __napi_schedule(&fep->napi);
1585 }
1586 }
1587
1588 if (int_events & FEC_ENET_MII) {
1589 ret = IRQ_HANDLED;
1590 complete(&fep->mdio_done);
1591 }
1592
1593 if (fep->ptp_clock)
1594 fec_ptp_check_pps_event(fep);
1595
1596 return ret;
1597 }
1598
1599 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1600 {
1601 struct net_device *ndev = napi->dev;
1602 struct fec_enet_private *fep = netdev_priv(ndev);
1603 int pkts;
1604
1605 pkts = fec_enet_rx(ndev, budget);
1606
1607 fec_enet_tx(ndev);
1608
1609 if (pkts < budget) {
1610 napi_complete(napi);
1611 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1612 }
1613 return pkts;
1614 }
1615
1616 /* ------------------------------------------------------------------------- */
1617 static void fec_get_mac(struct net_device *ndev)
1618 {
1619 struct fec_enet_private *fep = netdev_priv(ndev);
1620 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1621 unsigned char *iap, tmpaddr[ETH_ALEN];
1622
1623 /*
1624 * try to get mac address in following order:
1625 *
1626 * 1) module parameter via kernel command line in form
1627 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1628 */
1629 iap = macaddr;
1630
1631 /*
1632 * 2) from device tree data
1633 */
1634 if (!is_valid_ether_addr(iap)) {
1635 struct device_node *np = fep->pdev->dev.of_node;
1636 if (np) {
1637 const char *mac = of_get_mac_address(np);
1638 if (mac)
1639 iap = (unsigned char *) mac;
1640 }
1641 }
1642
1643 /*
1644 * 3) from flash or fuse (via platform data)
1645 */
1646 if (!is_valid_ether_addr(iap)) {
1647 #ifdef CONFIG_M5272
1648 if (FEC_FLASHMAC)
1649 iap = (unsigned char *)FEC_FLASHMAC;
1650 #else
1651 if (pdata)
1652 iap = (unsigned char *)&pdata->mac;
1653 #endif
1654 }
1655
1656 /*
1657 * 4) FEC mac registers set by bootloader
1658 */
1659 if (!is_valid_ether_addr(iap)) {
1660 *((__be32 *) &tmpaddr[0]) =
1661 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1662 *((__be16 *) &tmpaddr[4]) =
1663 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1664 iap = &tmpaddr[0];
1665 }
1666
1667 /*
1668 * 5) random mac address
1669 */
1670 if (!is_valid_ether_addr(iap)) {
1671 /* Report it and use a random ethernet address instead */
1672 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1673 eth_hw_addr_random(ndev);
1674 netdev_info(ndev, "Using random MAC address: %pM\n",
1675 ndev->dev_addr);
1676 return;
1677 }
1678
1679 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1680
1681 /* Adjust MAC if using macaddr */
1682 if (iap == macaddr)
1683 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1684 }
1685
1686 /* ------------------------------------------------------------------------- */
1687
1688 /*
1689 * Phy section
1690 */
1691 static void fec_enet_adjust_link(struct net_device *ndev)
1692 {
1693 struct fec_enet_private *fep = netdev_priv(ndev);
1694 struct phy_device *phy_dev = ndev->phydev;
1695 int status_change = 0;
1696
1697 /* Prevent a state halted on mii error */
1698 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1699 phy_dev->state = PHY_RESUMING;
1700 return;
1701 }
1702
1703 /*
1704 * If the netdev is down, or is going down, we're not interested
1705 * in link state events, so just mark our idea of the link as down
1706 * and ignore the event.
1707 */
1708 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1709 fep->link = 0;
1710 } else if (phy_dev->link) {
1711 if (!fep->link) {
1712 fep->link = phy_dev->link;
1713 status_change = 1;
1714 }
1715
1716 if (fep->full_duplex != phy_dev->duplex) {
1717 fep->full_duplex = phy_dev->duplex;
1718 status_change = 1;
1719 }
1720
1721 if (phy_dev->speed != fep->speed) {
1722 fep->speed = phy_dev->speed;
1723 status_change = 1;
1724 }
1725
1726 /* if any of the above changed restart the FEC */
1727 if (status_change) {
1728 napi_disable(&fep->napi);
1729 netif_tx_lock_bh(ndev);
1730 fec_restart(ndev);
1731 netif_wake_queue(ndev);
1732 netif_tx_unlock_bh(ndev);
1733 napi_enable(&fep->napi);
1734 }
1735 } else {
1736 if (fep->link) {
1737 napi_disable(&fep->napi);
1738 netif_tx_lock_bh(ndev);
1739 fec_stop(ndev);
1740 netif_tx_unlock_bh(ndev);
1741 napi_enable(&fep->napi);
1742 fep->link = phy_dev->link;
1743 status_change = 1;
1744 }
1745 }
1746
1747 if (status_change)
1748 phy_print_status(phy_dev);
1749 }
1750
1751 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1752 {
1753 struct fec_enet_private *fep = bus->priv;
1754 struct device *dev = &fep->pdev->dev;
1755 unsigned long time_left;
1756 int ret = 0;
1757
1758 ret = pm_runtime_get_sync(dev);
1759 if (ret < 0)
1760 return ret;
1761
1762 fep->mii_timeout = 0;
1763 reinit_completion(&fep->mdio_done);
1764
1765 /* start a read op */
1766 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1767 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1768 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1769
1770 /* wait for end of transfer */
1771 time_left = wait_for_completion_timeout(&fep->mdio_done,
1772 usecs_to_jiffies(FEC_MII_TIMEOUT));
1773 if (time_left == 0) {
1774 fep->mii_timeout = 1;
1775 netdev_err(fep->netdev, "MDIO read timeout\n");
1776 ret = -ETIMEDOUT;
1777 goto out;
1778 }
1779
1780 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1781
1782 out:
1783 pm_runtime_mark_last_busy(dev);
1784 pm_runtime_put_autosuspend(dev);
1785
1786 return ret;
1787 }
1788
1789 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1790 u16 value)
1791 {
1792 struct fec_enet_private *fep = bus->priv;
1793 struct device *dev = &fep->pdev->dev;
1794 unsigned long time_left;
1795 int ret;
1796
1797 ret = pm_runtime_get_sync(dev);
1798 if (ret < 0)
1799 return ret;
1800 else
1801 ret = 0;
1802
1803 fep->mii_timeout = 0;
1804 reinit_completion(&fep->mdio_done);
1805
1806 /* start a write op */
1807 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1808 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1809 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1810 fep->hwp + FEC_MII_DATA);
1811
1812 /* wait for end of transfer */
1813 time_left = wait_for_completion_timeout(&fep->mdio_done,
1814 usecs_to_jiffies(FEC_MII_TIMEOUT));
1815 if (time_left == 0) {
1816 fep->mii_timeout = 1;
1817 netdev_err(fep->netdev, "MDIO write timeout\n");
1818 ret = -ETIMEDOUT;
1819 }
1820
1821 pm_runtime_mark_last_busy(dev);
1822 pm_runtime_put_autosuspend(dev);
1823
1824 return ret;
1825 }
1826
1827 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1828 {
1829 struct fec_enet_private *fep = netdev_priv(ndev);
1830 int ret;
1831
1832 if (enable) {
1833 ret = clk_prepare_enable(fep->clk_ahb);
1834 if (ret)
1835 return ret;
1836 if (fep->clk_enet_out) {
1837 ret = clk_prepare_enable(fep->clk_enet_out);
1838 if (ret)
1839 goto failed_clk_enet_out;
1840 }
1841 if (fep->clk_ptp) {
1842 mutex_lock(&fep->ptp_clk_mutex);
1843 ret = clk_prepare_enable(fep->clk_ptp);
1844 if (ret) {
1845 mutex_unlock(&fep->ptp_clk_mutex);
1846 goto failed_clk_ptp;
1847 } else {
1848 fep->ptp_clk_on = true;
1849 }
1850 mutex_unlock(&fep->ptp_clk_mutex);
1851 }
1852 if (fep->clk_ref) {
1853 ret = clk_prepare_enable(fep->clk_ref);
1854 if (ret)
1855 goto failed_clk_ref;
1856 }
1857 } else {
1858 clk_disable_unprepare(fep->clk_ahb);
1859 if (fep->clk_enet_out)
1860 clk_disable_unprepare(fep->clk_enet_out);
1861 if (fep->clk_ptp) {
1862 mutex_lock(&fep->ptp_clk_mutex);
1863 clk_disable_unprepare(fep->clk_ptp);
1864 fep->ptp_clk_on = false;
1865 mutex_unlock(&fep->ptp_clk_mutex);
1866 }
1867 if (fep->clk_ref)
1868 clk_disable_unprepare(fep->clk_ref);
1869 }
1870
1871 return 0;
1872
1873 failed_clk_ref:
1874 if (fep->clk_ref)
1875 clk_disable_unprepare(fep->clk_ref);
1876 failed_clk_ptp:
1877 if (fep->clk_enet_out)
1878 clk_disable_unprepare(fep->clk_enet_out);
1879 failed_clk_enet_out:
1880 clk_disable_unprepare(fep->clk_ahb);
1881
1882 return ret;
1883 }
1884
1885 static int fec_enet_mii_probe(struct net_device *ndev)
1886 {
1887 struct fec_enet_private *fep = netdev_priv(ndev);
1888 struct phy_device *phy_dev = NULL;
1889 char mdio_bus_id[MII_BUS_ID_SIZE];
1890 char phy_name[MII_BUS_ID_SIZE + 3];
1891 int phy_id;
1892 int dev_id = fep->dev_id;
1893
1894 if (fep->phy_node) {
1895 phy_dev = of_phy_connect(ndev, fep->phy_node,
1896 &fec_enet_adjust_link, 0,
1897 fep->phy_interface);
1898 if (!phy_dev)
1899 return -ENODEV;
1900 } else {
1901 /* check for attached phy */
1902 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1903 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
1904 continue;
1905 if (dev_id--)
1906 continue;
1907 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1908 break;
1909 }
1910
1911 if (phy_id >= PHY_MAX_ADDR) {
1912 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1913 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1914 phy_id = 0;
1915 }
1916
1917 snprintf(phy_name, sizeof(phy_name),
1918 PHY_ID_FMT, mdio_bus_id, phy_id);
1919 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1920 fep->phy_interface);
1921 }
1922
1923 if (IS_ERR(phy_dev)) {
1924 netdev_err(ndev, "could not attach to PHY\n");
1925 return PTR_ERR(phy_dev);
1926 }
1927
1928 /* mask with MAC supported features */
1929 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
1930 phy_dev->supported &= PHY_GBIT_FEATURES;
1931 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1932 #if !defined(CONFIG_M5272)
1933 phy_dev->supported |= SUPPORTED_Pause;
1934 #endif
1935 }
1936 else
1937 phy_dev->supported &= PHY_BASIC_FEATURES;
1938
1939 phy_dev->advertising = phy_dev->supported;
1940
1941 fep->link = 0;
1942 fep->full_duplex = 0;
1943
1944 phy_attached_info(phy_dev);
1945
1946 return 0;
1947 }
1948
1949 static int fec_enet_mii_init(struct platform_device *pdev)
1950 {
1951 static struct mii_bus *fec0_mii_bus;
1952 struct net_device *ndev = platform_get_drvdata(pdev);
1953 struct fec_enet_private *fep = netdev_priv(ndev);
1954 struct device_node *node;
1955 int err = -ENXIO;
1956 u32 mii_speed, holdtime;
1957
1958 /*
1959 * The i.MX28 dual fec interfaces are not equal.
1960 * Here are the differences:
1961 *
1962 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1963 * - fec0 acts as the 1588 time master while fec1 is slave
1964 * - external phys can only be configured by fec0
1965 *
1966 * That is to say fec1 can not work independently. It only works
1967 * when fec0 is working. The reason behind this design is that the
1968 * second interface is added primarily for Switch mode.
1969 *
1970 * Because of the last point above, both phys are attached on fec0
1971 * mdio interface in board design, and need to be configured by
1972 * fec0 mii_bus.
1973 */
1974 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
1975 /* fec1 uses fec0 mii_bus */
1976 if (mii_cnt && fec0_mii_bus) {
1977 fep->mii_bus = fec0_mii_bus;
1978 mii_cnt++;
1979 return 0;
1980 }
1981 return -ENOENT;
1982 }
1983
1984 fep->mii_timeout = 0;
1985
1986 /*
1987 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1988 *
1989 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1990 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1991 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1992 * document.
1993 */
1994 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
1995 if (fep->quirks & FEC_QUIRK_ENET_MAC)
1996 mii_speed--;
1997 if (mii_speed > 63) {
1998 dev_err(&pdev->dev,
1999 "fec clock (%lu) to fast to get right mii speed\n",
2000 clk_get_rate(fep->clk_ipg));
2001 err = -EINVAL;
2002 goto err_out;
2003 }
2004
2005 /*
2006 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2007 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2008 * versions are RAZ there, so just ignore the difference and write the
2009 * register always.
2010 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2011 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2012 * output.
2013 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2014 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2015 * holdtime cannot result in a value greater than 3.
2016 */
2017 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2018
2019 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2020
2021 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2022
2023 fep->mii_bus = mdiobus_alloc();
2024 if (fep->mii_bus == NULL) {
2025 err = -ENOMEM;
2026 goto err_out;
2027 }
2028
2029 fep->mii_bus->name = "fec_enet_mii_bus";
2030 fep->mii_bus->read = fec_enet_mdio_read;
2031 fep->mii_bus->write = fec_enet_mdio_write;
2032 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2033 pdev->name, fep->dev_id + 1);
2034 fep->mii_bus->priv = fep;
2035 fep->mii_bus->parent = &pdev->dev;
2036
2037 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2038 if (node) {
2039 err = of_mdiobus_register(fep->mii_bus, node);
2040 of_node_put(node);
2041 } else {
2042 err = mdiobus_register(fep->mii_bus);
2043 }
2044
2045 if (err)
2046 goto err_out_free_mdiobus;
2047
2048 mii_cnt++;
2049
2050 /* save fec0 mii_bus */
2051 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2052 fec0_mii_bus = fep->mii_bus;
2053
2054 return 0;
2055
2056 err_out_free_mdiobus:
2057 mdiobus_free(fep->mii_bus);
2058 err_out:
2059 return err;
2060 }
2061
2062 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2063 {
2064 if (--mii_cnt == 0) {
2065 mdiobus_unregister(fep->mii_bus);
2066 mdiobus_free(fep->mii_bus);
2067 }
2068 }
2069
2070 static void fec_enet_get_drvinfo(struct net_device *ndev,
2071 struct ethtool_drvinfo *info)
2072 {
2073 struct fec_enet_private *fep = netdev_priv(ndev);
2074
2075 strlcpy(info->driver, fep->pdev->dev.driver->name,
2076 sizeof(info->driver));
2077 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2078 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2079 }
2080
2081 static int fec_enet_get_regs_len(struct net_device *ndev)
2082 {
2083 struct fec_enet_private *fep = netdev_priv(ndev);
2084 struct resource *r;
2085 int s = 0;
2086
2087 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2088 if (r)
2089 s = resource_size(r);
2090
2091 return s;
2092 }
2093
2094 /* List of registers that can be safety be read to dump them with ethtool */
2095 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2096 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
2097 static u32 fec_enet_register_offset[] = {
2098 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2099 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2100 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2101 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2102 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2103 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2104 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2105 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2106 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2107 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2108 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2109 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2110 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2111 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2112 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2113 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2114 RMON_T_P_GTE2048, RMON_T_OCTETS,
2115 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2116 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2117 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2118 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2119 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2120 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2121 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2122 RMON_R_P_GTE2048, RMON_R_OCTETS,
2123 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2124 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2125 };
2126 #else
2127 static u32 fec_enet_register_offset[] = {
2128 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2129 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2130 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2131 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2132 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2133 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2134 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2135 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2136 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2137 };
2138 #endif
2139
2140 static void fec_enet_get_regs(struct net_device *ndev,
2141 struct ethtool_regs *regs, void *regbuf)
2142 {
2143 struct fec_enet_private *fep = netdev_priv(ndev);
2144 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2145 u32 *buf = (u32 *)regbuf;
2146 u32 i, off;
2147
2148 memset(buf, 0, regs->len);
2149
2150 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2151 off = fec_enet_register_offset[i] / 4;
2152 buf[off] = readl(&theregs[off]);
2153 }
2154 }
2155
2156 static int fec_enet_get_ts_info(struct net_device *ndev,
2157 struct ethtool_ts_info *info)
2158 {
2159 struct fec_enet_private *fep = netdev_priv(ndev);
2160
2161 if (fep->bufdesc_ex) {
2162
2163 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2164 SOF_TIMESTAMPING_RX_SOFTWARE |
2165 SOF_TIMESTAMPING_SOFTWARE |
2166 SOF_TIMESTAMPING_TX_HARDWARE |
2167 SOF_TIMESTAMPING_RX_HARDWARE |
2168 SOF_TIMESTAMPING_RAW_HARDWARE;
2169 if (fep->ptp_clock)
2170 info->phc_index = ptp_clock_index(fep->ptp_clock);
2171 else
2172 info->phc_index = -1;
2173
2174 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2175 (1 << HWTSTAMP_TX_ON);
2176
2177 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2178 (1 << HWTSTAMP_FILTER_ALL);
2179 return 0;
2180 } else {
2181 return ethtool_op_get_ts_info(ndev, info);
2182 }
2183 }
2184
2185 #if !defined(CONFIG_M5272)
2186
2187 static void fec_enet_get_pauseparam(struct net_device *ndev,
2188 struct ethtool_pauseparam *pause)
2189 {
2190 struct fec_enet_private *fep = netdev_priv(ndev);
2191
2192 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2193 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2194 pause->rx_pause = pause->tx_pause;
2195 }
2196
2197 static int fec_enet_set_pauseparam(struct net_device *ndev,
2198 struct ethtool_pauseparam *pause)
2199 {
2200 struct fec_enet_private *fep = netdev_priv(ndev);
2201
2202 if (!ndev->phydev)
2203 return -ENODEV;
2204
2205 if (pause->tx_pause != pause->rx_pause) {
2206 netdev_info(ndev,
2207 "hardware only support enable/disable both tx and rx");
2208 return -EINVAL;
2209 }
2210
2211 fep->pause_flag = 0;
2212
2213 /* tx pause must be same as rx pause */
2214 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2215 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2216
2217 if (pause->rx_pause || pause->autoneg) {
2218 ndev->phydev->supported |= ADVERTISED_Pause;
2219 ndev->phydev->advertising |= ADVERTISED_Pause;
2220 } else {
2221 ndev->phydev->supported &= ~ADVERTISED_Pause;
2222 ndev->phydev->advertising &= ~ADVERTISED_Pause;
2223 }
2224
2225 if (pause->autoneg) {
2226 if (netif_running(ndev))
2227 fec_stop(ndev);
2228 phy_start_aneg(ndev->phydev);
2229 }
2230 if (netif_running(ndev)) {
2231 napi_disable(&fep->napi);
2232 netif_tx_lock_bh(ndev);
2233 fec_restart(ndev);
2234 netif_wake_queue(ndev);
2235 netif_tx_unlock_bh(ndev);
2236 napi_enable(&fep->napi);
2237 }
2238
2239 return 0;
2240 }
2241
2242 static const struct fec_stat {
2243 char name[ETH_GSTRING_LEN];
2244 u16 offset;
2245 } fec_stats[] = {
2246 /* RMON TX */
2247 { "tx_dropped", RMON_T_DROP },
2248 { "tx_packets", RMON_T_PACKETS },
2249 { "tx_broadcast", RMON_T_BC_PKT },
2250 { "tx_multicast", RMON_T_MC_PKT },
2251 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2252 { "tx_undersize", RMON_T_UNDERSIZE },
2253 { "tx_oversize", RMON_T_OVERSIZE },
2254 { "tx_fragment", RMON_T_FRAG },
2255 { "tx_jabber", RMON_T_JAB },
2256 { "tx_collision", RMON_T_COL },
2257 { "tx_64byte", RMON_T_P64 },
2258 { "tx_65to127byte", RMON_T_P65TO127 },
2259 { "tx_128to255byte", RMON_T_P128TO255 },
2260 { "tx_256to511byte", RMON_T_P256TO511 },
2261 { "tx_512to1023byte", RMON_T_P512TO1023 },
2262 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2263 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2264 { "tx_octets", RMON_T_OCTETS },
2265
2266 /* IEEE TX */
2267 { "IEEE_tx_drop", IEEE_T_DROP },
2268 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2269 { "IEEE_tx_1col", IEEE_T_1COL },
2270 { "IEEE_tx_mcol", IEEE_T_MCOL },
2271 { "IEEE_tx_def", IEEE_T_DEF },
2272 { "IEEE_tx_lcol", IEEE_T_LCOL },
2273 { "IEEE_tx_excol", IEEE_T_EXCOL },
2274 { "IEEE_tx_macerr", IEEE_T_MACERR },
2275 { "IEEE_tx_cserr", IEEE_T_CSERR },
2276 { "IEEE_tx_sqe", IEEE_T_SQE },
2277 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2278 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2279
2280 /* RMON RX */
2281 { "rx_packets", RMON_R_PACKETS },
2282 { "rx_broadcast", RMON_R_BC_PKT },
2283 { "rx_multicast", RMON_R_MC_PKT },
2284 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2285 { "rx_undersize", RMON_R_UNDERSIZE },
2286 { "rx_oversize", RMON_R_OVERSIZE },
2287 { "rx_fragment", RMON_R_FRAG },
2288 { "rx_jabber", RMON_R_JAB },
2289 { "rx_64byte", RMON_R_P64 },
2290 { "rx_65to127byte", RMON_R_P65TO127 },
2291 { "rx_128to255byte", RMON_R_P128TO255 },
2292 { "rx_256to511byte", RMON_R_P256TO511 },
2293 { "rx_512to1023byte", RMON_R_P512TO1023 },
2294 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2295 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2296 { "rx_octets", RMON_R_OCTETS },
2297
2298 /* IEEE RX */
2299 { "IEEE_rx_drop", IEEE_R_DROP },
2300 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2301 { "IEEE_rx_crc", IEEE_R_CRC },
2302 { "IEEE_rx_align", IEEE_R_ALIGN },
2303 { "IEEE_rx_macerr", IEEE_R_MACERR },
2304 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2305 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2306 };
2307
2308 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2309 struct ethtool_stats *stats, u64 *data)
2310 {
2311 struct fec_enet_private *fep = netdev_priv(dev);
2312 int i;
2313
2314 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2315 data[i] = readl(fep->hwp + fec_stats[i].offset);
2316 }
2317
2318 static void fec_enet_get_strings(struct net_device *netdev,
2319 u32 stringset, u8 *data)
2320 {
2321 int i;
2322 switch (stringset) {
2323 case ETH_SS_STATS:
2324 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2325 memcpy(data + i * ETH_GSTRING_LEN,
2326 fec_stats[i].name, ETH_GSTRING_LEN);
2327 break;
2328 }
2329 }
2330
2331 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2332 {
2333 switch (sset) {
2334 case ETH_SS_STATS:
2335 return ARRAY_SIZE(fec_stats);
2336 default:
2337 return -EOPNOTSUPP;
2338 }
2339 }
2340 #endif /* !defined(CONFIG_M5272) */
2341
2342 static int fec_enet_nway_reset(struct net_device *dev)
2343 {
2344 struct phy_device *phydev = dev->phydev;
2345
2346 if (!phydev)
2347 return -ENODEV;
2348
2349 return genphy_restart_aneg(phydev);
2350 }
2351
2352 /* ITR clock source is enet system clock (clk_ahb).
2353 * TCTT unit is cycle_ns * 64 cycle
2354 * So, the ICTT value = X us / (cycle_ns * 64)
2355 */
2356 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2357 {
2358 struct fec_enet_private *fep = netdev_priv(ndev);
2359
2360 return us * (fep->itr_clk_rate / 64000) / 1000;
2361 }
2362
2363 /* Set threshold for interrupt coalescing */
2364 static void fec_enet_itr_coal_set(struct net_device *ndev)
2365 {
2366 struct fec_enet_private *fep = netdev_priv(ndev);
2367 int rx_itr, tx_itr;
2368
2369 /* Must be greater than zero to avoid unpredictable behavior */
2370 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2371 !fep->tx_time_itr || !fep->tx_pkts_itr)
2372 return;
2373
2374 /* Select enet system clock as Interrupt Coalescing
2375 * timer Clock Source
2376 */
2377 rx_itr = FEC_ITR_CLK_SEL;
2378 tx_itr = FEC_ITR_CLK_SEL;
2379
2380 /* set ICFT and ICTT */
2381 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2382 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2383 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2384 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2385
2386 rx_itr |= FEC_ITR_EN;
2387 tx_itr |= FEC_ITR_EN;
2388
2389 writel(tx_itr, fep->hwp + FEC_TXIC0);
2390 writel(rx_itr, fep->hwp + FEC_RXIC0);
2391 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
2392 writel(tx_itr, fep->hwp + FEC_TXIC1);
2393 writel(rx_itr, fep->hwp + FEC_RXIC1);
2394 writel(tx_itr, fep->hwp + FEC_TXIC2);
2395 writel(rx_itr, fep->hwp + FEC_RXIC2);
2396 }
2397 }
2398
2399 static int
2400 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2401 {
2402 struct fec_enet_private *fep = netdev_priv(ndev);
2403
2404 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2405 return -EOPNOTSUPP;
2406
2407 ec->rx_coalesce_usecs = fep->rx_time_itr;
2408 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2409
2410 ec->tx_coalesce_usecs = fep->tx_time_itr;
2411 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2412
2413 return 0;
2414 }
2415
2416 static int
2417 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2418 {
2419 struct fec_enet_private *fep = netdev_priv(ndev);
2420 unsigned int cycle;
2421
2422 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2423 return -EOPNOTSUPP;
2424
2425 if (ec->rx_max_coalesced_frames > 255) {
2426 pr_err("Rx coalesced frames exceed hardware limitation\n");
2427 return -EINVAL;
2428 }
2429
2430 if (ec->tx_max_coalesced_frames > 255) {
2431 pr_err("Tx coalesced frame exceed hardware limitation\n");
2432 return -EINVAL;
2433 }
2434
2435 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2436 if (cycle > 0xFFFF) {
2437 pr_err("Rx coalesced usec exceed hardware limitation\n");
2438 return -EINVAL;
2439 }
2440
2441 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2442 if (cycle > 0xFFFF) {
2443 pr_err("Rx coalesced usec exceed hardware limitation\n");
2444 return -EINVAL;
2445 }
2446
2447 fep->rx_time_itr = ec->rx_coalesce_usecs;
2448 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2449
2450 fep->tx_time_itr = ec->tx_coalesce_usecs;
2451 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2452
2453 fec_enet_itr_coal_set(ndev);
2454
2455 return 0;
2456 }
2457
2458 static void fec_enet_itr_coal_init(struct net_device *ndev)
2459 {
2460 struct ethtool_coalesce ec;
2461
2462 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2463 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2464
2465 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2466 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2467
2468 fec_enet_set_coalesce(ndev, &ec);
2469 }
2470
2471 static int fec_enet_get_tunable(struct net_device *netdev,
2472 const struct ethtool_tunable *tuna,
2473 void *data)
2474 {
2475 struct fec_enet_private *fep = netdev_priv(netdev);
2476 int ret = 0;
2477
2478 switch (tuna->id) {
2479 case ETHTOOL_RX_COPYBREAK:
2480 *(u32 *)data = fep->rx_copybreak;
2481 break;
2482 default:
2483 ret = -EINVAL;
2484 break;
2485 }
2486
2487 return ret;
2488 }
2489
2490 static int fec_enet_set_tunable(struct net_device *netdev,
2491 const struct ethtool_tunable *tuna,
2492 const void *data)
2493 {
2494 struct fec_enet_private *fep = netdev_priv(netdev);
2495 int ret = 0;
2496
2497 switch (tuna->id) {
2498 case ETHTOOL_RX_COPYBREAK:
2499 fep->rx_copybreak = *(u32 *)data;
2500 break;
2501 default:
2502 ret = -EINVAL;
2503 break;
2504 }
2505
2506 return ret;
2507 }
2508
2509 static void
2510 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2511 {
2512 struct fec_enet_private *fep = netdev_priv(ndev);
2513
2514 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2515 wol->supported = WAKE_MAGIC;
2516 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2517 } else {
2518 wol->supported = wol->wolopts = 0;
2519 }
2520 }
2521
2522 static int
2523 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2524 {
2525 struct fec_enet_private *fep = netdev_priv(ndev);
2526
2527 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2528 return -EINVAL;
2529
2530 if (wol->wolopts & ~WAKE_MAGIC)
2531 return -EINVAL;
2532
2533 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2534 if (device_may_wakeup(&ndev->dev)) {
2535 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2536 if (fep->irq[0] > 0)
2537 enable_irq_wake(fep->irq[0]);
2538 } else {
2539 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2540 if (fep->irq[0] > 0)
2541 disable_irq_wake(fep->irq[0]);
2542 }
2543
2544 return 0;
2545 }
2546
2547 static const struct ethtool_ops fec_enet_ethtool_ops = {
2548 .get_drvinfo = fec_enet_get_drvinfo,
2549 .get_regs_len = fec_enet_get_regs_len,
2550 .get_regs = fec_enet_get_regs,
2551 .nway_reset = fec_enet_nway_reset,
2552 .get_link = ethtool_op_get_link,
2553 .get_coalesce = fec_enet_get_coalesce,
2554 .set_coalesce = fec_enet_set_coalesce,
2555 #ifndef CONFIG_M5272
2556 .get_pauseparam = fec_enet_get_pauseparam,
2557 .set_pauseparam = fec_enet_set_pauseparam,
2558 .get_strings = fec_enet_get_strings,
2559 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2560 .get_sset_count = fec_enet_get_sset_count,
2561 #endif
2562 .get_ts_info = fec_enet_get_ts_info,
2563 .get_tunable = fec_enet_get_tunable,
2564 .set_tunable = fec_enet_set_tunable,
2565 .get_wol = fec_enet_get_wol,
2566 .set_wol = fec_enet_set_wol,
2567 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2568 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2569 };
2570
2571 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2572 {
2573 struct fec_enet_private *fep = netdev_priv(ndev);
2574 struct phy_device *phydev = ndev->phydev;
2575
2576 if (!netif_running(ndev))
2577 return -EINVAL;
2578
2579 if (!phydev)
2580 return -ENODEV;
2581
2582 if (fep->bufdesc_ex) {
2583 if (cmd == SIOCSHWTSTAMP)
2584 return fec_ptp_set(ndev, rq);
2585 if (cmd == SIOCGHWTSTAMP)
2586 return fec_ptp_get(ndev, rq);
2587 }
2588
2589 return phy_mii_ioctl(phydev, rq, cmd);
2590 }
2591
2592 static void fec_enet_free_buffers(struct net_device *ndev)
2593 {
2594 struct fec_enet_private *fep = netdev_priv(ndev);
2595 unsigned int i;
2596 struct sk_buff *skb;
2597 struct bufdesc *bdp;
2598 struct fec_enet_priv_tx_q *txq;
2599 struct fec_enet_priv_rx_q *rxq;
2600 unsigned int q;
2601
2602 for (q = 0; q < fep->num_rx_queues; q++) {
2603 rxq = fep->rx_queue[q];
2604 bdp = rxq->bd.base;
2605 for (i = 0; i < rxq->bd.ring_size; i++) {
2606 skb = rxq->rx_skbuff[i];
2607 rxq->rx_skbuff[i] = NULL;
2608 if (skb) {
2609 dma_unmap_single(&fep->pdev->dev,
2610 fec32_to_cpu(bdp->cbd_bufaddr),
2611 FEC_ENET_RX_FRSIZE - fep->rx_align,
2612 DMA_FROM_DEVICE);
2613 dev_kfree_skb(skb);
2614 }
2615 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2616 }
2617 }
2618
2619 for (q = 0; q < fep->num_tx_queues; q++) {
2620 txq = fep->tx_queue[q];
2621 bdp = txq->bd.base;
2622 for (i = 0; i < txq->bd.ring_size; i++) {
2623 kfree(txq->tx_bounce[i]);
2624 txq->tx_bounce[i] = NULL;
2625 skb = txq->tx_skbuff[i];
2626 txq->tx_skbuff[i] = NULL;
2627 dev_kfree_skb(skb);
2628 }
2629 }
2630 }
2631
2632 static void fec_enet_free_queue(struct net_device *ndev)
2633 {
2634 struct fec_enet_private *fep = netdev_priv(ndev);
2635 int i;
2636 struct fec_enet_priv_tx_q *txq;
2637
2638 for (i = 0; i < fep->num_tx_queues; i++)
2639 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2640 txq = fep->tx_queue[i];
2641 dma_free_coherent(NULL,
2642 txq->bd.ring_size * TSO_HEADER_SIZE,
2643 txq->tso_hdrs,
2644 txq->tso_hdrs_dma);
2645 }
2646
2647 for (i = 0; i < fep->num_rx_queues; i++)
2648 kfree(fep->rx_queue[i]);
2649 for (i = 0; i < fep->num_tx_queues; i++)
2650 kfree(fep->tx_queue[i]);
2651 }
2652
2653 static int fec_enet_alloc_queue(struct net_device *ndev)
2654 {
2655 struct fec_enet_private *fep = netdev_priv(ndev);
2656 int i;
2657 int ret = 0;
2658 struct fec_enet_priv_tx_q *txq;
2659
2660 for (i = 0; i < fep->num_tx_queues; i++) {
2661 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2662 if (!txq) {
2663 ret = -ENOMEM;
2664 goto alloc_failed;
2665 }
2666
2667 fep->tx_queue[i] = txq;
2668 txq->bd.ring_size = TX_RING_SIZE;
2669 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
2670
2671 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2672 txq->tx_wake_threshold =
2673 (txq->bd.ring_size - txq->tx_stop_threshold) / 2;
2674
2675 txq->tso_hdrs = dma_alloc_coherent(NULL,
2676 txq->bd.ring_size * TSO_HEADER_SIZE,
2677 &txq->tso_hdrs_dma,
2678 GFP_KERNEL);
2679 if (!txq->tso_hdrs) {
2680 ret = -ENOMEM;
2681 goto alloc_failed;
2682 }
2683 }
2684
2685 for (i = 0; i < fep->num_rx_queues; i++) {
2686 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2687 GFP_KERNEL);
2688 if (!fep->rx_queue[i]) {
2689 ret = -ENOMEM;
2690 goto alloc_failed;
2691 }
2692
2693 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
2694 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
2695 }
2696 return ret;
2697
2698 alloc_failed:
2699 fec_enet_free_queue(ndev);
2700 return ret;
2701 }
2702
2703 static int
2704 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2705 {
2706 struct fec_enet_private *fep = netdev_priv(ndev);
2707 unsigned int i;
2708 struct sk_buff *skb;
2709 struct bufdesc *bdp;
2710 struct fec_enet_priv_rx_q *rxq;
2711
2712 rxq = fep->rx_queue[queue];
2713 bdp = rxq->bd.base;
2714 for (i = 0; i < rxq->bd.ring_size; i++) {
2715 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2716 if (!skb)
2717 goto err_alloc;
2718
2719 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2720 dev_kfree_skb(skb);
2721 goto err_alloc;
2722 }
2723
2724 rxq->rx_skbuff[i] = skb;
2725 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
2726
2727 if (fep->bufdesc_ex) {
2728 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2729 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
2730 }
2731
2732 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2733 }
2734
2735 /* Set the last buffer to wrap. */
2736 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
2737 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2738 return 0;
2739
2740 err_alloc:
2741 fec_enet_free_buffers(ndev);
2742 return -ENOMEM;
2743 }
2744
2745 static int
2746 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2747 {
2748 struct fec_enet_private *fep = netdev_priv(ndev);
2749 unsigned int i;
2750 struct bufdesc *bdp;
2751 struct fec_enet_priv_tx_q *txq;
2752
2753 txq = fep->tx_queue[queue];
2754 bdp = txq->bd.base;
2755 for (i = 0; i < txq->bd.ring_size; i++) {
2756 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2757 if (!txq->tx_bounce[i])
2758 goto err_alloc;
2759
2760 bdp->cbd_sc = cpu_to_fec16(0);
2761 bdp->cbd_bufaddr = cpu_to_fec32(0);
2762
2763 if (fep->bufdesc_ex) {
2764 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2765 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
2766 }
2767
2768 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
2769 }
2770
2771 /* Set the last buffer to wrap. */
2772 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
2773 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2774
2775 return 0;
2776
2777 err_alloc:
2778 fec_enet_free_buffers(ndev);
2779 return -ENOMEM;
2780 }
2781
2782 static int fec_enet_alloc_buffers(struct net_device *ndev)
2783 {
2784 struct fec_enet_private *fep = netdev_priv(ndev);
2785 unsigned int i;
2786
2787 for (i = 0; i < fep->num_rx_queues; i++)
2788 if (fec_enet_alloc_rxq_buffers(ndev, i))
2789 return -ENOMEM;
2790
2791 for (i = 0; i < fep->num_tx_queues; i++)
2792 if (fec_enet_alloc_txq_buffers(ndev, i))
2793 return -ENOMEM;
2794 return 0;
2795 }
2796
2797 static int
2798 fec_enet_open(struct net_device *ndev)
2799 {
2800 struct fec_enet_private *fep = netdev_priv(ndev);
2801 int ret;
2802
2803 ret = pm_runtime_get_sync(&fep->pdev->dev);
2804 if (ret < 0)
2805 return ret;
2806
2807 pinctrl_pm_select_default_state(&fep->pdev->dev);
2808 ret = fec_enet_clk_enable(ndev, true);
2809 if (ret)
2810 goto clk_enable;
2811
2812 /* I should reset the ring buffers here, but I don't yet know
2813 * a simple way to do that.
2814 */
2815
2816 ret = fec_enet_alloc_buffers(ndev);
2817 if (ret)
2818 goto err_enet_alloc;
2819
2820 /* Init MAC prior to mii bus probe */
2821 fec_restart(ndev);
2822
2823 /* Probe and connect to PHY when open the interface */
2824 ret = fec_enet_mii_probe(ndev);
2825 if (ret)
2826 goto err_enet_mii_probe;
2827
2828 napi_enable(&fep->napi);
2829 phy_start(ndev->phydev);
2830 netif_tx_start_all_queues(ndev);
2831
2832 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2833 FEC_WOL_FLAG_ENABLE);
2834
2835 return 0;
2836
2837 err_enet_mii_probe:
2838 fec_enet_free_buffers(ndev);
2839 err_enet_alloc:
2840 fec_enet_clk_enable(ndev, false);
2841 clk_enable:
2842 pm_runtime_mark_last_busy(&fep->pdev->dev);
2843 pm_runtime_put_autosuspend(&fep->pdev->dev);
2844 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2845 return ret;
2846 }
2847
2848 static int
2849 fec_enet_close(struct net_device *ndev)
2850 {
2851 struct fec_enet_private *fep = netdev_priv(ndev);
2852
2853 phy_stop(ndev->phydev);
2854
2855 if (netif_device_present(ndev)) {
2856 napi_disable(&fep->napi);
2857 netif_tx_disable(ndev);
2858 fec_stop(ndev);
2859 }
2860
2861 phy_disconnect(ndev->phydev);
2862
2863 fec_enet_clk_enable(ndev, false);
2864 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2865 pm_runtime_mark_last_busy(&fep->pdev->dev);
2866 pm_runtime_put_autosuspend(&fep->pdev->dev);
2867
2868 fec_enet_free_buffers(ndev);
2869
2870 return 0;
2871 }
2872
2873 /* Set or clear the multicast filter for this adaptor.
2874 * Skeleton taken from sunlance driver.
2875 * The CPM Ethernet implementation allows Multicast as well as individual
2876 * MAC address filtering. Some of the drivers check to make sure it is
2877 * a group multicast address, and discard those that are not. I guess I
2878 * will do the same for now, but just remove the test if you want
2879 * individual filtering as well (do the upper net layers want or support
2880 * this kind of feature?).
2881 */
2882
2883 #define HASH_BITS 6 /* #bits in hash */
2884 #define CRC32_POLY 0xEDB88320
2885
2886 static void set_multicast_list(struct net_device *ndev)
2887 {
2888 struct fec_enet_private *fep = netdev_priv(ndev);
2889 struct netdev_hw_addr *ha;
2890 unsigned int i, bit, data, crc, tmp;
2891 unsigned char hash;
2892
2893 if (ndev->flags & IFF_PROMISC) {
2894 tmp = readl(fep->hwp + FEC_R_CNTRL);
2895 tmp |= 0x8;
2896 writel(tmp, fep->hwp + FEC_R_CNTRL);
2897 return;
2898 }
2899
2900 tmp = readl(fep->hwp + FEC_R_CNTRL);
2901 tmp &= ~0x8;
2902 writel(tmp, fep->hwp + FEC_R_CNTRL);
2903
2904 if (ndev->flags & IFF_ALLMULTI) {
2905 /* Catch all multicast addresses, so set the
2906 * filter to all 1's
2907 */
2908 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2909 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2910
2911 return;
2912 }
2913
2914 /* Clear filter and add the addresses in hash register
2915 */
2916 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2917 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2918
2919 netdev_for_each_mc_addr(ha, ndev) {
2920 /* calculate crc32 value of mac address */
2921 crc = 0xffffffff;
2922
2923 for (i = 0; i < ndev->addr_len; i++) {
2924 data = ha->addr[i];
2925 for (bit = 0; bit < 8; bit++, data >>= 1) {
2926 crc = (crc >> 1) ^
2927 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2928 }
2929 }
2930
2931 /* only upper 6 bits (HASH_BITS) are used
2932 * which point to specific bit in he hash registers
2933 */
2934 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2935
2936 if (hash > 31) {
2937 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2938 tmp |= 1 << (hash - 32);
2939 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2940 } else {
2941 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2942 tmp |= 1 << hash;
2943 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2944 }
2945 }
2946 }
2947
2948 /* Set a MAC change in hardware. */
2949 static int
2950 fec_set_mac_address(struct net_device *ndev, void *p)
2951 {
2952 struct fec_enet_private *fep = netdev_priv(ndev);
2953 struct sockaddr *addr = p;
2954
2955 if (addr) {
2956 if (!is_valid_ether_addr(addr->sa_data))
2957 return -EADDRNOTAVAIL;
2958 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2959 }
2960
2961 /* Add netif status check here to avoid system hang in below case:
2962 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
2963 * After ethx down, fec all clocks are gated off and then register
2964 * access causes system hang.
2965 */
2966 if (!netif_running(ndev))
2967 return 0;
2968
2969 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2970 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
2971 fep->hwp + FEC_ADDR_LOW);
2972 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
2973 fep->hwp + FEC_ADDR_HIGH);
2974 return 0;
2975 }
2976
2977 #ifdef CONFIG_NET_POLL_CONTROLLER
2978 /**
2979 * fec_poll_controller - FEC Poll controller function
2980 * @dev: The FEC network adapter
2981 *
2982 * Polled functionality used by netconsole and others in non interrupt mode
2983 *
2984 */
2985 static void fec_poll_controller(struct net_device *dev)
2986 {
2987 int i;
2988 struct fec_enet_private *fep = netdev_priv(dev);
2989
2990 for (i = 0; i < FEC_IRQ_NUM; i++) {
2991 if (fep->irq[i] > 0) {
2992 disable_irq(fep->irq[i]);
2993 fec_enet_interrupt(fep->irq[i], dev);
2994 enable_irq(fep->irq[i]);
2995 }
2996 }
2997 }
2998 #endif
2999
3000 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3001 netdev_features_t features)
3002 {
3003 struct fec_enet_private *fep = netdev_priv(netdev);
3004 netdev_features_t changed = features ^ netdev->features;
3005
3006 netdev->features = features;
3007
3008 /* Receive checksum has been changed */
3009 if (changed & NETIF_F_RXCSUM) {
3010 if (features & NETIF_F_RXCSUM)
3011 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3012 else
3013 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3014 }
3015 }
3016
3017 static int fec_set_features(struct net_device *netdev,
3018 netdev_features_t features)
3019 {
3020 struct fec_enet_private *fep = netdev_priv(netdev);
3021 netdev_features_t changed = features ^ netdev->features;
3022
3023 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3024 napi_disable(&fep->napi);
3025 netif_tx_lock_bh(netdev);
3026 fec_stop(netdev);
3027 fec_enet_set_netdev_features(netdev, features);
3028 fec_restart(netdev);
3029 netif_tx_wake_all_queues(netdev);
3030 netif_tx_unlock_bh(netdev);
3031 napi_enable(&fep->napi);
3032 } else {
3033 fec_enet_set_netdev_features(netdev, features);
3034 }
3035
3036 return 0;
3037 }
3038
3039 static const struct net_device_ops fec_netdev_ops = {
3040 .ndo_open = fec_enet_open,
3041 .ndo_stop = fec_enet_close,
3042 .ndo_start_xmit = fec_enet_start_xmit,
3043 .ndo_set_rx_mode = set_multicast_list,
3044 .ndo_change_mtu = eth_change_mtu,
3045 .ndo_validate_addr = eth_validate_addr,
3046 .ndo_tx_timeout = fec_timeout,
3047 .ndo_set_mac_address = fec_set_mac_address,
3048 .ndo_do_ioctl = fec_enet_ioctl,
3049 #ifdef CONFIG_NET_POLL_CONTROLLER
3050 .ndo_poll_controller = fec_poll_controller,
3051 #endif
3052 .ndo_set_features = fec_set_features,
3053 };
3054
3055 static const unsigned short offset_des_active_rxq[] = {
3056 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3057 };
3058
3059 static const unsigned short offset_des_active_txq[] = {
3060 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3061 };
3062
3063 /*
3064 * XXX: We need to clean up on failure exits here.
3065 *
3066 */
3067 static int fec_enet_init(struct net_device *ndev)
3068 {
3069 struct fec_enet_private *fep = netdev_priv(ndev);
3070 struct bufdesc *cbd_base;
3071 dma_addr_t bd_dma;
3072 int bd_size;
3073 unsigned int i;
3074 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3075 sizeof(struct bufdesc);
3076 unsigned dsize_log2 = __fls(dsize);
3077
3078 WARN_ON(dsize != (1 << dsize_log2));
3079 #if defined(CONFIG_ARM)
3080 fep->rx_align = 0xf;
3081 fep->tx_align = 0xf;
3082 #else
3083 fep->rx_align = 0x3;
3084 fep->tx_align = 0x3;
3085 #endif
3086
3087 fec_enet_alloc_queue(ndev);
3088
3089 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
3090
3091 /* Allocate memory for buffer descriptors. */
3092 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3093 GFP_KERNEL);
3094 if (!cbd_base) {
3095 return -ENOMEM;
3096 }
3097
3098 memset(cbd_base, 0, bd_size);
3099
3100 /* Get the Ethernet address */
3101 fec_get_mac(ndev);
3102 /* make sure MAC we just acquired is programmed into the hw */
3103 fec_set_mac_address(ndev, NULL);
3104
3105 /* Set receive and transmit descriptor base. */
3106 for (i = 0; i < fep->num_rx_queues; i++) {
3107 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
3108 unsigned size = dsize * rxq->bd.ring_size;
3109
3110 rxq->bd.qid = i;
3111 rxq->bd.base = cbd_base;
3112 rxq->bd.cur = cbd_base;
3113 rxq->bd.dma = bd_dma;
3114 rxq->bd.dsize = dsize;
3115 rxq->bd.dsize_log2 = dsize_log2;
3116 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
3117 bd_dma += size;
3118 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3119 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3120 }
3121
3122 for (i = 0; i < fep->num_tx_queues; i++) {
3123 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
3124 unsigned size = dsize * txq->bd.ring_size;
3125
3126 txq->bd.qid = i;
3127 txq->bd.base = cbd_base;
3128 txq->bd.cur = cbd_base;
3129 txq->bd.dma = bd_dma;
3130 txq->bd.dsize = dsize;
3131 txq->bd.dsize_log2 = dsize_log2;
3132 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
3133 bd_dma += size;
3134 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3135 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3136 }
3137
3138
3139 /* The FEC Ethernet specific entries in the device structure */
3140 ndev->watchdog_timeo = TX_TIMEOUT;
3141 ndev->netdev_ops = &fec_netdev_ops;
3142 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3143
3144 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3145 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3146
3147 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3148 /* enable hw VLAN support */
3149 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3150
3151 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3152 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3153
3154 /* enable hw accelerator */
3155 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3156 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3157 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3158 }
3159
3160 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3161 fep->tx_align = 0;
3162 fep->rx_align = 0x3f;
3163 }
3164
3165 ndev->hw_features = ndev->features;
3166
3167 fec_restart(ndev);
3168
3169 return 0;
3170 }
3171
3172 #ifdef CONFIG_OF
3173 static void fec_reset_phy(struct platform_device *pdev)
3174 {
3175 int err, phy_reset;
3176 bool active_high = false;
3177 int msec = 1;
3178 struct device_node *np = pdev->dev.of_node;
3179
3180 if (!np)
3181 return;
3182
3183 of_property_read_u32(np, "phy-reset-duration", &msec);
3184 /* A sane reset duration should not be longer than 1s */
3185 if (msec > 1000)
3186 msec = 1;
3187
3188 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3189 if (!gpio_is_valid(phy_reset))
3190 return;
3191
3192 active_high = of_property_read_bool(np, "phy-reset-active-high");
3193
3194 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3195 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
3196 "phy-reset");
3197 if (err) {
3198 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3199 return;
3200 }
3201
3202 if (msec > 20)
3203 msleep(msec);
3204 else
3205 usleep_range(msec * 1000, msec * 1000 + 1000);
3206
3207 gpio_set_value_cansleep(phy_reset, !active_high);
3208 }
3209 #else /* CONFIG_OF */
3210 static void fec_reset_phy(struct platform_device *pdev)
3211 {
3212 /*
3213 * In case of platform probe, the reset has been done
3214 * by machine code.
3215 */
3216 }
3217 #endif /* CONFIG_OF */
3218
3219 static void
3220 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3221 {
3222 struct device_node *np = pdev->dev.of_node;
3223
3224 *num_tx = *num_rx = 1;
3225
3226 if (!np || !of_device_is_available(np))
3227 return;
3228
3229 /* parse the num of tx and rx queues */
3230 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3231
3232 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3233
3234 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3235 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3236 *num_tx);
3237 *num_tx = 1;
3238 return;
3239 }
3240
3241 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3242 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3243 *num_rx);
3244 *num_rx = 1;
3245 return;
3246 }
3247
3248 }
3249
3250 static int
3251 fec_probe(struct platform_device *pdev)
3252 {
3253 struct fec_enet_private *fep;
3254 struct fec_platform_data *pdata;
3255 struct net_device *ndev;
3256 int i, irq, ret = 0;
3257 struct resource *r;
3258 const struct of_device_id *of_id;
3259 static int dev_id;
3260 struct device_node *np = pdev->dev.of_node, *phy_node;
3261 int num_tx_qs;
3262 int num_rx_qs;
3263
3264 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3265
3266 /* Init network device */
3267 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3268 num_tx_qs, num_rx_qs);
3269 if (!ndev)
3270 return -ENOMEM;
3271
3272 SET_NETDEV_DEV(ndev, &pdev->dev);
3273
3274 /* setup board info structure */
3275 fep = netdev_priv(ndev);
3276
3277 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3278 if (of_id)
3279 pdev->id_entry = of_id->data;
3280 fep->quirks = pdev->id_entry->driver_data;
3281
3282 fep->netdev = ndev;
3283 fep->num_rx_queues = num_rx_qs;
3284 fep->num_tx_queues = num_tx_qs;
3285
3286 #if !defined(CONFIG_M5272)
3287 /* default enable pause frame auto negotiation */
3288 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3289 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3290 #endif
3291
3292 /* Select default pin state */
3293 pinctrl_pm_select_default_state(&pdev->dev);
3294
3295 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3296 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3297 if (IS_ERR(fep->hwp)) {
3298 ret = PTR_ERR(fep->hwp);
3299 goto failed_ioremap;
3300 }
3301
3302 fep->pdev = pdev;
3303 fep->dev_id = dev_id++;
3304
3305 platform_set_drvdata(pdev, ndev);
3306
3307 if (of_get_property(np, "fsl,magic-packet", NULL))
3308 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3309
3310 phy_node = of_parse_phandle(np, "phy-handle", 0);
3311 if (!phy_node && of_phy_is_fixed_link(np)) {
3312 ret = of_phy_register_fixed_link(np);
3313 if (ret < 0) {
3314 dev_err(&pdev->dev,
3315 "broken fixed-link specification\n");
3316 goto failed_phy;
3317 }
3318 phy_node = of_node_get(np);
3319 }
3320 fep->phy_node = phy_node;
3321
3322 ret = of_get_phy_mode(pdev->dev.of_node);
3323 if (ret < 0) {
3324 pdata = dev_get_platdata(&pdev->dev);
3325 if (pdata)
3326 fep->phy_interface = pdata->phy;
3327 else
3328 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3329 } else {
3330 fep->phy_interface = ret;
3331 }
3332
3333 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3334 if (IS_ERR(fep->clk_ipg)) {
3335 ret = PTR_ERR(fep->clk_ipg);
3336 goto failed_clk;
3337 }
3338
3339 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3340 if (IS_ERR(fep->clk_ahb)) {
3341 ret = PTR_ERR(fep->clk_ahb);
3342 goto failed_clk;
3343 }
3344
3345 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3346
3347 /* enet_out is optional, depends on board */
3348 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3349 if (IS_ERR(fep->clk_enet_out))
3350 fep->clk_enet_out = NULL;
3351
3352 fep->ptp_clk_on = false;
3353 mutex_init(&fep->ptp_clk_mutex);
3354
3355 /* clk_ref is optional, depends on board */
3356 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3357 if (IS_ERR(fep->clk_ref))
3358 fep->clk_ref = NULL;
3359
3360 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3361 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3362 if (IS_ERR(fep->clk_ptp)) {
3363 fep->clk_ptp = NULL;
3364 fep->bufdesc_ex = false;
3365 }
3366
3367 ret = fec_enet_clk_enable(ndev, true);
3368 if (ret)
3369 goto failed_clk;
3370
3371 ret = clk_prepare_enable(fep->clk_ipg);
3372 if (ret)
3373 goto failed_clk_ipg;
3374
3375 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3376 if (!IS_ERR(fep->reg_phy)) {
3377 ret = regulator_enable(fep->reg_phy);
3378 if (ret) {
3379 dev_err(&pdev->dev,
3380 "Failed to enable phy regulator: %d\n", ret);
3381 goto failed_regulator;
3382 }
3383 } else {
3384 fep->reg_phy = NULL;
3385 }
3386
3387 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3388 pm_runtime_use_autosuspend(&pdev->dev);
3389 pm_runtime_get_noresume(&pdev->dev);
3390 pm_runtime_set_active(&pdev->dev);
3391 pm_runtime_enable(&pdev->dev);
3392
3393 fec_reset_phy(pdev);
3394
3395 if (fep->bufdesc_ex)
3396 fec_ptp_init(pdev);
3397
3398 ret = fec_enet_init(ndev);
3399 if (ret)
3400 goto failed_init;
3401
3402 for (i = 0; i < FEC_IRQ_NUM; i++) {
3403 irq = platform_get_irq(pdev, i);
3404 if (irq < 0) {
3405 if (i)
3406 break;
3407 ret = irq;
3408 goto failed_irq;
3409 }
3410 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3411 0, pdev->name, ndev);
3412 if (ret)
3413 goto failed_irq;
3414
3415 fep->irq[i] = irq;
3416 }
3417
3418 init_completion(&fep->mdio_done);
3419 ret = fec_enet_mii_init(pdev);
3420 if (ret)
3421 goto failed_mii_init;
3422
3423 /* Carrier starts down, phylib will bring it up */
3424 netif_carrier_off(ndev);
3425 fec_enet_clk_enable(ndev, false);
3426 pinctrl_pm_select_sleep_state(&pdev->dev);
3427
3428 ret = register_netdev(ndev);
3429 if (ret)
3430 goto failed_register;
3431
3432 device_init_wakeup(&ndev->dev, fep->wol_flag &
3433 FEC_WOL_HAS_MAGIC_PACKET);
3434
3435 if (fep->bufdesc_ex && fep->ptp_clock)
3436 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3437
3438 fep->rx_copybreak = COPYBREAK_DEFAULT;
3439 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3440
3441 pm_runtime_mark_last_busy(&pdev->dev);
3442 pm_runtime_put_autosuspend(&pdev->dev);
3443
3444 return 0;
3445
3446 failed_register:
3447 fec_enet_mii_remove(fep);
3448 failed_mii_init:
3449 failed_irq:
3450 failed_init:
3451 fec_ptp_stop(pdev);
3452 if (fep->reg_phy)
3453 regulator_disable(fep->reg_phy);
3454 failed_regulator:
3455 clk_disable_unprepare(fep->clk_ipg);
3456 failed_clk_ipg:
3457 fec_enet_clk_enable(ndev, false);
3458 failed_clk:
3459 failed_phy:
3460 of_node_put(phy_node);
3461 failed_ioremap:
3462 free_netdev(ndev);
3463
3464 return ret;
3465 }
3466
3467 static int
3468 fec_drv_remove(struct platform_device *pdev)
3469 {
3470 struct net_device *ndev = platform_get_drvdata(pdev);
3471 struct fec_enet_private *fep = netdev_priv(ndev);
3472
3473 cancel_work_sync(&fep->tx_timeout_work);
3474 fec_ptp_stop(pdev);
3475 unregister_netdev(ndev);
3476 fec_enet_mii_remove(fep);
3477 if (fep->reg_phy)
3478 regulator_disable(fep->reg_phy);
3479 of_node_put(fep->phy_node);
3480 free_netdev(ndev);
3481
3482 return 0;
3483 }
3484
3485 static int __maybe_unused fec_suspend(struct device *dev)
3486 {
3487 struct net_device *ndev = dev_get_drvdata(dev);
3488 struct fec_enet_private *fep = netdev_priv(ndev);
3489
3490 rtnl_lock();
3491 if (netif_running(ndev)) {
3492 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3493 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3494 phy_stop(ndev->phydev);
3495 napi_disable(&fep->napi);
3496 netif_tx_lock_bh(ndev);
3497 netif_device_detach(ndev);
3498 netif_tx_unlock_bh(ndev);
3499 fec_stop(ndev);
3500 fec_enet_clk_enable(ndev, false);
3501 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3502 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3503 }
3504 rtnl_unlock();
3505
3506 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3507 regulator_disable(fep->reg_phy);
3508
3509 /* SOC supply clock to phy, when clock is disabled, phy link down
3510 * SOC control phy regulator, when regulator is disabled, phy link down
3511 */
3512 if (fep->clk_enet_out || fep->reg_phy)
3513 fep->link = 0;
3514
3515 return 0;
3516 }
3517
3518 static int __maybe_unused fec_resume(struct device *dev)
3519 {
3520 struct net_device *ndev = dev_get_drvdata(dev);
3521 struct fec_enet_private *fep = netdev_priv(ndev);
3522 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
3523 int ret;
3524 int val;
3525
3526 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3527 ret = regulator_enable(fep->reg_phy);
3528 if (ret)
3529 return ret;
3530 }
3531
3532 rtnl_lock();
3533 if (netif_running(ndev)) {
3534 ret = fec_enet_clk_enable(ndev, true);
3535 if (ret) {
3536 rtnl_unlock();
3537 goto failed_clk;
3538 }
3539 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3540 if (pdata && pdata->sleep_mode_enable)
3541 pdata->sleep_mode_enable(false);
3542 val = readl(fep->hwp + FEC_ECNTRL);
3543 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3544 writel(val, fep->hwp + FEC_ECNTRL);
3545 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3546 } else {
3547 pinctrl_pm_select_default_state(&fep->pdev->dev);
3548 }
3549 fec_restart(ndev);
3550 netif_tx_lock_bh(ndev);
3551 netif_device_attach(ndev);
3552 netif_tx_unlock_bh(ndev);
3553 napi_enable(&fep->napi);
3554 phy_start(ndev->phydev);
3555 }
3556 rtnl_unlock();
3557
3558 return 0;
3559
3560 failed_clk:
3561 if (fep->reg_phy)
3562 regulator_disable(fep->reg_phy);
3563 return ret;
3564 }
3565
3566 static int __maybe_unused fec_runtime_suspend(struct device *dev)
3567 {
3568 struct net_device *ndev = dev_get_drvdata(dev);
3569 struct fec_enet_private *fep = netdev_priv(ndev);
3570
3571 clk_disable_unprepare(fep->clk_ipg);
3572
3573 return 0;
3574 }
3575
3576 static int __maybe_unused fec_runtime_resume(struct device *dev)
3577 {
3578 struct net_device *ndev = dev_get_drvdata(dev);
3579 struct fec_enet_private *fep = netdev_priv(ndev);
3580
3581 return clk_prepare_enable(fep->clk_ipg);
3582 }
3583
3584 static const struct dev_pm_ops fec_pm_ops = {
3585 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3586 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3587 };
3588
3589 static struct platform_driver fec_driver = {
3590 .driver = {
3591 .name = DRIVER_NAME,
3592 .pm = &fec_pm_ops,
3593 .of_match_table = fec_dt_ids,
3594 },
3595 .id_table = fec_devtype,
3596 .probe = fec_probe,
3597 .remove = fec_drv_remove,
3598 };
3599
3600 module_platform_driver(fec_driver);
3601
3602 MODULE_ALIAS("platform:"DRIVER_NAME);
3603 MODULE_LICENSE("GPL");