2 * Copyright (C) 2001 MandrakeSoft S.A.
7 * http://www.linux-mandrake.com/
8 * http://www.mandrakesoft.com/
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2 of the License, or (at your option) any later version.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * Yunhong Jiang <yunhong.jiang@intel.com>
25 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
26 * Based on Xen 3.1 code.
29 #include <linux/kvm_host.h>
30 #include <linux/kvm.h>
32 #include <linux/highmem.h>
33 #include <linux/smp.h>
34 #include <linux/hrtimer.h>
36 #include <asm/processor.h>
38 #include <asm/current.h>
45 #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
47 #define ioapic_debug(fmt, arg...)
49 static int ioapic_deliver(struct kvm_ioapic
*vioapic
, int irq
);
51 static unsigned long ioapic_read_indirect(struct kvm_ioapic
*ioapic
,
55 unsigned long result
= 0;
57 switch (ioapic
->ioregsel
) {
58 case IOAPIC_REG_VERSION
:
59 result
= ((((IOAPIC_NUM_PINS
- 1) & 0xff) << 16)
60 | (IOAPIC_VERSION_ID
& 0xff));
63 case IOAPIC_REG_APIC_ID
:
64 case IOAPIC_REG_ARB_ID
:
65 result
= ((ioapic
->id
& 0xf) << 24);
70 u32 redir_index
= (ioapic
->ioregsel
- 0x10) >> 1;
73 ASSERT(redir_index
< IOAPIC_NUM_PINS
);
75 redir_content
= ioapic
->redirtbl
[redir_index
].bits
;
76 result
= (ioapic
->ioregsel
& 0x1) ?
77 (redir_content
>> 32) & 0xffffffff :
78 redir_content
& 0xffffffff;
86 static int ioapic_service(struct kvm_ioapic
*ioapic
, unsigned int idx
)
88 union kvm_ioapic_redirect_entry
*pent
;
91 pent
= &ioapic
->redirtbl
[idx
];
93 if (!pent
->fields
.mask
) {
94 injected
= ioapic_deliver(ioapic
, idx
);
95 if (injected
&& pent
->fields
.trig_mode
== IOAPIC_LEVEL_TRIG
)
96 pent
->fields
.remote_irr
= 1;
102 static void ioapic_write_indirect(struct kvm_ioapic
*ioapic
, u32 val
)
105 bool mask_before
, mask_after
;
107 switch (ioapic
->ioregsel
) {
108 case IOAPIC_REG_VERSION
:
109 /* Writes are ignored. */
112 case IOAPIC_REG_APIC_ID
:
113 ioapic
->id
= (val
>> 24) & 0xf;
116 case IOAPIC_REG_ARB_ID
:
120 index
= (ioapic
->ioregsel
- 0x10) >> 1;
122 ioapic_debug("change redir index %x val %x\n", index
, val
);
123 if (index
>= IOAPIC_NUM_PINS
)
125 mask_before
= ioapic
->redirtbl
[index
].fields
.mask
;
126 if (ioapic
->ioregsel
& 1) {
127 ioapic
->redirtbl
[index
].bits
&= 0xffffffff;
128 ioapic
->redirtbl
[index
].bits
|= (u64
) val
<< 32;
130 ioapic
->redirtbl
[index
].bits
&= ~0xffffffffULL
;
131 ioapic
->redirtbl
[index
].bits
|= (u32
) val
;
132 ioapic
->redirtbl
[index
].fields
.remote_irr
= 0;
134 mask_after
= ioapic
->redirtbl
[index
].fields
.mask
;
135 if (mask_before
!= mask_after
)
136 kvm_fire_mask_notifiers(ioapic
->kvm
, index
, mask_after
);
137 if (ioapic
->redirtbl
[index
].fields
.trig_mode
== IOAPIC_LEVEL_TRIG
138 && ioapic
->irr
& (1 << index
))
139 ioapic_service(ioapic
, index
);
144 static int ioapic_deliver(struct kvm_ioapic
*ioapic
, int irq
)
146 union kvm_ioapic_redirect_entry
*entry
= &ioapic
->redirtbl
[irq
];
147 struct kvm_lapic_irq irqe
;
149 ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
150 "vector=%x trig_mode=%x\n",
151 entry
->fields
.dest
, entry
->fields
.dest_mode
,
152 entry
->fields
.delivery_mode
, entry
->fields
.vector
,
153 entry
->fields
.trig_mode
);
155 irqe
.dest_id
= entry
->fields
.dest_id
;
156 irqe
.vector
= entry
->fields
.vector
;
157 irqe
.dest_mode
= entry
->fields
.dest_mode
;
158 irqe
.trig_mode
= entry
->fields
.trig_mode
;
159 irqe
.delivery_mode
= entry
->fields
.delivery_mode
<< 8;
164 /* Always delivery PIT interrupt to vcpu 0 */
166 irqe
.dest_mode
= 0; /* Physical mode. */
167 /* need to read apic_id from apic regiest since
168 * it can be rewritten */
169 irqe
.dest_id
= ioapic
->kvm
->bsp_vcpu
->vcpu_id
;
172 return kvm_irq_delivery_to_apic(ioapic
->kvm
, NULL
, &irqe
);
175 int kvm_ioapic_set_irq(struct kvm_ioapic
*ioapic
, int irq
, int level
)
177 u32 old_irr
= ioapic
->irr
;
179 union kvm_ioapic_redirect_entry entry
;
182 if (irq
>= 0 && irq
< IOAPIC_NUM_PINS
) {
183 entry
= ioapic
->redirtbl
[irq
];
184 level
^= entry
.fields
.polarity
;
186 ioapic
->irr
&= ~mask
;
188 int edge
= (entry
.fields
.trig_mode
== IOAPIC_EDGE_TRIG
);
190 if ((edge
&& old_irr
!= ioapic
->irr
) ||
191 (!edge
&& !entry
.fields
.remote_irr
))
192 ret
= ioapic_service(ioapic
, irq
);
198 static void __kvm_ioapic_update_eoi(struct kvm_ioapic
*ioapic
, int pin
,
201 union kvm_ioapic_redirect_entry
*ent
;
203 ent
= &ioapic
->redirtbl
[pin
];
205 kvm_notify_acked_irq(ioapic
->kvm
, KVM_IRQCHIP_IOAPIC
, pin
);
207 if (trigger_mode
== IOAPIC_LEVEL_TRIG
) {
208 ASSERT(ent
->fields
.trig_mode
== IOAPIC_LEVEL_TRIG
);
209 ent
->fields
.remote_irr
= 0;
210 if (!ent
->fields
.mask
&& (ioapic
->irr
& (1 << pin
)))
211 ioapic_service(ioapic
, pin
);
215 void kvm_ioapic_update_eoi(struct kvm
*kvm
, int vector
, int trigger_mode
)
217 struct kvm_ioapic
*ioapic
= kvm
->arch
.vioapic
;
220 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++)
221 if (ioapic
->redirtbl
[i
].fields
.vector
== vector
)
222 __kvm_ioapic_update_eoi(ioapic
, i
, trigger_mode
);
225 static inline struct kvm_ioapic
*to_ioapic(struct kvm_io_device
*dev
)
227 return container_of(dev
, struct kvm_ioapic
, dev
);
230 static inline int ioapic_in_range(struct kvm_ioapic
*ioapic
, gpa_t addr
)
232 return ((addr
>= ioapic
->base_address
&&
233 (addr
< ioapic
->base_address
+ IOAPIC_MEM_LENGTH
)));
236 static int ioapic_mmio_read(struct kvm_io_device
*this, gpa_t addr
, int len
,
239 struct kvm_ioapic
*ioapic
= to_ioapic(this);
241 if (!ioapic_in_range(ioapic
, addr
))
244 ioapic_debug("addr %lx\n", (unsigned long)addr
);
245 ASSERT(!(addr
& 0xf)); /* check alignment */
247 mutex_lock(&ioapic
->kvm
->irq_lock
);
250 case IOAPIC_REG_SELECT
:
251 result
= ioapic
->ioregsel
;
254 case IOAPIC_REG_WINDOW
:
255 result
= ioapic_read_indirect(ioapic
, addr
, len
);
264 *(u64
*) val
= result
;
269 memcpy(val
, (char *)&result
, len
);
272 printk(KERN_WARNING
"ioapic: wrong length %d\n", len
);
274 mutex_unlock(&ioapic
->kvm
->irq_lock
);
278 static int ioapic_mmio_write(struct kvm_io_device
*this, gpa_t addr
, int len
,
281 struct kvm_ioapic
*ioapic
= to_ioapic(this);
283 if (!ioapic_in_range(ioapic
, addr
))
286 ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
287 (void*)addr
, len
, val
);
288 ASSERT(!(addr
& 0xf)); /* check alignment */
290 mutex_lock(&ioapic
->kvm
->irq_lock
);
291 if (len
== 4 || len
== 8)
294 printk(KERN_WARNING
"ioapic: Unsupported size %d\n", len
);
300 case IOAPIC_REG_SELECT
:
301 ioapic
->ioregsel
= data
;
304 case IOAPIC_REG_WINDOW
:
305 ioapic_write_indirect(ioapic
, data
);
309 kvm_ioapic_update_eoi(ioapic
->kvm
, data
, IOAPIC_LEVEL_TRIG
);
316 mutex_unlock(&ioapic
->kvm
->irq_lock
);
320 void kvm_ioapic_reset(struct kvm_ioapic
*ioapic
)
324 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++)
325 ioapic
->redirtbl
[i
].fields
.mask
= 1;
326 ioapic
->base_address
= IOAPIC_DEFAULT_BASE_ADDRESS
;
327 ioapic
->ioregsel
= 0;
332 static const struct kvm_io_device_ops ioapic_mmio_ops
= {
333 .read
= ioapic_mmio_read
,
334 .write
= ioapic_mmio_write
,
337 int kvm_ioapic_init(struct kvm
*kvm
)
339 struct kvm_ioapic
*ioapic
;
341 ioapic
= kzalloc(sizeof(struct kvm_ioapic
), GFP_KERNEL
);
344 kvm
->arch
.vioapic
= ioapic
;
345 kvm_ioapic_reset(ioapic
);
346 kvm_iodevice_init(&ioapic
->dev
, &ioapic_mmio_ops
);
348 kvm_io_bus_register_dev(kvm
, &kvm
->mmio_bus
, &ioapic
->dev
);