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Merge branch 'for-rmk-fixes' of git://git.infradead.org/users/cbou/linux-cns3xxx
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / sh / fsi.c
1 /*
2 * Fifo-attached Serial Interface (FSI) support for SH7724
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ssi.c
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/delay.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <sound/soc.h>
20 #include <sound/sh_fsi.h>
21
22 #define DO_FMT 0x0000
23 #define DOFF_CTL 0x0004
24 #define DOFF_ST 0x0008
25 #define DI_FMT 0x000C
26 #define DIFF_CTL 0x0010
27 #define DIFF_ST 0x0014
28 #define CKG1 0x0018
29 #define CKG2 0x001C
30 #define DIDT 0x0020
31 #define DODT 0x0024
32 #define MUTE_ST 0x0028
33 #define OUT_SEL 0x0030
34 #define REG_END OUT_SEL
35
36 #define A_MST_CTLR 0x0180
37 #define B_MST_CTLR 0x01A0
38 #define CPU_INT_ST 0x01F4
39 #define CPU_IEMSK 0x01F8
40 #define CPU_IMSK 0x01FC
41 #define INT_ST 0x0200
42 #define IEMSK 0x0204
43 #define IMSK 0x0208
44 #define MUTE 0x020C
45 #define CLK_RST 0x0210
46 #define SOFT_RST 0x0214
47 #define FIFO_SZ 0x0218
48 #define MREG_START A_MST_CTLR
49 #define MREG_END FIFO_SZ
50
51 /* DO_FMT */
52 /* DI_FMT */
53 #define CR_MONO (0x0 << 4)
54 #define CR_MONO_D (0x1 << 4)
55 #define CR_PCM (0x2 << 4)
56 #define CR_I2S (0x3 << 4)
57 #define CR_TDM (0x4 << 4)
58 #define CR_TDM_D (0x5 << 4)
59 #define CR_SPDIF 0x00100120
60
61 /* DOFF_CTL */
62 /* DIFF_CTL */
63 #define IRQ_HALF 0x00100000
64 #define FIFO_CLR 0x00000001
65
66 /* DOFF_ST */
67 #define ERR_OVER 0x00000010
68 #define ERR_UNDER 0x00000001
69 #define ST_ERR (ERR_OVER | ERR_UNDER)
70
71 /* CKG1 */
72 #define ACKMD_MASK 0x00007000
73 #define BPFMD_MASK 0x00000700
74
75 /* A/B MST_CTLR */
76 #define BP (1 << 4) /* Fix the signal of Biphase output */
77 #define SE (1 << 0) /* Fix the master clock */
78
79 /* CLK_RST */
80 #define B_CLK 0x00000010
81 #define A_CLK 0x00000001
82
83 /* IO SHIFT / MACRO */
84 #define BI_SHIFT 12
85 #define BO_SHIFT 8
86 #define AI_SHIFT 4
87 #define AO_SHIFT 0
88 #define AB_IO(param, shift) (param << shift)
89
90 /* SOFT_RST */
91 #define PBSR (1 << 12) /* Port B Software Reset */
92 #define PASR (1 << 8) /* Port A Software Reset */
93 #define IR (1 << 4) /* Interrupt Reset */
94 #define FSISR (1 << 0) /* Software Reset */
95
96 /* FIFO_SZ */
97 #define FIFO_SZ_MASK 0x7
98
99 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
100
101 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
102
103 /*
104 * FSI driver use below type name for variable
105 *
106 * xxx_len : data length
107 * xxx_width : data width
108 * xxx_offset : data offset
109 * xxx_num : number of data
110 */
111
112 /*
113 * struct
114 */
115
116 struct fsi_stream {
117 struct snd_pcm_substream *substream;
118
119 int fifo_max_num;
120 int chan_num;
121
122 int buff_offset;
123 int buff_len;
124 int period_len;
125 int period_num;
126 };
127
128 struct fsi_priv {
129 void __iomem *base;
130 struct fsi_master *master;
131
132 struct fsi_stream playback;
133 struct fsi_stream capture;
134
135 long rate;
136
137 u32 mst_ctrl;
138 };
139
140 struct fsi_core {
141 int ver;
142
143 u32 int_st;
144 u32 iemsk;
145 u32 imsk;
146 };
147
148 struct fsi_master {
149 void __iomem *base;
150 int irq;
151 struct fsi_priv fsia;
152 struct fsi_priv fsib;
153 struct fsi_core *core;
154 struct sh_fsi_platform_info *info;
155 spinlock_t lock;
156 };
157
158 /*
159 * basic read write function
160 */
161
162 static void __fsi_reg_write(u32 reg, u32 data)
163 {
164 /* valid data area is 24bit */
165 data &= 0x00ffffff;
166
167 __raw_writel(data, reg);
168 }
169
170 static u32 __fsi_reg_read(u32 reg)
171 {
172 return __raw_readl(reg);
173 }
174
175 static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data)
176 {
177 u32 val = __fsi_reg_read(reg);
178
179 val &= ~mask;
180 val |= data & mask;
181
182 __fsi_reg_write(reg, val);
183 }
184
185 static void fsi_reg_write(struct fsi_priv *fsi, u32 reg, u32 data)
186 {
187 if (reg > REG_END) {
188 pr_err("fsi: register access err (%s)\n", __func__);
189 return;
190 }
191
192 __fsi_reg_write((u32)(fsi->base + reg), data);
193 }
194
195 static u32 fsi_reg_read(struct fsi_priv *fsi, u32 reg)
196 {
197 if (reg > REG_END) {
198 pr_err("fsi: register access err (%s)\n", __func__);
199 return 0;
200 }
201
202 return __fsi_reg_read((u32)(fsi->base + reg));
203 }
204
205 static void fsi_reg_mask_set(struct fsi_priv *fsi, u32 reg, u32 mask, u32 data)
206 {
207 if (reg > REG_END) {
208 pr_err("fsi: register access err (%s)\n", __func__);
209 return;
210 }
211
212 __fsi_reg_mask_set((u32)(fsi->base + reg), mask, data);
213 }
214
215 static void fsi_master_write(struct fsi_master *master, u32 reg, u32 data)
216 {
217 unsigned long flags;
218
219 if ((reg < MREG_START) ||
220 (reg > MREG_END)) {
221 pr_err("fsi: register access err (%s)\n", __func__);
222 return;
223 }
224
225 spin_lock_irqsave(&master->lock, flags);
226 __fsi_reg_write((u32)(master->base + reg), data);
227 spin_unlock_irqrestore(&master->lock, flags);
228 }
229
230 static u32 fsi_master_read(struct fsi_master *master, u32 reg)
231 {
232 u32 ret;
233 unsigned long flags;
234
235 if ((reg < MREG_START) ||
236 (reg > MREG_END)) {
237 pr_err("fsi: register access err (%s)\n", __func__);
238 return 0;
239 }
240
241 spin_lock_irqsave(&master->lock, flags);
242 ret = __fsi_reg_read((u32)(master->base + reg));
243 spin_unlock_irqrestore(&master->lock, flags);
244
245 return ret;
246 }
247
248 static void fsi_master_mask_set(struct fsi_master *master,
249 u32 reg, u32 mask, u32 data)
250 {
251 unsigned long flags;
252
253 if ((reg < MREG_START) ||
254 (reg > MREG_END)) {
255 pr_err("fsi: register access err (%s)\n", __func__);
256 return;
257 }
258
259 spin_lock_irqsave(&master->lock, flags);
260 __fsi_reg_mask_set((u32)(master->base + reg), mask, data);
261 spin_unlock_irqrestore(&master->lock, flags);
262 }
263
264 /*
265 * basic function
266 */
267
268 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
269 {
270 return fsi->master;
271 }
272
273 static int fsi_is_port_a(struct fsi_priv *fsi)
274 {
275 return fsi->master->base == fsi->base;
276 }
277
278 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
279 {
280 struct snd_soc_pcm_runtime *rtd = substream->private_data;
281
282 return rtd->cpu_dai;
283 }
284
285 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
286 {
287 struct snd_soc_dai *dai = fsi_get_dai(substream);
288 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
289
290 if (dai->id == 0)
291 return &master->fsia;
292 else
293 return &master->fsib;
294 }
295
296 static u32 fsi_get_info_flags(struct fsi_priv *fsi)
297 {
298 int is_porta = fsi_is_port_a(fsi);
299 struct fsi_master *master = fsi_get_master(fsi);
300
301 return is_porta ? master->info->porta_flags :
302 master->info->portb_flags;
303 }
304
305 static inline int fsi_stream_is_play(int stream)
306 {
307 return stream == SNDRV_PCM_STREAM_PLAYBACK;
308 }
309
310 static inline int fsi_is_play(struct snd_pcm_substream *substream)
311 {
312 return fsi_stream_is_play(substream->stream);
313 }
314
315 static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi,
316 int is_play)
317 {
318 return is_play ? &fsi->playback : &fsi->capture;
319 }
320
321 static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play)
322 {
323 u32 mode;
324 u32 flags = fsi_get_info_flags(fsi);
325
326 mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE;
327
328 /* return
329 * 1 : master mode
330 * 0 : slave mode
331 */
332
333 return (mode & flags) != mode;
334 }
335
336 static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play)
337 {
338 int is_porta = fsi_is_port_a(fsi);
339 u32 shift;
340
341 if (is_porta)
342 shift = is_play ? AO_SHIFT : AI_SHIFT;
343 else
344 shift = is_play ? BO_SHIFT : BI_SHIFT;
345
346 return shift;
347 }
348
349 static void fsi_stream_push(struct fsi_priv *fsi,
350 int is_play,
351 struct snd_pcm_substream *substream,
352 u32 buffer_len,
353 u32 period_len)
354 {
355 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
356
357 io->substream = substream;
358 io->buff_len = buffer_len;
359 io->buff_offset = 0;
360 io->period_len = period_len;
361 io->period_num = 0;
362 }
363
364 static void fsi_stream_pop(struct fsi_priv *fsi, int is_play)
365 {
366 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
367
368 io->substream = NULL;
369 io->buff_len = 0;
370 io->buff_offset = 0;
371 io->period_len = 0;
372 io->period_num = 0;
373 }
374
375 static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play)
376 {
377 u32 status;
378 u32 reg = is_play ? DOFF_ST : DIFF_ST;
379 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
380 int data_num;
381
382 status = fsi_reg_read(fsi, reg);
383 data_num = 0x1ff & (status >> 8);
384 data_num *= io->chan_num;
385
386 return data_num;
387 }
388
389 static int fsi_len2num(int len, int width)
390 {
391 return len / width;
392 }
393
394 #define fsi_num2offset(a, b) fsi_num2len(a, b)
395 static int fsi_num2len(int num, int width)
396 {
397 return num * width;
398 }
399
400 static int fsi_get_frame_width(struct fsi_priv *fsi, int is_play)
401 {
402 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
403 struct snd_pcm_substream *substream = io->substream;
404 struct snd_pcm_runtime *runtime = substream->runtime;
405
406 return frames_to_bytes(runtime, 1) / io->chan_num;
407 }
408
409 /*
410 * dma function
411 */
412
413 static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream)
414 {
415 int is_play = fsi_stream_is_play(stream);
416 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
417
418 return io->substream->runtime->dma_area + io->buff_offset;
419 }
420
421 static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num)
422 {
423 u16 *start;
424 int i;
425
426 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
427
428 for (i = 0; i < num; i++)
429 fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8));
430 }
431
432 static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num)
433 {
434 u16 *start;
435 int i;
436
437 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
438
439
440 for (i = 0; i < num; i++)
441 *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
442 }
443
444 static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num)
445 {
446 u32 *start;
447 int i;
448
449 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
450
451
452 for (i = 0; i < num; i++)
453 fsi_reg_write(fsi, DODT, *(start + i));
454 }
455
456 static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num)
457 {
458 u32 *start;
459 int i;
460
461 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
462
463 for (i = 0; i < num; i++)
464 *(start + i) = fsi_reg_read(fsi, DIDT);
465 }
466
467 /*
468 * irq function
469 */
470
471 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
472 {
473 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
474 struct fsi_master *master = fsi_get_master(fsi);
475
476 fsi_master_mask_set(master, master->core->imsk, data, data);
477 fsi_master_mask_set(master, master->core->iemsk, data, data);
478 }
479
480 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
481 {
482 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
483 struct fsi_master *master = fsi_get_master(fsi);
484
485 fsi_master_mask_set(master, master->core->imsk, data, 0);
486 fsi_master_mask_set(master, master->core->iemsk, data, 0);
487 }
488
489 static u32 fsi_irq_get_status(struct fsi_master *master)
490 {
491 return fsi_master_read(master, master->core->int_st);
492 }
493
494 static void fsi_irq_clear_all_status(struct fsi_master *master)
495 {
496 fsi_master_write(master, master->core->int_st, 0);
497 }
498
499 static void fsi_irq_clear_status(struct fsi_priv *fsi)
500 {
501 u32 data = 0;
502 struct fsi_master *master = fsi_get_master(fsi);
503
504 data |= AB_IO(1, fsi_get_port_shift(fsi, 0));
505 data |= AB_IO(1, fsi_get_port_shift(fsi, 1));
506
507 /* clear interrupt factor */
508 fsi_master_mask_set(master, master->core->int_st, data, 0);
509 }
510
511 /*
512 * SPDIF master clock function
513 *
514 * These functions are used later FSI2
515 */
516 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
517 {
518 struct fsi_master *master = fsi_get_master(fsi);
519 u32 val = BP | SE;
520
521 if (master->core->ver < 2) {
522 pr_err("fsi: register access err (%s)\n", __func__);
523 return;
524 }
525
526 if (enable)
527 fsi_master_mask_set(master, fsi->mst_ctrl, val, val);
528 else
529 fsi_master_mask_set(master, fsi->mst_ctrl, val, 0);
530 }
531
532 /*
533 * ctrl function
534 */
535
536 static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable)
537 {
538 u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4);
539 struct fsi_master *master = fsi_get_master(fsi);
540
541 if (enable)
542 fsi_master_mask_set(master, CLK_RST, val, val);
543 else
544 fsi_master_mask_set(master, CLK_RST, val, 0);
545 }
546
547 static void fsi_fifo_init(struct fsi_priv *fsi,
548 int is_play,
549 struct snd_soc_dai *dai)
550 {
551 struct fsi_master *master = fsi_get_master(fsi);
552 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
553 u32 ctrl, shift, i;
554
555 /* get on-chip RAM capacity */
556 shift = fsi_master_read(master, FIFO_SZ);
557 shift >>= fsi_get_port_shift(fsi, is_play);
558 shift &= FIFO_SZ_MASK;
559 io->fifo_max_num = 256 << shift;
560 dev_dbg(dai->dev, "fifo = %d words\n", io->fifo_max_num);
561
562 /*
563 * The maximum number of sample data varies depending
564 * on the number of channels selected for the format.
565 *
566 * FIFOs are used in 4-channel units in 3-channel mode
567 * and in 8-channel units in 5- to 7-channel mode
568 * meaning that more FIFOs than the required size of DPRAM
569 * are used.
570 *
571 * ex) if 256 words of DP-RAM is connected
572 * 1 channel: 256 (256 x 1 = 256)
573 * 2 channels: 128 (128 x 2 = 256)
574 * 3 channels: 64 ( 64 x 3 = 192)
575 * 4 channels: 64 ( 64 x 4 = 256)
576 * 5 channels: 32 ( 32 x 5 = 160)
577 * 6 channels: 32 ( 32 x 6 = 192)
578 * 7 channels: 32 ( 32 x 7 = 224)
579 * 8 channels: 32 ( 32 x 8 = 256)
580 */
581 for (i = 1; i < io->chan_num; i <<= 1)
582 io->fifo_max_num >>= 1;
583 dev_dbg(dai->dev, "%d channel %d store\n",
584 io->chan_num, io->fifo_max_num);
585
586 ctrl = is_play ? DOFF_CTL : DIFF_CTL;
587
588 /* set interrupt generation factor */
589 fsi_reg_write(fsi, ctrl, IRQ_HALF);
590
591 /* clear FIFO */
592 fsi_reg_mask_set(fsi, ctrl, FIFO_CLR, FIFO_CLR);
593 }
594
595 static void fsi_soft_all_reset(struct fsi_master *master)
596 {
597 /* port AB reset */
598 fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0);
599 mdelay(10);
600
601 /* soft reset */
602 fsi_master_mask_set(master, SOFT_RST, FSISR, 0);
603 fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR);
604 mdelay(10);
605 }
606
607 static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int startup, int stream)
608 {
609 struct snd_pcm_runtime *runtime;
610 struct snd_pcm_substream *substream = NULL;
611 int is_play = fsi_stream_is_play(stream);
612 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
613 u32 status_reg = is_play ? DOFF_ST : DIFF_ST;
614 int data_residue_num;
615 int data_num;
616 int data_num_max;
617 int ch_width;
618 int over_period;
619 void (*fn)(struct fsi_priv *fsi, int size);
620
621 if (!fsi ||
622 !io->substream ||
623 !io->substream->runtime)
624 return -EINVAL;
625
626 over_period = 0;
627 substream = io->substream;
628 runtime = substream->runtime;
629
630 /* FSI FIFO has limit.
631 * So, this driver can not send periods data at a time
632 */
633 if (io->buff_offset >=
634 fsi_num2offset(io->period_num + 1, io->period_len)) {
635
636 over_period = 1;
637 io->period_num = (io->period_num + 1) % runtime->periods;
638
639 if (0 == io->period_num)
640 io->buff_offset = 0;
641 }
642
643 /* get 1 channel data width */
644 ch_width = fsi_get_frame_width(fsi, is_play);
645
646 /* get residue data number of alsa */
647 data_residue_num = fsi_len2num(io->buff_len - io->buff_offset,
648 ch_width);
649
650 if (is_play) {
651 /*
652 * for play-back
653 *
654 * data_num_max : number of FSI fifo free space
655 * data_num : number of ALSA residue data
656 */
657 data_num_max = io->fifo_max_num * io->chan_num;
658 data_num_max -= fsi_get_fifo_data_num(fsi, is_play);
659
660 data_num = data_residue_num;
661
662 switch (ch_width) {
663 case 2:
664 fn = fsi_dma_soft_push16;
665 break;
666 case 4:
667 fn = fsi_dma_soft_push32;
668 break;
669 default:
670 return -EINVAL;
671 }
672 } else {
673 /*
674 * for capture
675 *
676 * data_num_max : number of ALSA free space
677 * data_num : number of data in FSI fifo
678 */
679 data_num_max = data_residue_num;
680 data_num = fsi_get_fifo_data_num(fsi, is_play);
681
682 switch (ch_width) {
683 case 2:
684 fn = fsi_dma_soft_pop16;
685 break;
686 case 4:
687 fn = fsi_dma_soft_pop32;
688 break;
689 default:
690 return -EINVAL;
691 }
692 }
693
694 data_num = min(data_num, data_num_max);
695
696 fn(fsi, data_num);
697
698 /* update buff_offset */
699 io->buff_offset += fsi_num2offset(data_num, ch_width);
700
701 /* check fifo status */
702 if (!startup) {
703 struct snd_soc_dai *dai = fsi_get_dai(substream);
704 u32 status = fsi_reg_read(fsi, status_reg);
705
706 if (status & ERR_OVER)
707 dev_err(dai->dev, "over run\n");
708 if (status & ERR_UNDER)
709 dev_err(dai->dev, "under run\n");
710 }
711 fsi_reg_write(fsi, status_reg, 0);
712
713 /* re-enable irq */
714 fsi_irq_enable(fsi, is_play);
715
716 if (over_period)
717 snd_pcm_period_elapsed(substream);
718
719 return 0;
720 }
721
722 static int fsi_data_pop(struct fsi_priv *fsi, int startup)
723 {
724 return fsi_fifo_data_ctrl(fsi, startup, SNDRV_PCM_STREAM_CAPTURE);
725 }
726
727 static int fsi_data_push(struct fsi_priv *fsi, int startup)
728 {
729 return fsi_fifo_data_ctrl(fsi, startup, SNDRV_PCM_STREAM_PLAYBACK);
730 }
731
732 static irqreturn_t fsi_interrupt(int irq, void *data)
733 {
734 struct fsi_master *master = data;
735 u32 int_st = fsi_irq_get_status(master);
736
737 /* clear irq status */
738 fsi_master_mask_set(master, SOFT_RST, IR, 0);
739 fsi_master_mask_set(master, SOFT_RST, IR, IR);
740
741 if (int_st & AB_IO(1, AO_SHIFT))
742 fsi_data_push(&master->fsia, 0);
743 if (int_st & AB_IO(1, BO_SHIFT))
744 fsi_data_push(&master->fsib, 0);
745 if (int_st & AB_IO(1, AI_SHIFT))
746 fsi_data_pop(&master->fsia, 0);
747 if (int_st & AB_IO(1, BI_SHIFT))
748 fsi_data_pop(&master->fsib, 0);
749
750 fsi_irq_clear_all_status(master);
751
752 return IRQ_HANDLED;
753 }
754
755 /*
756 * dai ops
757 */
758
759 static int fsi_dai_startup(struct snd_pcm_substream *substream,
760 struct snd_soc_dai *dai)
761 {
762 struct fsi_priv *fsi = fsi_get_priv(substream);
763 struct fsi_master *master = fsi_get_master(fsi);
764 struct fsi_stream *io;
765 u32 flags = fsi_get_info_flags(fsi);
766 u32 fmt;
767 u32 reg;
768 u32 data;
769 int is_play = fsi_is_play(substream);
770 int is_master;
771
772 io = fsi_get_stream(fsi, is_play);
773
774 pm_runtime_get_sync(dai->dev);
775
776 /* CKG1 */
777 data = is_play ? (1 << 0) : (1 << 4);
778 is_master = fsi_is_master_mode(fsi, is_play);
779 if (is_master)
780 fsi_reg_mask_set(fsi, CKG1, data, data);
781 else
782 fsi_reg_mask_set(fsi, CKG1, data, 0);
783
784 /* clock inversion (CKG2) */
785 data = 0;
786 if (SH_FSI_LRM_INV & flags)
787 data |= 1 << 12;
788 if (SH_FSI_BRM_INV & flags)
789 data |= 1 << 8;
790 if (SH_FSI_LRS_INV & flags)
791 data |= 1 << 4;
792 if (SH_FSI_BRS_INV & flags)
793 data |= 1 << 0;
794
795 fsi_reg_write(fsi, CKG2, data);
796
797 /* do fmt, di fmt */
798 data = 0;
799 reg = is_play ? DO_FMT : DI_FMT;
800 fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags);
801 switch (fmt) {
802 case SH_FSI_FMT_MONO:
803 data = CR_MONO;
804 io->chan_num = 1;
805 break;
806 case SH_FSI_FMT_MONO_DELAY:
807 data = CR_MONO_D;
808 io->chan_num = 1;
809 break;
810 case SH_FSI_FMT_PCM:
811 data = CR_PCM;
812 io->chan_num = 2;
813 break;
814 case SH_FSI_FMT_I2S:
815 data = CR_I2S;
816 io->chan_num = 2;
817 break;
818 case SH_FSI_FMT_TDM:
819 io->chan_num = is_play ?
820 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
821 data = CR_TDM | (io->chan_num - 1);
822 break;
823 case SH_FSI_FMT_TDM_DELAY:
824 io->chan_num = is_play ?
825 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
826 data = CR_TDM_D | (io->chan_num - 1);
827 break;
828 case SH_FSI_FMT_SPDIF:
829 if (master->core->ver < 2) {
830 dev_err(dai->dev, "This FSI can not use SPDIF\n");
831 return -EINVAL;
832 }
833 data = CR_SPDIF;
834 io->chan_num = 2;
835 fsi_spdif_clk_ctrl(fsi, 1);
836 fsi_reg_mask_set(fsi, OUT_SEL, 0x0010, 0x0010);
837 break;
838 default:
839 dev_err(dai->dev, "unknown format.\n");
840 return -EINVAL;
841 }
842 fsi_reg_write(fsi, reg, data);
843
844 /* irq clear */
845 fsi_irq_disable(fsi, is_play);
846 fsi_irq_clear_status(fsi);
847
848 /* fifo init */
849 fsi_fifo_init(fsi, is_play, dai);
850
851 return 0;
852 }
853
854 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
855 struct snd_soc_dai *dai)
856 {
857 struct fsi_priv *fsi = fsi_get_priv(substream);
858 int is_play = fsi_is_play(substream);
859 struct fsi_master *master = fsi_get_master(fsi);
860 int (*set_rate)(struct device *dev, int is_porta, int rate, int enable);
861
862 fsi_irq_disable(fsi, is_play);
863 fsi_clk_ctrl(fsi, 0);
864
865 set_rate = master->info->set_rate;
866 if (set_rate && fsi->rate)
867 set_rate(dai->dev, fsi_is_port_a(fsi), fsi->rate, 0);
868 fsi->rate = 0;
869
870 pm_runtime_put_sync(dai->dev);
871 }
872
873 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
874 struct snd_soc_dai *dai)
875 {
876 struct fsi_priv *fsi = fsi_get_priv(substream);
877 struct snd_pcm_runtime *runtime = substream->runtime;
878 int is_play = fsi_is_play(substream);
879 int ret = 0;
880
881 switch (cmd) {
882 case SNDRV_PCM_TRIGGER_START:
883 fsi_stream_push(fsi, is_play, substream,
884 frames_to_bytes(runtime, runtime->buffer_size),
885 frames_to_bytes(runtime, runtime->period_size));
886 ret = is_play ? fsi_data_push(fsi, 1) : fsi_data_pop(fsi, 1);
887 break;
888 case SNDRV_PCM_TRIGGER_STOP:
889 fsi_irq_disable(fsi, is_play);
890 fsi_stream_pop(fsi, is_play);
891 break;
892 }
893
894 return ret;
895 }
896
897 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
898 struct snd_pcm_hw_params *params,
899 struct snd_soc_dai *dai)
900 {
901 struct fsi_priv *fsi = fsi_get_priv(substream);
902 struct fsi_master *master = fsi_get_master(fsi);
903 int (*set_rate)(struct device *dev, int is_porta, int rate, int enable);
904 int fsi_ver = master->core->ver;
905 long rate = params_rate(params);
906 int ret;
907
908 set_rate = master->info->set_rate;
909 if (!set_rate)
910 return 0;
911
912 ret = set_rate(dai->dev, fsi_is_port_a(fsi), rate, 1);
913 if (ret < 0) /* error */
914 return ret;
915
916 fsi->rate = rate;
917 if (ret > 0) {
918 u32 data = 0;
919
920 switch (ret & SH_FSI_ACKMD_MASK) {
921 default:
922 /* FALL THROUGH */
923 case SH_FSI_ACKMD_512:
924 data |= (0x0 << 12);
925 break;
926 case SH_FSI_ACKMD_256:
927 data |= (0x1 << 12);
928 break;
929 case SH_FSI_ACKMD_128:
930 data |= (0x2 << 12);
931 break;
932 case SH_FSI_ACKMD_64:
933 data |= (0x3 << 12);
934 break;
935 case SH_FSI_ACKMD_32:
936 if (fsi_ver < 2)
937 dev_err(dai->dev, "unsupported ACKMD\n");
938 else
939 data |= (0x4 << 12);
940 break;
941 }
942
943 switch (ret & SH_FSI_BPFMD_MASK) {
944 default:
945 /* FALL THROUGH */
946 case SH_FSI_BPFMD_32:
947 data |= (0x0 << 8);
948 break;
949 case SH_FSI_BPFMD_64:
950 data |= (0x1 << 8);
951 break;
952 case SH_FSI_BPFMD_128:
953 data |= (0x2 << 8);
954 break;
955 case SH_FSI_BPFMD_256:
956 data |= (0x3 << 8);
957 break;
958 case SH_FSI_BPFMD_512:
959 data |= (0x4 << 8);
960 break;
961 case SH_FSI_BPFMD_16:
962 if (fsi_ver < 2)
963 dev_err(dai->dev, "unsupported ACKMD\n");
964 else
965 data |= (0x7 << 8);
966 break;
967 }
968
969 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
970 udelay(10);
971 fsi_clk_ctrl(fsi, 1);
972 ret = 0;
973 }
974
975 return ret;
976
977 }
978
979 static struct snd_soc_dai_ops fsi_dai_ops = {
980 .startup = fsi_dai_startup,
981 .shutdown = fsi_dai_shutdown,
982 .trigger = fsi_dai_trigger,
983 .hw_params = fsi_dai_hw_params,
984 };
985
986 /*
987 * pcm ops
988 */
989
990 static struct snd_pcm_hardware fsi_pcm_hardware = {
991 .info = SNDRV_PCM_INFO_INTERLEAVED |
992 SNDRV_PCM_INFO_MMAP |
993 SNDRV_PCM_INFO_MMAP_VALID |
994 SNDRV_PCM_INFO_PAUSE,
995 .formats = FSI_FMTS,
996 .rates = FSI_RATES,
997 .rate_min = 8000,
998 .rate_max = 192000,
999 .channels_min = 1,
1000 .channels_max = 2,
1001 .buffer_bytes_max = 64 * 1024,
1002 .period_bytes_min = 32,
1003 .period_bytes_max = 8192,
1004 .periods_min = 1,
1005 .periods_max = 32,
1006 .fifo_size = 256,
1007 };
1008
1009 static int fsi_pcm_open(struct snd_pcm_substream *substream)
1010 {
1011 struct snd_pcm_runtime *runtime = substream->runtime;
1012 int ret = 0;
1013
1014 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
1015
1016 ret = snd_pcm_hw_constraint_integer(runtime,
1017 SNDRV_PCM_HW_PARAM_PERIODS);
1018
1019 return ret;
1020 }
1021
1022 static int fsi_hw_params(struct snd_pcm_substream *substream,
1023 struct snd_pcm_hw_params *hw_params)
1024 {
1025 return snd_pcm_lib_malloc_pages(substream,
1026 params_buffer_bytes(hw_params));
1027 }
1028
1029 static int fsi_hw_free(struct snd_pcm_substream *substream)
1030 {
1031 return snd_pcm_lib_free_pages(substream);
1032 }
1033
1034 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
1035 {
1036 struct snd_pcm_runtime *runtime = substream->runtime;
1037 struct fsi_priv *fsi = fsi_get_priv(substream);
1038 struct fsi_stream *io = fsi_get_stream(fsi, fsi_is_play(substream));
1039 long location;
1040
1041 location = (io->buff_offset - 1);
1042 if (location < 0)
1043 location = 0;
1044
1045 return bytes_to_frames(runtime, location);
1046 }
1047
1048 static struct snd_pcm_ops fsi_pcm_ops = {
1049 .open = fsi_pcm_open,
1050 .ioctl = snd_pcm_lib_ioctl,
1051 .hw_params = fsi_hw_params,
1052 .hw_free = fsi_hw_free,
1053 .pointer = fsi_pointer,
1054 };
1055
1056 /*
1057 * snd_soc_platform
1058 */
1059
1060 #define PREALLOC_BUFFER (32 * 1024)
1061 #define PREALLOC_BUFFER_MAX (32 * 1024)
1062
1063 static void fsi_pcm_free(struct snd_pcm *pcm)
1064 {
1065 snd_pcm_lib_preallocate_free_for_all(pcm);
1066 }
1067
1068 static int fsi_pcm_new(struct snd_card *card,
1069 struct snd_soc_dai *dai,
1070 struct snd_pcm *pcm)
1071 {
1072 /*
1073 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
1074 * in MMAP mode (i.e. aplay -M)
1075 */
1076 return snd_pcm_lib_preallocate_pages_for_all(
1077 pcm,
1078 SNDRV_DMA_TYPE_CONTINUOUS,
1079 snd_dma_continuous_data(GFP_KERNEL),
1080 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1081 }
1082
1083 /*
1084 * alsa struct
1085 */
1086
1087 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1088 {
1089 .name = "fsia-dai",
1090 .playback = {
1091 .rates = FSI_RATES,
1092 .formats = FSI_FMTS,
1093 .channels_min = 1,
1094 .channels_max = 8,
1095 },
1096 .capture = {
1097 .rates = FSI_RATES,
1098 .formats = FSI_FMTS,
1099 .channels_min = 1,
1100 .channels_max = 8,
1101 },
1102 .ops = &fsi_dai_ops,
1103 },
1104 {
1105 .name = "fsib-dai",
1106 .playback = {
1107 .rates = FSI_RATES,
1108 .formats = FSI_FMTS,
1109 .channels_min = 1,
1110 .channels_max = 8,
1111 },
1112 .capture = {
1113 .rates = FSI_RATES,
1114 .formats = FSI_FMTS,
1115 .channels_min = 1,
1116 .channels_max = 8,
1117 },
1118 .ops = &fsi_dai_ops,
1119 },
1120 };
1121
1122 static struct snd_soc_platform_driver fsi_soc_platform = {
1123 .ops = &fsi_pcm_ops,
1124 .pcm_new = fsi_pcm_new,
1125 .pcm_free = fsi_pcm_free,
1126 };
1127
1128 /*
1129 * platform function
1130 */
1131
1132 static int fsi_probe(struct platform_device *pdev)
1133 {
1134 struct fsi_master *master;
1135 const struct platform_device_id *id_entry;
1136 struct resource *res;
1137 unsigned int irq;
1138 int ret;
1139
1140 id_entry = pdev->id_entry;
1141 if (!id_entry) {
1142 dev_err(&pdev->dev, "unknown fsi device\n");
1143 return -ENODEV;
1144 }
1145
1146 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1147 irq = platform_get_irq(pdev, 0);
1148 if (!res || (int)irq <= 0) {
1149 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1150 ret = -ENODEV;
1151 goto exit;
1152 }
1153
1154 master = kzalloc(sizeof(*master), GFP_KERNEL);
1155 if (!master) {
1156 dev_err(&pdev->dev, "Could not allocate master\n");
1157 ret = -ENOMEM;
1158 goto exit;
1159 }
1160
1161 master->base = ioremap_nocache(res->start, resource_size(res));
1162 if (!master->base) {
1163 ret = -ENXIO;
1164 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1165 goto exit_kfree;
1166 }
1167
1168 /* master setting */
1169 master->irq = irq;
1170 master->info = pdev->dev.platform_data;
1171 master->core = (struct fsi_core *)id_entry->driver_data;
1172 spin_lock_init(&master->lock);
1173
1174 /* FSI A setting */
1175 master->fsia.base = master->base;
1176 master->fsia.master = master;
1177 master->fsia.mst_ctrl = A_MST_CTLR;
1178
1179 /* FSI B setting */
1180 master->fsib.base = master->base + 0x40;
1181 master->fsib.master = master;
1182 master->fsib.mst_ctrl = B_MST_CTLR;
1183
1184 pm_runtime_enable(&pdev->dev);
1185 pm_runtime_resume(&pdev->dev);
1186 dev_set_drvdata(&pdev->dev, master);
1187
1188 fsi_soft_all_reset(master);
1189
1190 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED,
1191 id_entry->name, master);
1192 if (ret) {
1193 dev_err(&pdev->dev, "irq request err\n");
1194 goto exit_iounmap;
1195 }
1196
1197 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
1198 if (ret < 0) {
1199 dev_err(&pdev->dev, "cannot snd soc register\n");
1200 goto exit_free_irq;
1201 }
1202
1203 return snd_soc_register_dais(&pdev->dev, fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
1204
1205 exit_free_irq:
1206 free_irq(irq, master);
1207 exit_iounmap:
1208 iounmap(master->base);
1209 pm_runtime_disable(&pdev->dev);
1210 exit_kfree:
1211 kfree(master);
1212 master = NULL;
1213 exit:
1214 return ret;
1215 }
1216
1217 static int fsi_remove(struct platform_device *pdev)
1218 {
1219 struct fsi_master *master;
1220
1221 master = dev_get_drvdata(&pdev->dev);
1222
1223 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai));
1224 snd_soc_unregister_platform(&pdev->dev);
1225
1226 pm_runtime_disable(&pdev->dev);
1227
1228 free_irq(master->irq, master);
1229
1230 iounmap(master->base);
1231 kfree(master);
1232
1233 return 0;
1234 }
1235
1236 static int fsi_runtime_nop(struct device *dev)
1237 {
1238 /* Runtime PM callback shared between ->runtime_suspend()
1239 * and ->runtime_resume(). Simply returns success.
1240 *
1241 * This driver re-initializes all registers after
1242 * pm_runtime_get_sync() anyway so there is no need
1243 * to save and restore registers here.
1244 */
1245 return 0;
1246 }
1247
1248 static struct dev_pm_ops fsi_pm_ops = {
1249 .runtime_suspend = fsi_runtime_nop,
1250 .runtime_resume = fsi_runtime_nop,
1251 };
1252
1253 static struct fsi_core fsi1_core = {
1254 .ver = 1,
1255
1256 /* Interrupt */
1257 .int_st = INT_ST,
1258 .iemsk = IEMSK,
1259 .imsk = IMSK,
1260 };
1261
1262 static struct fsi_core fsi2_core = {
1263 .ver = 2,
1264
1265 /* Interrupt */
1266 .int_st = CPU_INT_ST,
1267 .iemsk = CPU_IEMSK,
1268 .imsk = CPU_IMSK,
1269 };
1270
1271 static struct platform_device_id fsi_id_table[] = {
1272 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
1273 { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
1274 {},
1275 };
1276 MODULE_DEVICE_TABLE(platform, fsi_id_table);
1277
1278 static struct platform_driver fsi_driver = {
1279 .driver = {
1280 .name = "fsi-pcm-audio",
1281 .pm = &fsi_pm_ops,
1282 },
1283 .probe = fsi_probe,
1284 .remove = fsi_remove,
1285 .id_table = fsi_id_table,
1286 };
1287
1288 static int __init fsi_mobile_init(void)
1289 {
1290 return platform_driver_register(&fsi_driver);
1291 }
1292
1293 static void __exit fsi_mobile_exit(void)
1294 {
1295 platform_driver_unregister(&fsi_driver);
1296 }
1297
1298 module_init(fsi_mobile_init);
1299 module_exit(fsi_mobile_exit);
1300
1301 MODULE_LICENSE("GPL");
1302 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
1303 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
kernel source for telekom puls (alcatel/mediatek)