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[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / sound / soc / sh / fsi.c
1 /*
2 * Fifo-attached Serial Interface (FSI) support for SH7724
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ssi.c
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/delay.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <sound/soc.h>
20 #include <sound/sh_fsi.h>
21
22 /* PortA/PortB register */
23 #define REG_DO_FMT 0x0000
24 #define REG_DOFF_CTL 0x0004
25 #define REG_DOFF_ST 0x0008
26 #define REG_DI_FMT 0x000C
27 #define REG_DIFF_CTL 0x0010
28 #define REG_DIFF_ST 0x0014
29 #define REG_CKG1 0x0018
30 #define REG_CKG2 0x001C
31 #define REG_DIDT 0x0020
32 #define REG_DODT 0x0024
33 #define REG_MUTE_ST 0x0028
34 #define REG_OUT_SEL 0x0030
35
36 /* master register */
37 #define MST_CLK_RST 0x0210
38 #define MST_SOFT_RST 0x0214
39 #define MST_FIFO_SZ 0x0218
40
41 /* core register (depend on FSI version) */
42 #define A_MST_CTLR 0x0180
43 #define B_MST_CTLR 0x01A0
44 #define CPU_INT_ST 0x01F4
45 #define CPU_IEMSK 0x01F8
46 #define CPU_IMSK 0x01FC
47 #define INT_ST 0x0200
48 #define IEMSK 0x0204
49 #define IMSK 0x0208
50
51 /* DO_FMT */
52 /* DI_FMT */
53 #define CR_BWS_24 (0x0 << 20) /* FSI2 */
54 #define CR_BWS_16 (0x1 << 20) /* FSI2 */
55 #define CR_BWS_20 (0x2 << 20) /* FSI2 */
56
57 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
58 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
59 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
60
61 #define CR_MONO (0x0 << 4)
62 #define CR_MONO_D (0x1 << 4)
63 #define CR_PCM (0x2 << 4)
64 #define CR_I2S (0x3 << 4)
65 #define CR_TDM (0x4 << 4)
66 #define CR_TDM_D (0x5 << 4)
67
68 /* DOFF_CTL */
69 /* DIFF_CTL */
70 #define IRQ_HALF 0x00100000
71 #define FIFO_CLR 0x00000001
72
73 /* DOFF_ST */
74 #define ERR_OVER 0x00000010
75 #define ERR_UNDER 0x00000001
76 #define ST_ERR (ERR_OVER | ERR_UNDER)
77
78 /* CKG1 */
79 #define ACKMD_MASK 0x00007000
80 #define BPFMD_MASK 0x00000700
81 #define DIMD (1 << 4)
82 #define DOMD (1 << 0)
83
84 /* A/B MST_CTLR */
85 #define BP (1 << 4) /* Fix the signal of Biphase output */
86 #define SE (1 << 0) /* Fix the master clock */
87
88 /* CLK_RST */
89 #define B_CLK 0x00000010
90 #define A_CLK 0x00000001
91
92 /* IO SHIFT / MACRO */
93 #define BI_SHIFT 12
94 #define BO_SHIFT 8
95 #define AI_SHIFT 4
96 #define AO_SHIFT 0
97 #define AB_IO(param, shift) (param << shift)
98
99 /* SOFT_RST */
100 #define PBSR (1 << 12) /* Port B Software Reset */
101 #define PASR (1 << 8) /* Port A Software Reset */
102 #define IR (1 << 4) /* Interrupt Reset */
103 #define FSISR (1 << 0) /* Software Reset */
104
105 /* OUT_SEL (FSI2) */
106 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
107 /* 1: Biphase and serial */
108
109 /* FIFO_SZ */
110 #define FIFO_SZ_MASK 0x7
111
112 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
113
114 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
115
116 typedef int (*set_rate_func)(struct device *dev, int is_porta, int rate, int enable);
117
118 /*
119 * FSI driver use below type name for variable
120 *
121 * xxx_len : data length
122 * xxx_width : data width
123 * xxx_offset : data offset
124 * xxx_num : number of data
125 */
126
127 /*
128 * struct
129 */
130
131 struct fsi_stream {
132 struct snd_pcm_substream *substream;
133
134 int fifo_max_num;
135
136 int buff_offset;
137 int buff_len;
138 int period_len;
139 int period_num;
140
141 int uerr_num;
142 int oerr_num;
143 };
144
145 struct fsi_priv {
146 void __iomem *base;
147 struct fsi_master *master;
148
149 int chan_num;
150 struct fsi_stream playback;
151 struct fsi_stream capture;
152
153 long rate;
154 };
155
156 struct fsi_core {
157 int ver;
158
159 u32 int_st;
160 u32 iemsk;
161 u32 imsk;
162 u32 a_mclk;
163 u32 b_mclk;
164 };
165
166 struct fsi_master {
167 void __iomem *base;
168 int irq;
169 struct fsi_priv fsia;
170 struct fsi_priv fsib;
171 struct fsi_core *core;
172 struct sh_fsi_platform_info *info;
173 spinlock_t lock;
174 };
175
176 /*
177 * basic read write function
178 */
179
180 static void __fsi_reg_write(u32 reg, u32 data)
181 {
182 /* valid data area is 24bit */
183 data &= 0x00ffffff;
184
185 __raw_writel(data, reg);
186 }
187
188 static u32 __fsi_reg_read(u32 reg)
189 {
190 return __raw_readl(reg);
191 }
192
193 static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data)
194 {
195 u32 val = __fsi_reg_read(reg);
196
197 val &= ~mask;
198 val |= data & mask;
199
200 __fsi_reg_write(reg, val);
201 }
202
203 #define fsi_reg_write(p, r, d)\
204 __fsi_reg_write((u32)(p->base + REG_##r), d)
205
206 #define fsi_reg_read(p, r)\
207 __fsi_reg_read((u32)(p->base + REG_##r))
208
209 #define fsi_reg_mask_set(p, r, m, d)\
210 __fsi_reg_mask_set((u32)(p->base + REG_##r), m, d)
211
212 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
213 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
214 static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
215 {
216 u32 ret;
217 unsigned long flags;
218
219 spin_lock_irqsave(&master->lock, flags);
220 ret = __fsi_reg_read((u32)(master->base + reg));
221 spin_unlock_irqrestore(&master->lock, flags);
222
223 return ret;
224 }
225
226 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
227 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
228 static void _fsi_master_mask_set(struct fsi_master *master,
229 u32 reg, u32 mask, u32 data)
230 {
231 unsigned long flags;
232
233 spin_lock_irqsave(&master->lock, flags);
234 __fsi_reg_mask_set((u32)(master->base + reg), mask, data);
235 spin_unlock_irqrestore(&master->lock, flags);
236 }
237
238 /*
239 * basic function
240 */
241
242 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
243 {
244 return fsi->master;
245 }
246
247 static int fsi_is_port_a(struct fsi_priv *fsi)
248 {
249 return fsi->master->base == fsi->base;
250 }
251
252 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
253 {
254 struct snd_soc_pcm_runtime *rtd = substream->private_data;
255
256 return rtd->cpu_dai;
257 }
258
259 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
260 {
261 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
262
263 if (dai->id == 0)
264 return &master->fsia;
265 else
266 return &master->fsib;
267 }
268
269 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
270 {
271 return fsi_get_priv_frm_dai(fsi_get_dai(substream));
272 }
273
274 static set_rate_func fsi_get_info_set_rate(struct fsi_master *master)
275 {
276 if (!master->info)
277 return NULL;
278
279 return master->info->set_rate;
280 }
281
282 static u32 fsi_get_info_flags(struct fsi_priv *fsi)
283 {
284 int is_porta = fsi_is_port_a(fsi);
285 struct fsi_master *master = fsi_get_master(fsi);
286
287 if (!master->info)
288 return 0;
289
290 return is_porta ? master->info->porta_flags :
291 master->info->portb_flags;
292 }
293
294 static inline int fsi_stream_is_play(int stream)
295 {
296 return stream == SNDRV_PCM_STREAM_PLAYBACK;
297 }
298
299 static inline int fsi_is_play(struct snd_pcm_substream *substream)
300 {
301 return fsi_stream_is_play(substream->stream);
302 }
303
304 static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi,
305 int is_play)
306 {
307 return is_play ? &fsi->playback : &fsi->capture;
308 }
309
310 static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play)
311 {
312 int is_porta = fsi_is_port_a(fsi);
313 u32 shift;
314
315 if (is_porta)
316 shift = is_play ? AO_SHIFT : AI_SHIFT;
317 else
318 shift = is_play ? BO_SHIFT : BI_SHIFT;
319
320 return shift;
321 }
322
323 static void fsi_stream_push(struct fsi_priv *fsi,
324 int is_play,
325 struct snd_pcm_substream *substream,
326 u32 buffer_len,
327 u32 period_len)
328 {
329 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
330
331 io->substream = substream;
332 io->buff_len = buffer_len;
333 io->buff_offset = 0;
334 io->period_len = period_len;
335 io->period_num = 0;
336 io->oerr_num = -1; /* ignore 1st err */
337 io->uerr_num = -1; /* ignore 1st err */
338 }
339
340 static void fsi_stream_pop(struct fsi_priv *fsi, int is_play)
341 {
342 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
343 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
344
345
346 if (io->oerr_num > 0)
347 dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
348
349 if (io->uerr_num > 0)
350 dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
351
352 io->substream = NULL;
353 io->buff_len = 0;
354 io->buff_offset = 0;
355 io->period_len = 0;
356 io->period_num = 0;
357 io->oerr_num = 0;
358 io->uerr_num = 0;
359 }
360
361 static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play)
362 {
363 u32 status;
364 int data_num;
365
366 status = is_play ?
367 fsi_reg_read(fsi, DOFF_ST) :
368 fsi_reg_read(fsi, DIFF_ST);
369
370 data_num = 0x1ff & (status >> 8);
371 data_num *= fsi->chan_num;
372
373 return data_num;
374 }
375
376 static int fsi_len2num(int len, int width)
377 {
378 return len / width;
379 }
380
381 #define fsi_num2offset(a, b) fsi_num2len(a, b)
382 static int fsi_num2len(int num, int width)
383 {
384 return num * width;
385 }
386
387 static int fsi_get_frame_width(struct fsi_priv *fsi, int is_play)
388 {
389 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
390 struct snd_pcm_substream *substream = io->substream;
391 struct snd_pcm_runtime *runtime = substream->runtime;
392
393 return frames_to_bytes(runtime, 1) / fsi->chan_num;
394 }
395
396 static void fsi_count_fifo_err(struct fsi_priv *fsi)
397 {
398 u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
399 u32 istatus = fsi_reg_read(fsi, DIFF_ST);
400
401 if (ostatus & ERR_OVER)
402 fsi->playback.oerr_num++;
403
404 if (ostatus & ERR_UNDER)
405 fsi->playback.uerr_num++;
406
407 if (istatus & ERR_OVER)
408 fsi->capture.oerr_num++;
409
410 if (istatus & ERR_UNDER)
411 fsi->capture.uerr_num++;
412
413 fsi_reg_write(fsi, DOFF_ST, 0);
414 fsi_reg_write(fsi, DIFF_ST, 0);
415 }
416
417 /*
418 * dma function
419 */
420
421 static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream)
422 {
423 int is_play = fsi_stream_is_play(stream);
424 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
425
426 return io->substream->runtime->dma_area + io->buff_offset;
427 }
428
429 static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num)
430 {
431 u16 *start;
432 int i;
433
434 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
435
436 for (i = 0; i < num; i++)
437 fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8));
438 }
439
440 static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num)
441 {
442 u16 *start;
443 int i;
444
445 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
446
447
448 for (i = 0; i < num; i++)
449 *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
450 }
451
452 static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num)
453 {
454 u32 *start;
455 int i;
456
457 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
458
459
460 for (i = 0; i < num; i++)
461 fsi_reg_write(fsi, DODT, *(start + i));
462 }
463
464 static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num)
465 {
466 u32 *start;
467 int i;
468
469 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
470
471 for (i = 0; i < num; i++)
472 *(start + i) = fsi_reg_read(fsi, DIDT);
473 }
474
475 /*
476 * irq function
477 */
478
479 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
480 {
481 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
482 struct fsi_master *master = fsi_get_master(fsi);
483
484 fsi_core_mask_set(master, imsk, data, data);
485 fsi_core_mask_set(master, iemsk, data, data);
486 }
487
488 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
489 {
490 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
491 struct fsi_master *master = fsi_get_master(fsi);
492
493 fsi_core_mask_set(master, imsk, data, 0);
494 fsi_core_mask_set(master, iemsk, data, 0);
495 }
496
497 static u32 fsi_irq_get_status(struct fsi_master *master)
498 {
499 return fsi_core_read(master, int_st);
500 }
501
502 static void fsi_irq_clear_status(struct fsi_priv *fsi)
503 {
504 u32 data = 0;
505 struct fsi_master *master = fsi_get_master(fsi);
506
507 data |= AB_IO(1, fsi_get_port_shift(fsi, 0));
508 data |= AB_IO(1, fsi_get_port_shift(fsi, 1));
509
510 /* clear interrupt factor */
511 fsi_core_mask_set(master, int_st, data, 0);
512 }
513
514 /*
515 * SPDIF master clock function
516 *
517 * These functions are used later FSI2
518 */
519 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
520 {
521 struct fsi_master *master = fsi_get_master(fsi);
522 u32 mask, val;
523
524 if (master->core->ver < 2) {
525 pr_err("fsi: register access err (%s)\n", __func__);
526 return;
527 }
528
529 mask = BP | SE;
530 val = enable ? mask : 0;
531
532 fsi_is_port_a(fsi) ?
533 fsi_core_mask_set(master, a_mclk, mask, val) :
534 fsi_core_mask_set(master, b_mclk, mask, val);
535 }
536
537 /*
538 * ctrl function
539 */
540
541 static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable)
542 {
543 u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4);
544 struct fsi_master *master = fsi_get_master(fsi);
545
546 if (enable)
547 fsi_master_mask_set(master, CLK_RST, val, val);
548 else
549 fsi_master_mask_set(master, CLK_RST, val, 0);
550 }
551
552 static void fsi_fifo_init(struct fsi_priv *fsi,
553 int is_play,
554 struct snd_soc_dai *dai)
555 {
556 struct fsi_master *master = fsi_get_master(fsi);
557 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
558 u32 shift, i;
559
560 /* get on-chip RAM capacity */
561 shift = fsi_master_read(master, FIFO_SZ);
562 shift >>= fsi_get_port_shift(fsi, is_play);
563 shift &= FIFO_SZ_MASK;
564 io->fifo_max_num = 256 << shift;
565 dev_dbg(dai->dev, "fifo = %d words\n", io->fifo_max_num);
566
567 /*
568 * The maximum number of sample data varies depending
569 * on the number of channels selected for the format.
570 *
571 * FIFOs are used in 4-channel units in 3-channel mode
572 * and in 8-channel units in 5- to 7-channel mode
573 * meaning that more FIFOs than the required size of DPRAM
574 * are used.
575 *
576 * ex) if 256 words of DP-RAM is connected
577 * 1 channel: 256 (256 x 1 = 256)
578 * 2 channels: 128 (128 x 2 = 256)
579 * 3 channels: 64 ( 64 x 3 = 192)
580 * 4 channels: 64 ( 64 x 4 = 256)
581 * 5 channels: 32 ( 32 x 5 = 160)
582 * 6 channels: 32 ( 32 x 6 = 192)
583 * 7 channels: 32 ( 32 x 7 = 224)
584 * 8 channels: 32 ( 32 x 8 = 256)
585 */
586 for (i = 1; i < fsi->chan_num; i <<= 1)
587 io->fifo_max_num >>= 1;
588 dev_dbg(dai->dev, "%d channel %d store\n",
589 fsi->chan_num, io->fifo_max_num);
590
591 /*
592 * set interrupt generation factor
593 * clear FIFO
594 */
595 if (is_play) {
596 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
597 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
598 } else {
599 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
600 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
601 }
602 }
603
604 static void fsi_soft_all_reset(struct fsi_master *master)
605 {
606 /* port AB reset */
607 fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0);
608 mdelay(10);
609
610 /* soft reset */
611 fsi_master_mask_set(master, SOFT_RST, FSISR, 0);
612 fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR);
613 mdelay(10);
614 }
615
616 static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int stream)
617 {
618 struct snd_pcm_runtime *runtime;
619 struct snd_pcm_substream *substream = NULL;
620 int is_play = fsi_stream_is_play(stream);
621 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
622 int data_residue_num;
623 int data_num;
624 int data_num_max;
625 int ch_width;
626 int over_period;
627 void (*fn)(struct fsi_priv *fsi, int size);
628
629 if (!fsi ||
630 !io->substream ||
631 !io->substream->runtime)
632 return -EINVAL;
633
634 over_period = 0;
635 substream = io->substream;
636 runtime = substream->runtime;
637
638 /* FSI FIFO has limit.
639 * So, this driver can not send periods data at a time
640 */
641 if (io->buff_offset >=
642 fsi_num2offset(io->period_num + 1, io->period_len)) {
643
644 over_period = 1;
645 io->period_num = (io->period_num + 1) % runtime->periods;
646
647 if (0 == io->period_num)
648 io->buff_offset = 0;
649 }
650
651 /* get 1 channel data width */
652 ch_width = fsi_get_frame_width(fsi, is_play);
653
654 /* get residue data number of alsa */
655 data_residue_num = fsi_len2num(io->buff_len - io->buff_offset,
656 ch_width);
657
658 if (is_play) {
659 /*
660 * for play-back
661 *
662 * data_num_max : number of FSI fifo free space
663 * data_num : number of ALSA residue data
664 */
665 data_num_max = io->fifo_max_num * fsi->chan_num;
666 data_num_max -= fsi_get_fifo_data_num(fsi, is_play);
667
668 data_num = data_residue_num;
669
670 switch (ch_width) {
671 case 2:
672 fn = fsi_dma_soft_push16;
673 break;
674 case 4:
675 fn = fsi_dma_soft_push32;
676 break;
677 default:
678 return -EINVAL;
679 }
680 } else {
681 /*
682 * for capture
683 *
684 * data_num_max : number of ALSA free space
685 * data_num : number of data in FSI fifo
686 */
687 data_num_max = data_residue_num;
688 data_num = fsi_get_fifo_data_num(fsi, is_play);
689
690 switch (ch_width) {
691 case 2:
692 fn = fsi_dma_soft_pop16;
693 break;
694 case 4:
695 fn = fsi_dma_soft_pop32;
696 break;
697 default:
698 return -EINVAL;
699 }
700 }
701
702 data_num = min(data_num, data_num_max);
703
704 fn(fsi, data_num);
705
706 /* update buff_offset */
707 io->buff_offset += fsi_num2offset(data_num, ch_width);
708
709 if (over_period)
710 snd_pcm_period_elapsed(substream);
711
712 return 0;
713 }
714
715 static int fsi_data_pop(struct fsi_priv *fsi)
716 {
717 return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_CAPTURE);
718 }
719
720 static int fsi_data_push(struct fsi_priv *fsi)
721 {
722 return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_PLAYBACK);
723 }
724
725 static irqreturn_t fsi_interrupt(int irq, void *data)
726 {
727 struct fsi_master *master = data;
728 u32 int_st = fsi_irq_get_status(master);
729
730 /* clear irq status */
731 fsi_master_mask_set(master, SOFT_RST, IR, 0);
732 fsi_master_mask_set(master, SOFT_RST, IR, IR);
733
734 if (int_st & AB_IO(1, AO_SHIFT))
735 fsi_data_push(&master->fsia);
736 if (int_st & AB_IO(1, BO_SHIFT))
737 fsi_data_push(&master->fsib);
738 if (int_st & AB_IO(1, AI_SHIFT))
739 fsi_data_pop(&master->fsia);
740 if (int_st & AB_IO(1, BI_SHIFT))
741 fsi_data_pop(&master->fsib);
742
743 fsi_count_fifo_err(&master->fsia);
744 fsi_count_fifo_err(&master->fsib);
745
746 fsi_irq_clear_status(&master->fsia);
747 fsi_irq_clear_status(&master->fsib);
748
749 return IRQ_HANDLED;
750 }
751
752 /*
753 * dai ops
754 */
755
756 static int fsi_dai_startup(struct snd_pcm_substream *substream,
757 struct snd_soc_dai *dai)
758 {
759 struct fsi_priv *fsi = fsi_get_priv(substream);
760 u32 flags = fsi_get_info_flags(fsi);
761 u32 data;
762 int is_play = fsi_is_play(substream);
763
764 pm_runtime_get_sync(dai->dev);
765
766
767 /* clock inversion (CKG2) */
768 data = 0;
769 if (SH_FSI_LRM_INV & flags)
770 data |= 1 << 12;
771 if (SH_FSI_BRM_INV & flags)
772 data |= 1 << 8;
773 if (SH_FSI_LRS_INV & flags)
774 data |= 1 << 4;
775 if (SH_FSI_BRS_INV & flags)
776 data |= 1 << 0;
777
778 fsi_reg_write(fsi, CKG2, data);
779
780 /* irq clear */
781 fsi_irq_disable(fsi, is_play);
782 fsi_irq_clear_status(fsi);
783
784 /* fifo init */
785 fsi_fifo_init(fsi, is_play, dai);
786
787 return 0;
788 }
789
790 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
791 struct snd_soc_dai *dai)
792 {
793 struct fsi_priv *fsi = fsi_get_priv(substream);
794 int is_play = fsi_is_play(substream);
795 struct fsi_master *master = fsi_get_master(fsi);
796 set_rate_func set_rate;
797
798 fsi_irq_disable(fsi, is_play);
799 fsi_clk_ctrl(fsi, 0);
800
801 set_rate = fsi_get_info_set_rate(master);
802 if (set_rate && fsi->rate)
803 set_rate(dai->dev, fsi_is_port_a(fsi), fsi->rate, 0);
804 fsi->rate = 0;
805
806 pm_runtime_put_sync(dai->dev);
807 }
808
809 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
810 struct snd_soc_dai *dai)
811 {
812 struct fsi_priv *fsi = fsi_get_priv(substream);
813 struct snd_pcm_runtime *runtime = substream->runtime;
814 int is_play = fsi_is_play(substream);
815 int ret = 0;
816
817 switch (cmd) {
818 case SNDRV_PCM_TRIGGER_START:
819 fsi_stream_push(fsi, is_play, substream,
820 frames_to_bytes(runtime, runtime->buffer_size),
821 frames_to_bytes(runtime, runtime->period_size));
822 ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi);
823 fsi_irq_enable(fsi, is_play);
824 break;
825 case SNDRV_PCM_TRIGGER_STOP:
826 fsi_irq_disable(fsi, is_play);
827 fsi_stream_pop(fsi, is_play);
828 break;
829 }
830
831 return ret;
832 }
833
834 static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
835 {
836 u32 data = 0;
837
838 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
839 case SND_SOC_DAIFMT_I2S:
840 data = CR_I2S;
841 fsi->chan_num = 2;
842 break;
843 case SND_SOC_DAIFMT_LEFT_J:
844 data = CR_PCM;
845 fsi->chan_num = 2;
846 break;
847 default:
848 return -EINVAL;
849 }
850
851 fsi_reg_write(fsi, DO_FMT, data);
852 fsi_reg_write(fsi, DI_FMT, data);
853
854 return 0;
855 }
856
857 static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
858 {
859 struct fsi_master *master = fsi_get_master(fsi);
860 u32 data = 0;
861
862 if (master->core->ver < 2)
863 return -EINVAL;
864
865 data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM;
866 fsi->chan_num = 2;
867 fsi_spdif_clk_ctrl(fsi, 1);
868 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
869
870 fsi_reg_write(fsi, DO_FMT, data);
871 fsi_reg_write(fsi, DI_FMT, data);
872
873 return 0;
874 }
875
876 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
877 {
878 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
879 u32 flags = fsi_get_info_flags(fsi);
880 u32 data = 0;
881 int ret;
882
883 pm_runtime_get_sync(dai->dev);
884
885 /* set master/slave audio interface */
886 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
887 case SND_SOC_DAIFMT_CBM_CFM:
888 data = DIMD | DOMD;
889 break;
890 case SND_SOC_DAIFMT_CBS_CFS:
891 break;
892 default:
893 ret = -EINVAL;
894 goto set_fmt_exit;
895 }
896 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
897
898 /* set format */
899 switch (flags & SH_FSI_FMT_MASK) {
900 case SH_FSI_FMT_DAI:
901 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
902 break;
903 case SH_FSI_FMT_SPDIF:
904 ret = fsi_set_fmt_spdif(fsi);
905 break;
906 default:
907 ret = -EINVAL;
908 }
909
910 set_fmt_exit:
911 pm_runtime_put_sync(dai->dev);
912
913 return ret;
914 }
915
916 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
917 struct snd_pcm_hw_params *params,
918 struct snd_soc_dai *dai)
919 {
920 struct fsi_priv *fsi = fsi_get_priv(substream);
921 struct fsi_master *master = fsi_get_master(fsi);
922 set_rate_func set_rate;
923 int fsi_ver = master->core->ver;
924 long rate = params_rate(params);
925 int ret;
926
927 set_rate = fsi_get_info_set_rate(master);
928 if (!set_rate)
929 return 0;
930
931 ret = set_rate(dai->dev, fsi_is_port_a(fsi), rate, 1);
932 if (ret < 0) /* error */
933 return ret;
934
935 fsi->rate = rate;
936 if (ret > 0) {
937 u32 data = 0;
938
939 switch (ret & SH_FSI_ACKMD_MASK) {
940 default:
941 /* FALL THROUGH */
942 case SH_FSI_ACKMD_512:
943 data |= (0x0 << 12);
944 break;
945 case SH_FSI_ACKMD_256:
946 data |= (0x1 << 12);
947 break;
948 case SH_FSI_ACKMD_128:
949 data |= (0x2 << 12);
950 break;
951 case SH_FSI_ACKMD_64:
952 data |= (0x3 << 12);
953 break;
954 case SH_FSI_ACKMD_32:
955 if (fsi_ver < 2)
956 dev_err(dai->dev, "unsupported ACKMD\n");
957 else
958 data |= (0x4 << 12);
959 break;
960 }
961
962 switch (ret & SH_FSI_BPFMD_MASK) {
963 default:
964 /* FALL THROUGH */
965 case SH_FSI_BPFMD_32:
966 data |= (0x0 << 8);
967 break;
968 case SH_FSI_BPFMD_64:
969 data |= (0x1 << 8);
970 break;
971 case SH_FSI_BPFMD_128:
972 data |= (0x2 << 8);
973 break;
974 case SH_FSI_BPFMD_256:
975 data |= (0x3 << 8);
976 break;
977 case SH_FSI_BPFMD_512:
978 data |= (0x4 << 8);
979 break;
980 case SH_FSI_BPFMD_16:
981 if (fsi_ver < 2)
982 dev_err(dai->dev, "unsupported ACKMD\n");
983 else
984 data |= (0x7 << 8);
985 break;
986 }
987
988 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
989 udelay(10);
990 fsi_clk_ctrl(fsi, 1);
991 ret = 0;
992 }
993
994 return ret;
995
996 }
997
998 static struct snd_soc_dai_ops fsi_dai_ops = {
999 .startup = fsi_dai_startup,
1000 .shutdown = fsi_dai_shutdown,
1001 .trigger = fsi_dai_trigger,
1002 .set_fmt = fsi_dai_set_fmt,
1003 .hw_params = fsi_dai_hw_params,
1004 };
1005
1006 /*
1007 * pcm ops
1008 */
1009
1010 static struct snd_pcm_hardware fsi_pcm_hardware = {
1011 .info = SNDRV_PCM_INFO_INTERLEAVED |
1012 SNDRV_PCM_INFO_MMAP |
1013 SNDRV_PCM_INFO_MMAP_VALID |
1014 SNDRV_PCM_INFO_PAUSE,
1015 .formats = FSI_FMTS,
1016 .rates = FSI_RATES,
1017 .rate_min = 8000,
1018 .rate_max = 192000,
1019 .channels_min = 1,
1020 .channels_max = 2,
1021 .buffer_bytes_max = 64 * 1024,
1022 .period_bytes_min = 32,
1023 .period_bytes_max = 8192,
1024 .periods_min = 1,
1025 .periods_max = 32,
1026 .fifo_size = 256,
1027 };
1028
1029 static int fsi_pcm_open(struct snd_pcm_substream *substream)
1030 {
1031 struct snd_pcm_runtime *runtime = substream->runtime;
1032 int ret = 0;
1033
1034 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
1035
1036 ret = snd_pcm_hw_constraint_integer(runtime,
1037 SNDRV_PCM_HW_PARAM_PERIODS);
1038
1039 return ret;
1040 }
1041
1042 static int fsi_hw_params(struct snd_pcm_substream *substream,
1043 struct snd_pcm_hw_params *hw_params)
1044 {
1045 return snd_pcm_lib_malloc_pages(substream,
1046 params_buffer_bytes(hw_params));
1047 }
1048
1049 static int fsi_hw_free(struct snd_pcm_substream *substream)
1050 {
1051 return snd_pcm_lib_free_pages(substream);
1052 }
1053
1054 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
1055 {
1056 struct snd_pcm_runtime *runtime = substream->runtime;
1057 struct fsi_priv *fsi = fsi_get_priv(substream);
1058 struct fsi_stream *io = fsi_get_stream(fsi, fsi_is_play(substream));
1059 long location;
1060
1061 location = (io->buff_offset - 1);
1062 if (location < 0)
1063 location = 0;
1064
1065 return bytes_to_frames(runtime, location);
1066 }
1067
1068 static struct snd_pcm_ops fsi_pcm_ops = {
1069 .open = fsi_pcm_open,
1070 .ioctl = snd_pcm_lib_ioctl,
1071 .hw_params = fsi_hw_params,
1072 .hw_free = fsi_hw_free,
1073 .pointer = fsi_pointer,
1074 };
1075
1076 /*
1077 * snd_soc_platform
1078 */
1079
1080 #define PREALLOC_BUFFER (32 * 1024)
1081 #define PREALLOC_BUFFER_MAX (32 * 1024)
1082
1083 static void fsi_pcm_free(struct snd_pcm *pcm)
1084 {
1085 snd_pcm_lib_preallocate_free_for_all(pcm);
1086 }
1087
1088 static int fsi_pcm_new(struct snd_card *card,
1089 struct snd_soc_dai *dai,
1090 struct snd_pcm *pcm)
1091 {
1092 /*
1093 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
1094 * in MMAP mode (i.e. aplay -M)
1095 */
1096 return snd_pcm_lib_preallocate_pages_for_all(
1097 pcm,
1098 SNDRV_DMA_TYPE_CONTINUOUS,
1099 snd_dma_continuous_data(GFP_KERNEL),
1100 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1101 }
1102
1103 /*
1104 * alsa struct
1105 */
1106
1107 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1108 {
1109 .name = "fsia-dai",
1110 .playback = {
1111 .rates = FSI_RATES,
1112 .formats = FSI_FMTS,
1113 .channels_min = 1,
1114 .channels_max = 8,
1115 },
1116 .capture = {
1117 .rates = FSI_RATES,
1118 .formats = FSI_FMTS,
1119 .channels_min = 1,
1120 .channels_max = 8,
1121 },
1122 .ops = &fsi_dai_ops,
1123 },
1124 {
1125 .name = "fsib-dai",
1126 .playback = {
1127 .rates = FSI_RATES,
1128 .formats = FSI_FMTS,
1129 .channels_min = 1,
1130 .channels_max = 8,
1131 },
1132 .capture = {
1133 .rates = FSI_RATES,
1134 .formats = FSI_FMTS,
1135 .channels_min = 1,
1136 .channels_max = 8,
1137 },
1138 .ops = &fsi_dai_ops,
1139 },
1140 };
1141
1142 static struct snd_soc_platform_driver fsi_soc_platform = {
1143 .ops = &fsi_pcm_ops,
1144 .pcm_new = fsi_pcm_new,
1145 .pcm_free = fsi_pcm_free,
1146 };
1147
1148 /*
1149 * platform function
1150 */
1151
1152 static int fsi_probe(struct platform_device *pdev)
1153 {
1154 struct fsi_master *master;
1155 const struct platform_device_id *id_entry;
1156 struct resource *res;
1157 unsigned int irq;
1158 int ret;
1159
1160 id_entry = pdev->id_entry;
1161 if (!id_entry) {
1162 dev_err(&pdev->dev, "unknown fsi device\n");
1163 return -ENODEV;
1164 }
1165
1166 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1167 irq = platform_get_irq(pdev, 0);
1168 if (!res || (int)irq <= 0) {
1169 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1170 ret = -ENODEV;
1171 goto exit;
1172 }
1173
1174 master = kzalloc(sizeof(*master), GFP_KERNEL);
1175 if (!master) {
1176 dev_err(&pdev->dev, "Could not allocate master\n");
1177 ret = -ENOMEM;
1178 goto exit;
1179 }
1180
1181 master->base = ioremap_nocache(res->start, resource_size(res));
1182 if (!master->base) {
1183 ret = -ENXIO;
1184 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1185 goto exit_kfree;
1186 }
1187
1188 /* master setting */
1189 master->irq = irq;
1190 master->info = pdev->dev.platform_data;
1191 master->core = (struct fsi_core *)id_entry->driver_data;
1192 spin_lock_init(&master->lock);
1193
1194 /* FSI A setting */
1195 master->fsia.base = master->base;
1196 master->fsia.master = master;
1197
1198 /* FSI B setting */
1199 master->fsib.base = master->base + 0x40;
1200 master->fsib.master = master;
1201
1202 pm_runtime_enable(&pdev->dev);
1203 dev_set_drvdata(&pdev->dev, master);
1204
1205 pm_runtime_get_sync(&pdev->dev);
1206 fsi_soft_all_reset(master);
1207 pm_runtime_put_sync(&pdev->dev);
1208
1209 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED,
1210 id_entry->name, master);
1211 if (ret) {
1212 dev_err(&pdev->dev, "irq request err\n");
1213 goto exit_iounmap;
1214 }
1215
1216 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
1217 if (ret < 0) {
1218 dev_err(&pdev->dev, "cannot snd soc register\n");
1219 goto exit_free_irq;
1220 }
1221
1222 ret = snd_soc_register_dais(&pdev->dev, fsi_soc_dai,
1223 ARRAY_SIZE(fsi_soc_dai));
1224 if (ret < 0) {
1225 dev_err(&pdev->dev, "cannot snd dai register\n");
1226 goto exit_snd_soc;
1227 }
1228
1229 return ret;
1230
1231 exit_snd_soc:
1232 snd_soc_unregister_platform(&pdev->dev);
1233 exit_free_irq:
1234 free_irq(irq, master);
1235 exit_iounmap:
1236 iounmap(master->base);
1237 pm_runtime_disable(&pdev->dev);
1238 exit_kfree:
1239 kfree(master);
1240 master = NULL;
1241 exit:
1242 return ret;
1243 }
1244
1245 static int fsi_remove(struct platform_device *pdev)
1246 {
1247 struct fsi_master *master;
1248
1249 master = dev_get_drvdata(&pdev->dev);
1250
1251 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai));
1252 snd_soc_unregister_platform(&pdev->dev);
1253
1254 pm_runtime_disable(&pdev->dev);
1255
1256 free_irq(master->irq, master);
1257
1258 iounmap(master->base);
1259 kfree(master);
1260
1261 return 0;
1262 }
1263
1264 static int fsi_runtime_nop(struct device *dev)
1265 {
1266 /* Runtime PM callback shared between ->runtime_suspend()
1267 * and ->runtime_resume(). Simply returns success.
1268 *
1269 * This driver re-initializes all registers after
1270 * pm_runtime_get_sync() anyway so there is no need
1271 * to save and restore registers here.
1272 */
1273 return 0;
1274 }
1275
1276 static struct dev_pm_ops fsi_pm_ops = {
1277 .runtime_suspend = fsi_runtime_nop,
1278 .runtime_resume = fsi_runtime_nop,
1279 };
1280
1281 static struct fsi_core fsi1_core = {
1282 .ver = 1,
1283
1284 /* Interrupt */
1285 .int_st = INT_ST,
1286 .iemsk = IEMSK,
1287 .imsk = IMSK,
1288 };
1289
1290 static struct fsi_core fsi2_core = {
1291 .ver = 2,
1292
1293 /* Interrupt */
1294 .int_st = CPU_INT_ST,
1295 .iemsk = CPU_IEMSK,
1296 .imsk = CPU_IMSK,
1297 .a_mclk = A_MST_CTLR,
1298 .b_mclk = B_MST_CTLR,
1299 };
1300
1301 static struct platform_device_id fsi_id_table[] = {
1302 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
1303 { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
1304 {},
1305 };
1306 MODULE_DEVICE_TABLE(platform, fsi_id_table);
1307
1308 static struct platform_driver fsi_driver = {
1309 .driver = {
1310 .name = "fsi-pcm-audio",
1311 .pm = &fsi_pm_ops,
1312 },
1313 .probe = fsi_probe,
1314 .remove = fsi_remove,
1315 .id_table = fsi_id_table,
1316 };
1317
1318 static int __init fsi_mobile_init(void)
1319 {
1320 return platform_driver_register(&fsi_driver);
1321 }
1322
1323 static void __exit fsi_mobile_exit(void)
1324 {
1325 platform_driver_unregister(&fsi_driver);
1326 }
1327
1328 module_init(fsi_mobile_init);
1329 module_exit(fsi_mobile_exit);
1330
1331 MODULE_LICENSE("GPL");
1332 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
1333 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");