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ASoC: s3c24xx 8 bit sound fix
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / s3c24xx / s3c24xx-i2s.c
1 /*
2 * s3c24xx-i2s.c -- ALSA Soc Audio Layer
3 *
4 * (c) 2006 Wolfson Microelectronics PLC.
5 * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
6 *
7 * (c) 2004-2005 Simtec Electronics
8 * http://armlinux.simtec.co.uk/
9 * Ben Dooks <ben@simtec.co.uk>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/delay.h>
21 #include <linux/clk.h>
22 #include <linux/jiffies.h>
23 #include <linux/io.h>
24 #include <sound/core.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/initval.h>
28 #include <sound/soc.h>
29
30 #include <mach/hardware.h>
31 #include <mach/regs-gpio.h>
32 #include <mach/regs-clock.h>
33 #include <mach/audio.h>
34 #include <asm/dma.h>
35 #include <mach/dma.h>
36
37 #include <asm/plat-s3c24xx/regs-iis.h>
38
39 #include "s3c24xx-pcm.h"
40 #include "s3c24xx-i2s.h"
41
42 #define S3C24XX_I2S_DEBUG 0
43 #if S3C24XX_I2S_DEBUG
44 #define DBG(x...) printk(KERN_DEBUG "s3c24xx-i2s: " x)
45 #else
46 #define DBG(x...)
47 #endif
48
49 static struct s3c2410_dma_client s3c24xx_dma_client_out = {
50 .name = "I2S PCM Stereo out"
51 };
52
53 static struct s3c2410_dma_client s3c24xx_dma_client_in = {
54 .name = "I2S PCM Stereo in"
55 };
56
57 static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_out = {
58 .client = &s3c24xx_dma_client_out,
59 .channel = DMACH_I2S_OUT,
60 .dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFO,
61 .dma_size = 2,
62 };
63
64 static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_in = {
65 .client = &s3c24xx_dma_client_in,
66 .channel = DMACH_I2S_IN,
67 .dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFO,
68 .dma_size = 2,
69 };
70
71 struct s3c24xx_i2s_info {
72 void __iomem *regs;
73 struct clk *iis_clk;
74 u32 iiscon;
75 u32 iismod;
76 u32 iisfcon;
77 u32 iispsr;
78 };
79 static struct s3c24xx_i2s_info s3c24xx_i2s;
80
81 static void s3c24xx_snd_txctrl(int on)
82 {
83 u32 iisfcon;
84 u32 iiscon;
85 u32 iismod;
86
87 DBG("Entered %s\n", __func__);
88
89 iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
90 iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
91 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
92
93 DBG("r: IISCON: %lx IISMOD: %lx IISFCON: %lx\n", iiscon, iismod, iisfcon);
94
95 if (on) {
96 iisfcon |= S3C2410_IISFCON_TXDMA | S3C2410_IISFCON_TXENABLE;
97 iiscon |= S3C2410_IISCON_TXDMAEN | S3C2410_IISCON_IISEN;
98 iiscon &= ~S3C2410_IISCON_TXIDLE;
99 iismod |= S3C2410_IISMOD_TXMODE;
100
101 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
102 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
103 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
104 } else {
105 /* note, we have to disable the FIFOs otherwise bad things
106 * seem to happen when the DMA stops. According to the
107 * Samsung supplied kernel, this should allow the DMA
108 * engine and FIFOs to reset. If this isn't allowed, the
109 * DMA engine will simply freeze randomly.
110 */
111
112 iisfcon &= ~S3C2410_IISFCON_TXENABLE;
113 iisfcon &= ~S3C2410_IISFCON_TXDMA;
114 iiscon |= S3C2410_IISCON_TXIDLE;
115 iiscon &= ~S3C2410_IISCON_TXDMAEN;
116 iismod &= ~S3C2410_IISMOD_TXMODE;
117
118 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
119 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
120 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
121 }
122
123 DBG("w: IISCON: %lx IISMOD: %lx IISFCON: %lx\n", iiscon, iismod, iisfcon);
124 }
125
126 static void s3c24xx_snd_rxctrl(int on)
127 {
128 u32 iisfcon;
129 u32 iiscon;
130 u32 iismod;
131
132 DBG("Entered %s\n", __func__);
133
134 iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
135 iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
136 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
137
138 DBG("r: IISCON: %lx IISMOD: %lx IISFCON: %lx\n", iiscon, iismod, iisfcon);
139
140 if (on) {
141 iisfcon |= S3C2410_IISFCON_RXDMA | S3C2410_IISFCON_RXENABLE;
142 iiscon |= S3C2410_IISCON_RXDMAEN | S3C2410_IISCON_IISEN;
143 iiscon &= ~S3C2410_IISCON_RXIDLE;
144 iismod |= S3C2410_IISMOD_RXMODE;
145
146 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
147 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
148 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
149 } else {
150 /* note, we have to disable the FIFOs otherwise bad things
151 * seem to happen when the DMA stops. According to the
152 * Samsung supplied kernel, this should allow the DMA
153 * engine and FIFOs to reset. If this isn't allowed, the
154 * DMA engine will simply freeze randomly.
155 */
156
157 iisfcon &= ~S3C2410_IISFCON_RXENABLE;
158 iisfcon &= ~S3C2410_IISFCON_RXDMA;
159 iiscon |= S3C2410_IISCON_RXIDLE;
160 iiscon &= ~S3C2410_IISCON_RXDMAEN;
161 iismod &= ~S3C2410_IISMOD_RXMODE;
162
163 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
164 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
165 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
166 }
167
168 DBG("w: IISCON: %lx IISMOD: %lx IISFCON: %lx\n", iiscon, iismod, iisfcon);
169 }
170
171 /*
172 * Wait for the LR signal to allow synchronisation to the L/R clock
173 * from the codec. May only be needed for slave mode.
174 */
175 static int s3c24xx_snd_lrsync(void)
176 {
177 u32 iiscon;
178 int timeout = 50; /* 5ms */
179
180 DBG("Entered %s\n", __func__);
181
182 while (1) {
183 iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
184 if (iiscon & S3C2410_IISCON_LRINDEX)
185 break;
186
187 if (!timeout--)
188 return -ETIMEDOUT;
189 udelay(100);
190 }
191
192 return 0;
193 }
194
195 /*
196 * Check whether CPU is the master or slave
197 */
198 static inline int s3c24xx_snd_is_clkmaster(void)
199 {
200 DBG("Entered %s\n", __func__);
201
202 return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1;
203 }
204
205 /*
206 * Set S3C24xx I2S DAI format
207 */
208 static int s3c24xx_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
209 unsigned int fmt)
210 {
211 u32 iismod;
212
213 DBG("Entered %s\n", __func__);
214
215 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
216 DBG("hw_params r: IISMOD: %lx \n", iismod);
217
218 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
219 case SND_SOC_DAIFMT_CBM_CFM:
220 iismod |= S3C2410_IISMOD_SLAVE;
221 break;
222 case SND_SOC_DAIFMT_CBS_CFS:
223 iismod &= ~S3C2410_IISMOD_SLAVE;
224 break;
225 default:
226 return -EINVAL;
227 }
228
229 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
230 case SND_SOC_DAIFMT_LEFT_J:
231 iismod |= S3C2410_IISMOD_MSB;
232 break;
233 case SND_SOC_DAIFMT_I2S:
234 iismod &= ~S3C2410_IISMOD_MSB;
235 break;
236 default:
237 return -EINVAL;
238 }
239
240 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
241 DBG("hw_params w: IISMOD: %lx \n", iismod);
242 return 0;
243 }
244
245 static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream,
246 struct snd_pcm_hw_params *params)
247 {
248 struct snd_soc_pcm_runtime *rtd = substream->private_data;
249 u32 iismod;
250
251 DBG("Entered %s\n", __func__);
252
253 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
254 rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_out;
255 else
256 rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_in;
257
258 /* Working copies of register */
259 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
260 DBG("hw_params r: IISMOD: %lx\n", iismod);
261
262 switch (params_format(params)) {
263 case SNDRV_PCM_FORMAT_S8:
264 iismod &= ~S3C2410_IISMOD_16BIT;
265 ((struct s3c24xx_pcm_dma_params *)
266 rtd->dai->cpu_dai->dma_data)->dma_size = 1;
267 break;
268 case SNDRV_PCM_FORMAT_S16_LE:
269 iismod |= S3C2410_IISMOD_16BIT;
270 ((struct s3c24xx_pcm_dma_params *)
271 rtd->dai->cpu_dai->dma_data)->dma_size = 2;
272 break;
273 default:
274 return -EINVAL;
275 }
276
277 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
278 DBG("hw_params w: IISMOD: %lx\n", iismod);
279 return 0;
280 }
281
282 static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
283 {
284 int ret = 0;
285
286 DBG("Entered %s\n", __func__);
287
288 switch (cmd) {
289 case SNDRV_PCM_TRIGGER_START:
290 case SNDRV_PCM_TRIGGER_RESUME:
291 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
292 if (!s3c24xx_snd_is_clkmaster()) {
293 ret = s3c24xx_snd_lrsync();
294 if (ret)
295 goto exit_err;
296 }
297
298 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
299 s3c24xx_snd_rxctrl(1);
300 else
301 s3c24xx_snd_txctrl(1);
302 break;
303 case SNDRV_PCM_TRIGGER_STOP:
304 case SNDRV_PCM_TRIGGER_SUSPEND:
305 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
306 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
307 s3c24xx_snd_rxctrl(0);
308 else
309 s3c24xx_snd_txctrl(0);
310 break;
311 default:
312 ret = -EINVAL;
313 break;
314 }
315
316 exit_err:
317 return ret;
318 }
319
320 /*
321 * Set S3C24xx Clock source
322 */
323 static int s3c24xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
324 int clk_id, unsigned int freq, int dir)
325 {
326 u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
327
328 DBG("Entered %s\n", __func__);
329
330 iismod &= ~S3C2440_IISMOD_MPLL;
331
332 switch (clk_id) {
333 case S3C24XX_CLKSRC_PCLK:
334 break;
335 case S3C24XX_CLKSRC_MPLL:
336 iismod |= S3C2440_IISMOD_MPLL;
337 break;
338 default:
339 return -EINVAL;
340 }
341
342 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
343 return 0;
344 }
345
346 /*
347 * Set S3C24xx Clock dividers
348 */
349 static int s3c24xx_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
350 int div_id, int div)
351 {
352 u32 reg;
353
354 DBG("Entered %s\n", __func__);
355
356 switch (div_id) {
357 case S3C24XX_DIV_BCLK:
358 reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK;
359 writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
360 break;
361 case S3C24XX_DIV_MCLK:
362 reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS);
363 writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
364 break;
365 case S3C24XX_DIV_PRESCALER:
366 writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR);
367 reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
368 writel(reg | S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON);
369 break;
370 default:
371 return -EINVAL;
372 }
373
374 return 0;
375 }
376
377 /*
378 * To avoid duplicating clock code, allow machine driver to
379 * get the clockrate from here.
380 */
381 u32 s3c24xx_i2s_get_clockrate(void)
382 {
383 return clk_get_rate(s3c24xx_i2s.iis_clk);
384 }
385 EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate);
386
387 static int s3c24xx_i2s_probe(struct platform_device *pdev,
388 struct snd_soc_dai *dai)
389 {
390 DBG("Entered %s\n", __func__);
391
392 s3c24xx_i2s.regs = ioremap(S3C2410_PA_IIS, 0x100);
393 if (s3c24xx_i2s.regs == NULL)
394 return -ENXIO;
395
396 s3c24xx_i2s.iis_clk = clk_get(&pdev->dev, "iis");
397 if (s3c24xx_i2s.iis_clk == NULL) {
398 DBG("failed to get iis_clock\n");
399 iounmap(s3c24xx_i2s.regs);
400 return -ENODEV;
401 }
402 clk_enable(s3c24xx_i2s.iis_clk);
403
404 /* Configure the I2S pins in correct mode */
405 s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK);
406 s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK);
407 s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK);
408 s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI);
409 s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO);
410
411 writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);
412
413 s3c24xx_snd_txctrl(0);
414 s3c24xx_snd_rxctrl(0);
415
416 return 0;
417 }
418
419 #ifdef CONFIG_PM
420 static int s3c24xx_i2s_suspend(struct platform_device *pdev,
421 struct snd_soc_dai *cpu_dai)
422 {
423 DBG("Entered %s\n", __func__);
424
425 s3c24xx_i2s.iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
426 s3c24xx_i2s.iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
427 s3c24xx_i2s.iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
428 s3c24xx_i2s.iispsr = readl(s3c24xx_i2s.regs + S3C2410_IISPSR);
429
430 clk_disable(s3c24xx_i2s.iis_clk);
431
432 return 0;
433 }
434
435 static int s3c24xx_i2s_resume(struct platform_device *pdev,
436 struct snd_soc_dai *cpu_dai)
437 {
438 DBG("Entered %s\n", __func__);
439 clk_enable(s3c24xx_i2s.iis_clk);
440
441 writel(s3c24xx_i2s.iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
442 writel(s3c24xx_i2s.iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
443 writel(s3c24xx_i2s.iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
444 writel(s3c24xx_i2s.iispsr, s3c24xx_i2s.regs + S3C2410_IISPSR);
445
446 return 0;
447 }
448 #else
449 #define s3c24xx_i2s_suspend NULL
450 #define s3c24xx_i2s_resume NULL
451 #endif
452
453
454 #define S3C24XX_I2S_RATES \
455 (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
456 SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
457 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
458
459 struct snd_soc_dai s3c24xx_i2s_dai = {
460 .name = "s3c24xx-i2s",
461 .id = 0,
462 .type = SND_SOC_DAI_I2S,
463 .probe = s3c24xx_i2s_probe,
464 .suspend = s3c24xx_i2s_suspend,
465 .resume = s3c24xx_i2s_resume,
466 .playback = {
467 .channels_min = 2,
468 .channels_max = 2,
469 .rates = S3C24XX_I2S_RATES,
470 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
471 .capture = {
472 .channels_min = 2,
473 .channels_max = 2,
474 .rates = S3C24XX_I2S_RATES,
475 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
476 .ops = {
477 .trigger = s3c24xx_i2s_trigger,
478 .hw_params = s3c24xx_i2s_hw_params,},
479 .dai_ops = {
480 .set_fmt = s3c24xx_i2s_set_fmt,
481 .set_clkdiv = s3c24xx_i2s_set_clkdiv,
482 .set_sysclk = s3c24xx_i2s_set_sysclk,
483 },
484 };
485 EXPORT_SYMBOL_GPL(s3c24xx_i2s_dai);
486
487 /* Module information */
488 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
489 MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
490 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)