sound/soc/s3c24xx/s3c2443-ac97.c

   1 /*
   2  * s3c2443-ac97.c  --  ALSA Soc Audio Layer
   3  *
   4  * (c) 2007 Wolfson Microelectronics PLC.
   5  * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
   6  *
   7  *  Copyright (C) 2005, Sean Choi <sh428.choi@samsung.com>
   8  *  All rights reserved.
   9  *
  10  *  This program is free software; you can redistribute it and/or modify
  11  *  it under the terms of the GNU General Public License version 2 as
  12  *  published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/wait.h>
  21 #include <linux/delay.h>
  22 #include <linux/clk.h>
  23
  24 #include <sound/core.h>
  25 #include <sound/pcm.h>
  26 #include <sound/ac97_codec.h>
  27 #include <sound/initval.h>
  28 #include <sound/soc.h>
  29
  30 #include <asm/hardware.h>
  31 #include <asm/plat-s3c/regs-ac97.h>
  32 #include <asm/arch/regs-gpio.h>
  33 #include <asm/arch/regs-clock.h>
  34 #include <asm/arch/audio.h>
  35 #include <asm/dma.h>
  36 #include <asm/arch/dma.h>
  37
  38 #include "s3c24xx-pcm.h"
  39 #include "s3c24xx-ac97.h"
  40
  41 struct s3c24xx_ac97_info {
  42         void __iomem    *regs;
  43         struct clk      *ac97_clk;
  44 };
  45 static struct s3c24xx_ac97_info s3c24xx_ac97;
  46
  47 static DECLARE_COMPLETION(ac97_completion);
  48 static u32 codec_ready;
  49 static DECLARE_MUTEX(ac97_mutex);
  50
  51 static unsigned short s3c2443_ac97_read(struct snd_ac97 *ac97,
  52         unsigned short reg)
  53 {
  54         u32 ac_glbctrl;
  55         u32 ac_codec_cmd;
  56         u32 stat, addr, data;
  57
  58         down(&ac97_mutex);
  59
  60         codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
  61         ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
  62         ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
  63         writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
  64
  65         udelay(50);
  66
  67         ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  68         ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
  69         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  70
  71         wait_for_completion(&ac97_completion);
  72
  73         stat = readl(s3c24xx_ac97.regs + S3C_AC97_STAT);
  74         addr = (stat >> 16) & 0x7f;
  75         data = (stat & 0xffff);
  76
  77         if (addr != reg)
  78                 printk(KERN_ERR "s3c24xx-ac97: req addr = %02x,"
  79                                 " rep addr = %02x\n", reg, addr);
  80
  81         up(&ac97_mutex);
  82
  83         return (unsigned short)data;
  84 }
  85
  86 static void s3c2443_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
  87         unsigned short val)
  88 {
  89         u32 ac_glbctrl;
  90         u32 ac_codec_cmd;
  91
  92         down(&ac97_mutex);
  93
  94         codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
  95         ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
  96         ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
  97         writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
  98
  99         udelay(50);
 100
 101         ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 102         ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
 103         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 104
 105         wait_for_completion(&ac97_completion);
 106
 107         ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
 108         ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
 109         writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
 110
 111         up(&ac97_mutex);
 112
 113 }
 114
 115 static void s3c2443_ac97_warm_reset(struct snd_ac97 *ac97)
 116 {
 117         u32 ac_glbctrl;
 118
 119         ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 120         ac_glbctrl = S3C_AC97_GLBCTRL_WARMRESET;
 121         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 122         msleep(1);
 123
 124         ac_glbctrl = 0;
 125         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 126         msleep(1);
 127 }
 128
 129 static void s3c2443_ac97_cold_reset(struct snd_ac97 *ac97)
 130 {
 131         u32 ac_glbctrl;
 132
 133         ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 134         ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
 135         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 136         msleep(1);
 137
 138         ac_glbctrl = 0;
 139         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 140         msleep(1);
 141
 142         ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 143         ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
 144         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 145         msleep(1);
 146
 147         ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
 148         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 149         msleep(1);
 150
 151         ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA |
 152                 S3C_AC97_GLBCTRL_PCMINTM_DMA | S3C_AC97_GLBCTRL_MICINTM_DMA;
 153         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 154 }
 155
 156 static irqreturn_t s3c2443_ac97_irq(int irq, void *dev_id)
 157 {
 158         int status;
 159         u32 ac_glbctrl;
 160
 161         status = readl(s3c24xx_ac97.regs + S3C_AC97_GLBSTAT) & codec_ready;
 162
 163         if (status) {
 164                 ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 165                 ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
 166                 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 167                 complete(&ac97_completion);
 168         }
 169         return IRQ_HANDLED;
 170 }
 171
 172 struct snd_ac97_bus_ops soc_ac97_ops = {
 173         .read   = s3c2443_ac97_read,
 174         .write  = s3c2443_ac97_write,
 175         .warm_reset     = s3c2443_ac97_warm_reset,
 176         .reset  = s3c2443_ac97_cold_reset,
 177 };
 178
 179 static struct s3c2410_dma_client s3c2443_dma_client_out = {
 180         .name = "AC97 PCM Stereo out"
 181 };
 182
 183 static struct s3c2410_dma_client s3c2443_dma_client_in = {
 184         .name = "AC97 PCM Stereo in"
 185 };
 186
 187 static struct s3c2410_dma_client s3c2443_dma_client_micin = {
 188         .name = "AC97 Mic Mono in"
 189 };
 190
 191 static struct s3c24xx_pcm_dma_params s3c2443_ac97_pcm_stereo_out = {
 192         .client         = &s3c2443_dma_client_out,
 193         .channel        = DMACH_PCM_OUT,
 194         .dma_addr       = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
 195         .dma_size       = 4,
 196 };
 197
 198 static struct s3c24xx_pcm_dma_params s3c2443_ac97_pcm_stereo_in = {
 199         .client         = &s3c2443_dma_client_in,
 200         .channel        = DMACH_PCM_IN,
 201         .dma_addr       = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
 202         .dma_size       = 4,
 203 };
 204
 205 static struct s3c24xx_pcm_dma_params s3c2443_ac97_mic_mono_in = {
 206         .client         = &s3c2443_dma_client_micin,
 207         .channel        = DMACH_MIC_IN,
 208         .dma_addr       = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
 209         .dma_size       = 4,
 210 };
 211
 212 static int s3c2443_ac97_probe(struct platform_device *pdev)
 213 {
 214         int ret;
 215         u32 ac_glbctrl;
 216
 217         s3c24xx_ac97.regs = ioremap(S3C2440_PA_AC97, 0x100);
 218         if (s3c24xx_ac97.regs == NULL)
 219                 return -ENXIO;
 220
 221         s3c24xx_ac97.ac97_clk = clk_get(&pdev->dev, "ac97");
 222         if (s3c24xx_ac97.ac97_clk == NULL) {
 223                 printk(KERN_ERR "s3c2443-ac97 failed to get ac97_clock\n");
 224                 iounmap(s3c24xx_ac97.regs);
 225                 return -ENODEV;
 226         }
 227         clk_enable(s3c24xx_ac97.ac97_clk);
 228
 229         s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2443_GPE0_AC_nRESET);
 230         s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2443_GPE1_AC_SYNC);
 231         s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2443_GPE2_AC_BITCLK);
 232         s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2443_GPE3_AC_SDI);
 233         s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2443_GPE4_AC_SDO);
 234
 235         ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 236         ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
 237         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 238         msleep(1);
 239
 240         ac_glbctrl = 0;
 241         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 242         msleep(1);
 243
 244         ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 245         ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
 246         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 247         msleep(1);
 248
 249         ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
 250         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 251
 252         ret = request_irq(IRQ_S3C244x_AC97, s3c2443_ac97_irq,
 253                 IRQF_DISABLED, "AC97", NULL);
 254         if (ret < 0) {
 255                 printk(KERN_ERR "s3c24xx-ac97: interrupt request failed.\n");
 256                 clk_disable(s3c24xx_ac97.ac97_clk);
 257                 clk_put(s3c24xx_ac97.ac97_clk);
 258                 iounmap(s3c24xx_ac97.regs);
 259         }
 260         return ret;
 261 }
 262
 263 static void s3c2443_ac97_remove(struct platform_device *pdev)
 264 {
 265         free_irq(IRQ_S3C244x_AC97, NULL);
 266         clk_disable(s3c24xx_ac97.ac97_clk);
 267         clk_put(s3c24xx_ac97.ac97_clk);
 268         iounmap(s3c24xx_ac97.regs);
 269 }
 270
 271 static int s3c2443_ac97_hw_params(struct snd_pcm_substream *substream,
 272                                 struct snd_pcm_hw_params *params)
 273 {
 274         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 275         struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
 276
 277         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 278                 cpu_dai->dma_data = &s3c2443_ac97_pcm_stereo_out;
 279         else
 280                 cpu_dai->dma_data = &s3c2443_ac97_pcm_stereo_in;
 281
 282         return 0;
 283 }
 284
 285 static int s3c2443_ac97_trigger(struct snd_pcm_substream *substream, int cmd)
 286 {
 287         u32 ac_glbctrl;
 288
 289         ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 290         switch (cmd) {
 291         case SNDRV_PCM_TRIGGER_START:
 292         case SNDRV_PCM_TRIGGER_RESUME:
 293         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 294                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 295                         ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
 296                 else
 297                         ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
 298                 break;
 299         case SNDRV_PCM_TRIGGER_STOP:
 300         case SNDRV_PCM_TRIGGER_SUSPEND:
 301         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 302                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 303                         ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
 304                 else
 305                         ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
 306                 break;
 307         }
 308         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 309
 310         return 0;
 311 }
 312
 313 static int s3c2443_ac97_hw_mic_params(struct snd_pcm_substream *substream,
 314         struct snd_pcm_hw_params *params)
 315 {
 316         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 317         struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
 318
 319         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 320                 return -ENODEV;
 321         else
 322                 cpu_dai->dma_data = &s3c2443_ac97_mic_mono_in;
 323
 324         return 0;
 325 }
 326
 327 static int s3c2443_ac97_mic_trigger(struct snd_pcm_substream *substream,
 328         int cmd)
 329 {
 330         u32 ac_glbctrl;
 331
 332         ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 333         switch (cmd) {
 334         case SNDRV_PCM_TRIGGER_START:
 335         case SNDRV_PCM_TRIGGER_RESUME:
 336         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 337                 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
 338                 break;
 339         case SNDRV_PCM_TRIGGER_STOP:
 340         case SNDRV_PCM_TRIGGER_SUSPEND:
 341         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 342                 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
 343         }
 344         writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
 345
 346         return 0;
 347 }
 348
 349 #define s3c2443_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
 350                 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
 351                 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
 352
 353 struct snd_soc_cpu_dai s3c2443_ac97_dai[] = {
 354 {
 355         .name = "s3c2443-ac97",
 356         .id = 0,
 357         .type = SND_SOC_DAI_AC97,
 358         .probe = s3c2443_ac97_probe,
 359         .remove = s3c2443_ac97_remove,
 360         .playback = {
 361                 .stream_name = "AC97 Playback",
 362                 .channels_min = 2,
 363                 .channels_max = 2,
 364                 .rates = s3c2443_AC97_RATES,
 365                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 366         .capture = {
 367                 .stream_name = "AC97 Capture",
 368                 .channels_min = 2,
 369                 .channels_max = 2,
 370                 .rates = s3c2443_AC97_RATES,
 371                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 372         .ops = {
 373                 .hw_params = s3c2443_ac97_hw_params,
 374                 .trigger = s3c2443_ac97_trigger},
 375 },
 376 {
 377         .name = "pxa2xx-ac97-mic",
 378         .id = 1,
 379         .type = SND_SOC_DAI_AC97,
 380         .capture = {
 381                 .stream_name = "AC97 Mic Capture",
 382                 .channels_min = 1,
 383                 .channels_max = 1,
 384                 .rates = s3c2443_AC97_RATES,
 385                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 386         .ops = {
 387                 .hw_params = s3c2443_ac97_hw_mic_params,
 388                 .trigger = s3c2443_ac97_mic_trigger,},
 389 },
 390 };
 391 EXPORT_SYMBOL_GPL(s3c2443_ac97_dai);
 392 EXPORT_SYMBOL_GPL(soc_ac97_ops);
 393
 394 MODULE_AUTHOR("Graeme Gregory");
 395 MODULE_DESCRIPTION("AC97 driver for the Samsung s3c2443 chip");
 396 MODULE_LICENSE("GPL");