sound/soc/mediatek/mt_soc_audio_v3/mt_soc_pcm_dl1.c

   1 /*
   2  * Copyright (C) 2007 The Android Open Source Project
   3  *
   4  * Licensed under the Apache License, Version 2.0 (the "License");
   5  * you may not use this file except in compliance with the License.
   6  * You may obtain a copy of the License at
   7  *
   8  *      http://www.apache.org/licenses/LICENSE-2.0
   9  *
  10  * Unless required by applicable law or agreed to in writing, software
  11  * distributed under the License is distributed on an "AS IS" BASIS,
  12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13  * See the License for the specific language governing permissions and
  14  * limitations under the License.
  15  */
  16 /*******************************************************************************
  17  *
  18  * Filename:
  19  * ---------
  20  *   mt_soc_pcm_afe.c
  21  *
  22  * Project:
  23  * --------
  24  *    Audio Driver Kernel Function
  25  *
  26  * Description:
  27  * ------------
  28  *   Audio dl1 data1 playback
  29  *
  30  * Author:
  31  * -------
  32  * Chipeng Chang
  33  *
  34  *------------------------------------------------------------------------------
  35  * $Revision: #1 $
  36  * $Modtime:$
  37  * $Log:$
  38  *
  39  *
  40  *******************************************************************************/
  41
  42
  43 /*****************************************************************************
  44  *                     C O M P I L E R   F L A G S
  45  *****************************************************************************/
  46
  47
  48 /*****************************************************************************
  49  *                E X T E R N A L   R E F E R E N C E S
  50  *****************************************************************************/
  51
  52 #include "AudDrv_Common.h"
  53 #include "AudDrv_Def.h"
  54 #include "AudDrv_Afe.h"
  55 #include "AudDrv_Ana.h"
  56 #include "AudDrv_Clk.h"
  57 #include "AudDrv_Kernel.h"
  58 #include "mt_soc_afe_control.h"
  59 #include "mt_soc_digital_type.h"
  60 #include "mt_soc_pcm_common.h"
  61
  62 #include <linux/kernel.h>
  63 #include <linux/module.h>
  64 #include <linux/init.h>
  65 #include <linux/device.h>
  66 #include <linux/slab.h>
  67 #include <linux/fs.h>
  68 #include <linux/completion.h>
  69 #include <linux/mm.h>
  70 #include <linux/delay.h>
  71 #include <linux/interrupt.h>
  72 #include <linux/dma-mapping.h>
  73 #include <linux/vmalloc.h>
  74 #include <linux/platform_device.h>
  75 #include <linux/miscdevice.h>
  76 #include <linux/wait.h>
  77 #include <linux/spinlock.h>
  78 #include <linux/sched.h>
  79 #include <linux/wakelock.h>
  80 #include <linux/semaphore.h>
  81 #include <linux/jiffies.h>
  82 #include <linux/proc_fs.h>
  83 #include <linux/string.h>
  84 #include <linux/mutex.h>
  85 #include <linux/xlog.h>
  86 #include <mach/irqs.h>
  87 #include <asm/uaccess.h>
  88 #include <asm/irq.h>
  89 #include <asm/io.h>
  90 #include <mach/mt_reg_base.h>
  91 #include <asm/div64.h>
  92 #include <linux/aee.h>
  93 #include <mach/upmu_common.h>
  94 #include <mach/upmu_hw.h>
  95 #include <mach/mt_gpio.h>
  96 #include <mach/mt_typedefs.h>
  97 #include <linux/clk.h>
  98 #include <linux/delay.h>
  99 #include <linux/platform_device.h>
 100 #include <linux/slab.h>
 101 #include <sound/core.h>
 102 #include <sound/soc.h>
 103 #include <sound/soc-dapm.h>
 104 #include <sound/pcm.h>
 105 //#include <asm/mach-types.h>
 106
 107 #ifdef CONFIG_OF
 108 #include <linux/of.h>
 109 #include <linux/of_irq.h>
 110 #include <linux/of_address.h>
 111 static unsigned int pin_extspkamp, pin_vowclk, pin_audclk, pin_audmiso, pin_audmosi, pin_i2s1clk, pin_i2s1dat, pin_i2s1mclk, pin_i2s1ws;
 112 static unsigned int pin_mode_audclk, pin_mode_audmosi, pin_mode_audmiso, pin_mode_vowclk, pin_mode_extspkamp, pin_mode_i2s1clk, pin_mode_i2s1dat, pin_mode_i2s1mclk, pin_mode_i2s1ws;
 113 static unsigned int if_config1, if_config2, if_config3, if_config4, if_config5, if_config6, if_config7, if_config8, if_config9;
 114 #endif
 115
 116 static AFE_MEM_CONTROL_T *pMemControl = NULL;
 117 static int mPlaybackSramState = 0;
 118 static struct snd_dma_buffer *Dl1_Playback_dma_buf  = NULL;
 119
 120 static DEFINE_SPINLOCK(auddrv_DLCtl_lock);
 121
 122 static struct device *mDev = NULL;
 123
 124 /*
 125  *    function implementation
 126  */
 127
 128 void StartAudioPcmHardware(void);
 129 void StopAudioPcmHardware(void);
 130 static int mtk_soc_dl1_probe(struct platform_device *pdev);
 131 static int mtk_soc_pcm_dl1_close(struct snd_pcm_substream *substream);
 132 static int mtk_asoc_pcm_dl1_new(struct snd_soc_pcm_runtime *rtd);
 133 static int mtk_asoc_dl1_probe(struct snd_soc_platform *platform);
 134
 135 static bool mPrepareDone = false;
 136
 137 #define USE_RATE        SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000
 138 #define USE_RATE_MIN        8000
 139 #define USE_RATE_MAX        192000
 140 #define USE_CHANNELS_MIN     1
 141 #define USE_CHANNELS_MAX    2
 142 #define USE_PERIODS_MIN     512
 143 #define USE_PERIODS_MAX     8192
 144
 145 static struct snd_pcm_hardware mtk_pcm_dl1_hardware =
 146 {
 147     .info = (SNDRV_PCM_INFO_MMAP |
 148     SNDRV_PCM_INFO_INTERLEAVED |
 149     SNDRV_PCM_INFO_RESUME |
 150     SNDRV_PCM_INFO_MMAP_VALID),
 151     .formats =      SND_SOC_ADV_MT_FMTS,
 152     .rates =           SOC_HIGH_USE_RATE,
 153     .rate_min =     SOC_HIGH_USE_RATE_MIN,
 154     .rate_max =     SOC_HIGH_USE_RATE_MAX,
 155     .channels_min =     SOC_NORMAL_USE_CHANNELS_MIN,
 156     .channels_max =     SOC_NORMAL_USE_CHANNELS_MAX,
 157     .buffer_bytes_max = Dl1_MAX_BUFFER_SIZE,
 158     .period_bytes_max = Dl1_MAX_PERIOD_SIZE,
 159     .periods_min =      SOC_NORMAL_USE_PERIODS_MIN,
 160     .periods_max =    SOC_NORMAL_USE_PERIODS_MAX,
 161     .fifo_size =        0,
 162 };
 163
 164 static int mtk_pcm_dl1_stop(struct snd_pcm_substream *substream)
 165 {
 166     printk("%s \n", __func__);
 167
 168     SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, false);
 169     SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DL1, false);
 170
 171     // here start digital part
 172     SetConnection(Soc_Aud_InterCon_DisConnect, Soc_Aud_InterConnectionInput_I05, Soc_Aud_InterConnectionOutput_O03);
 173     SetConnection(Soc_Aud_InterCon_DisConnect, Soc_Aud_InterConnectionInput_I06, Soc_Aud_InterConnectionOutput_O04);
 174
 175     ClearMemBlock(Soc_Aud_Digital_Block_MEM_DL1);
 176     return 0;
 177 }
 178
 179 static snd_pcm_uframes_t mtk_pcm_pointer(struct snd_pcm_substream *substream)
 180 {
 181     kal_int32 HW_memory_index = 0;
 182     kal_int32 HW_Cur_ReadIdx = 0;
 183     kal_uint32 Frameidx = 0;
 184     kal_int32 Afe_consumed_bytes = 0;
 185     AFE_BLOCK_T *Afe_Block = &pMemControl->rBlock;
 186     //struct snd_pcm_runtime *runtime = substream->runtime;
 187     PRINTK_AUD_DL1(" %s Afe_Block->u4DMAReadIdx = 0x%x\n", __func__, Afe_Block->u4DMAReadIdx);
 188
 189     Auddrv_Dl1_Spinlock_lock();
 190
 191     // get total bytes to copy
 192     //Frameidx = audio_bytes_to_frame(substream , Afe_Block->u4DMAReadIdx);
 193     //return Frameidx;
 194
 195     if (GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DL1) == true)
 196     {
 197         HW_Cur_ReadIdx = Afe_Get_Reg(AFE_DL1_CUR);
 198         if (HW_Cur_ReadIdx == 0)
 199         {
 200             PRINTK_AUDDRV("[Auddrv] HW_Cur_ReadIdx ==0 \n");
 201             HW_Cur_ReadIdx = Afe_Block->pucPhysBufAddr;
 202         }
 203
 204         HW_memory_index = (HW_Cur_ReadIdx - Afe_Block->pucPhysBufAddr);
 205         if (HW_memory_index >=  Afe_Block->u4DMAReadIdx)
 206         {
 207             Afe_consumed_bytes = HW_memory_index - Afe_Block->u4DMAReadIdx;
 208         }
 209         else
 210         {
 211             Afe_consumed_bytes = Afe_Block->u4BufferSize + HW_memory_index - Afe_Block->u4DMAReadIdx ;
 212         }
 213
 214         Afe_consumed_bytes = Align64ByteSize(Afe_consumed_bytes);
 215
 216         Afe_Block->u4DataRemained -= Afe_consumed_bytes;
 217         Afe_Block->u4DMAReadIdx += Afe_consumed_bytes;
 218         Afe_Block->u4DMAReadIdx %= Afe_Block->u4BufferSize;
 219         PRINTK_AUD_DL1("[Auddrv] HW_Cur_ReadIdx =0x%x HW_memory_index = 0x%x Afe_consumed_bytes  = 0x%x\n", HW_Cur_ReadIdx, HW_memory_index, Afe_consumed_bytes);
 220         Auddrv_Dl1_Spinlock_unlock();
 221
 222         return audio_bytes_to_frame(substream , Afe_Block->u4DMAReadIdx);
 223     }
 224     else
 225     {
 226         Frameidx = audio_bytes_to_frame(substream , Afe_Block->u4DMAReadIdx);
 227         Auddrv_Dl1_Spinlock_unlock();
 228         return Frameidx;
 229     }
 230 }
 231
 232 static void SetDL1Buffer(struct snd_pcm_substream *substream,
 233                          struct snd_pcm_hw_params *hw_params)
 234 {
 235     struct snd_pcm_runtime *runtime = substream->runtime;
 236     AFE_BLOCK_T *pblock = &pMemControl->rBlock;
 237     pblock->pucPhysBufAddr =  runtime->dma_addr;
 238     pblock->pucVirtBufAddr =  runtime->dma_area;
 239     pblock->u4BufferSize = runtime->dma_bytes;
 240     pblock->u4SampleNumMask = 0x001f;  // 32 byte align
 241     pblock->u4WriteIdx     = 0;
 242     pblock->u4DMAReadIdx    = 0;
 243     pblock->u4DataRemained  = 0;
 244     pblock->u4fsyncflag     = false;
 245     pblock->uResetFlag      = true;
 246     printk("SetDL1Buffer u4BufferSize = %d pucVirtBufAddr = %p pucPhysBufAddr = 0x%x\n",
 247            pblock->u4BufferSize, pblock->pucVirtBufAddr, pblock->pucPhysBufAddr);
 248     // set dram address top hardware
 249     Afe_Set_Reg(AFE_DL1_BASE , pblock->pucPhysBufAddr , 0xffffffff);
 250     Afe_Set_Reg(AFE_DL1_END  , pblock->pucPhysBufAddr + (pblock->u4BufferSize - 1), 0xffffffff);
 251     memset((void *)pblock->pucVirtBufAddr, 0, pblock->u4BufferSize);
 252
 253 }
 254
 255 static int mtk_pcm_dl1_params(struct snd_pcm_substream *substream,
 256                               struct snd_pcm_hw_params *hw_params)
 257 {
 258     //struct snd_dma_buffer *dma_buf = &substream->dma_buffer;
 259     int ret = 0;
 260     PRINTK_AUDDRV("mtk_pcm_dl1_params \n");
 261
 262     /* runtime->dma_bytes has to be set manually to allow mmap */
 263     substream->runtime->dma_bytes = params_buffer_bytes(hw_params);
 264
 265     if (mPlaybackSramState == SRAM_STATE_PLAYBACKFULL)
 266     {
 267         //substream->runtime->dma_bytes = AFE_INTERNAL_SRAM_SIZE;
 268         substream->runtime->dma_area = (unsigned char *)Get_Afe_SramBase_Pointer();
 269         substream->runtime->dma_addr = AFE_INTERNAL_SRAM_PHY_BASE;
 270         AudDrv_Allocate_DL1_Buffer(mDev, substream->runtime->dma_bytes);
 271     }
 272     else
 273     {
 274         substream->runtime->dma_bytes = params_buffer_bytes(hw_params);
 275         substream->runtime->dma_area = Dl1_Playback_dma_buf->area;
 276         substream->runtime->dma_addr = Dl1_Playback_dma_buf->addr;
 277         SetDL1Buffer(substream, hw_params);
 278     }
 279
 280     PRINTK_AUDDRV("dma_bytes = %zu dma_area = %p dma_addr = 0x%lx\n",
 281                   substream->runtime->dma_bytes, substream->runtime->dma_area, (long)substream->runtime->dma_addr);
 282     return ret;
 283 }
 284
 285 static int mtk_pcm_dl1_hw_free(struct snd_pcm_substream *substream)
 286 {
 287     PRINTK_AUDDRV("mtk_pcm_dl1_hw_free \n");
 288     return 0;
 289 }
 290
 291
 292 static struct snd_pcm_hw_constraint_list constraints_sample_rates =
 293 {
 294     .count = ARRAY_SIZE(soc_high_supported_sample_rates),
 295     .list = soc_high_supported_sample_rates,
 296     .mask = 0,
 297 };
 298
 299 static int mtk_pcm_dl1_open(struct snd_pcm_substream *substream)
 300 {
 301     int ret = 0;
 302     struct snd_pcm_runtime *runtime = substream->runtime;
 303     PRINTK_AUDDRV("mtk_pcm_dl1_open\n");
 304
 305     AfeControlSramLock();
 306     if (GetSramState() == SRAM_STATE_FREE)
 307     {
 308         mtk_pcm_dl1_hardware.buffer_bytes_max = GetPLaybackSramFullSize();
 309         mPlaybackSramState = SRAM_STATE_PLAYBACKFULL;
 310         SetSramState(mPlaybackSramState);
 311     }
 312     else
 313     {
 314         mtk_pcm_dl1_hardware.buffer_bytes_max = GetPLaybackDramSize();
 315         mPlaybackSramState = SRAM_STATE_PLAYBACKDRAM;
 316     }
 317     AfeControlSramUnLock();
 318     if (mPlaybackSramState == SRAM_STATE_PLAYBACKDRAM)
 319     {
 320         AudDrv_Emi_Clk_On();
 321     }
 322
 323     printk("mtk_pcm_dl1_hardware.buffer_bytes_max = %zu mPlaybackSramState = %d\n", mtk_pcm_dl1_hardware.buffer_bytes_max, mPlaybackSramState);
 324     runtime->hw = mtk_pcm_dl1_hardware;
 325
 326     AudDrv_Clk_On();
 327     memcpy((void *)(&(runtime->hw)), (void *)&mtk_pcm_dl1_hardware , sizeof(struct snd_pcm_hardware));
 328     pMemControl = Get_Mem_ControlT(Soc_Aud_Digital_Block_MEM_DL1);
 329
 330     ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
 331                                      &constraints_sample_rates);
 332
 333     if (ret < 0)
 334     {
 335         printk("snd_pcm_hw_constraint_integer failed\n");
 336     }
 337
 338     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 339     {
 340         printk("SNDRV_PCM_STREAM_PLAYBACK mtkalsa_dl1playback_constraints\n");
 341     }
 342     else
 343     {
 344         printk("SNDRV_PCM_STREAM_CAPTURE mtkalsa_dl1playback_constraints\n");
 345     }
 346
 347     if (ret < 0)
 348     {
 349         printk("ret < 0 mtk_soc_pcm_dl1_close\n");
 350         mtk_soc_pcm_dl1_close(substream);
 351         return ret;
 352     }
 353
 354     //PRINTK_AUDDRV("mtk_pcm_dl1_open return\n");
 355     return 0;
 356 }
 357
 358 static int mtk_soc_pcm_dl1_close(struct snd_pcm_substream *substream)
 359 {
 360     printk("%s \n", __func__);
 361     if (mPrepareDone == true)
 362     {
 363         // stop DAC output
 364         SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, false);
 365         if (GetI2SDacEnable() == false)
 366         {
 367             SetI2SDacEnable(false);
 368         }
 369
 370         RemoveMemifSubStream(Soc_Aud_Digital_Block_MEM_DL1, substream);
 371
 372         EnableAfe(false);
 373         mPrepareDone = false;
 374     }
 375
 376     if (mPlaybackSramState == SRAM_STATE_PLAYBACKDRAM)
 377     {
 378         AudDrv_Emi_Clk_Off();
 379     }
 380     AfeControlSramLock();
 381     ClearSramState(mPlaybackSramState);
 382     mPlaybackSramState = GetSramState();
 383     AfeControlSramUnLock();
 384     AudDrv_Clk_Off();
 385     return 0;
 386 }
 387
 388 static int mtk_pcm_prepare(struct snd_pcm_substream *substream)
 389 {
 390     bool mI2SWLen;
 391     struct snd_pcm_runtime *runtime = substream->runtime;
 392     if (mPrepareDone == false)
 393     {
 394         printk("%s format = %d SNDRV_PCM_FORMAT_S32_LE = %d SNDRV_PCM_FORMAT_U32_LE = %d \n", __func__, runtime->format, SNDRV_PCM_FORMAT_S32_LE, SNDRV_PCM_FORMAT_U32_LE);
 395         SetMemifSubStream(Soc_Aud_Digital_Block_MEM_DL1, substream);
 396
 397         if (runtime->format == SNDRV_PCM_FORMAT_S32_LE || runtime->format == SNDRV_PCM_FORMAT_U32_LE)
 398         {
 399             SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL1, AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA);
 400             SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL2, AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA);
 401             SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_24BIT, Soc_Aud_InterConnectionOutput_O03);
 402             SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_24BIT, Soc_Aud_InterConnectionOutput_O04);
 403             mI2SWLen = Soc_Aud_I2S_WLEN_WLEN_32BITS;
 404         }
 405         else
 406         {
 407             SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL1, AFE_WLEN_16_BIT);
 408             SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL2, AFE_WLEN_16_BIT);
 409             SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O03);
 410             SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O04);
 411             mI2SWLen = Soc_Aud_I2S_WLEN_WLEN_16BITS;
 412         }
 413
 414         SetSampleRate(Soc_Aud_Digital_Block_MEM_I2S,  runtime->rate);
 415
 416         // start I2S DAC out
 417         if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC) == false)
 418         {
 419             SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, true);
 420             SetI2SDacOut(substream->runtime->rate, false, mI2SWLen);
 421             SetI2SDacEnable(true);
 422         }
 423         else
 424         {
 425             SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, true);
 426         }
 427         // here to set interrupt_distributor
 428         SetIrqMcuCounter(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, runtime->period_size);
 429         SetIrqMcuSampleRate(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, runtime->rate);
 430
 431         EnableAfe(true);
 432         mPrepareDone = true;
 433     }
 434     return 0;
 435 }
 436
 437
 438 static int mtk_pcm_dl1_start(struct snd_pcm_substream *substream)
 439 {
 440     struct snd_pcm_runtime *runtime = substream->runtime;
 441     printk("%s\n", __func__);
 442     // here start digital part
 443
 444     SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I05, Soc_Aud_InterConnectionOutput_O03);
 445     SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I06, Soc_Aud_InterConnectionOutput_O04);
 446
 447     SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, true);
 448
 449     SetSampleRate(Soc_Aud_Digital_Block_MEM_DL1, runtime->rate);
 450     SetChannels(Soc_Aud_Digital_Block_MEM_DL1, runtime->channels);
 451     SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DL1, true);
 452
 453     EnableAfe(true);
 454
 455 #ifdef DENALI_FPGA_EARLYPORTING //ccc early porting, copy from TurnOnDacPower() and ADC_LOOP_DAC_Func()
 456     printk("%s pcm loopback_b \n", __func__);
 457         Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0000, 0xffff);   //power on clock
 458
 459         Ana_Set_Reg(AFUNC_AUD_CON2, 0x0006, 0xffffffff);
 460         Ana_Set_Reg(AFUNC_AUD_CON0, 0xc3a1, 0xffffffff); //sdm audio fifo clock power on
 461         Ana_Set_Reg(AFUNC_AUD_CON2, 0x0003, 0xffffffff); //sdm power on
 462         Ana_Set_Reg(AFUNC_AUD_CON2, 0x000b, 0xffffffff); //sdm fifo enable
 463         Ana_Set_Reg(AFE_DL_SDM_CON1, 0x001e, 0xffffffff); //set attenuation gain
 464         Ana_Set_Reg(AFE_UL_DL_CON0 , 0x0001, 0xffffffff); //[0] afe enable
 465
 466         //Ana_Set_Reg(AFE_UL_SRC0_CON0_H, 0x0000 , 0x0010); // UL1
 467         //      Ana_Set_Reg(AFE_UL_SRC0_CON0_L, 0x0001, 0xffff);   //power on uplink
 468         //Ana_Set_Reg(AFE_PMIC_NEWIF_CFG0, 0x0380, 0xffff); //MTKIF
 469         //Ana_Set_Reg(AFE_DL_SRC2_CON0_H, 0x0800, 0xffff);   //DL
 470         //Ana_Set_Reg(AFE_DL_SRC2_CON0_L, 0x0001, 0xffff); //DL
 471
 472 //    Ana_Set_Reg(AFE_PMIC_NEWIF_CFG0 , 0 << 12 | 0x330 , 0xffffffff); //8k sample rate
 473     Ana_Set_Reg(AFE_PMIC_NEWIF_CFG0 , 8 << 12 | 0x330 , 0xffffffff); //48k sample rate
 474
 475 //    Ana_Set_Reg(AFE_DL_SRC2_CON0_H , 0 << 12 | 0x300 , 0xffffffff);//8k sample rate
 476     Ana_Set_Reg(AFE_DL_SRC2_CON0_H , 8 << 12 | 0x300 , 0xffffffff); //48k sample rate
 477     Ana_Set_Reg(AFE_DL_SRC2_CON0_L , 0x0001 , 0xffffffff); //turn off mute function and turn on dl
 478     Ana_Set_Reg(PMIC_AFE_TOP_CON0 , 0x0000 , 0xffffffff); //set DL in normal path, not from sine gen table
 479     Afe_Set_Reg(FPGA_CFG1, 0x1, 0xffff); // must set in FPGA platform for PMIC digital loopback
 480
 481     printk("%s pcm loopback_e \n", __func__);
 482 #endif
 483
 484
 485     return 0;
 486 }
 487
 488 static int mtk_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 489 {
 490     PRINTK_AUDDRV("mtk_pcm_trigger cmd = %d\n", cmd);
 491     switch (cmd)
 492     {
 493         case SNDRV_PCM_TRIGGER_START:
 494         case SNDRV_PCM_TRIGGER_RESUME:
 495             return mtk_pcm_dl1_start(substream);
 496         case SNDRV_PCM_TRIGGER_STOP:
 497         case SNDRV_PCM_TRIGGER_SUSPEND:
 498             return mtk_pcm_dl1_stop(substream);
 499     }
 500     return -EINVAL;
 501 }
 502
 503 static int mtk_pcm_copy(struct snd_pcm_substream *substream,
 504                         int channel, snd_pcm_uframes_t pos,
 505                         void __user *dst, snd_pcm_uframes_t count)
 506 {
 507     AFE_BLOCK_T  *Afe_Block = NULL;
 508     int copy_size = 0, Afe_WriteIdx_tmp;
 509     unsigned long flags;
 510     //struct snd_pcm_runtime *runtime = substream->runtime;
 511     char *data_w_ptr = (char *)dst;
 512     PRINTK_AUD_DL1("mtk_pcm_copy pos = %lu count = %lu\n ", pos, count);
 513     // get total bytes to copy
 514     count = audio_frame_to_bytes(substream , count);
 515
 516     // check which memif nned to be write
 517     Afe_Block = &pMemControl->rBlock;
 518
 519     PRINTK_AUD_DL1("AudDrv_write WriteIdx=0x%x, ReadIdx=0x%x, DataRemained=0x%x \n",
 520                    Afe_Block->u4WriteIdx, Afe_Block->u4DMAReadIdx, Afe_Block->u4DataRemained);
 521
 522     if (Afe_Block->u4BufferSize == 0)
 523     {
 524         printk("AudDrv_write: u4BufferSize=0 Error");
 525         return 0;
 526     }
 527
 528     spin_lock_irqsave(&auddrv_DLCtl_lock, flags);
 529     copy_size = Afe_Block->u4BufferSize - Afe_Block->u4DataRemained;  //  free space of the buffer
 530     spin_unlock_irqrestore(&auddrv_DLCtl_lock, flags);
 531     if (count <=  copy_size)
 532     {
 533         if (copy_size < 0)
 534         {
 535             copy_size = 0;
 536         }
 537         else
 538         {
 539             copy_size = count;
 540         }
 541     }
 542
 543     copy_size = Align64ByteSize(copy_size);
 544     PRINTK_AUD_DL1("copy_size=0x%x, count=0x%x \n", copy_size,(unsigned int) count);
 545
 546     if (copy_size != 0)
 547     {
 548         spin_lock_irqsave(&auddrv_DLCtl_lock, flags);
 549         Afe_WriteIdx_tmp = Afe_Block->u4WriteIdx;
 550         spin_unlock_irqrestore(&auddrv_DLCtl_lock, flags);
 551
 552         if (Afe_WriteIdx_tmp + copy_size < Afe_Block->u4BufferSize) // copy once
 553         {
 554             if (!access_ok(VERIFY_READ, data_w_ptr, copy_size))
 555             {
 556                 PRINTK_AUDDRV("AudDrv_write 0ptr invalid data_w_ptr=%p, size=%d", data_w_ptr, copy_size);
 557                 PRINTK_AUDDRV("AudDrv_write u4BufferSize=%d, u4DataRemained=%d", Afe_Block->u4BufferSize, Afe_Block->u4DataRemained);
 558             }
 559             else
 560             {
 561                 PRINTK_AUD_DL1("memcpy Afe_Block->pucVirtBufAddr+Afe_WriteIdx= %p data_w_ptr = %p copy_size = 0x%x\n",
 562                                Afe_Block->pucVirtBufAddr + Afe_WriteIdx_tmp, data_w_ptr, copy_size);
 563                 if (copy_from_user((Afe_Block->pucVirtBufAddr + Afe_WriteIdx_tmp), data_w_ptr, copy_size))
 564                 {
 565                     PRINTK_AUDDRV("AudDrv_write Fail copy from user \n");
 566                     return -1;
 567                 }
 568             }
 569
 570             spin_lock_irqsave(&auddrv_DLCtl_lock, flags);
 571             Afe_Block->u4DataRemained += copy_size;
 572             Afe_Block->u4WriteIdx = Afe_WriteIdx_tmp + copy_size;
 573             Afe_Block->u4WriteIdx %= Afe_Block->u4BufferSize;
 574             spin_unlock_irqrestore(&auddrv_DLCtl_lock, flags);
 575             data_w_ptr += copy_size;
 576             count -= copy_size;
 577
 578             PRINTK_AUD_DL1("AudDrv_write finish1, copy_size:%x, WriteIdx:%x, ReadIdx=%x, DataRemained:%x, count=%d \r\n",
 579                            copy_size, Afe_Block->u4WriteIdx, Afe_Block->u4DMAReadIdx, Afe_Block->u4DataRemained, (int)count);
 580
 581         }
 582         else  // copy twice
 583         {
 584             kal_uint32 size_1 = 0, size_2 = 0;
 585             size_1 = Align64ByteSize((Afe_Block->u4BufferSize - Afe_WriteIdx_tmp));
 586             size_2 = Align64ByteSize((copy_size - size_1));
 587             PRINTK_AUD_DL1("size_1=0x%x, size_2=0x%x \n", size_1, size_2);
 588             if (!access_ok(VERIFY_READ, data_w_ptr, size_1))
 589             {
 590                 printk("AudDrv_write 1ptr invalid data_w_ptr=%p, size_1=%d", data_w_ptr, size_1);
 591                 printk("AudDrv_write u4BufferSize=%d, u4DataRemained=%d", Afe_Block->u4BufferSize, Afe_Block->u4DataRemained);
 592             }
 593             else
 594             {
 595
 596                 PRINTK_AUD_DL1("mcmcpy Afe_Block->pucVirtBufAddr+Afe_WriteIdx= %p data_w_ptr = %p size_1 = %x\n",
 597                               Afe_Block->pucVirtBufAddr + Afe_WriteIdx_tmp, data_w_ptr, size_1);
 598                 if ((copy_from_user((Afe_Block->pucVirtBufAddr + Afe_WriteIdx_tmp), data_w_ptr , (unsigned int)size_1)))
 599                 {
 600                     PRINTK_AUDDRV("AudDrv_write Fail 1 copy from user");
 601                     return -1;
 602                 }
 603             }
 604             spin_lock_irqsave(&auddrv_DLCtl_lock, flags);
 605             Afe_Block->u4DataRemained += size_1;
 606             Afe_Block->u4WriteIdx = Afe_WriteIdx_tmp + size_1;
 607             Afe_Block->u4WriteIdx %= Afe_Block->u4BufferSize;
 608             Afe_WriteIdx_tmp = Afe_Block->u4WriteIdx;
 609             spin_unlock_irqrestore(&auddrv_DLCtl_lock, flags);
 610
 611             if (!access_ok(VERIFY_READ, data_w_ptr + size_1, size_2))
 612             {
 613                 PRINTK_AUDDRV("AudDrv_write 2ptr invalid data_w_ptr=%p, size_1=%d, size_2=%d", data_w_ptr, size_1, size_2);
 614                 PRINTK_AUDDRV("AudDrv_write u4BufferSize=%d, u4DataRemained=%d", Afe_Block->u4BufferSize, Afe_Block->u4DataRemained);
 615             }
 616             else
 617             {
 618
 619                 PRINTK_AUD_DL1("mcmcpy Afe_Block->pucVirtBufAddr+Afe_WriteIdx= %p data_w_ptr+size_1 = %p size_2 = %x\n",
 620                                Afe_Block->pucVirtBufAddr + Afe_WriteIdx_tmp, data_w_ptr + size_1, (unsigned int)size_2);
 621                 if ((copy_from_user((Afe_Block->pucVirtBufAddr + Afe_WriteIdx_tmp), (data_w_ptr + size_1), size_2)))
 622                 {
 623                     PRINTK_AUDDRV("AudDrv_write Fail 2  copy from user");
 624                     return -1;
 625                 }
 626             }
 627             spin_lock_irqsave(&auddrv_DLCtl_lock, flags);
 628
 629             Afe_Block->u4DataRemained += size_2;
 630             Afe_Block->u4WriteIdx = Afe_WriteIdx_tmp + size_2;
 631             Afe_Block->u4WriteIdx %= Afe_Block->u4BufferSize;
 632             spin_unlock_irqrestore(&auddrv_DLCtl_lock, flags);
 633             count -= copy_size;
 634             data_w_ptr += copy_size;
 635
 636             PRINTK_AUD_DL1("AudDrv_write finish2, copy size:%x, WriteIdx:%x,ReadIdx=%x DataRemained:%x \r\n",
 637                            copy_size, Afe_Block->u4WriteIdx, Afe_Block->u4DMAReadIdx, Afe_Block->u4DataRemained);
 638         }
 639     }
 640     return 0;
 641 }
 642
 643 static int mtk_pcm_silence(struct snd_pcm_substream *substream,
 644                            int channel, snd_pcm_uframes_t pos,
 645                            snd_pcm_uframes_t count)
 646 {
 647     PRINTK_AUDDRV("%s \n", __func__);
 648     return 0; /* do nothing */
 649 }
 650
 651 static void *dummy_page[2];
 652
 653 static struct page *mtk_pcm_page(struct snd_pcm_substream *substream,
 654                                  unsigned long offset)
 655 {
 656     PRINTK_AUDDRV("%s \n", __func__);
 657     return virt_to_page(dummy_page[substream->stream]); /* the same page */
 658 }
 659
 660 static struct snd_pcm_ops mtk_afe_ops =
 661 {
 662     .open =     mtk_pcm_dl1_open,
 663     .close =    mtk_soc_pcm_dl1_close,
 664     .ioctl =    snd_pcm_lib_ioctl,
 665     .hw_params =    mtk_pcm_dl1_params,
 666     .hw_free =  mtk_pcm_dl1_hw_free,
 667     .prepare =  mtk_pcm_prepare,
 668     .trigger =  mtk_pcm_trigger,
 669     .pointer =  mtk_pcm_pointer,
 670     .copy =     mtk_pcm_copy,
 671     .silence =  mtk_pcm_silence,
 672     .page =     mtk_pcm_page,
 673 };
 674
 675 static struct snd_soc_platform_driver mtk_soc_platform =
 676 {
 677     .ops        = &mtk_afe_ops,
 678     .pcm_new    = mtk_asoc_pcm_dl1_new,
 679     .probe      = mtk_asoc_dl1_probe,
 680 };
 681
 682 static int mtk_soc_dl1_probe(struct platform_device *pdev)
 683 {
 684     int ret = 0;
 685     PRINTK_AUDDRV("%s \n", __func__);
 686
 687     pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64);
 688     if (!pdev->dev.dma_mask)
 689     {
 690         pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
 691     }
 692
 693     if (pdev->dev.of_node)
 694     {
 695         dev_set_name(&pdev->dev, "%s", MT_SOC_DL1_PCM);
 696     }
 697
 698     PRINTK_AUDDRV("%s: dev name %s\n", __func__, dev_name(&pdev->dev));
 699     InitAfeControl();
 700 #ifndef CONFIG_OF
 701     ret = Register_Aud_Irq(&pdev->dev, MT6735_AFE_MCU_IRQ_LINE);
 702 #endif
 703
 704     mDev = &pdev->dev;
 705
 706     return snd_soc_register_platform(&pdev->dev,
 707                                      &mtk_soc_platform);
 708 }
 709
 710 static int mtk_asoc_pcm_dl1_new(struct snd_soc_pcm_runtime *rtd)
 711 {
 712     int ret = 0;
 713     PRINTK_AUDDRV("%s\n", __func__);
 714     return ret;
 715 }
 716
 717
 718 static int mtk_asoc_dl1_probe(struct snd_soc_platform *platform)
 719 {
 720     PRINTK_AUDDRV("mtk_asoc_dl1_probe\n");
 721     // allocate dram
 722     AudDrv_Allocate_mem_Buffer(platform->dev, Soc_Aud_Digital_Block_MEM_DL1, Dl1_MAX_BUFFER_SIZE);
 723     Dl1_Playback_dma_buf =  Get_Mem_Buffer(Soc_Aud_Digital_Block_MEM_DL1);
 724     return 0;
 725 }
 726
 727 static int mtk_afe_remove(struct platform_device *pdev)
 728 {
 729     PRINTK_AUDDRV("%s \n", __func__);
 730     snd_soc_unregister_platform(&pdev->dev);
 731     return 0;
 732 }
 733
 734 #ifdef CONFIG_OF
 735 extern void *AFE_BASE_ADDRESS;
 736 u32 afe_irq_number = 0;
 737 int AFE_BASE_PHY;
 738
 739 static const struct of_device_id mt_soc_pcm_dl1_of_ids[] =
 740 {
 741     { .compatible = "mediatek,mt_soc_pcm_dl1", },
 742     {}
 743 };
 744
 745 static int Auddrv_Reg_map_new(void)
 746 {
 747     struct device_node *node = NULL;
 748
 749     node = of_find_compatible_node(NULL, NULL, "mediatek,mt_soc_pcm_dl1");
 750     if (node)
 751     {
 752         /* Setup IO addresses */
 753         AFE_BASE_ADDRESS = of_iomap(node, 0);
 754         printk("[mt_soc_pcm_dl1] AFE_BASE_ADDRESS=0x%p\n", AFE_BASE_ADDRESS);
 755     }
 756     else
 757     {
 758         printk("[mt_soc_pcm_dl1] node NULL, can't iomap AFE_BASE!!!\n");
 759     }
 760     of_property_read_u32(node, "reg", &AFE_BASE_PHY);
 761     printk("[mt_soc_pcm_dl1] AFE_BASE_PHY=0x%x\n", AFE_BASE_PHY);
 762
 763     /*get afe irq num*/
 764     afe_irq_number = irq_of_parse_and_map(node, 0);
 765     printk("[mt_soc_pcm_dl1] afe_irq_number=0x%x\n", afe_irq_number);
 766     if (!afe_irq_number)
 767     {
 768         printk("[mt_soc_pcm_dl1] get afe_irq_number failed!!!\n");
 769         return -1;
 770     }
 771     return 0;
 772 }
 773 static int Auddrv_OF_ParseGPIO(void)
 774 {
 775     struct device_node *node = NULL;
 776
 777     node = of_find_compatible_node(NULL, NULL, "mediatek,mt_soc_pcm_dl1");
 778     if (node)
 779     {
 780         if_config1 = 1;
 781         if_config2 = 1;
 782         if_config3 = 1;
 783         if_config4 = 1;
 784         if_config5 = 1;
 785         if_config6 = 1;
 786         if_config7 = 1;
 787         if_config8 = 1;
 788         if_config9 = 1;
 789
 790         if (of_property_read_u32_index(node, "audclk-gpio", 0, &pin_audclk))
 791         {
 792             if_config1 = 0;
 793             printk("audclk-gpio get pin fail!!!\n");
 794         }
 795         if (of_property_read_u32_index(node, "audclk-gpio", 1, &pin_mode_audclk))
 796         {
 797             if_config1 = 0;
 798             printk("audclk-gpio get pin_mode fail!!!\n");
 799         }
 800
 801         if (of_property_read_u32_index(node, "audmiso-gpio", 0, &pin_audmiso))
 802         {
 803             if_config2 = 0;
 804             printk("audmiso-gpio get pin fail!!!\n");
 805         }
 806         if (of_property_read_u32_index(node, "audmiso-gpio", 1, &pin_mode_audmiso))
 807         {
 808             if_config2 = 0;
 809             printk("audmiso-gpio get pin_mode fail!!!\n");
 810         }
 811
 812         if (of_property_read_u32_index(node, "audmosi-gpio", 0, &pin_audmosi))
 813         {
 814             if_config3 = 0;
 815             printk("audmosi-gpio get pin fail!!!\n");
 816         }
 817         if (of_property_read_u32_index(node, "audmosi-gpio", 1, &pin_mode_audmosi))
 818         {
 819             if_config3 = 0;
 820             printk("audmosi-gpio get pin_mode fail!!!\n");
 821         }
 822
 823         if (of_property_read_u32_index(node, "vowclk-gpio", 0, &pin_vowclk))
 824         {
 825             if_config4 = 0;
 826             printk("vowclk-gpio get pin fail!!!\n");
 827         }
 828         if (of_property_read_u32_index(node, "vowclk-gpio", 1, &pin_mode_vowclk))
 829         {
 830             if_config4 = 0;
 831             printk("vowclk-gpio get pin_mode fail!!!\n");
 832         }
 833
 834         if (of_property_read_u32_index(node, "extspkamp-gpio", 0, &pin_extspkamp))
 835         {
 836             if_config5 = 0;
 837             printk("extspkamp-gpio get pin fail!!!\n");
 838         }
 839         if (of_property_read_u32_index(node, "extspkamp-gpio", 1, &pin_mode_extspkamp))
 840         {
 841             if_config5 = 0;
 842             printk("extspkamp-gpio get pin_mode fail!!!\n");
 843         }
 844
 845         if (of_property_read_u32_index(node, "i2s1clk-gpio", 0, &pin_i2s1clk))
 846         {
 847             if_config6 = 0;
 848             printk("i2s1clk-gpio get pin fail!!!\n");
 849         }
 850         if (of_property_read_u32_index(node, "i2s1clk-gpio", 1, &pin_mode_i2s1clk))
 851         {
 852             if_config6 = 0;
 853             printk("i2s1clk-gpio get pin_mode fail!!!\n");
 854         }
 855
 856         if (of_property_read_u32_index(node, "i2s1dat-gpio", 0, &pin_i2s1dat))
 857         {
 858             if_config7 = 0;
 859             printk("i2s1dat-gpio get pin fail!!!\n");
 860         }
 861         if (of_property_read_u32_index(node, "i2s1dat-gpio", 1, &pin_mode_i2s1dat))
 862         {
 863             if_config7 = 0;
 864             printk("i2s1dat-gpio get pin_mode fail!!!\n");
 865         }
 866
 867         if (of_property_read_u32_index(node, "i2s1mclk-gpio", 0, &pin_i2s1mclk))
 868         {
 869             if_config8 = 0;
 870             printk("i2s1mclk-gpio get pin fail!!!\n");
 871         }
 872         if (of_property_read_u32_index(node, "i2s1mclk-gpio", 1, &pin_mode_i2s1mclk))
 873         {
 874             if_config8 = 0;
 875             printk("i2s1mclk-gpio get pin_mode fail!!!\n");
 876         }
 877
 878         if (of_property_read_u32_index(node, "i2s1ws-gpio", 0, &pin_i2s1ws))
 879         {
 880             if_config9 = 0;
 881             printk("i2s1ws-gpio get pin fail!!!\n");
 882         }
 883         if (of_property_read_u32_index(node, "i2s1ws-gpio", 1, &pin_mode_i2s1ws))
 884         {
 885             if_config9 = 0;
 886             printk("i2s1ws-gpio get pin_mode fail!!!\n");
 887         }
 888
 889         printk("Auddrv_OF_ParseGPIO pin_audclk=%d, pin_audmiso=%d, pin_audmosi=%d \n", pin_audclk, pin_audmiso, pin_audmosi);
 890         printk("Auddrv_OF_ParseGPIO pin_vowclk=%d, pin_extspkamp=%d \n", pin_vowclk, pin_extspkamp);
 891         printk("Auddrv_OF_ParseGPIO pin_i2s1clk=%d, pin_i2s1dat=%d, pin_i2s1mclk=%d, pin_i2s1ws=%d \n", pin_i2s1clk, pin_i2s1dat, pin_i2s1mclk, pin_i2s1ws);
 892     }
 893     else
 894     {
 895         printk("Auddrv_OF_ParseGPIO node NULL!!!\n");
 896         return -1;
 897     }
 898     return 0;
 899 }
 900
 901 int GetGPIO_Info(int type, int *pin, int *pinmode)
 902 {
 903     switch (type)
 904     {
 905         case 1: //pin_audclk
 906             if (if_config1 == 1)
 907             {
 908                 *pin = pin_audclk | 0x80000000;
 909                 *pinmode = pin_mode_audclk;
 910             }
 911             else
 912             {
 913                 printk("GetGPIO_Info type %d fail!!!\n", type);
 914                 *pin = -1;
 915                 *pinmode = -1;
 916             }
 917             break;
 918
 919         case 2: //pin_audmiso
 920             if (if_config2 == 1)
 921             {
 922                 *pin = pin_audmiso | 0x80000000;
 923                 *pinmode = pin_mode_audmiso;
 924             }
 925             else
 926             {
 927                 printk("GetGPIO_Info type %d fail!!!\n", type);
 928                 *pin = -1;
 929                 *pinmode = -1;
 930             }
 931             break;
 932
 933         case 3: //pin_audmosi
 934             if (if_config3 == 1)
 935             {
 936                 *pin = pin_audmosi | 0x80000000;
 937                 *pinmode = pin_mode_audmosi;
 938             }
 939             else
 940             {
 941                 printk("GetGPIO_Info type %d fail!!!\n", type);
 942                 *pin = -1;
 943                 *pinmode = -1;
 944             }
 945             break;
 946
 947         case 4: //pin_vowclk
 948             if (if_config4 == 1)
 949             {
 950                 *pin = pin_vowclk | 0x80000000;
 951                 *pinmode = pin_mode_vowclk;
 952             }
 953             else
 954             {
 955                 printk("GetGPIO_Info type %d fail!!!\n", type);
 956                 *pin = -1;
 957                 *pinmode = -1;
 958             }
 959             break;
 960
 961         case 5: //pin_extspkamp
 962             if (if_config5 == 1)
 963             {
 964                 *pin = pin_extspkamp | 0x80000000;
 965                 *pinmode = pin_mode_extspkamp;
 966             }
 967             else
 968             {
 969                 printk("GetGPIO_Info type %d fail!!!\n", type);
 970                 *pin = -1;
 971                 *pinmode = -1;
 972             }
 973             break;
 974
 975         case 6: //pin_i2s1clk
 976             if (if_config6 == 1)
 977             {
 978                 *pin = pin_i2s1clk | 0x80000000;
 979                 *pinmode = pin_mode_i2s1clk;
 980             }
 981             else
 982             {
 983                 printk("GetGPIO_Info type %d fail!!!\n", type);
 984                 *pin = -1;
 985                 *pinmode = -1;
 986             }
 987             break;
 988
 989         case 7: //pin_i2s1dat
 990             if (if_config7 == 1)
 991             {
 992                 *pin = pin_i2s1dat | 0x80000000;
 993                 *pinmode = pin_mode_i2s1dat;
 994             }
 995             else
 996             {
 997                 printk("GetGPIO_Info type %d fail!!!\n", type);
 998                 *pin = -1;
 999                 *pinmode = -1;
1000             }
1001             break;
1002
1003         case 8: //pin_i2s1mclk
1004             if (if_config8 == 1)
1005             {
1006                 *pin = pin_i2s1mclk | 0x80000000;
1007                 *pinmode = pin_mode_i2s1mclk;
1008             }
1009             else
1010             {
1011                 printk("GetGPIO_Info type %d fail!!!\n", type);
1012                 *pin = -1;
1013                 *pinmode = -1;
1014             }
1015             break;
1016
1017         case 9: //pin_i2s1ws
1018             if (if_config9 == 1)
1019             {
1020                 *pin = pin_i2s1ws | 0x80000000;
1021                 *pinmode = pin_mode_i2s1ws;
1022             }
1023             else
1024             {
1025                 printk("GetGPIO_Info type %d fail!!!\n", type);
1026                 *pin = -1;
1027                 *pinmode = -1;
1028             }
1029             break;
1030
1031         default:
1032             *pin = -1;
1033             *pinmode = -1;
1034             printk("Auddrv_OF_ParseGPIO invalid type=%d!!!\n", type);
1035             break;
1036     }
1037 }
1038
1039 EXPORT_SYMBOL(GetGPIO_Info);
1040 #endif
1041
1042 static struct platform_driver mtk_afe_driver =
1043 {
1044     .driver = {
1045         .name = MT_SOC_DL1_PCM,
1046         .owner = THIS_MODULE,
1047 #ifdef CONFIG_OF
1048         .of_match_table = mt_soc_pcm_dl1_of_ids,
1049 #endif
1050     },
1051     .probe = mtk_soc_dl1_probe,
1052     .remove = mtk_afe_remove,
1053 };
1054
1055 #ifndef CONFIG_OF
1056 static struct platform_device *soc_mtkafe_dev;
1057 #endif
1058
1059 static int __init mtk_soc_platform_init(void)
1060 {
1061     int ret;
1062     PRINTK_AUDDRV("%s \n", __func__);
1063 #ifdef CONFIG_OF
1064     Auddrv_Reg_map_new();
1065     ret = Register_Aud_Irq(NULL, afe_irq_number);
1066     Auddrv_OF_ParseGPIO();
1067 #else
1068     soc_mtkafe_dev = platform_device_alloc(MT_SOC_DL1_PCM, -1);
1069     if (!soc_mtkafe_dev)
1070     {
1071         return -ENOMEM;
1072     }
1073
1074     ret = platform_device_add(soc_mtkafe_dev);
1075     if (ret != 0)
1076     {
1077         platform_device_put(soc_mtkafe_dev);
1078         return ret;
1079     }
1080 #endif
1081     ret = platform_driver_register(&mtk_afe_driver);
1082     return ret;
1083
1084 }
1085 module_init(mtk_soc_platform_init);
1086
1087 static void __exit mtk_soc_platform_exit(void)
1088 {
1089     PRINTK_AUDDRV("%s \n", __func__);
1090
1091     platform_driver_unregister(&mtk_afe_driver);
1092 }
1093 module_exit(mtk_soc_platform_exit);
1094
1095 MODULE_DESCRIPTION("AFE PCM module platform driver");
1096 MODULE_LICENSE("GPL");
1097
1098