sound/soc/mediatek/mt_soc_audio_v3/mt_soc_digital_type.h

   1 /*
   2  * Copyright (C) 2007 The Android Open Source Project
   3  *
   4  * Licensed under the Apache License, Version 2.0 (the "License");
   5  * you may not use this file except in compliance with the License.
   6  * You may obtain a copy of the License at
   7  *
   8  *      http://www.apache.org/licenses/LICENSE-2.0
   9  *
  10  * Unless required by applicable law or agreed to in writing, software
  11  * distributed under the License is distributed on an "AS IS" BASIS,
  12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13  * See the License for the specific language governing permissions and
  14  * limitations under the License.
  15  */
  16 /*******************************************************************************
  17  *
  18  * Filename:
  19  * ---------
  20  *  mt_sco_digital_type.h
  21  *
  22  * Project:
  23  * --------
  24  *   MT6583  Audio Driver Kernel Function
  25  *
  26  * Description:
  27  * ------------
  28  *   Audio register
  29  *
  30  * Author:
  31  * -------
  32  * Chipeng Chang
  33  *
  34  *------------------------------------------------------------------------------
  35  * $Revision: #1 $
  36  * $Modtime:$
  37  * $Log:$
  38  *
  39  *
  40  *******************************************************************************/
  41
  42 #ifndef _AUDIO_DIGITAL_TYPE_H
  43 #define _AUDIO_DIGITAL_TYPE_H
  44
  45
  46 /*****************************************************************************
  47  *                ENUM DEFINITION
  48  *****************************************************************************/
  49
  50
  51 typedef enum
  52 {
  53     // memmory interfrace
  54     Soc_Aud_Digital_Block_MEM_DL1 = 0,
  55     Soc_Aud_Digital_Block_MEM_DL2,
  56     Soc_Aud_Digital_Block_MEM_VUL,
  57     Soc_Aud_Digital_Block_MEM_DAI,
  58     Soc_Aud_Digital_Block_MEM_I2S,  // currently no use
  59     Soc_Aud_Digital_Block_MEM_AWB,
  60     Soc_Aud_Digital_Block_MEM_MOD_DAI,
  61     Soc_Aud_Digital_Block_MEM_DL1_DATA2 ,
  62     Soc_Aud_Digital_Block_MEM_VUL_DATA2,
  63     Soc_Aud_Digital_Block_MEM_HDMI,
  64     // connection to int main modem
  65     Soc_Aud_Digital_Block_MODEM_PCM_1_O ,
  66     // connection to extrt/int modem
  67     Soc_Aud_Digital_Block_MODEM_PCM_2_O ,
  68     // 1st I2S for DAC and ADC
  69     Soc_Aud_Digital_Block_I2S_OUT_DAC ,
  70     Soc_Aud_Digital_Block_I2S_OUT_DAC_2 , // 4 channel
  71     Soc_Aud_Digital_Block_I2S_IN_ADC ,
  72     Soc_Aud_Digital_Block_I2S_IN_ADC_2,  //  4 channel
  73     // 2nd I2S
  74     Soc_Aud_Digital_Block_I2S_OUT_2 ,
  75     Soc_Aud_Digital_Block_I2S_IN_2 ,
  76     // HW gain contorl
  77     Soc_Aud_Digital_Block_HW_GAIN1,
  78     Soc_Aud_Digital_Block_HW_GAIN2,
  79     // megrge interface
  80     Soc_Aud_Digital_Block_MRG_I2S_OUT,
  81     Soc_Aud_Digital_Block_MRG_I2S_IN,
  82     Soc_Aud_Digital_Block_DAI_BT,
  83     Soc_Aud_Digital_Block_NUM_OF_DIGITAL_BLOCK,
  84     Soc_Aud_Digital_Block_NUM_OF_MEM_INTERFACE = Soc_Aud_Digital_Block_MEM_HDMI + 1
  85 } Soc_Aud_Digital_Block;
  86
  87 typedef enum
  88 {
  89     Soc_Aud_MemIF_Direction_DIRECTION_OUTPUT,
  90     Soc_Aud_MemIF_Direction_DIRECTION_INPUT
  91 } Soc_Aud_MemIF_Direction;
  92
  93 typedef enum
  94 {
  95     Soc_Aud_InterConnectionInput_I00,
  96     Soc_Aud_InterConnectionInput_I01,
  97     Soc_Aud_InterConnectionInput_I02,
  98     Soc_Aud_InterConnectionInput_I03,
  99     Soc_Aud_InterConnectionInput_I04,
 100     Soc_Aud_InterConnectionInput_I05,
 101     Soc_Aud_InterConnectionInput_I06,
 102     Soc_Aud_InterConnectionInput_I07,
 103     Soc_Aud_InterConnectionInput_I08,
 104     Soc_Aud_InterConnectionInput_I09,
 105     Soc_Aud_InterConnectionInput_I10,
 106     Soc_Aud_InterConnectionInput_I11,
 107     Soc_Aud_InterConnectionInput_I12,
 108     Soc_Aud_InterConnectionInput_I13,
 109     Soc_Aud_InterConnectionInput_I14,
 110     Soc_Aud_InterConnectionInput_I15,
 111     Soc_Aud_InterConnectionInput_I16,
 112     Soc_Aud_InterConnectionInput_I17,
 113     Soc_Aud_InterConnectionInput_I18,
 114     Soc_Aud_InterConnectionInput_I19,
 115     Soc_Aud_InterConnectionInput_I20,
 116     Soc_Aud_InterConnectionInput_I21,
 117     Soc_Aud_InterConnectionInput_I22,
 118     Soc_Aud_InterConnectionInput_Num_Input
 119 } Soc_Aud_InterConnectionInput;
 120
 121 typedef enum
 122 {
 123     Soc_Aud_InterConnectionOutput_O00,
 124     Soc_Aud_InterConnectionOutput_O01,
 125     Soc_Aud_InterConnectionOutput_O02,
 126     Soc_Aud_InterConnectionOutput_O03,
 127     Soc_Aud_InterConnectionOutput_O04,
 128     Soc_Aud_InterConnectionOutput_O05,
 129     Soc_Aud_InterConnectionOutput_O06,
 130     Soc_Aud_InterConnectionOutput_O07,
 131     Soc_Aud_InterConnectionOutput_O08,
 132     Soc_Aud_InterConnectionOutput_O09,
 133     Soc_Aud_InterConnectionOutput_O10,
 134     Soc_Aud_InterConnectionOutput_O11,
 135     Soc_Aud_InterConnectionOutput_O12,
 136     Soc_Aud_InterConnectionOutput_O13,
 137     Soc_Aud_InterConnectionOutput_O14,
 138     Soc_Aud_InterConnectionOutput_O15,
 139     Soc_Aud_InterConnectionOutput_O16,
 140     Soc_Aud_InterConnectionOutput_O17,
 141     Soc_Aud_InterConnectionOutput_O18,
 142     Soc_Aud_InterConnectionOutput_O19,
 143     Soc_Aud_InterConnectionOutput_O20,
 144     Soc_Aud_InterConnectionOutput_O21,
 145     Soc_Aud_InterConnectionOutput_O22,
 146     Soc_Aud_InterConnectionOutput_O23,
 147     Soc_Aud_InterConnectionOutput_O24,
 148     Soc_Aud_InterConnectionOutput_O25,
 149     Soc_Aud_InterConnectionOutput_Num_Output
 150 } Soc_Aud_InterConnectionOutput;
 151
 152 typedef enum
 153 {
 154     Soc_Aud_InterConnectionInput_I30,
 155     Soc_Aud_InterConnectionInput_I31,
 156     Soc_Aud_InterConnectionInput_I32,
 157     Soc_Aud_InterConnectionInput_I33,
 158     Soc_Aud_InterConnectionInput_I34,
 159     Soc_Aud_InterConnectionInput_I35,
 160     Soc_Aud_InterConnectionInput_I36,
 161     Soc_Aud_InterConnectionInput_I37,
 162 } Soc_Aud_Hdmi_InterConnectionInput;
 163
 164
 165 typedef enum
 166 {
 167     Soc_Aud_InterConnectionOutput_O30,
 168     Soc_Aud_InterConnectionOutput_O31,
 169     Soc_Aud_InterConnectionOutput_O32,
 170     Soc_Aud_InterConnectionOutput_O33,
 171     Soc_Aud_InterConnectionOutput_O34,
 172     Soc_Aud_InterConnectionOutput_O35,
 173     Soc_Aud_InterConnectionOutput_O36,
 174     Soc_Aud_InterConnectionOutput_O37,
 175 } Soc_Aud_Hdmi_InterConnectionOutput;
 176
 177
 178 typedef enum
 179 {
 180     Soc_Aud_InterCon_DisConnect = 0x0,
 181     Soc_Aud_InterCon_Connection = 0x1,
 182     Soc_Aud_InterCon_ConnectionShift = 0x2
 183 } Soc_Aud_InterConnectionState;
 184
 185
 186 typedef enum
 187 {
 188     STREAMSTATUS_STATE_FREE = -1,     // memory is not allocate
 189     STREAMSTATUS_STATE_STANDBY,  // memory allocate and ready
 190     STREAMSTATUS_STATE_EXECUTING, // stream is running
 191 } STREAMSTATUS;
 192
 193 enum Soc_Aud_TopClockType
 194 {
 195     Soc_Aud_TopClockType_APB_CLOCK = 1,
 196     Soc_Aud_TopClockType_APB_AFE_CLOCK = 2,
 197     Soc_Aud_TopClockType_APB_I2S_INPUT_CLOCK = 6,
 198     Soc_Aud_TopClockType_APB_AFE_CK_DIV_RRST = 16,
 199     Soc_Aud_TopClockType_APB_PDN_APLL_TUNER  = 19,
 200     Soc_Aud_TopClockType_APB_PDN_HDMI_CK     = 20,
 201     Soc_Aud_TopClockType_APB_PDN_SPDIF_CK    = 21
 202 };
 203
 204 enum Soc_Aud_AFEClockType
 205 {
 206     Soc_Aud_AFEClockType_AFE_ON = 0,
 207     Soc_Aud_AFEClockType_DL1_ON = 1,
 208     Soc_Aud_AFEClockType_DL2_ON = 2,
 209     Soc_Aud_AFEClockType_VUL_ON = 3,
 210     Soc_Aud_AFEClockType_DAI_ON = 4,
 211     Soc_Aud_AFEClockType_I2S_ON = 5,
 212     Soc_Aud_AFEClockType_AWB_ON = 6,
 213     Soc_Aud_AFEClockType_MOD_PCM_ON = 7,
 214     Soc_Aud_AFEClockType_DL1Data2 = 8 ,
 215     Soc_Aud_AFEClockType_VULdata2 = 9,
 216     Soc_Aud_AFEClockType_VUL2data = 10,
 217 };
 218
 219 enum Soc_Aud_IRQ_MCU_MODE
 220 {
 221     Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE = 0,
 222     Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE,
 223     Soc_Aud_IRQ_MCU_MODE_IRQ3_MCU_MODE,
 224     Soc_Aud_IRQ_MCU_MODE_IRQ4_MCU_MODE,
 225     Soc_Aud_IRQ_MCU_MODE_IRQ5_MCU_MODE,
 226     Soc_Aud_IRQ_MCU_MODE_NUM_OF_IRQ_MODE
 227 };
 228
 229 enum Soc_Aud_Hw_Digital_Gain
 230 {
 231     Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN1,
 232     Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN2
 233 };
 234
 235 enum Soc_Aud_BCK_INV
 236 {
 237     Soc_Aud_INV_BCK_NO_INVERSE = 0,
 238     Soc_Aud_INV_BCK_INVESE = 1
 239 };
 240
 241 enum Soc_Aud_I2S_IN_PAD_SEL
 242 {
 243     Soc_Aud_I2S_IN_PAD_SEL_I2S_IN_FROM_CONNSYS = 0,
 244     Soc_Aud_I2S_IN_PAD_SEL_I2S_IN_FROM_IO_MUX = 1
 245 };
 246
 247 enum Soc_Aud_LR_SWAP
 248 {
 249     Soc_Aud_LR_SWAP_NO_SWAP = 0,
 250     Soc_Aud_LR_SWAP_LR_DATASWAP = 1
 251 };
 252
 253 enum Soc_Aud_INV_LRCK
 254 {
 255     Soc_Aud_INV_LRCK_NO_INVERSE = 0,
 256     Soc_Aud_INV_LRCK_INVESE_LRCK = 1
 257 };
 258
 259 enum Soc_Aud_I2S_FORMAT
 260 {
 261     Soc_Aud_I2S_FORMAT_EIAJ = 0,
 262     Soc_Aud_I2S_FORMAT_I2S  = 1
 263 };
 264
 265 enum Soc_Aud_I2S_SRC
 266 {
 267     Soc_Aud_I2S_SRC_MASTER_MODE = 0,
 268     Soc_Aud_I2S_SRC_SLAVE_MODE = 1
 269 };
 270
 271 enum  Soc_Aud_I2S_HD_EN
 272 {
 273     Soc_Aud_NORMAL_CLOCK = 0,
 274     Soc_Aud_LOW_JITTER_CLOCK = 1
 275 };
 276
 277 enum Soc_Aud_I2S_WLEN
 278 {
 279     Soc_Aud_I2S_WLEN_WLEN_16BITS = 0 ,
 280     Soc_Aud_I2S_WLEN_WLEN_32BITS = 1
 281 };
 282
 283 enum Soc_Aud_I2S_SAMPLERATE
 284 {
 285     Soc_Aud_I2S_SAMPLERATE_I2S_8K = 0,
 286     Soc_Aud_I2S_SAMPLERATE_I2S_11K = 1,
 287     Soc_Aud_I2S_SAMPLERATE_I2S_12K = 2,
 288     Soc_Aud_I2S_SAMPLERATE_I2S_16K = 4,
 289     Soc_Aud_I2S_SAMPLERATE_I2S_22K = 5,
 290     Soc_Aud_I2S_SAMPLERATE_I2S_24K = 6,
 291     Soc_Aud_I2S_SAMPLERATE_I2S_32K = 8,
 292     Soc_Aud_I2S_SAMPLERATE_I2S_44K = 9,
 293     Soc_Aud_I2S_SAMPLERATE_I2S_48K = 10,
 294     Soc_Aud_I2S_SAMPLERATE_I2S_88K = 11,
 295     Soc_Aud_I2S_SAMPLERATE_I2S_96K = 12,
 296     Soc_Aud_I2S_SAMPLERATE_I2S_174K = 13,
 297     Soc_Aud_I2S_SAMPLERATE_I2S_192K = 14,
 298     Soc_Aud_I2S_SAMPLERATE_I2S_260K = 15,
 299 };
 300
 301 enum Soc_Aud_I2S
 302 {
 303     Soc_Aud_I2S0 = 0,
 304     Soc_Aud_I2S1,
 305     Soc_Aud_I2S2,
 306     Soc_Aud_I2S3,
 307 };
 308
 309 enum Soc_Aud_APLL_SOURCE
 310 {
 311     Soc_Aud_APLL1 = 0,  // 44.1K base
 312     Soc_Aud_APLL2,        // 48base
 313 };
 314
 315 typedef struct
 316 {
 317     bool mLR_SWAP;
 318     bool mI2S_SLAVE;
 319     uint32 mI2S_SAMPLERATE;
 320     bool mINV_LRCK;
 321     bool mI2S_FMT;
 322     bool mI2S_WLEN;
 323     bool mI2S_EN;
 324     bool mI2S_HDEN;
 325     bool mI2S_IN_PAD_SEL;
 326
 327     // her for ADC usage , DAC will not use this
 328     int mBuffer_Update_word;
 329     bool mloopback;
 330     bool mFpga_bit;
 331     bool mFpga_bit_test;
 332 } AudioDigtalI2S;
 333
 334 enum Soc_Aud_TX_LCH_RPT
 335 {
 336     Soc_Aud_TX_LCH_RPT_TX_LCH_NO_REPEAT = 0,
 337     Soc_Aud_TX_LCH_RPT_TX_LCH_REPEAT    = 1
 338 };
 339
 340 enum Soc_Aud_VBT_16K_MODE
 341 {
 342     Soc_Aud_VBT_16K_MODE_VBT_16K_MODE_DISABLE = 0,
 343     Soc_Aud_VBT_16K_MODE_VBT_16K_MODE_ENABLE  = 1
 344 };
 345
 346 enum Soc_Aud_EXT_MODEM
 347 {
 348     Soc_Aud_EXT_MODEM_MODEM_2_USE_INTERNAL_MODEM = 0,
 349     Soc_Aud_EXT_MODEM_MODEM_2_USE_EXTERNAL_MODEM = 1
 350 };
 351
 352 enum Soc_Aud_PCM_SYNC_TYPE
 353 {
 354     Soc_Aud_PCM_SYNC_TYPE_BCK_CYCLE_SYNC        = 0, // bck sync length = 1
 355     Soc_Aud_PCM_SYNC_TYPE_EXTEND_BCK_CYCLE_SYNC = 1  // bck sync length = PCM_INTF_CON[9:13]
 356 };
 357
 358 enum Soc_Aud_BT_MODE
 359 {
 360     Soc_Aud_BT_MODE_DUAL_MIC_ON_TX   = 0,
 361     Soc_Aud_BT_MODE_SINGLE_MIC_ON_TX = 1
 362 };
 363
 364 enum Soc_Aud_BYPASS_SRC
 365 {
 366     Soc_Aud_BYPASS_SRC_SLAVE_USE_ASRC       = 0, // slave mode & external modem uses different crystal
 367     Soc_Aud_BYPASS_SRC_SLAVE_USE_ASYNC_FIFO = 1  // slave mode & external modem uses the same crystal
 368 };
 369
 370 enum Soc_Aud_PCM_CLOCK_SOURCE
 371 {
 372     Soc_Aud_PCM_CLOCK_SOURCE_MASTER_MODE = 0,
 373     Soc_Aud_PCM_CLOCK_SOURCE_SALVE_MODE  = 1
 374 };
 375
 376 enum Soc_Aud_PCM_WLEN_LEN
 377 {
 378     Soc_Aud_PCM_WLEN_LEN_PCM_16BIT = 0,
 379     Soc_Aud_PCM_WLEN_LEN_PCM_32BIT = 1
 380 };
 381
 382 enum Soc_Aud_PCM_MODE
 383 {
 384     Soc_Aud_PCM_MODE_PCM_MODE_8K  = 0,
 385     Soc_Aud_PCM_MODE_PCM_MODE_16K = 1 ,
 386     Soc_Aud_PCM_MODE_PCM_MODE_32K = 2 ,
 387 };
 388
 389 enum Soc_Aud_PCM_FMT
 390 {
 391     Soc_Aud_PCM_FMT_PCM_I2S    = 0,
 392     Soc_Aud_PCM_FMT_PCM_EIAJ   = 1,
 393     Soc_Aud_PCM_FMT_PCM_MODE_A = 2,
 394     Soc_Aud_PCM_FMT_PCM_MODE_B = 3
 395 };
 396
 397 typedef struct
 398 {
 399     uint32      mBclkOutInv;
 400     uint32          mTxLchRepeatSel;
 401     uint32        mVbt16kModeSel;
 402     uint32           mExtModemSel;
 403     uint8             mExtendBckSyncLength;
 404     uint32       mExtendBckSyncTypeSel;
 405     uint32             mSingelMicSel;
 406     uint32          mAsyncFifoSel;
 407     uint32    mSlaveModeSel;
 408     uint32        mPcmWordLength;
 409     uint32            mPcmModeWidebandSel;
 410     uint32            mPcmFormat;
 411     uint8              mModemPcmOn;
 412 } AudioDigitalPCM;
 413
 414 enum Soc_Aud_BT_DAI_INPUT
 415 {
 416     Soc_Aud_BT_DAI_INPUT_FROM_BT,
 417     Soc_Aud_BT_DAI_INPUT_FROM_MGRIF
 418 };
 419
 420 enum Soc_Aud_DATBT_MODE
 421 {
 422     Soc_Aud_DATBT_MODE_Mode8K,
 423     Soc_Aud_DATBT_MODE_Mode16K
 424 };
 425
 426 enum Soc_Aud_DAI_DEL
 427 {
 428     Soc_Aud_DAI_DEL_HighWord,
 429     Soc_Aud_DAI_DEL_LowWord
 430 };
 431
 432 enum Soc_Aud_BTSYNC
 433 {
 434     Soc_Aud_BTSYNC_Short_Sync,
 435     Soc_Aud_BTSYNC_Long_Sync
 436 };
 437
 438 typedef struct
 439 {
 440     bool mUSE_MRGIF_INPUT;
 441     bool mDAI_BT_MODE;
 442     bool mDAI_DEL;
 443     int mBT_LEN;
 444     bool mDATA_RDY;
 445     bool mBT_SYNC;
 446     bool mBT_ON;
 447     bool mDAIBT_ON;
 448 } AudioDigitalDAIBT;
 449
 450 enum Soc_Aud_MRFIF_I2S_SAMPLERATE
 451 {
 452     Soc_Aud_MRFIF_I2S_SAMPLERATE_MRFIF_I2S_8K = 0,
 453     Soc_Aud_MRFIF_I2S_SAMPLERATE_MRFIF_I2S_11K = 1,
 454     Soc_Aud_MRFIF_I2S_SAMPLERATE_MRFIF_I2S_12K = 2,
 455     Soc_Aud_MRFIF_I2S_SAMPLERATE_MRFIF_I2S_16K = 4,
 456     Soc_Aud_MRFIF_I2S_SAMPLERATE_MRFIF_I2S_22K = 5,
 457     Soc_Aud_MRFIF_I2S_SAMPLERATE_MRFIF_I2S_24K = 6,
 458     Soc_Aud_MRFIF_I2S_SAMPLERATE_MRFIF_I2S_32K = 8,
 459     Soc_Aud_MRFIF_I2S_SAMPLERATE_MRFIF_I2S_44K = 9,
 460     Soc_Aud_MRFIF_I2S_SAMPLERATE_MRFIF_I2S_48K = 10
 461 };
 462
 463 typedef struct
 464 {
 465     bool Mergeif_I2S_Enable;
 466     bool Merge_cnt_Clear;
 467     int Mrg_I2S_SampleRate;
 468     int Mrg_Sync_Dly;
 469     int Mrg_Clk_Edge_Dly;
 470     int Mrg_Clk_Dly;
 471     bool MrgIf_En;
 472 } AudioMrgIf;
 473
 474 // class for irq mode and counter.
 475 typedef struct
 476 {
 477     unsigned int mStatus;  // on,off
 478     unsigned int mIrqMcuCounter;
 479     unsigned int mSampleRate;
 480 } AudioIrqMcuMode;
 481
 482 typedef struct
 483 {
 484     int mFormat;
 485     int mDirection;
 486     unsigned int mSampleRate;
 487     unsigned int mChannels;
 488     unsigned int mBufferSize;
 489     unsigned int mInterruptSample;
 490     unsigned int mMemoryInterFaceType;
 491     unsigned int mClockInverse;
 492     unsigned int mMonoSel;
 493     unsigned int mdupwrite;
 494     unsigned int mState;
 495     unsigned int mFetchFormatPerSample;
 496     int mUserCount;
 497     void *privatedata;
 498 } AudioMemIFAttribute;
 499
 500 typedef struct
 501 {
 502     unsigned int  offset;
 503     unsigned int  value;
 504     unsigned int  mask;
 505 } Register_Control;
 506
 507 typedef struct
 508 {
 509     int bSpeechFlag;
 510     int bBgsFlag;
 511     int bRecordFlag;
 512     int bTtyFlag;
 513     int bVT;
 514     int bAudioPlay;
 515 } SPH_Control;
 516
 517 typedef struct
 518 {
 519     int SampleRate;
 520     int ClkApllSel; // 0-5
 521 } Hdmi_Clock_Control;
 522
 523 enum SPEAKER_CHANNEL
 524 {
 525     Channel_None = 0 ,
 526     Channel_Right,
 527     Channel_Left,
 528     Channel_Stereo
 529 };
 530
 531 enum SOUND_PATH
 532 {
 533     DEFAULT_PATH = 0,
 534     IN1_PATH,
 535     IN2_PATH,
 536     IN3_PATH,
 537     IN1_IN2_MIX,
 538 };
 539
 540 enum MIC_ANALOG_SWICTH
 541 {
 542     MIC_ANA_DEFAULT_PATH = 0,
 543     MIC_ANA_SWITCH1_HIGH
 544 };
 545 enum PolicyParameters
 546 {
 547     POLICY_LOAD_VOLUME =         0,
 548     POLICY_SET_FM_SPEAKER,
 549     POLICY_CHECK_FM_PRIMARY_KEY_ROUTING,
 550     POLICY_SET_FM_PRESTOP,
 551 };
 552
 553 enum modem_index_t
 554 {
 555     MODEM_1   = 0,
 556     MODEM_2   = 1,
 557     MODEM_EXTERNAL   = 2,
 558     NUM_MODEM
 559 };
 560
 561 typedef enum
 562 {
 563     AFE_WLEN_16_BIT = 0,
 564     AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA = 1,
 565     AFE_WLEN_32_BIT_ALIGN_24BIT_DATA_8BIT_0 = 3,
 566 } FETCHFORMATPERSAMPLE;
 567
 568 typedef enum
 569 {
 570     OUTPUT_DATA_FORMAT_16BIT = 0,
 571     OUTPUT_DATA_FORMAT_24BIT
 572 } OUTPUT_DATA_FORMAT;
 573
 574
 575 typedef enum
 576 {
 577     APLL_SOURCE_24576 = 0,
 578     APLL_SOURCE_225792 = 1
 579 } APLL_SOURCE_SEL;
 580
 581 typedef enum
 582 {
 583     HDMI_SDATA0 = 0,
 584     HDMI_SDATA1,
 585     HDMI_SDATA2,
 586     HDMI_SDATA3,
 587 } HDMI_SDATA_CHANNEL;
 588
 589 typedef enum
 590 {
 591     HDMI_8_CHANNELS = 0,
 592     HDMI_6_CHANNELS,
 593     HDMI_4_CHANNELS,
 594     HDMI_2_CHANNELS,
 595 } HDMI_SDATA_SEQUENCE;
 596
 597
 598 typedef struct
 599 {
 600     bool mLR_SWAP;
 601     bool mI2S_SLAVE;
 602     uint32 mSampleRate;
 603     bool mINV_LRCK;
 604     bool mI2S_FMT;
 605     bool mI2S_WLEN;
 606     bool mI2S_EN;
 607
 608     uint32 mChannels;
 609     uint32 mApllSource;
 610     uint32 mApllSamplerate;
 611     uint32 mHdmiMckDiv;
 612     uint32 mMckSamplerate;
 613     uint32 mHdmiBckDiv;
 614     uint32 mBckSamplerate;
 615
 616     // her for ADC usage , DAC will not use this
 617     int mBuffer_Update_word;
 618     bool mloopback;
 619     bool mFpga_bit;
 620     bool mFpga_bit_test;
 621 } AudioHdmi;
 622
 623 typedef enum
 624 {
 625     SRAM_STATE_FREE = 0,
 626     SRAM_STATE_PLAYBACKFULL = 0x1,
 627     SRAM_STATE_PLAYBACKPARTIAL = 0x2 ,
 628     SRAM_STATE_CAPTURE  = 0x4,
 629     SRAM_STATE_PLAYBACKDRAM  =0x8,
 630 } AUDIO_SRAM_STATE;
 631
 632 typedef struct
 633 {
 634     unsigned int mMemoryState;
 635     bool mPlaybackAllocated;
 636     bool mPlaybackAllocateSize;
 637     bool mCaptureAllocated;
 638     bool mCaptureAllocateSize;
 639 } AudioSramManager;
 640
 641 typedef enum
 642 {
 643     AUDIO_ANC_ON = 0,
 644     AUDIO_ANC_OFF ,
 645 } AUDIO_ANC_MODE;
 646
 647
 648
 649 typedef enum
 650 {
 651     AUDIO_APLL1_DIV0 = 8 ,
 652     AUDIO_APLL1_DIV1 = 9,
 653     AUDIO_APLL1_DIV2 = 10,
 654     AUDIO_APLL1_DIV3 = 11,
 655     AUDIO_APLL1_DIV4 = 12,
 656     AUDIO_APLL1_DIV5 = 13,
 657     AUDIO_APLL2_DIV0 = 16,
 658     AUDIO_APLL2_DIV1 = 17,
 659     AUDIO_APLL2_DIV2 = 18,
 660     AUDIO_APLL2_DIV3 = 19,
 661     AUDIO_APLL2_DIV4 = 20,
 662     AUDIO_APLL2_DIV5 = 21
 663 } AUDIO_APLL_DIVIDER_GROUP;
 664
 665 typedef enum
 666 {
 667     AUDIO_MODE_NORMAL = 0 ,
 668     AUDIO_MODE_RINGTONE,
 669     AUDIO_MODE_INCALL,
 670     AUDIO_MODE_INCALL2 ,
 671     AUDIO_MODE_INCALL_EXTERNAL ,
 672 } AUDIO_MODE;
 673
 674 typedef struct
 675 {
 676     uint32 REG_AUDIO_TOP_CON1;
 677     uint32 REG_AUDIO_TOP_CON2;
 678     uint32 REG_AUDIO_TOP_CON3;
 679     uint32 REG_AFE_DAC_CON0;
 680     uint32 REG_AFE_DAC_CON1;
 681     uint32 REG_AFE_I2S_CON;
 682     uint32 REG_AFE_DAIBT_CON0;
 683     uint32 REG_AFE_CONN0;
 684     uint32 REG_AFE_CONN1;
 685     uint32 REG_AFE_CONN2;
 686     uint32 REG_AFE_CONN3;
 687     uint32 REG_AFE_CONN4;
 688     uint32 REG_AFE_I2S_CON1;
 689     uint32 REG_AFE_I2S_CON2;
 690     uint32 REG_AFE_MRGIF_CON;
 691     uint32 REG_AFE_DL1_BASE;
 692     uint32 REG_AFE_DL1_CUR;
 693     uint32 REG_AFE_DL1_END;
 694     uint32 REG_AFE_DL1_D2_BASE;
 695     uint32 REG_AFE_DL1_D2_CUR;
 696     uint32 REG_AFE_DL1_D2_END;
 697     uint32 REG_AFE_VUL_D2_BASE;
 698     uint32 REG_AFE_VUL_D2_END;
 699     uint32 REG_AFE_VUL_D2_CUR;
 700     uint32 REG_AFE_I2S_CON3;
 701     uint32 REG_AFE_DL2_BASE;
 702     uint32 REG_AFE_DL2_CUR;
 703     uint32 REG_AFE_DL2_END;
 704     uint32 REG_AFE_CONN5;
 705     uint32 REG_AFE_CONN_24BIT;
 706     uint32 REG_AFE_AWB_BASE;
 707     uint32 REG_AFE_AWB_END;
 708     uint32 REG_AFE_AWB_CUR;
 709     uint32 REG_AFE_VUL_BASE;
 710     uint32 REG_AFE_VUL_END;
 711     uint32 REG_AFE_VUL_CUR;
 712     uint32 REG_AFE_DAI_BASE;
 713     uint32 REG_AFE_DAI_END;
 714     uint32 REG_AFE_DAI_CUR;
 715     uint32 REG_AFE_CONN6;
 716     uint32 REG_AFE_MEMIF_MSB;
 717     uint32 REG_AFE_MEMIF_MON0;
 718     uint32 REG_AFE_MEMIF_MON1;
 719     uint32 REG_AFE_MEMIF_MON2;
 720     uint32 REG_AFE_MEMIF_MON3;
 721     uint32 REG_AFE_MEMIF_MON4;
 722     uint32 REG_AFE_ADDA_DL_SRC2_CON0;
 723     uint32 REG_AFE_ADDA_DL_SRC2_CON1;
 724     uint32 REG_AFE_ADDA_UL_SRC_CON0;
 725     uint32 REG_AFE_ADDA_UL_SRC_CON1;
 726     uint32 REG_AFE_ADDA_TOP_CON0;
 727     uint32 REG_AFE_ADDA_UL_DL_CON0;
 728     uint32 REG_AFE_ADDA_SRC_DEBUG;
 729     uint32 REG_AFE_ADDA_SRC_DEBUG_MON0;
 730     uint32 REG_AFE_ADDA_SRC_DEBUG_MON1;
 731     uint32 REG_AFE_ADDA_NEWIF_CFG0;
 732     uint32 REG_AFE_ADDA_NEWIF_CFG1;
 733     uint32 REG_AFE_SIDETONE_DEBUG;
 734     uint32 REG_AFE_SIDETONE_MON;
 735     uint32 REG_AFE_SIDETONE_CON0;
 736     uint32 REG_AFE_SIDETONE_COEFF;
 737     uint32 REG_AFE_SIDETONE_CON1;
 738     uint32 REG_AFE_SIDETONE_GAIN;
 739     uint32 REG_AFE_SGEN_CON0;
 740     uint32 REG_AFE_SGEN_CON1;
 741     uint32 REG_AFE_TOP_CON0;
 742     uint32 REG_AFE_ADDA_PREDIS_CON0;
 743     uint32 REG_AFE_ADDA_PREDIS_CON1;
 744     uint32 REG_AFE_MRGIF_MON0;
 745     uint32 REG_AFE_MRGIF_MON1;
 746     uint32 REG_AFE_MRGIF_MON2;
 747     uint32 REG_AFE_MOD_DAI_BASE;
 748     uint32 REG_AFE_MOD_DAI_END;
 749     uint32 REG_AFE_MOD_DAI_CUR;
 750     uint32 REG_AFE_HDMI_OUT_CON0;
 751     uint32 REG_AFE_HDMI_BASE;
 752     uint32 REG_AFE_HDMI_CUR;
 753     uint32 REG_AFE_HDMI_END;
 754     uint32 REG_AFE_HDMI_CONN0;
 755     uint32 REG_AFE_IRQ_MCU_CON;
 756     uint32 REG_AFE_IRQ_MCU_STATUS;
 757     uint32 REG_AFE_IRQ_MCU_CLR;
 758     uint32 REG_AFE_IRQ_MCU_CNT1;
 759     uint32 REG_AFE_IRQ_MCU_CNT2;
 760     uint32 REG_AFE_IRQ_MCU_EN;
 761     uint32 REG_AFE_IRQ_MCU_MON2;
 762     uint32 REG_AFE_IRQ1_MCU_CNT_MON;
 763     uint32 REG_AFE_IRQ2_MCU_CNT_MON;
 764     uint32 REG_AFE_IRQ1_MCU_EN_CNT_MON;
 765     uint32 REG_AFE_MEMIF_MAXLEN;
 766     uint32 REG_AFE_MEMIF_PBUF_SIZE;
 767     uint32 REG_AFE_IRQ_MCU_CNT7; //K2
 768     uint32 REG_AFE_APLL1_TUNER_CFG;
 769     uint32 REG_AFE_APLL2_TUNER_CFG;
 770     uint32 REG_AFE_GAIN1_CON0;
 771     uint32 REG_AFE_GAIN1_CON1;
 772     uint32 REG_AFE_GAIN1_CON2;
 773     uint32 REG_AFE_GAIN1_CON3;
 774     uint32 REG_AFE_GAIN1_CONN;
 775     uint32 REG_AFE_GAIN1_CUR;
 776     uint32 REG_AFE_GAIN2_CON0;
 777     uint32 REG_AFE_GAIN2_CON1;
 778     uint32 REG_AFE_GAIN2_CON2;
 779     uint32 REG_AFE_GAIN2_CON3;
 780     uint32 REG_AFE_GAIN2_CONN;
 781     uint32 REG_AFE_GAIN2_CUR;
 782     uint32 REG_AFE_GAIN2_CONN2;
 783     uint32 REG_AFE_GAIN2_CONN3;
 784     uint32 REG_AFE_GAIN1_CONN2;
 785     uint32 REG_AFE_GAIN1_CONN3;
 786     uint32 REG_AFE_CONN7;
 787     uint32 REG_AFE_CONN8;
 788     uint32 REG_AFE_CONN9;
 789     uint32 REG_AFE_CONN10; //K2
 790     uint32 REG_FPGA_CFG2;
 791     uint32 REG_FPGA_CFG3;;
 792     uint32 REG_FPGA_CFG0;
 793     uint32 REG_FPGA_CFG1;
 794     uint32 REG_FPGA_VER;
 795     uint32 REG_FPGA_STC;
 796     uint32 REG_AFE_ASRC_CON0;
 797     uint32 REG_AFE_ASRC_CON1;
 798     uint32 REG_AFE_ASRC_CON2;
 799     uint32 REG_AFE_ASRC_CON3;
 800     uint32 REG_AFE_ASRC_CON4;
 801     uint32 REG_AFE_ASRC_CON5;
 802     uint32 REG_AFE_ASRC_CON6;
 803     uint32 REG_AFE_ASRC_CON7;
 804     uint32 REG_AFE_ASRC_CON8;
 805     uint32 REG_AFE_ASRC_CON9;
 806     uint32 REG_AFE_ASRC_CON10;
 807     uint32 REG_AFE_ASRC_CON11;
 808     uint32 REG_PCM_INTF_CON;
 809     uint32 REG_PCM_INTF_CON2;
 810     uint32 REG_PCM2_INTF_CON;
 811 #if 1 //K2
 812     uint32 REG_AUDIO_CLK_AUDDIV_0;
 813     uint32 REG_AUDIO_CLK_AUDDIV_1;
 814     uint32 REG_AUDIO_CLK_AUDDIV_2;
 815     uint32 REG_AUDIO_CLK_AUDDIV_3;
 816     uint32 REG_AFE_ASRC4_CON0;
 817     uint32 REG_AFE_ASRC4_CON1;
 818     uint32 REG_AFE_ASRC4_CON2;
 819     uint32 REG_AFE_ASRC4_CON3;
 820     uint32 REG_AFE_ASRC4_CON4;
 821     uint32 REG_AFE_ASRC4_CON5;
 822     uint32 REG_AFE_ASRC4_CON6;
 823     uint32 REG_AFE_ASRC4_CON7;
 824     uint32 REG_AFE_ASRC4_CON8;
 825     uint32 REG_AFE_ASRC4_CON9;
 826     uint32 REG_AFE_ASRC4_CON10;
 827     uint32 REG_AFE_ASRC4_CON11;
 828     uint32 REG_AFE_ASRC4_CON12;
 829     uint32 REG_AFE_ASRC4_CON13;
 830     uint32 REG_AFE_ASRC4_CON14;
 831 #endif
 832     uint32 REG_AFE_TDM_CON1;
 833     uint32 REG_AFE_TDM_CON2;
 834     uint32 REG_AFE_ASRC_CON13;
 835     uint32 REG_AFE_ASRC_CON14;
 836     uint32 REG_AFE_ASRC_CON15;
 837     uint32 REG_AFE_ASRC_CON16;
 838     uint32 REG_AFE_ASRC_CON17;
 839     uint32 REG_AFE_ASRC_CON18;
 840     uint32 REG_AFE_ASRC_CON19;
 841     uint32 REG_AFE_ASRC_CON20;
 842     uint32 REG_AFE_ASRC_CON21;
 843     uint32 REG_AFE_ADDA2_TOP_CON0;
 844     uint32 REG_AFE_ADDA2_UL_SRC_CON0;
 845     uint32 REG_AFE_ADDA2_UL_SRC_CON1;
 846     uint32 REG_AFE_ADDA2_SRC_DEBUG;
 847     uint32 REG_AFE_ADDA2_SRC_DEBUG_MON0;
 848     uint32 REG_AFE_ADDA2_SRC_DEBUG_MON1;
 849     uint32 REG_AFE_ADDA2_NEWIF_CFG0;
 850     uint32 REG_AFE_ADDA2_NEWIF_CFG1;
 851     uint32 REG_AFE_ADDA2_ULCF_CFG_02_01;
 852     uint32 REG_AFE_ADDA2_ULCF_CFG_04_03;
 853     uint32 REG_AFE_ADDA2_ULCF_CFG_06_05;
 854     uint32 REG_AFE_ADDA2_ULCF_CFG_08_07;
 855     uint32 REG_AFE_ADDA2_ULCF_CFG_10_09;
 856     uint32 REG_AFE_ADDA2_ULCF_CFG_12_11;
 857     uint32 REG_AFE_ADDA2_ULCF_CFG_14_13;
 858     uint32 REG_AFE_ADDA2_ULCF_CFG_16_15;
 859     uint32 REG_AFE_ADDA2_ULCF_CFG_18_17;
 860     uint32 REG_AFE_ADDA2_ULCF_CFG_20_19;
 861     uint32 REG_AFE_ADDA2_ULCF_CFG_22_21;
 862     uint32 REG_AFE_ADDA2_ULCF_CFG_24_23;
 863     uint32 REG_AFE_ADDA2_ULCF_CFG_26_25;
 864     uint32 REG_AFE_ADDA2_ULCF_CFG_28_27;
 865     uint32 REG_AFE_ADDA2_ULCF_CFG_30_29;
 866     uint32 REG_AFE_ADDA3_UL_SRC_CON0;
 867     uint32 REG_AFE_ADDA3_UL_SRC_CON1;
 868     uint32 REG_AFE_ADDA3_SRC_DEBUG;
 869     uint32 REG_AFE_ADDA3_SRC_DEBUG_MON0;
 870     uint32 REG_AFE_ADDA3_ULCF_CFG_02_01;
 871     uint32 REG_AFE_ADDA3_ULCF_CFG_04_03;
 872     uint32 REG_AFE_ADDA3_ULCF_CFG_06_05;
 873     uint32 REG_AFE_ADDA3_ULCF_CFG_08_07;
 874     uint32 REG_AFE_ADDA3_ULCF_CFG_10_09;
 875     uint32 REG_AFE_ADDA3_ULCF_CFG_12_11;
 876     uint32 REG_AFE_ADDA3_ULCF_CFG_14_13;
 877     uint32 REG_AFE_ADDA3_ULCF_CFG_16_15;
 878     uint32 REG_AFE_ADDA3_ULCF_CFG_18_17;
 879     uint32 REG_AFE_ADDA3_ULCF_CFG_20_19;
 880     uint32 REG_AFE_ADDA3_ULCF_CFG_22_21;
 881     uint32 REG_AFE_ADDA3_ULCF_CFG_24_23;
 882     uint32 REG_AFE_ADDA3_ULCF_CFG_26_25;
 883     uint32 REG_AFE_ADDA3_ULCF_CFG_28_27;
 884     uint32 REG_AFE_ADDA3_ULCF_CFG_30_29;
 885     uint32 REG_AFE_ASRC2_CON0;
 886     uint32 REG_AFE_ASRC2_CON1;
 887     uint32 REG_AFE_ASRC2_CON2;
 888     uint32 REG_AFE_ASRC2_CON3;
 889     uint32 REG_AFE_ASRC2_CON4;
 890     uint32 REG_AFE_ASRC2_CON5;
 891     uint32 REG_AFE_ASRC2_CON6;
 892     uint32 REG_AFE_ASRC2_CON7;
 893     uint32 REG_AFE_ASRC2_CON8;
 894     uint32 REG_AFE_ASRC2_CON9;
 895     uint32 REG_AFE_ASRC2_CON10;
 896     uint32 REG_AFE_ASRC2_CON11;
 897     uint32 REG_AFE_ASRC2_CON12;
 898     uint32 REG_AFE_ASRC2_CON13;
 899     uint32 REG_AFE_ASRC2_CON14;
 900     uint32 REG_AFE_ASRC3_CON0;
 901     uint32 REG_AFE_ASRC3_CON1;
 902     uint32 REG_AFE_ASRC3_CON2;
 903     uint32 REG_AFE_ASRC3_CON3;
 904     uint32 REG_AFE_ASRC3_CON4;
 905     uint32 REG_AFE_ASRC3_CON5;
 906     uint32 REG_AFE_ASRC3_CON6;
 907     uint32 REG_AFE_ASRC3_CON7;
 908     uint32 REG_AFE_ASRC3_CON8;
 909     uint32 REG_AFE_ASRC3_CON9;
 910     uint32 REG_AFE_ASRC3_CON10;
 911     uint32 REG_AFE_ASRC3_CON11;
 912     uint32 REG_AFE_ASRC3_CON12;
 913     uint32 REG_AFE_ASRC3_CON13;
 914     uint32 REG_AFE_ASRC3_CON14;
 915 #if 1 //K2
 916     uint32 REG_AFE_ADDA4_TOP_CON0;
 917     uint32 REG_AFE_ADDA4_UL_SRC_CON0;
 918     uint32 REG_AFE_ADDA4_UL_SRC_CON1;
 919     uint32 REG_AFE_ADDA4_NEWIF_CFG0;
 920     uint32 REG_AFE_ADDA4_NEWIF_CFG1;
 921     uint32 REG_AFE_ADDA4_ULCF_CFG_02_01;
 922     uint32 REG_AFE_ADDA4_ULCF_CFG_04_03;
 923     uint32 REG_AFE_ADDA4_ULCF_CFG_06_05;
 924     uint32 REG_AFE_ADDA4_ULCF_CFG_08_07;
 925     uint32 REG_AFE_ADDA4_ULCF_CFG_10_09;
 926     uint32 REG_AFE_ADDA4_ULCF_CFG_12_11;
 927     uint32 REG_AFE_ADDA4_ULCF_CFG_14_13;
 928     uint32 REG_AFE_ADDA4_ULCF_CFG_16_15;
 929     uint32 REG_AFE_ADDA4_ULCF_CFG_18_17;
 930     uint32 REG_AFE_ADDA4_ULCF_CFG_20_19;
 931     uint32 REG_AFE_ADDA4_ULCF_CFG_22_21;
 932     uint32 REG_AFE_ADDA4_ULCF_CFG_24_23;
 933     uint32 REG_AFE_ADDA4_ULCF_CFG_26_25;
 934     uint32 REG_AFE_ADDA4_ULCF_CFG_28_27;
 935     uint32 REG_AFE_ADDA4_ULCF_CFG_30_29;
 936 #endif
 937 } AudioAfeRegCache;
 938
 939 #endif
 940