sound/soc/mediatek/mt_soc_audio_v3/AudDrv_Ana.h

   1 /*
   2  * Copyright (C) 2007 The Android Open Source Project
   3  *
   4  * Licensed under the Apache License, Version 2.0 (the "License");
   5  * you may not use this file except in compliance with the License.
   6  * You may obtain a copy of the License at
   7  *
   8  *      http://www.apache.org/licenses/LICENSE-2.0
   9  *
  10  * Unless required by applicable law or agreed to in writing, software
  11  * distributed under the License is distributed on an "AS IS" BASIS,
  12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13  * See the License for the specific language governing permissions and
  14  * limitations under the License.
  15  */
  16 /*******************************************************************************
  17  *
  18  * Filename:
  19  * ---------
  20  *   AudDrv_Ana.h
  21  *
  22  * Project:
  23  * --------
  24  *   MT6583  Audio Driver Ana
  25  *
  26  * Description:
  27  * ------------
  28  *   Audio register
  29  *
  30  * Author:
  31  * -------
  32  *   Chipeng Chang (mtk02308)
  33  *
  34  *------------------------------------------------------------------------------
  35  * $Revision: #1 $
  36  * $Modtime:$
  37  * $Log:$
  38  *
  39  *
  40  *******************************************************************************/
  41
  42 #ifndef _AUDDRV_ANA_H_
  43 #define _AUDDRV_ANA_H_
  44
  45 /*****************************************************************************
  46  *                     C O M P I L E R   F L A G S
  47  *****************************************************************************/
  48
  49
  50 /*****************************************************************************
  51  *                E X T E R N A L   R E F E R E N C E S
  52  *****************************************************************************/
  53
  54 #include "AudDrv_Common.h"
  55 #include "AudDrv_Def.h"
  56
  57
  58 /*****************************************************************************
  59  *                         D A T A   T Y P E S
  60  *****************************************************************************/
  61
  62
  63 /*****************************************************************************
  64  *                         M A C R O
  65  *****************************************************************************/
  66
  67 /*****************************************************************************
  68  *                  R E G I S T E R       D E F I N I T I O N
  69  *****************************************************************************/
  70 #define PMIC_REG_BASE                    (0x0000)
  71 #define AFE_UL_DL_CON0                                   ((UINT32)(PMIC_REG_BASE+0x2000+0x0))
  72 #define AFE_DL_SRC2_CON0_H                         ((UINT32)(PMIC_REG_BASE+0x2000+0x2))
  73 #define AFE_DL_SRC2_CON0_L                          ((UINT32)(PMIC_REG_BASE+0x2000+0x4))
  74 #define AFE_DL_SDM_CON0                                ((UINT32)(PMIC_REG_BASE+0x2000+0x6))
  75 #define AFE_DL_SDM_CON1                                ((UINT32)(PMIC_REG_BASE+0x2000+0x8))
  76 #define AFE_UL_SRC0_CON0_H                         ((UINT32)(PMIC_REG_BASE+0x2000+0xa))
  77 #define AFE_UL_SRC0_CON0_L                          ((UINT32)(PMIC_REG_BASE+0x2000+0xc))
  78 #define AFE_UL_SRC1_CON0_H                         ((UINT32)(PMIC_REG_BASE+0x2000+0xe))
  79 #define AFE_UL_SRC1_CON0_L                          ((UINT32)(PMIC_REG_BASE+0x2000+0x10))
  80 #define PMIC_AFE_TOP_CON0                            ((UINT32)(PMIC_REG_BASE+0x2000+0x12))
  81 #define AFE_AUDIO_TOP_CON0                         ((UINT32)(PMIC_REG_BASE+0x2000+0x14))
  82 #define AFE_DL_SRC_MON0                                ((UINT32)(PMIC_REG_BASE+0x2000+0x16))
  83 #define AFE_DL_SDM_TEST0                               ((UINT32)(PMIC_REG_BASE+0x2000+0x18))
  84 #define AFE_MON_DEBUG0                                 ((UINT32)(PMIC_REG_BASE+0x2000+0x1a))
  85 #define AFUNC_AUD_CON0                                 ((UINT32)(PMIC_REG_BASE+0x2000+0x1c))
  86 #define AFUNC_AUD_CON1                                 ((UINT32)(PMIC_REG_BASE+0x2000+0x1e))
  87 #define AFUNC_AUD_CON2                                 ((UINT32)(PMIC_REG_BASE+0x2000+0x20))
  88 #define AFUNC_AUD_CON3                                 ((UINT32)(PMIC_REG_BASE+0x2000+0x22))
  89 #define AFUNC_AUD_CON4                                 ((UINT32)(PMIC_REG_BASE+0x2000+0x24))
  90 #define AFUNC_AUD_MON0                                ((UINT32)(PMIC_REG_BASE+0x2000+0x26))
  91 #define AFUNC_AUD_MON1                                ((UINT32)(PMIC_REG_BASE+0x2000+0x28))
  92 #define AUDRC_TUNE_MON0                              ((UINT32)(PMIC_REG_BASE+0x2000+0x2a))
  93 #define AFE_UP8X_FIFO_CFG0                         ((UINT32)(PMIC_REG_BASE+0x2000+0x2c))
  94 #define AFE_UP8X_FIFO_LOG_MON0              ((UINT32)(PMIC_REG_BASE+0x2000+0x2e))
  95 #define AFE_UP8X_FIFO_LOG_MON1              ((UINT32)(PMIC_REG_BASE+0x2000+0x30))
  96 #define AFE_DL_DC_COMP_CFG0                    ((UINT32)(PMIC_REG_BASE+0x2000+0x32))
  97 #define AFE_DL_DC_COMP_CFG1                    ((UINT32)(PMIC_REG_BASE+0x2000+0x34))
  98 #define AFE_DL_DC_COMP_CFG2                    ((UINT32)(PMIC_REG_BASE+0x2000+0x36))
  99 #define AFE_PMIC_NEWIF_CFG0                     ((UINT32)(PMIC_REG_BASE+0x2000+0x38))
 100 #define AFE_PMIC_NEWIF_CFG1                     ((UINT32)(PMIC_REG_BASE+0x2000+0x3a))
 101 #define AFE_PMIC_NEWIF_CFG2                     ((UINT32)(PMIC_REG_BASE+0x2000+0x3c))
 102 #define AFE_PMIC_NEWIF_CFG3                     ((UINT32)(PMIC_REG_BASE+0x2000+0x3e))
 103 #define AFE_SGEN_CFG0                                   ((UINT32)(PMIC_REG_BASE+0x2000+0x40))
 104 #define AFE_SGEN_CFG1                                   ((UINT32)(PMIC_REG_BASE+0x2000+0x42))
 105 #define AFE_VOW_TOP                                        ((UINT32)(PMIC_REG_BASE+0x2000+0x70))
 106 #define AFE_VOW_CFG0                                     ((UINT32)(PMIC_REG_BASE+0x2000+0x72))
 107 #define AFE_VOW_CFG1                                     ((UINT32)(PMIC_REG_BASE+0x2000+0x74))
 108 #define AFE_VOW_CFG2                                     ((UINT32)(PMIC_REG_BASE+0x2000+0x76))
 109 #define AFE_VOW_CFG3                                     ((UINT32)(PMIC_REG_BASE+0x2000+0x78))
 110 #define AFE_VOW_CFG4                                     ((UINT32)(PMIC_REG_BASE+0x2000+0x7a))
 111 #define AFE_VOW_CFG5                                     ((UINT32)(PMIC_REG_BASE+0x2000+0x7c))
 112 #define AFE_VOW_MON0                                    ((UINT32)(PMIC_REG_BASE+0x2000+0x7e))
 113 #define AFE_VOW_MON1                                    ((UINT32)(PMIC_REG_BASE+0x2000+0x80))
 114 #define AFE_VOW_MON2                                    ((UINT32)(PMIC_REG_BASE+0x2000+0x82))
 115 #define AFE_VOW_MON3                                    ((UINT32)(PMIC_REG_BASE+0x2000+0x84))
 116 #define AFE_VOW_MON4                                    ((UINT32)(PMIC_REG_BASE+0x2000+0x86))
 117 #define AFE_VOW_MON5                                    ((UINT32)(PMIC_REG_BASE+0x2000+0x88))
 118 #define AFE_VOW_TGEN_CFG0                               ((UINT32)(PMIC_REG_BASE+0x2000+0x8A))
 119 #define AFE_VOW_POSDIV_CFG0                             ((UINT32)(PMIC_REG_BASE+0x2000+0x8C))
 120 #define AFE_DCCLK_CFG0                                  ((UINT32)(PMIC_REG_BASE+0x2000+0x90))
 121 #define AFE_DCCLK_CFG1                                  ((UINT32)(PMIC_REG_BASE+0x2000+0x92))
 122
 123 // TODO: 6328 analog part
 124
 125 #define STRUP_CON0          ((UINT32)(PMIC_REG_BASE+0x0000))
 126 #define STRUP_CON2          ((UINT32)(PMIC_REG_BASE+0x0002))
 127 #define STRUP_CON3          ((UINT32)(PMIC_REG_BASE+0x0004))
 128 #define STRUP_CON4          ((UINT32)(PMIC_REG_BASE+0x0006))
 129 #define STRUP_CON5          ((UINT32)(PMIC_REG_BASE+0x0008))
 130 #define STRUP_CON6          ((UINT32)(PMIC_REG_BASE+0x000A))
 131 #define STRUP_CON7          ((UINT32)(PMIC_REG_BASE+0x000C))
 132 #define STRUP_CON8          ((UINT32)(PMIC_REG_BASE+0x000E))
 133 #define STRUP_CON9          ((UINT32)(PMIC_REG_BASE+0x0010))
 134 #define STRUP_CON10         ((UINT32)(PMIC_REG_BASE+0x0012))
 135 #define STRUP_CON11         ((UINT32)(PMIC_REG_BASE+0x0014))
 136 #define STRUP_CON12         ((UINT32)(PMIC_REG_BASE+0x0016))
 137 #define STRUP_CON13         ((UINT32)(PMIC_REG_BASE+0x0018))
 138 #define STRUP_CON14         ((UINT32)(PMIC_REG_BASE+0x001A))
 139 #define STRUP_CON15         ((UINT32)(PMIC_REG_BASE+0x001C))
 140 #define STRUP_CON16         ((UINT32)(PMIC_REG_BASE+0x001E))
 141 #define STRUP_CON17         ((UINT32)(PMIC_REG_BASE+0x0020))
 142 #define STRUP_CON18         ((UINT32)(PMIC_REG_BASE+0x0022))
 143 #define STRUP_CON19         ((UINT32)(PMIC_REG_BASE+0x0024))
 144 #define STRUP_CON20         ((UINT32)(PMIC_REG_BASE+0x0026))
 145 #define STRUP_CON21         ((UINT32)(PMIC_REG_BASE+0x0028))
 146 #define STRUP_CON22         ((UINT32)(PMIC_REG_BASE+0x002A))
 147 #define STRUP_CON23         ((UINT32)(PMIC_REG_BASE+0x002C))
 148 #define STRUP_ANA_CON0      ((UINT32)(PMIC_REG_BASE+0x0040))
 149 #define HWCID               ((UINT32)(PMIC_REG_BASE+0x0200))
 150 #define SWCID               ((UINT32)(PMIC_REG_BASE+0x0202))
 151 #define TOP_CON             ((UINT32)(PMIC_REG_BASE+0x0204))
 152 #define TEST_OUT            ((UINT32)(PMIC_REG_BASE+0x0206))
 153 #define TEST_CON0           ((UINT32)(PMIC_REG_BASE+0x0208))
 154 #define TEST_CON1           ((UINT32)(PMIC_REG_BASE+0x020A))
 155 #define TESTMODE_SW         ((UINT32)(PMIC_REG_BASE+0x020C))
 156 #define EN_STATUS0          ((UINT32)(PMIC_REG_BASE+0x020E))
 157 #define EN_STATUS1          ((UINT32)(PMIC_REG_BASE+0x0210))
 158 #define EN_STATUS2          ((UINT32)(PMIC_REG_BASE+0x0212))
 159 #define OCSTATUS0           ((UINT32)(PMIC_REG_BASE+0x0214))
 160 #define OCSTATUS1           ((UINT32)(PMIC_REG_BASE+0x0216))
 161 #define OCSTATUS2           ((UINT32)(PMIC_REG_BASE+0x0218))
 162 #define PGSTATUS            ((UINT32)(PMIC_REG_BASE+0x021C))
 163 #define TOPSTATUS           ((UINT32)(PMIC_REG_BASE+0x0220))
 164 #define TDSEL_CON           ((UINT32)(PMIC_REG_BASE+0x0222))
 165 #define RDSEL_CON           ((UINT32)(PMIC_REG_BASE+0x0224))
 166 #define SMT_CON0            ((UINT32)(PMIC_REG_BASE+0x0226))
 167 #define SMT_CON1            ((UINT32)(PMIC_REG_BASE+0x0228))
 168 #define SMT_CON2            ((UINT32)(PMIC_REG_BASE+0x022A))
 169 #define DRV_CON0            ((UINT32)(PMIC_REG_BASE+0x022C))
 170 #define DRV_CON1            ((UINT32)(PMIC_REG_BASE+0x022E))
 171 #define DRV_CON2            ((UINT32)(PMIC_REG_BASE+0x0230))
 172 #define DRV_CON3            ((UINT32)(PMIC_REG_BASE+0x0232))
 173 #define TOP_STATUS          ((UINT32)(PMIC_REG_BASE+0x0234))
 174 #define TOP_STATUS_SET      ((UINT32)(PMIC_REG_BASE+0x0236))
 175 #define TOP_STATUS_CLR      ((UINT32)(PMIC_REG_BASE+0x0238))
 176 #define RGS_ANA_MON         ((UINT32)(PMIC_REG_BASE+0x023A))
 177 #define TOP_CKPDN_CON0      ((UINT32)(PMIC_REG_BASE+0x023C))
 178 #define TOP_CKPDN_CON0_SET  ((UINT32)(PMIC_REG_BASE+0x023E))
 179 #define TOP_CKPDN_CON0_CLR  ((UINT32)(PMIC_REG_BASE+0x0240))
 180 #define TOP_CKPDN_CON1      ((UINT32)(PMIC_REG_BASE+0x0242))
 181 #define TOP_CKPDN_CON1_SET  ((UINT32)(PMIC_REG_BASE+0x0244))
 182 #define TOP_CKPDN_CON1_CLR  ((UINT32)(PMIC_REG_BASE+0x0246))
 183 #define TOP_CKPDN_CON2      ((UINT32)(PMIC_REG_BASE+0x0248))
 184 #define TOP_CKPDN_CON2_SET  ((UINT32)(PMIC_REG_BASE+0x024A))
 185 #define TOP_CKPDN_CON2_CLR  ((UINT32)(PMIC_REG_BASE+0x024C))
 186 #define TOP_CKPDN_CON3      ((UINT32)(PMIC_REG_BASE+0x024E))
 187 #define TOP_CKPDN_CON3_SET  ((UINT32)(PMIC_REG_BASE+0x0250))
 188 #define TOP_CKPDN_CON3_CLR  ((UINT32)(PMIC_REG_BASE+0x0252))
 189 #define TOP_CKSEL_CON0      ((UINT32)(PMIC_REG_BASE+0x025A))
 190 #define TOP_CKSEL_CON0_SET  ((UINT32)(PMIC_REG_BASE+0x025C))
 191 #define TOP_CKSEL_CON0_CLR  ((UINT32)(PMIC_REG_BASE+0x025E))
 192 #define TOP_CKSEL_CON1      ((UINT32)(PMIC_REG_BASE+0x0260))
 193 #define TOP_CKSEL_CON1_SET  ((UINT32)(PMIC_REG_BASE+0x0262))
 194 #define TOP_CKSEL_CON1_CLR  ((UINT32)(PMIC_REG_BASE+0x0264))
 195 #define TOP_CKSEL_CON2      ((UINT32)(PMIC_REG_BASE+0x0266))
 196 #define TOP_CKSEL_CON2_SET  ((UINT32)(PMIC_REG_BASE+0x0268))
 197 #define TOP_CKSEL_CON2_CLR  ((UINT32)(PMIC_REG_BASE+0x026A))
 198 #define TOP_CKDIVSEL_CON    ((UINT32)(PMIC_REG_BASE+0x026C))
 199 #define TOP_CKDIVSEL_CON_SET ((UINT32)(PMIC_REG_BASE+0x026E))
 200 #define TOP_CKDIVSEL_CON_CLR ((UINT32)(PMIC_REG_BASE+0x0270))
 201 #define TOP_CKHWEN_CON      ((UINT32)(PMIC_REG_BASE+0x0278))
 202 #define TOP_CKHWEN_CON_SET  ((UINT32)(PMIC_REG_BASE+0x027A))
 203 #define TOP_CKHWEN_CON_CLR  ((UINT32)(PMIC_REG_BASE+0x027C))
 204 #define TOP_CKTST_CON0      ((UINT32)(PMIC_REG_BASE+0x0284))
 205 #define TOP_CKTST_CON1      ((UINT32)(PMIC_REG_BASE+0x0286))
 206 #define TOP_CKTST_CON2      ((UINT32)(PMIC_REG_BASE+0x0288))
 207 #define TOP_CLKSQ           ((UINT32)(PMIC_REG_BASE+0x028A))
 208 #define TOP_CLKSQ_SET       ((UINT32)(PMIC_REG_BASE+0x028C))
 209 #define TOP_CLKSQ_CLR       ((UINT32)(PMIC_REG_BASE+0x028E))
 210 #define TOP_CLKSQ_RTC       ((UINT32)(PMIC_REG_BASE+0x0290))
 211 #define TOP_CLKSQ_RTC_SET   ((UINT32)(PMIC_REG_BASE+0x0292))
 212 #define TOP_CLKSQ_RTC_CLR   ((UINT32)(PMIC_REG_BASE+0x0294))
 213 #define TOP_CLK_TRIM        ((UINT32)(PMIC_REG_BASE+0x0296))
 214 #define TOP_RST_CON0        ((UINT32)(PMIC_REG_BASE+0x0298))
 215 #define TOP_RST_CON0_SET    ((UINT32)(PMIC_REG_BASE+0x029A))
 216 #define TOP_RST_CON0_CLR    ((UINT32)(PMIC_REG_BASE+0x029C))
 217 #define TOP_RST_CON1        ((UINT32)(PMIC_REG_BASE+0x029E))
 218 #define TOP_RST_MISC        ((UINT32)(PMIC_REG_BASE+0x02A0))
 219 #define TOP_RST_MISC_SET    ((UINT32)(PMIC_REG_BASE+0x02A2))
 220 #define TOP_RST_MISC_CLR    ((UINT32)(PMIC_REG_BASE+0x02A4))
 221 #define TOP_RST_STATUS      ((UINT32)(PMIC_REG_BASE+0x02A6))
 222 #define TOP_RST_STATUS_SET  ((UINT32)(PMIC_REG_BASE+0x02A8))
 223 #define TOP_RST_STATUS_CLR  ((UINT32)(PMIC_REG_BASE+0x02AA))
 224 #define INT_CON0            ((UINT32)(PMIC_REG_BASE+0x02AC))
 225 #define INT_CON0_SET        ((UINT32)(PMIC_REG_BASE+0x02AE))
 226 #define INT_CON0_CLR        ((UINT32)(PMIC_REG_BASE+0x02B0))
 227 #define INT_CON1            ((UINT32)(PMIC_REG_BASE+0x02B2))
 228 #define INT_CON1_SET        ((UINT32)(PMIC_REG_BASE+0x02B4))
 229 #define INT_CON1_CLR        ((UINT32)(PMIC_REG_BASE+0x02B6))
 230 #define INT_CON2            ((UINT32)(PMIC_REG_BASE+0x02B8))
 231 #define INT_CON2_SET        ((UINT32)(PMIC_REG_BASE+0x02BA))
 232 #define INT_CON2_CLR        ((UINT32)(PMIC_REG_BASE+0x02BC))
 233 #define INT_MISC_CON        ((UINT32)(PMIC_REG_BASE+0x02BE))
 234 #define INT_MISC_CON_SET    ((UINT32)(PMIC_REG_BASE+0x02C0))
 235 #define INT_MISC_CON_CLR    ((UINT32)(PMIC_REG_BASE+0x02C2))
 236 #define INT_STATUS0         ((UINT32)(PMIC_REG_BASE+0x02C4))
 237 #define INT_STATUS1         ((UINT32)(PMIC_REG_BASE+0x02C6))
 238 #define INT_STATUS2         ((UINT32)(PMIC_REG_BASE+0x02C8))
 239 #define OC_GEAR_0           ((UINT32)(PMIC_REG_BASE+0x02CA))
 240 #define FQMTR_CON0          ((UINT32)(PMIC_REG_BASE+0x02CC))
 241 #define FQMTR_CON1          ((UINT32)(PMIC_REG_BASE+0x02CE))
 242 #define FQMTR_CON2          ((UINT32)(PMIC_REG_BASE+0x02D0))
 243 #define RG_SPI_CON          ((UINT32)(PMIC_REG_BASE+0x02D2))
 244 #define DEW_DIO_EN          ((UINT32)(PMIC_REG_BASE+0x02D4))
 245 #define DEW_READ_TEST       ((UINT32)(PMIC_REG_BASE+0x02D6))
 246 #define DEW_WRITE_TEST      ((UINT32)(PMIC_REG_BASE+0x02D8))
 247 #define DEW_CRC_SWRST       ((UINT32)(PMIC_REG_BASE+0x02DA))
 248 #define DEW_CRC_EN          ((UINT32)(PMIC_REG_BASE+0x02DC))
 249 #define DEW_CRC_VAL         ((UINT32)(PMIC_REG_BASE+0x02DE))
 250 #define DEW_DBG_MON_SEL     ((UINT32)(PMIC_REG_BASE+0x02E0))
 251 #define DEW_CIPHER_KEY_SEL  ((UINT32)(PMIC_REG_BASE+0x02E2))
 252 #define DEW_CIPHER_IV_SEL   ((UINT32)(PMIC_REG_BASE+0x02E4))
 253 #define DEW_CIPHER_EN       ((UINT32)(PMIC_REG_BASE+0x02E6))
 254 #define DEW_CIPHER_RDY      ((UINT32)(PMIC_REG_BASE+0x02E8))
 255 #define DEW_CIPHER_MODE     ((UINT32)(PMIC_REG_BASE+0x02EA))
 256 #define DEW_CIPHER_SWRST    ((UINT32)(PMIC_REG_BASE+0x02EC))
 257 #define DEW_RDDMY_NO        ((UINT32)(PMIC_REG_BASE+0x02EE))
 258 #define INT_TYPE_CON0       ((UINT32)(PMIC_REG_BASE+0x02F0))
 259 #define INT_TYPE_CON0_SET   ((UINT32)(PMIC_REG_BASE+0x02F2))
 260 #define INT_TYPE_CON0_CLR   ((UINT32)(PMIC_REG_BASE+0x02F4))
 261 #define INT_TYPE_CON1       ((UINT32)(PMIC_REG_BASE+0x02F6))
 262 #define INT_TYPE_CON1_SET   ((UINT32)(PMIC_REG_BASE+0x02F8))
 263 #define INT_TYPE_CON1_CLR   ((UINT32)(PMIC_REG_BASE+0x02FA))
 264 #define INT_TYPE_CON2       ((UINT32)(PMIC_REG_BASE+0x02FC))
 265 #define INT_TYPE_CON2_SET   ((UINT32)(PMIC_REG_BASE+0x02FE))`
 266 #define INT_TYPE_CON2_CLR   ((UINT32)(PMIC_REG_BASE+0x0300))
 267 #define INT_STA             ((UINT32)(PMIC_REG_BASE+0x0302))
 268 #define BUCK_ALL_CON0       ((UINT32)(PMIC_REG_BASE+0x0400))
 269 #define BUCK_ALL_CON1       ((UINT32)(PMIC_REG_BASE+0x0402))
 270 #define BUCK_ALL_CON2       ((UINT32)(PMIC_REG_BASE+0x0404))
 271 #define BUCK_ALL_CON3       ((UINT32)(PMIC_REG_BASE+0x0406))
 272 #define BUCK_ALL_CON4       ((UINT32)(PMIC_REG_BASE+0x0408))
 273 #define BUCK_ALL_CON5       ((UINT32)(PMIC_REG_BASE+0x040A))
 274 #define BUCK_ALL_CON6       ((UINT32)(PMIC_REG_BASE+0x040C))
 275 //#define BUCK_ALL_CON7       ((UINT32)(PMIC_REG_BASE+0x040E))
 276 //#define BUCK_ALL_CON8       ((UINT32)(PMIC_REG_BASE+0x0410))
 277 //#define BUCK_ALL_CON9       ((UINT32)(PMIC_REG_BASE+0x040E))
 278 //#define BUCK_ALL_CON10      ((UINT32)(PMIC_REG_BASE+0x0414))
 279 //#define BUCK_ALL_CON11      ((UINT32)(PMIC_REG_BASE+0x0416))
 280 #define BUCK_ALL_CON12      ((UINT32)(PMIC_REG_BASE+0x0410))
 281 #define BUCK_ALL_CON13      ((UINT32)(PMIC_REG_BASE+0x0412))
 282 #define BUCK_ALL_CON14      ((UINT32)(PMIC_REG_BASE+0x0414))
 283 //#define BUCK_ALL_CON15      ((UINT32)(PMIC_REG_BASE+0x041E))
 284 #define BUCK_ALL_CON16      ((UINT32)(PMIC_REG_BASE+0x0416))
 285 //#define BUCK_ALL_CON17      ((UINT32)(PMIC_REG_BASE+0x0422))
 286 #define BUCK_ALL_CON18      ((UINT32)(PMIC_REG_BASE+0x0418))
 287 #define BUCK_ALL_CON19      ((UINT32)(PMIC_REG_BASE+0x041A))
 288 #define BUCK_ALL_CON20      ((UINT32)(PMIC_REG_BASE+0x041C))
 289 #define BUCK_ALL_CON21      ((UINT32)(PMIC_REG_BASE+0x041E))
 290 #define BUCK_ALL_CON22      ((UINT32)(PMIC_REG_BASE+0x0420))
 291 #define BUCK_ALL_CON23      ((UINT32)(PMIC_REG_BASE+0x0422))
 292 #define BUCK_ALL_CON24      ((UINT32)(PMIC_REG_BASE+0x0424))
 293 #define BUCK_ALL_CON25      ((UINT32)(PMIC_REG_BASE+0x0426))
 294 #define BUCK_ALL_CON26      ((UINT32)(PMIC_REG_BASE+0x0428))
 295 #define BUCK_ALL_CON27      ((UINT32)(PMIC_REG_BASE+0x042A))
 296 #define BUCK_ALL_CON28      ((UINT32)(PMIC_REG_BASE+0x042C))
 297 //#define VDRAM_ANA_CON0      ((UINT32)(PMIC_REG_BASE+0x043A))
 298 //#define VDRAM_ANA_CON1      ((UINT32)(PMIC_REG_BASE+0x043C))
 299 //#define VDRAM_ANA_CON2      ((UINT32)(PMIC_REG_BASE+0x043E))
 300 //#define VDRAM_ANA_CON3      ((UINT32)(PMIC_REG_BASE+0x0440))
 301 //#define VDRAM_ANA_CON4      ((UINT32)(PMIC_REG_BASE+0x0442))
 302 #define VCORE1_ANA_CON0     ((UINT32)(PMIC_REG_BASE+0x0440))
 303 #define VCORE1_ANA_CON1     ((UINT32)(PMIC_REG_BASE+0x0442))
 304 #define VCORE1_ANA_CON2     ((UINT32)(PMIC_REG_BASE+0x0444))
 305 #define VCORE1_ANA_CON3     ((UINT32)(PMIC_REG_BASE+0x0446))
 306 #define VCORE1_ANA_CON4     ((UINT32)(PMIC_REG_BASE+0x0448))
 307 #define SMPS_TOP_ANA_CON0   ((UINT32)(PMIC_REG_BASE+0x042E))
 308 #define SMPS_TOP_ANA_CON1   ((UINT32)(PMIC_REG_BASE+0x0430))
 309 #define SMPS_TOP_ANA_CON2   ((UINT32)(PMIC_REG_BASE+0x0432))
 310 #define SMPS_TOP_ANA_CON3   ((UINT32)(PMIC_REG_BASE+0x0434))
 311 #define SMPS_TOP_ANA_CON4   ((UINT32)(PMIC_REG_BASE+0x0436))
 312 #define SMPS_TOP_ANA_CON5   ((UINT32)(PMIC_REG_BASE+0x0438))
 313 #define SMPS_TOP_ANA_CON6   ((UINT32)(PMIC_REG_BASE+0x043A))
 314 #define SMPS_TOP_ANA_CON7   ((UINT32)(PMIC_REG_BASE+0x043C))
 315 #define SMPS_TOP_ANA_CON8   ((UINT32)(PMIC_REG_BASE+0x043E))
 316 //#define SMPS_TOP_ANA_CON9   ((UINT32)(PMIC_REG_BASE+0x0460))
 317 //#define VDVFS1_ANA_CON0     ((UINT32)(PMIC_REG_BASE+0x0462))
 318 //#define VDVFS1_ANA_CON1     ((UINT32)(PMIC_REG_BASE+0x0464))
 319 //#define VDVFS1_ANA_CON2     ((UINT32)(PMIC_REG_BASE+0x0466))
 320 //#define VDVFS1_ANA_CON3     ((UINT32)(PMIC_REG_BASE+0x0468))
 321 //#define VDVFS1_ANA_CON4     ((UINT32)(PMIC_REG_BASE+0x046A))
 322 //#define VDVFS1_ANA_CON5     ((UINT32)(PMIC_REG_BASE+0x046C))
 323 //#define VDVFS1_ANA_CON6     ((UINT32)(PMIC_REG_BASE+0x046E))
 324 //#define VDVFS1_ANA_CON7     ((UINT32)(PMIC_REG_BASE+0x0470))
 325 //#define VGPU_ANA_CON0       ((UINT32)(PMIC_REG_BASE+0x0472))
 326 //#define VGPU_ANA_CON1       ((UINT32)(PMIC_REG_BASE+0x0474))
 327 //#define VGPU_ANA_CON2       ((UINT32)(PMIC_REG_BASE+0x0476))
 328 //#define VGPU_ANA_CON3       ((UINT32)(PMIC_REG_BASE+0x0478))
 329 //#define VGPU_ANA_CON4       ((UINT32)(PMIC_REG_BASE+0x047A))
 330 #define VPA_ANA_CON0        ((UINT32)(PMIC_REG_BASE+0x0462))
 331 #define VPA_ANA_CON1        ((UINT32)(PMIC_REG_BASE+0x0464))
 332 #define VPA_ANA_CON2        ((UINT32)(PMIC_REG_BASE+0x0466))
 333 #define VPA_ANA_CON3        ((UINT32)(PMIC_REG_BASE+0x0468))
 334 #if 0
 335 #define VCORE2_ANA_CON0     ((UINT32)(PMIC_REG_BASE+0x0484))
 336 #define VCORE2_ANA_CON1     ((UINT32)(PMIC_REG_BASE+0x0486))
 337 #define VCORE2_ANA_CON2     ((UINT32)(PMIC_REG_BASE+0x0488))
 338 #define VCORE2_ANA_CON3     ((UINT32)(PMIC_REG_BASE+0x048A))
 339 #define VCORE2_ANA_CON4     ((UINT32)(PMIC_REG_BASE+0x048C))
 340 #define VIO18_ANA_CON0      ((UINT32)(PMIC_REG_BASE+0x048E))
 341 #define VIO18_ANA_CON1      ((UINT32)(PMIC_REG_BASE+0x0490))
 342 #define VIO18_ANA_CON2      ((UINT32)(PMIC_REG_BASE+0x0492))
 343 #define VIO18_ANA_CON3      ((UINT32)(PMIC_REG_BASE+0x0494))
 344 #define VIO18_ANA_CON4      ((UINT32)(PMIC_REG_BASE+0x0496))
 345 #define VRF18_0_ANA_CON0    ((UINT32)(PMIC_REG_BASE+0x0498))
 346 #define VRF18_0_ANA_CON1    ((UINT32)(PMIC_REG_BASE+0x049A))
 347 #define VRF18_0_ANA_CON2    ((UINT32)(PMIC_REG_BASE+0x049C))
 348 #define VRF18_0_ANA_CON3    ((UINT32)(PMIC_REG_BASE+0x049E))
 349 #define VRF18_0_ANA_CON4    ((UINT32)(PMIC_REG_BASE+0x04A0))
 350 #define VDVFS11_CON0        ((UINT32)(PMIC_REG_BASE+0x04A2))
 351 #define VDVFS11_CON7        ((UINT32)(PMIC_REG_BASE+0x04B0))
 352 #define VDVFS11_CON8        ((UINT32)(PMIC_REG_BASE+0x04B2))
 353 #define VDVFS11_CON9        ((UINT32)(PMIC_REG_BASE+0x04B4))
 354 #define VDVFS11_CON10       ((UINT32)(PMIC_REG_BASE+0x04B6))
 355 #define VDVFS11_CON11       ((UINT32)(PMIC_REG_BASE+0x04B8))
 356 #define VDVFS11_CON12       ((UINT32)(PMIC_REG_BASE+0x04BA))
 357 #define VDVFS11_CON13       ((UINT32)(PMIC_REG_BASE+0x04BC))
 358 #define VDVFS11_CON14       ((UINT32)(PMIC_REG_BASE+0x04BE))
 359 #define VDVFS11_CON18       ((UINT32)(PMIC_REG_BASE+0x04C6))
 360 #define VDVFS12_CON0        ((UINT32)(PMIC_REG_BASE+0x04C8))
 361 #define VDVFS12_CON7        ((UINT32)(PMIC_REG_BASE+0x04D6))
 362 #define VDVFS12_CON8        ((UINT32)(PMIC_REG_BASE+0x04D8))
 363 #define VDVFS12_CON9        ((UINT32)(PMIC_REG_BASE+0x04DA))
 364 #define VDVFS12_CON10       ((UINT32)(PMIC_REG_BASE+0x04DC))
 365 #define VDVFS12_CON11       ((UINT32)(PMIC_REG_BASE+0x04DE))
 366 #define VDVFS12_CON12       ((UINT32)(PMIC_REG_BASE+0x04E0))
 367 #define VDVFS12_CON13       ((UINT32)(PMIC_REG_BASE+0x04E2))
 368 #define VDVFS12_CON14       ((UINT32)(PMIC_REG_BASE+0x04E4))
 369 #define VDVFS12_CON18       ((UINT32)(PMIC_REG_BASE+0x04EC))
 370 #define VSRAM_DVFS1_CON0    ((UINT32)(PMIC_REG_BASE+0x04EE))
 371 #define VSRAM_DVFS1_CON7    ((UINT32)(PMIC_REG_BASE+0x04FC))
 372 #define VSRAM_DVFS1_CON8    ((UINT32)(PMIC_REG_BASE+0x04FE))
 373 #define VSRAM_DVFS1_CON9    ((UINT32)(PMIC_REG_BASE+0x0500))
 374 #endif
 375
 376 #define ZCD_CON0            ((UINT32)(PMIC_REG_BASE+0x0800))
 377 #define ZCD_CON1            ((UINT32)(PMIC_REG_BASE+0x0802))
 378 #define ZCD_CON2            ((UINT32)(PMIC_REG_BASE+0x0804))
 379 #define ZCD_CON3            ((UINT32)(PMIC_REG_BASE+0x0806))
 380 #define ZCD_CON4            ((UINT32)(PMIC_REG_BASE+0x0808))
 381 #define ZCD_CON5            ((UINT32)(PMIC_REG_BASE+0x080A))
 382
 383 #define LDO_CON1            ((UINT32)(PMIC_REG_BASE + 0x0A02))
 384 #define LDO_CON2            ((UINT32)(PMIC_REG_BASE + 0x0A04))
 385
 386 #define LDO_VCON1           ((UINT32)(PMIC_REG_BASE + 0x0A40))
 387
 388 #define SPK_CON0            ((UINT32)(PMIC_REG_BASE+0x0A90))
 389 #define SPK_CON1            ((UINT32)(PMIC_REG_BASE+0x0A92))
 390 #define SPK_CON2            ((UINT32)(PMIC_REG_BASE+0x0A94))
 391 #define SPK_CON3            ((UINT32)(PMIC_REG_BASE+0x0A96))
 392 #define SPK_CON4            ((UINT32)(PMIC_REG_BASE+0x0A98))
 393 #define SPK_CON5            ((UINT32)(PMIC_REG_BASE+0x0A9A))
 394 #define SPK_CON6            ((UINT32)(PMIC_REG_BASE+0x0A9C))
 395 #define SPK_CON7            ((UINT32)(PMIC_REG_BASE+0x0A9E))
 396 #define SPK_CON8            ((UINT32)(PMIC_REG_BASE+0x0AA0))
 397 #define SPK_CON9            ((UINT32)(PMIC_REG_BASE+0x0AA2))
 398 #define SPK_CON10           ((UINT32)(PMIC_REG_BASE+0x0AA4))
 399 #define SPK_CON11           ((UINT32)(PMIC_REG_BASE+0x0AA6))
 400 #define SPK_CON12           ((UINT32)(PMIC_REG_BASE+0x0AA8))
 401 #define SPK_CON13           ((UINT32)(PMIC_REG_BASE+0x0AAA))
 402 #define SPK_CON14           ((UINT32)(PMIC_REG_BASE+0x0AAC))
 403 #define SPK_CON15           ((UINT32)(PMIC_REG_BASE+0x0AAE))
 404 #define SPK_CON16           ((UINT32)(PMIC_REG_BASE+0x0AB0))
 405 #define SPK_ANA_CON0        ((UINT32)(PMIC_REG_BASE+0x0AB2))
 406 #define SPK_ANA_CON1        ((UINT32)(PMIC_REG_BASE+0x0AB4))
 407 #define SPK_ANA_CON3        ((UINT32)(PMIC_REG_BASE+0x0AB6))
 408
 409 //#define FGADC_ANA_CON0      ((UINT32)(PMIC_REG_BASE+0x0CDC))
 410 #define AUDDEC_ANA_CON0     ((UINT32)(PMIC_REG_BASE+0x0CDC))
 411 #define AUDDEC_ANA_CON1     ((UINT32)(PMIC_REG_BASE+0x0CDE))
 412 #define AUDDEC_ANA_CON2     ((UINT32)(PMIC_REG_BASE+0x0CE0))
 413 #define AUDDEC_ANA_CON3     ((UINT32)(PMIC_REG_BASE+0x0CE2))
 414 #define AUDDEC_ANA_CON4     ((UINT32)(PMIC_REG_BASE+0x0CE4))
 415 #define AUDDEC_ANA_CON5     ((UINT32)(PMIC_REG_BASE+0x0CE6))
 416 #define AUDDEC_ANA_CON6     ((UINT32)(PMIC_REG_BASE+0x0CE8))
 417 #define AUDDEC_ANA_CON7     ((UINT32)(PMIC_REG_BASE+0x0CEA))
 418 #define AUDDEC_ANA_CON8     ((UINT32)(PMIC_REG_BASE+0x0CEC))
 419 #define AUDENC_ANA_CON0     ((UINT32)(PMIC_REG_BASE+0x0CEE))
 420 #define AUDENC_ANA_CON1     ((UINT32)(PMIC_REG_BASE+0x0CF0))
 421 #define AUDENC_ANA_CON2     ((UINT32)(PMIC_REG_BASE+0x0CF2))
 422 #define AUDENC_ANA_CON3     ((UINT32)(PMIC_REG_BASE+0x0CF4))
 423 #define AUDENC_ANA_CON4     ((UINT32)(PMIC_REG_BASE+0x0CF6))
 424 #define AUDENC_ANA_CON5     ((UINT32)(PMIC_REG_BASE+0x0CF8))
 425 #define AUDENC_ANA_CON6     ((UINT32)(PMIC_REG_BASE+0x0CFA))
 426 #define AUDENC_ANA_CON7     ((UINT32)(PMIC_REG_BASE+0x0CFC))
 427 #define AUDENC_ANA_CON8     ((UINT32)(PMIC_REG_BASE+0x0CFE))
 428 #define AUDENC_ANA_CON9     ((UINT32)(PMIC_REG_BASE+0x0D00))
 429 #define AUDENC_ANA_CON10    ((UINT32)(PMIC_REG_BASE+0x0D02))
 430 //#define AUDENC_ANA_CON12    ((UINT32)(PMIC_REG_BASE+0x0D06))
 431 //#define AUDENC_ANA_CON13    ((UINT32)(PMIC_REG_BASE+0x0D08))
 432
 433 //#define AUDENC_ANA_CON14    ((UINT32)(PMIC_REG_BASE+0x0D0A))
 434 //#define AUDENC_ANA_CON15    ((UINT32)(PMIC_REG_BASE+0xFFFF)) // George temp checkreg
 435 #define AUDNCP_CLKDIV_CON0  ((UINT32)(PMIC_REG_BASE+0x0D04))
 436 #define AUDNCP_CLKDIV_CON1  ((UINT32)(PMIC_REG_BASE+0x0D06))
 437 #define AUDNCP_CLKDIV_CON2  ((UINT32)(PMIC_REG_BASE+0x0D08))
 438 #define AUDNCP_CLKDIV_CON3  ((UINT32)(PMIC_REG_BASE+0x0D0A))
 439 #define AUDNCP_CLKDIV_CON4  ((UINT32)(PMIC_REG_BASE+0x0D0C))
 440
 441 #define GPIO_MODE3          ((UINT32)(0x60D0))
 442
 443 #if 1
 444 //register number
 445
 446 #else
 447 #include <mach/upmu_hw.h>
 448 #endif
 449
 450 void Ana_Set_Reg(uint32 offset, uint32 value, uint32 mask);
 451 uint32  Ana_Get_Reg(uint32 offset);
 452
 453 // for debug usage
 454 void Ana_Log_Print(void);
 455
 456 #endif
 457
 458