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import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / mediatek / mt_soc_audio_v2 / mt_soc_codec_63xx.c
1 /*
2 * Copyright (C) 2007 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16 /*******************************************************************************
17 *
18 * Filename:
19 * ---------
20 * mtk_soc_codec_63xx
21 *
22 * Project:
23 * --------
24 *
25 *
26 * Description:
27 * ------------
28 * Audio codec stub file
29 *
30 * Author:
31 * -------
32 * Chipeng Chang
33 *
34 *------------------------------------------------------------------------------
35 * $Revision: #1 $
36 * $Modtime:$
37 * $Log:$
38 *
39 *
40 *******************************************************************************/
41
42
43 /*****************************************************************************
44 * C O M P I L E R F L A G S
45 *****************************************************************************/
46
47
48 /*****************************************************************************
49 * E X T E R N A L R E F E R E N C E S
50 *****************************************************************************/
51
52 #include <linux/dma-mapping.h>
53 #include <linux/platform_device.h>
54 #include <linux/slab.h>
55 #include <linux/module.h>
56 #include <linux/of_device.h>
57 #include <sound/core.h>
58 #include <sound/pcm.h>
59 #include <sound/soc.h>
60 #include <mach/mt_gpio.h>
61
62 #include "AudDrv_Common.h"
63 #include "AudDrv_Def.h"
64 #include "AudDrv_Afe.h"
65 #include "AudDrv_Ana.h"
66 #include "AudDrv_Clk.h"
67 #include "mt_soc_analog_type.h"
68 #include <mach/mt_clkbuf_ctl.h>
69 #include <mach/mt_chip.h>
70 #include <sound/mt_soc_audio.h>
71 #include <mach/vow_api.h>
72 #include "mt_soc_afe_control.h"
73 #include <mach/upmu_common_sw.h>
74 #include <mach/upmu_hw.h>
75 #include <mach/mt_pmic_wrap.h>
76
77 #ifdef CONFIG_MTK_SPEAKER
78 #include "mt_soc_codec_speaker_63xx.h"
79 #include <cust_pmic.h>
80 int PMIC_IMM_GetOneChannelValue(int dwChannel, int deCount, int trimd);
81 #endif
82
83 #include "mt_soc_pcm_common.h"
84
85 #define AW8736_MODE_CTRL // AW8736 PA output power mode control
86
87 // static function declaration
88 static bool AudioPreAmp1_Sel(int Mul_Sel);
89 static bool GetAdcStatus(void);
90 static void Apply_Speaker_Gain(void);
91 static bool TurnOnVOWDigitalHW(bool enable);
92 static void TurnOffDacPower(void);
93 static void TurnOnDacPower(void);
94 static void SetDcCompenSation(void);
95 static void Voice_Amp_Change(bool enable);
96 static void Speaker_Amp_Change(bool enable);
97 static bool TurnOnVOWADcPowerACC(int MicType, bool enable);
98
99 extern int PMIC_IMM_GetOneChannelValue(int dwChannel, int deCount, int trimd);
100
101 static mt6331_Codec_Data_Priv *mCodec_data = NULL;
102 static uint32 mBlockSampleRate[AUDIO_ANALOG_DEVICE_INOUT_MAX] = {48000, 48000, 48000};
103 static DEFINE_MUTEX(Ana_Ctrl_Mutex);
104 static DEFINE_MUTEX(Ana_buf_Ctrl_Mutex);
105 static DEFINE_MUTEX(Ana_Clk_Mutex);
106 static DEFINE_MUTEX(Ana_Power_Mutex);
107 static DEFINE_MUTEX(AudAna_lock);
108
109 static int mAudio_Analog_Mic1_mode = AUDIO_ANALOGUL_MODE_ACC;
110 static int mAudio_Analog_Mic2_mode = AUDIO_ANALOGUL_MODE_ACC;
111 static int mAudio_Analog_Mic3_mode = AUDIO_ANALOGUL_MODE_ACC;
112 static int mAudio_Analog_Mic4_mode = AUDIO_ANALOGUL_MODE_ACC;
113
114 static int mAudio_Vow_Analog_Func_Enable = false;
115 static int mAudio_Vow_Digital_Func_Enable = false;
116
117 static int TrimOffset = 2048;
118 static const int DC1unit_in_uv = 19184; // in uv with 0DB
119 static const int DC1devider = 8; // in uv
120
121 static uint32 RG_AUDHPLTRIM_VAUDP15, RG_AUDHPRTRIM_VAUDP15, RG_AUDHPLFINETRIM_VAUDP15, RG_AUDHPRFINETRIM_VAUDP15,
122 RG_AUDHPLTRIM_VAUDP15_SPKHP, RG_AUDHPRTRIM_VAUDP15_SPKHP, RG_AUDHPLFINETRIM_VAUDP15_SPKHP, RG_AUDHPRFINETRIM_VAUDP15_SPKHP;
123
124 #ifdef CONFIG_MTK_SPEAKER
125 static int Speaker_mode = AUDIO_SPEAKER_MODE_AB;
126 static unsigned int Speaker_pga_gain = 1 ; // default 0Db.
127 static bool mSpeaker_Ocflag = false;
128 #endif
129 static int mAdc_Power_Mode = 0;
130 static unsigned int dAuxAdcChannel = 16;
131 static const int mDcOffsetTrimChannel = 9;
132 static bool mInitCodec = false;
133
134 static uint32 MicbiasRef, GetMicbias;
135
136 static int reg_AFE_VOW_CFG0 = 0x0000; //VOW AMPREF Setting
137 static int reg_AFE_VOW_CFG1 = 0x0000; //VOW A,B timeout initial value (timer)
138 static int reg_AFE_VOW_CFG2 = 0x2222; //VOW A,B value setting (BABA)
139 static int reg_AFE_VOW_CFG3 = 0x8767; //alhpa and beta K value setting (beta_rise,fall,alpha_rise,fall)
140 static int reg_AFE_VOW_CFG4 = 0x006E; //gamma K value setting (gamma), bit4:8 should not modify
141 static int reg_AFE_VOW_CFG5 = 0x0001; //N mini value setting (Nmin)
142 static bool mIsVOWOn = false;
143
144 //VOW using
145 typedef enum
146 {
147 AUDIO_VOW_MIC_TYPE_Handset_AMIC = 0,
148 AUDIO_VOW_MIC_TYPE_Headset_MIC,
149 AUDIO_VOW_MIC_TYPE_Handset_DMIC, //1P6
150 AUDIO_VOW_MIC_TYPE_Handset_DMIC_800K, //800K
151 AUDIO_VOW_MIC_TYPE_Handset_AMIC_DCC, //DCC mems
152 AUDIO_VOW_MIC_TYPE_Headset_MIC_DCC,
153 AUDIO_VOW_MIC_TYPE_Handset_AMIC_DCCECM, //DCC ECM, dual differential
154 AUDIO_VOW_MIC_TYPE_Headset_MIC_DCCECM //DCC ECM, signal differential
155 } AUDIO_VOW_MIC_TYPE;
156
157 static int mAudio_VOW_Mic_type = AUDIO_VOW_MIC_TYPE_Handset_AMIC;
158 static void Audio_Amp_Change(int channels , bool enable);
159 static void SavePowerState(void)
160 {
161 int i = 0;
162 for (i = 0; i < AUDIO_ANALOG_DEVICE_MAX ; i++)
163 {
164 mCodec_data->mAudio_BackUpAna_DevicePower[i] = mCodec_data->mAudio_Ana_DevicePower[i];
165 }
166 }
167
168 static void RestorePowerState(void)
169 {
170 int i = 0;
171 for (i = 0; i < AUDIO_ANALOG_DEVICE_MAX ; i++)
172 {
173 mCodec_data->mAudio_Ana_DevicePower[i] = mCodec_data->mAudio_BackUpAna_DevicePower[i];
174 }
175 }
176
177 static bool GetDLStatus(void)
178 {
179 int i = 0;
180 for (i = 0; i < AUDIO_ANALOG_DEVICE_2IN1_SPK ; i++)
181 {
182 if (mCodec_data->mAudio_Ana_DevicePower[i] == true)
183 {
184 return true;
185 }
186 }
187 return false;
188 }
189
190 static bool mAnaSuspend = false;
191 void SetAnalogSuspend(bool bEnable)
192 {
193 printk("%s bEnable ==%d mAnaSuspend = %d \n", __func__, bEnable, mAnaSuspend);
194 if ((bEnable == true) && (mAnaSuspend == false))
195 {
196 Ana_Log_Print();
197 SavePowerState();
198 if (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETL] == true)
199 {
200 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETL] = false;
201 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_LEFT1 , false);
202 }
203 if (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETR] == true)
204 {
205 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETR] = false;
206 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_RIGHT1 , false);
207 }
208 if (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_EARPIECEL] == true)
209 {
210 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_EARPIECEL] = false;
211 Voice_Amp_Change(false);
212 }
213 if (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_SPEAKERL] == true)
214 {
215 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_SPEAKERL] = false;
216 Speaker_Amp_Change(false);
217 }
218 Ana_Log_Print();
219 mAnaSuspend = true;
220 }
221 else if ((bEnable == false) && (mAnaSuspend == true))
222 {
223 Ana_Log_Print();
224 if (mCodec_data->mAudio_BackUpAna_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETL] == true)
225 {
226 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_LEFT1 , true);
227 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETL] = true;
228 }
229 if (mCodec_data->mAudio_BackUpAna_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETR] == true)
230 {
231 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_RIGHT1 , true);
232 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETR] = false;
233 }
234 if (mCodec_data->mAudio_BackUpAna_DevicePower[AUDIO_ANALOG_DEVICE_OUT_EARPIECEL] == true)
235 {
236 Voice_Amp_Change(true);
237 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_EARPIECEL] = false;
238 }
239 if (mCodec_data->mAudio_BackUpAna_DevicePower[AUDIO_ANALOG_DEVICE_OUT_SPEAKERL] == true)
240 {
241 Speaker_Amp_Change(true);
242 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_SPEAKERL] = false;
243 }
244 RestorePowerState();
245 Ana_Log_Print();
246 mAnaSuspend = false;
247 }
248 }
249
250 static int audck_buf_Count = 0;
251 void audckbufEnable(bool enable)
252 {
253 printk("audckbufEnable audck_buf_Count = %d enable = %d \n", audck_buf_Count, enable);
254 mutex_lock(&Ana_buf_Ctrl_Mutex);
255 if (enable)
256 {
257 if (audck_buf_Count == 0)
258 {
259 printk("+clk_buf_ctrl(CLK_BUF_AUDIO,true)\n");
260 clk_buf_ctrl(CLK_BUF_AUDIO, true);
261 printk("-clk_buf_ctrl(CLK_BUF_AUDIO,true)\n");
262 }
263 audck_buf_Count++;
264 }
265 else
266 {
267 audck_buf_Count--;
268 if (audck_buf_Count == 0)
269 {
270 printk("+clk_buf_ctrl(CLK_BUF_AUDIO,false)\n");
271 clk_buf_ctrl(CLK_BUF_AUDIO, false);
272 printk("-clk_buf_ctrl(CLK_BUF_AUDIO,false)\n");
273 }
274 if (audck_buf_Count < 0)
275 {
276 printk("audck_buf_Count count <0 \n");
277 audck_buf_Count = 0;
278 }
279 }
280 mutex_unlock(&Ana_buf_Ctrl_Mutex);
281 }
282
283 static int ClsqCount = 0;
284 static void ClsqEnable(bool enable)
285 {
286 printk("ClsqEnable ClsqCount = %d enable = %d \n", ClsqCount, enable);
287 mutex_lock(& AudAna_lock);
288 if (enable)
289 {
290 if (ClsqCount == 0)
291 {
292 Ana_Set_Reg(TOP_CLKSQ, 0x0001, 0x0001); //Enable CLKSQ 26MHz
293 Ana_Set_Reg(TOP_CLKSQ_SET, 0x0001, 0x0001); //Turn on 26MHz source clock
294 }
295 ClsqCount++;
296 }
297 else
298 {
299 ClsqCount--;
300 if (ClsqCount < 0)
301 {
302 printk("ClsqEnable count <0 \n");
303 ClsqCount = 0;
304 }
305 if (ClsqCount == 0)
306 {
307 Ana_Set_Reg(TOP_CLKSQ_CLR, 0x0001, 0x0001); //Turn off 26MHz source clock
308 Ana_Set_Reg(TOP_CLKSQ, 0x0000, 0x0001); //Disable CLKSQ 26MHz
309 }
310 }
311 mutex_unlock(& AudAna_lock);
312 }
313
314 static int TopCkCount = 0;
315 static void Topck_Enable(bool enable)
316 {
317 printk("Topck_Enable enable = %d TopCkCount = %d \n", enable, TopCkCount);
318 mutex_lock(&Ana_Clk_Mutex);
319 if (enable == true)
320 {
321 if (TopCkCount == 0)
322 {
323 Ana_Set_Reg(TOP_CKPDN_CON0_CLR, 0x3800, 0x3800); //Turn on AUDNCP_CLKDIV engine clock,Turn on AUD 26M
324 }
325 TopCkCount++;
326 }
327 else
328 {
329 TopCkCount--;
330 if (TopCkCount == 0)
331 {
332 Ana_Set_Reg(TOP_CKPDN_CON0_SET, 0x3800, 0x3800); //Turn off AUDNCP_CLKDIV engine clock,Turn off AUD 26M
333 }
334 if (TopCkCount <= 0)
335 {
336 printk("TopCkCount <0 =%d\n ", TopCkCount);
337 TopCkCount = 0;
338 }
339 }
340 mutex_unlock(&Ana_Clk_Mutex);
341 }
342
343 static int NvRegCount = 0;
344 static void NvregEnable(bool enable)
345 {
346 printk("NvregEnable NvRegCount == %d enable = %d \n", NvRegCount, enable);
347 mutex_lock(&Ana_Clk_Mutex);
348 if (enable == true)
349 {
350 if (NvRegCount == 0)
351 {
352 Ana_Set_Reg(AUDDEC_ANA_CON8, 0x0000, 0x0002); // Enable AUDGLB
353 }
354 NvRegCount++;
355 }
356 else
357 {
358 NvRegCount--;
359 if (NvRegCount == 0)
360 {
361 Ana_Set_Reg(AUDDEC_ANA_CON8, 0x0002, 0x0002); // disable AUDGLB
362 }
363 if (NvRegCount < 0)
364 {
365 printk("NvRegCount <0 =%d\n ", NvRegCount);
366 NvRegCount = 0;
367 }
368 }
369 mutex_unlock(&Ana_Clk_Mutex);
370 }
371
372 static int VOW12MCKCount = 0;
373 static void VOW12MCK_Enable(bool enable)
374 {
375 printk("VOW12MCK_Enable VOW12MCKCount == %d enable = %d \n", VOW12MCKCount, enable);
376 mutex_lock(&Ana_Clk_Mutex);
377 if (enable == true)
378 {
379 if (VOW12MCKCount == 0)
380 {
381 Ana_Set_Reg(TOP_CKPDN_CON0_CLR, 0x8000, 0x8000); // Enable TOP_CKPDN_CON0 bit15 for enable VOW 12M clock
382 }
383 VOW12MCKCount++;
384 }
385 else
386 {
387 VOW12MCKCount--;
388 if (VOW12MCKCount == 0)
389 {
390 Ana_Set_Reg(TOP_CKPDN_CON0_SET, 0x8000, 0x8000); // disable TOP_CKPDN_CON0 bit15 for enable VOW 12M clock
391 }
392 if (VOW12MCKCount < 0)
393 {
394 printk("VOW12MCKCount <0 =%d\n ", VOW12MCKCount);
395 VOW12MCKCount = 0;
396 }
397 }
398 mutex_unlock(&Ana_Clk_Mutex);
399 }
400
401 void vow_irq_handler(void)
402 {
403 printk("vow_irq_handler,audio irq event....\n");
404 //TurnOnVOWADcPowerACC(AUDIO_ANALOG_DEVICE_IN_ADC1, false);
405 //TurnOnVOWDigitalHW(false);
406 #if defined(VOW_TONE_TEST)
407 EnableSideGenHw(Soc_Aud_InterConnectionOutput_O03, Soc_Aud_MemIF_Direction_DIRECTION_OUTPUT, true);
408 #endif
409 //VowDrv_ChangeStatus();
410 }
411
412 extern kal_uint32 upmu_get_reg_value(kal_uint32 reg);
413
414 void Auddrv_Read_Efuse_HPOffset(void)
415 {
416 U32 ret = 0;
417 U32 reg_val = 0;
418 int i = 0, j = 0;
419 U32 efusevalue[3];
420
421 printk("Auddrv_Read_Efuse_HPOffset(+)\n");
422
423 //1. enable efuse ctrl engine clock
424 ret = pmic_config_interface(0x026C, 0x0040, 0xFFFF, 0);
425 ret = pmic_config_interface(0x024E, 0x0004, 0xFFFF, 0);
426
427 //2.
428 ret = pmic_config_interface(0x0C16, 0x1, 0x1, 0);
429
430 /*
431 Audio data from 746 to 770
432 0xe 746 751
433 0xf 752 767
434 0x10 768 770
435 */
436
437 for (i = 0xe; i <= 0x10; i++)
438 {
439 //3. set row to read
440 ret = pmic_config_interface(0x0C00, i, 0x1F, 1);
441
442 //4. Toggle
443 ret = pmic_read_interface(0xC10, &reg_val, 0x1, 0);
444 if (reg_val == 0)
445 {
446 ret = pmic_config_interface(0xC10, 1, 0x1, 0);
447 }
448 else
449 {
450 ret = pmic_config_interface(0xC10, 0, 0x1, 0);
451 }
452
453 //5. polling Reg[0xC1A]
454 reg_val = 1;
455 while (reg_val == 1)
456 {
457 ret = pmic_read_interface(0xC1A, &reg_val, 0x1, 0);
458 printk("Auddrv_Read_Efuse_HPOffset polling 0xC1A=0x%x\n", reg_val);
459 }
460
461 udelay(1000);//Need to delay at least 1ms for 0xC1A and than can read 0xC18
462
463 //6. read data
464 efusevalue[j] = upmu_get_reg_value(0x0C18);
465 printk("HPoffset : efuse[%d]=0x%x\n", j, efusevalue[j]);
466 j++;
467 }
468
469 //7. Disable efuse ctrl engine clock
470 ret = pmic_config_interface(0x024C, 0x0004, 0xFFFF, 0);
471 ret = pmic_config_interface(0x026A, 0x0040, 0xFFFF, 0);
472
473 RG_AUDHPLTRIM_VAUDP15 = (efusevalue[0] >> 10) & 0xf;
474 RG_AUDHPRTRIM_VAUDP15 = ((efusevalue[0] >> 14) & 0x3) + ((efusevalue[1] & 0x3) << 2);
475 RG_AUDHPLFINETRIM_VAUDP15 = (efusevalue[1] >> 3) & 0x3;
476 RG_AUDHPRFINETRIM_VAUDP15 = (efusevalue[1] >> 5) & 0x3;
477 RG_AUDHPLTRIM_VAUDP15_SPKHP = (efusevalue[1] >> 7) & 0xF;
478 RG_AUDHPRTRIM_VAUDP15_SPKHP = (efusevalue[1] >> 11) & 0xF;
479 RG_AUDHPLFINETRIM_VAUDP15_SPKHP = ((efusevalue[1] >> 15) & 0x1) + ((efusevalue[2] & 0x1) << 1);
480 RG_AUDHPRFINETRIM_VAUDP15_SPKHP = ((efusevalue[2] >> 1) & 0x3);
481
482 printk("RG_AUDHPLTRIM_VAUDP15 = %x\n", RG_AUDHPLTRIM_VAUDP15);
483 printk("RG_AUDHPRTRIM_VAUDP15 = %x\n", RG_AUDHPRTRIM_VAUDP15);
484 printk("RG_AUDHPLFINETRIM_VAUDP15 = %x\n", RG_AUDHPLFINETRIM_VAUDP15);
485 printk("RG_AUDHPRFINETRIM_VAUDP15 = %x\n", RG_AUDHPRFINETRIM_VAUDP15);
486 printk("RG_AUDHPLTRIM_VAUDP15_SPKHP = %x\n", RG_AUDHPLTRIM_VAUDP15_SPKHP);
487 printk("RG_AUDHPRTRIM_VAUDP15_SPKHP = %x\n", RG_AUDHPRTRIM_VAUDP15_SPKHP);
488 printk("RG_AUDHPLFINETRIM_VAUDP15_SPKHP = %x\n", RG_AUDHPLFINETRIM_VAUDP15_SPKHP);
489 printk("RG_AUDHPRFINETRIM_VAUDP15_SPKHP = %x\n", RG_AUDHPRFINETRIM_VAUDP15_SPKHP);
490
491 printk("Auddrv_Read_Efuse_HPOffset(-)\n");
492 }
493
494 EXPORT_SYMBOL(Auddrv_Read_Efuse_HPOffset);
495
496 #ifdef CONFIG_MTK_SPEAKER
497 static void Apply_Speaker_Gain(void)
498 {
499 printk("%s Speaker_pga_gain= %d\n", __func__, Speaker_pga_gain);
500
501 Ana_Set_Reg(SPK_ANA_CON0, Speaker_pga_gain << 11, 0x7800);
502 }
503 #else
504 static void Apply_Speaker_Gain(void)
505 {
506
507 }
508 #endif
509
510 void setOffsetTrimMux(unsigned int Mux)
511 {
512 printk("%s Mux = %d\n", __func__, Mux);
513 Ana_Set_Reg(AUDDEC_ANA_CON3 , Mux << 1, 0xf << 1); // Audio offset trimming buffer mux selection
514 }
515
516 void setOffsetTrimBufferGain(unsigned int gain)
517 {
518 Ana_Set_Reg(AUDDEC_ANA_CON3 , gain << 5, 0x3 << 5); // Audio offset trimming buffer gain selection
519 }
520
521 static int mHplTrimOffset = 2048;
522 static int mHprTrimOffset = 2048;
523
524 void SetHplTrimOffset(int Offset)
525 {
526 printk("%s Offset = %d\n", __func__, Offset);
527 mHplTrimOffset = Offset;
528 if ((Offset > 2098) || (Offset < 1998))
529 {
530 mHplTrimOffset = 2048;
531 printk("SetHplTrimOffset offset may be invalid offset = %d\n", Offset);
532 }
533 }
534
535 void SetHprTrimOffset(int Offset)
536 {
537 printk("%s Offset = %d\n", __func__, Offset);
538 mHprTrimOffset = Offset;
539 if ((Offset > 2098) || (Offset < 1998))
540 {
541 mHprTrimOffset = 2048;
542 printk("SetHprTrimOffset offset may be invalid offset = %d\n", Offset);
543 }
544 }
545
546 void EnableTrimbuffer(bool benable)
547 {
548 if (benable == true)
549 {
550 Ana_Set_Reg(AUDDEC_ANA_CON3 , 0x1, 0x1); // Audio offset trimming buffer enable
551 }
552 else
553 {
554 Ana_Set_Reg(AUDDEC_ANA_CON3 , 0x0, 0x1); // Audio offset trimming buffer disable
555 }
556 }
557
558
559 void OpenTrimBufferHardware(bool enable) //0804 TODO!!!
560 {
561 if (enable)
562 {
563 printk("%s true\n", __func__);
564 TurnOnDacPower();
565 //set analog part (HP playback)
566 Ana_Set_Reg(AUDDEC_ANA_CON8, 0x0000, 0x0002); // Enable AUDGLB
567 Ana_Set_Reg(AUDNCP_CLKDIV_CON1, 0x0001, 0xffff); //Turn on DA_600K_NCP_VA18
568 Ana_Set_Reg(AUDNCP_CLKDIV_CON2, 0x002B, 0xffff); //Set NCP clock as 604kHz // 26MHz/43 = 604KHz
569 Ana_Set_Reg(AUDNCP_CLKDIV_CON0, 0x0001, 0xffff); //Toggle RG_DIVCKS_CHG
570 Ana_Set_Reg(AUDNCP_CLKDIV_CON4, 0x0000, 0xffff); //Set NCP soft start mode as default mode
571 Ana_Set_Reg(AUDNCP_CLKDIV_CON3, 0x0000, 0xffff); //Enable NCP
572 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0A41, 0xfeeb); //Enable cap-less HC LDO (1.5V) & LDO VA33REFGEN
573 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC1, 0xfeeb); //Enable cap-less LC LDO (1.5V)
574 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x8000, 0x8000); //Enable NV regulator (-1.5V)
575 Ana_Set_Reg(ZCD_CON0, 0x0000, 0xffff); //Disable AUD_ZCD
576 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xE080, 0xffff); //Disable headphone, voice and short-ckt protection. voice MUX is set mute
577 //Ana_Set_Reg(AUDDEC_ANA_CON7, 0x, 0xffff); // Enable AU_REFN short circuit //6325 TRIM no need set AU_REFN
578
579 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC0, 0xfeeb); //Enable IBIST
580 //Ana_Set_Reg(AUDDEC_ANA_CON4, 0x0700, 0xffff); //Enable HP & HS drivers bias circuit
581 Ana_Set_Reg(AUDDEC_ANA_CON4, 0x1f00, 0xffff); //Enable HP & HS drivers bias circuit //trim
582
583 Ana_Set_Reg(AUDDEC_ANA_CON5, 0x5490, 0xffff); //HP/HS ibias & DR bias current optimization
584 udelay(50);
585 Ana_Set_Reg(ZCD_CON2, 0x0489, 0xffff); //Set HPR/HPL gain as -1dB
586 Ana_Set_Reg(ZCD_CON3, 0x001F, 0xffff); //Set voice gain as minimum (~ -40dB)
587 Ana_Set_Reg(AUDDEC_ANA_CON1, 0x0480, 0xffff); //De_OSC of HP and enable output STBENH
588 Ana_Set_Reg(AUDDEC_ANA_CON1, 0x1480, 0xffff); //De_OSC of voice, enable output STBENH
589 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xE090, 0xffff); //Enable voice driver
590 Ana_Set_Reg(AUDDEC_ANA_CON1, 0x14A0, 0xffff); //Enable pre-charge buffer
591 udelay(50);
592 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC2, 0xfeeb); //Enable AUD_CLK
593 Ana_Set_Reg(AUDDEC_ANA_CON0, 0x0009, 0x0009); //Enable Audio DACL
594 Ana_Set_Reg(AUDDEC_ANA_CON0, 0x0006, 0x0006); //Enable Audio DACR
595
596 }
597 else
598 {
599 printk("%s false\n", __func__);
600 Ana_Set_Reg(AUDDEC_ANA_CON4, 0x0000, 0xffff); //Disable drivers bias circuit
601 Ana_Set_Reg(AUDDEC_ANA_CON0, 0x0000, 0xffff); //Disable Audio DAC
602 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC0, 0xfeeb); //Disable AUD_CLK, bit2/4/8 is for ADC, do not set
603 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x0000, 0x8000); //Disable NV regulator (-1.5V)
604 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0001, 0xfeeb); //Disable cap-less LDOs (1.5V) & Disable IBIST
605 TurnOffDacPower();
606 }
607 }
608
609 void OpenAnalogTrimHardware(bool enable)
610 {
611 if (enable)
612 {
613 printk("%s true\n", __func__);
614 TurnOnDacPower();
615 //set analog part (HP playback)
616 Ana_Set_Reg(AUDNCP_CLKDIV_CON1, 0x0001, 0xffff); //Turn on DA_600K_NCP_VA18
617 Ana_Set_Reg(AUDNCP_CLKDIV_CON2, 0x002B, 0xffff); //Set NCP clock as 604kHz // 26MHz/43 = 604KHz
618 Ana_Set_Reg(AUDNCP_CLKDIV_CON0, 0x0001, 0xffff); //Toggle RG_DIVCKS_CHG
619 Ana_Set_Reg(AUDNCP_CLKDIV_CON4, 0x0000, 0xffff); //Set NCP soft start mode as default mode
620 Ana_Set_Reg(AUDNCP_CLKDIV_CON3, 0x0000, 0xffff); //Enable NCP
621 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0A41, 0xfeeb); //Enable cap-less HC LDO (1.5V) & LDO VA33REFGEN
622 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC1, 0xfeeb); //Enable cap-less LC LDO (1.5V)
623 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x8000, 0x8000); //Enable NV regulator (-1.5V)
624 Ana_Set_Reg(ZCD_CON0, 0x0000, 0xffff); //Disable AUD_ZCD
625 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xE080, 0xffff); //Disable headphone, voice and short-ckt protection. voice MUX is set mute
626 //Ana_Set_Reg(AUDDEC_ANA_CON7, 0x, 0xffff); // Enable AU_REFN short circuit //6325 TRIM no need set AU_REFN
627
628 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC0, 0xfeeb); //Enable IBIST
629 //Ana_Set_Reg(AUDDEC_ANA_CON4, 0x0700, 0xffff); //Enable HP & HS drivers bias circuit
630 Ana_Set_Reg(AUDDEC_ANA_CON4, 0x1f00, 0xffff); //Enable HP & HS drivers bias circuit //trim
631
632 Ana_Set_Reg(AUDDEC_ANA_CON5, 0x5490, 0xffff); //HP/HS ibias & DR bias current optimization
633 udelay(50);
634 Ana_Set_Reg(ZCD_CON2, 0x0489, 0xffff); //Set HPR/HPL gain as -1dB
635 Ana_Set_Reg(ZCD_CON3, 0x001F, 0xffff); //Set voice gain as minimum (~ -40dB)
636 Ana_Set_Reg(AUDDEC_ANA_CON1, 0x0480, 0xffff); //De_OSC of HP and enable output STBENH
637 Ana_Set_Reg(AUDDEC_ANA_CON1, 0x1480, 0xffff); //De_OSC of voice, enable output STBENH
638 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xE090, 0xffff); //Enable voice driver
639 Ana_Set_Reg(AUDDEC_ANA_CON1, 0x14A0, 0xffff); //Enable pre-charge buffer
640 udelay(50);
641 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC2, 0xfeeb); //Enable AUD_CLK
642 Ana_Set_Reg(AUDDEC_ANA_CON0, 0x0009, 0x0009); //Enable Audio DACL
643 Ana_Set_Reg(AUDDEC_ANA_CON0, 0x0006, 0x0006); //Enable Audio DACR
644
645 }
646 else
647 {
648 printk("%s false\n", __func__);
649 Ana_Set_Reg(AUDDEC_ANA_CON4, 0x0000, 0xffff); //Disable drivers bias circuit
650 Ana_Set_Reg(AUDDEC_ANA_CON0, 0x0000, 0xffff); //Disable Audio DAC
651 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC0, 0xfeeb); //Disable AUD_CLK, bit2/4/8 is for ADC, do not set
652 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x0000, 0x8000); //Disable NV regulator (-1.5V)
653 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0001, 0xfeeb); //Disable cap-less LDOs (1.5V) & Disable IBIST
654 TurnOffDacPower();
655 }
656 }
657
658 void OpenAnalogHeadphone(bool bEnable)
659 {
660 printk("OpenAnalogHeadphone bEnable = %d", bEnable);
661 if (bEnable)
662 {
663 SetHplTrimOffset(2048);
664 SetHprTrimOffset(2048);
665 mBlockSampleRate[AUDIO_ANALOG_DEVICE_OUT_DAC] = 44100;
666 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_LEFT1 , true);
667 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETL] = true;
668 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_RIGHT1 , true);
669 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETR] = true;
670 }
671 else
672 {
673 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETL] = false;
674 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_LEFT1 , false);
675 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETR] = false;
676 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_RIGHT1 , false);
677 }
678 }
679
680 bool OpenHeadPhoneImpedanceSetting(bool bEnable)
681 {
682 printk("%s benable = %d\n", __func__, bEnable);
683 if (GetDLStatus() == true)
684 {
685 return false;
686 }
687 if (bEnable == true)
688 {
689 TurnOnDacPower();
690
691 //set analog part (HP playback)
692 Ana_Set_Reg(AUDNCP_CLKDIV_CON1, 0x0001, 0xffff); //Turn on DA_600K_NCP_VA18
693 Ana_Set_Reg(AUDNCP_CLKDIV_CON2, 0x002B, 0xffff); //Set NCP clock as 604kHz // 26MHz/43 = 604KHz
694 Ana_Set_Reg(AUDNCP_CLKDIV_CON0, 0x0001, 0xffff); //Toggle RG_DIVCKS_CHG
695 Ana_Set_Reg(AUDNCP_CLKDIV_CON4, 0x0000, 0xffff); //Set NCP soft start mode as default mode
696 Ana_Set_Reg(AUDNCP_CLKDIV_CON3, 0x0000, 0xffff); //Enable NCP
697
698 Ana_Set_Reg(AUDDEC_ANA_CON4, 0x0300, 0xffff); //Enable HP driver bias circuit
699
700 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0A41, 0xfeeb); //Enable cap-less HC LDO (1.5V) & LDO VA33REFGEN
701 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC1, 0xfeeb); //Enable cap-less LC LDO (1.5V)
702 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x8000, 0x8000); //Enable NV regulator (-1.5V)
703 Ana_Set_Reg(ZCD_CON0, 0x0000, 0xffff); //Disable AUD_ZCD
704 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xE000, 0xffff); //Disable headphone, voice and short-ckt protection. HP and voice MUX is opened
705 Ana_Set_Reg(AUDDEC_ANA_CON1, 0x0000, 0xffff); //no De_OSC of HP and disable output STBENH
706 Ana_Set_Reg(AUDDEC_ANA_CON3, 0x0080, 0xffff); //Audio headphone speaker detection enable
707 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC0, 0xfeeb); //Enable IBIST
708 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC2, 0xfeeb); //Enable AUD_CLK
709 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xE009, 0xffff); //Enable Audio DAC
710 Ana_Set_Reg(AUDDEC_ANA_CON3, 0x0900, 0x0f00); //Audio headphone speaker detection output mux selection:(10)HPR, Audio headphone speaker detection input mux enable:(01)DACLP
711 }
712 else
713 {
714 Ana_Set_Reg(AUDDEC_ANA_CON4, 0x0000, 0xffff); //Disable drivers bias circuit
715 Ana_Set_Reg(AUDDEC_ANA_CON0, 0x0000, 0xffff); //Disable Audio DAC
716 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC0, 0xfeeb); //Disable AUD_CLK, bit2/4/8 is for ADC, do not set
717 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x0000, 0x8000); //Disable NV regulator (-1.5V)
718 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0001, 0xfeeb); //Disable cap-less LDOs (1.5V) & Disable IBIST
719 Ana_Set_Reg(AUDDEC_ANA_CON3, 0x0000, 0x0080); //Audio headphone speaker detection disable
720 Ana_Set_Reg(AUDDEC_ANA_CON3, 0x0000, 0x0f00); //output mux selection:(00)OPEN, input mux selection:(00)OPEN,
721 TurnOffDacPower();
722 }
723 return true;
724 }
725
726 void setHpGainZero(void)
727 {
728 Ana_Set_Reg(ZCD_CON2, 0x8 << 7, 0x0f80);
729 Ana_Set_Reg(ZCD_CON2, 0x8 , 0x001f);
730 }
731
732 void SetSdmLevel(unsigned int level)
733 {
734 Ana_Set_Reg(AFE_DL_SDM_CON1, level, 0xffffffff);
735 }
736
737
738 static void SetHprOffset(int OffsetTrimming)
739 {
740 short Dccompsentation = 0;
741 int DCoffsetValue = 0;
742 unsigned short RegValue = 0;
743 printk("%s OffsetTrimming = %d \n", __func__, OffsetTrimming);
744 DCoffsetValue = OffsetTrimming * 1000000;
745 DCoffsetValue = (DCoffsetValue / DC1devider); // in uv
746 printk("%s DCoffsetValue = %d \n", __func__, DCoffsetValue);
747 DCoffsetValue = (DCoffsetValue / DC1unit_in_uv);
748 printk("%s DCoffsetValue = %d \n", __func__, DCoffsetValue);
749 Dccompsentation = DCoffsetValue;
750 RegValue = Dccompsentation;
751 printk("%s RegValue = 0x%x\n", __func__, RegValue);
752 Ana_Set_Reg(AFE_DL_DC_COMP_CFG1, RegValue , 0xffff);
753 }
754
755 static void SetHplOffset(int OffsetTrimming)
756 {
757 short Dccompsentation = 0;
758 int DCoffsetValue = 0;
759 unsigned short RegValue = 0;
760 printk("%s OffsetTrimming = %d \n", __func__, OffsetTrimming);
761 DCoffsetValue = OffsetTrimming * 1000000;
762 DCoffsetValue = (DCoffsetValue / DC1devider); // in uv
763 printk("%s DCoffsetValue = %d \n", __func__, DCoffsetValue);
764 DCoffsetValue = (DCoffsetValue / DC1unit_in_uv);
765 printk("%s DCoffsetValue = %d \n", __func__, DCoffsetValue);
766 Dccompsentation = DCoffsetValue;
767 RegValue = Dccompsentation;
768 printk("%s RegValue = 0x%x\n", __func__, RegValue);
769 Ana_Set_Reg(AFE_DL_DC_COMP_CFG0, RegValue , 0xffff);
770 }
771
772 static void EnableDcCompensation(bool bEnable)
773 {
774 #ifndef EFUSE_HP_TRIM
775 Ana_Set_Reg(AFE_DL_DC_COMP_CFG2, bEnable , 0x1);
776 #endif
777 }
778
779 static void SetHprOffsetTrim(void)
780 {
781 int OffsetTrimming = mHprTrimOffset - TrimOffset;
782 printk("%s mHprTrimOffset = %d TrimOffset = %d \n", __func__, mHprTrimOffset, TrimOffset);
783 SetHprOffset(OffsetTrimming);
784 }
785
786 static void SetHpLOffsetTrim(void)
787 {
788 int OffsetTrimming = mHplTrimOffset - TrimOffset;
789 printk("%s mHprTrimOffset = %d TrimOffset = %d \n", __func__, mHplTrimOffset, TrimOffset);
790 SetHplOffset(OffsetTrimming);
791 }
792
793 static void SetDcCompenSation(void)
794 {
795 #ifndef EFUSE_HP_TRIM
796 SetHprOffsetTrim();
797 SetHpLOffsetTrim();
798 EnableDcCompensation(true);
799 #else //use efuse trim
800 Ana_Set_Reg(AUDDEC_ANA_CON2, 0x0800, 0x0800); //Enable trim circuit of HP
801 Ana_Set_Reg(AUDDEC_ANA_CON2, RG_AUDHPLTRIM_VAUDP15 << 3, 0x0078); //Trim offset voltage of HPL
802 Ana_Set_Reg(AUDDEC_ANA_CON2, RG_AUDHPRTRIM_VAUDP15 << 7, 0x0780); //Trim offset voltage of HPR
803 Ana_Set_Reg(AUDDEC_ANA_CON2, RG_AUDHPLFINETRIM_VAUDP15 << 12, 0x3000); //Fine trim offset voltage of HPL
804 Ana_Set_Reg(AUDDEC_ANA_CON2, RG_AUDHPRFINETRIM_VAUDP15 << 14, 0xC000); //Fine trim offset voltage of HPR
805 #endif
806 }
807
808 static void SetDcCompenSation_SPKHP(void)
809 {
810 #ifdef EFUSE_HP_TRIM //use efuse trim
811 Ana_Set_Reg(AUDDEC_ANA_CON2, 0x0800, 0x0800); //Enable trim circuit of HP
812 Ana_Set_Reg(AUDDEC_ANA_CON2, RG_AUDHPLTRIM_VAUDP15_SPKHP << 3, 0x0078); //Trim offset voltage of HPL
813 Ana_Set_Reg(AUDDEC_ANA_CON2, RG_AUDHPRTRIM_VAUDP15_SPKHP << 7, 0x0780); //Trim offset voltage of HPR
814 Ana_Set_Reg(AUDDEC_ANA_CON2, RG_AUDHPLFINETRIM_VAUDP15_SPKHP << 12, 0x3000); //Fine trim offset voltage of HPL
815 Ana_Set_Reg(AUDDEC_ANA_CON2, RG_AUDHPRFINETRIM_VAUDP15_SPKHP << 14, 0xC000); //Fine trim offset voltage of HPR
816 #endif
817 }
818
819
820 static void SetDCcoupleNP(int MicBias, int mode)
821 {
822 printk("%s MicBias= %d mode = %d\n", __func__, MicBias, mode);
823 switch (mode)
824 {
825 case AUDIO_ANALOGUL_MODE_ACC:
826 case AUDIO_ANALOGUL_MODE_DCC:
827 case AUDIO_ANALOGUL_MODE_DMIC:
828 {
829 if (MicBias == AUDIO_MIC_BIAS0)
830 {
831 Ana_Set_Reg(AUDENC_ANA_CON9, 0x0000, 0x0006);
832 }
833 else if (MicBias == AUDIO_MIC_BIAS1)
834 {
835 Ana_Set_Reg(AUDENC_ANA_CON9, 0x0000, 0x0060);
836 }
837 }
838 break;
839 case AUDIO_ANALOGUL_MODE_DCCECMDIFF:
840 {
841 if (MicBias == AUDIO_MIC_BIAS0)
842 {
843 Ana_Set_Reg(AUDENC_ANA_CON9, 0x0006, 0x0006);
844 }
845 else if (MicBias == AUDIO_MIC_BIAS1)
846 {
847 Ana_Set_Reg(AUDENC_ANA_CON9, 0x0060, 0x0060);
848 }
849 }
850 break;
851 case AUDIO_ANALOGUL_MODE_DCCECMSINGLE:
852 {
853 if (MicBias == AUDIO_MIC_BIAS0)
854 {
855 Ana_Set_Reg(AUDENC_ANA_CON9, 0x0002, 0x0006);
856 }
857 else if (MicBias == AUDIO_MIC_BIAS1)
858 {
859 Ana_Set_Reg(AUDENC_ANA_CON9, 0x0020, 0x0060);
860 }
861 }
862 break;
863 default:
864 break;
865 }
866 }
867
868 uint32 GetULFrequency(uint32 frequency)
869 {
870 uint32 Reg_value = 0;
871 printk("%s frequency =%d\n", __func__, frequency);
872 switch (frequency)
873 {
874 case 8000:
875 case 16000:
876 case 32000:
877 Reg_value = 0x0;
878 break;
879 case 48000:
880 Reg_value = 0x1;
881 default:
882 break;
883
884 }
885 return Reg_value;
886 }
887
888
889 uint32 ULSampleRateTransform(uint32 SampleRate)
890 {
891 switch (SampleRate)
892 {
893 case 8000:
894 return 0;
895 case 16000:
896 return 1;
897 case 32000:
898 return 2;
899 case 48000:
900 return 3;
901 default:
902 break;
903 }
904 return 0;
905 }
906
907
908 static int mt63xx_codec_startup(struct snd_pcm_substream *substream , struct snd_soc_dai *Daiport)
909 {
910 //printk("+mt63xx_codec_startup name = %s number = %d\n", substream->name, substream->number);
911 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && substream->runtime->rate)
912 {
913 //printk("mt63xx_codec_startup set up SNDRV_PCM_STREAM_CAPTURE rate = %d\n", substream->runtime->rate);
914 mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC] = substream->runtime->rate;
915
916 }
917 else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && substream->runtime->rate)
918 {
919 //printk("mt63xx_codec_startup set up SNDRV_PCM_STREAM_PLAYBACK rate = %d\n", substream->runtime->rate);
920 mBlockSampleRate[AUDIO_ANALOG_DEVICE_OUT_DAC] = substream->runtime->rate;
921 }
922 //printk("-mt63xx_codec_startup name = %s number = %d\n", substream->name, substream->number);
923 return 0;
924 }
925
926 static int mt63xx_codec_prepare(struct snd_pcm_substream *substream , struct snd_soc_dai *Daiport)
927 {
928 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
929 {
930 printk("mt63xx_codec_prepare set up SNDRV_PCM_STREAM_CAPTURE rate = %d\n", substream->runtime->rate);
931 mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC] = substream->runtime->rate;
932
933 }
934 else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
935 {
936 printk("mt63xx_codec_prepare set up SNDRV_PCM_STREAM_PLAYBACK rate = %d\n", substream->runtime->rate);
937 mBlockSampleRate[AUDIO_ANALOG_DEVICE_OUT_DAC] = substream->runtime->rate;
938 }
939 return 0;
940 }
941
942 static int mt6323_codec_trigger(struct snd_pcm_substream *substream , int command , struct snd_soc_dai *Daiport)
943 {
944 switch (command)
945 {
946 case SNDRV_PCM_TRIGGER_START:
947 case SNDRV_PCM_TRIGGER_RESUME:
948 case SNDRV_PCM_TRIGGER_STOP:
949 case SNDRV_PCM_TRIGGER_SUSPEND:
950 break;
951 }
952
953 //printk("mt6323_codec_trigger command = %d\n ", command);
954 return 0;
955 }
956
957 static const struct snd_soc_dai_ops mt6323_aif1_dai_ops =
958 {
959 .startup = mt63xx_codec_startup,
960 .prepare = mt63xx_codec_prepare,
961 .trigger = mt6323_codec_trigger,
962 };
963
964 static struct snd_soc_dai_driver mtk_6331_dai_codecs[] =
965 {
966 {
967 .name = MT_SOC_CODEC_TXDAI_NAME,
968 .ops = &mt6323_aif1_dai_ops,
969 .playback = {
970 .stream_name = MT_SOC_DL1_STREAM_NAME,
971 .channels_min = 1,
972 .channels_max = 2,
973 .rates = SNDRV_PCM_RATE_8000_192000,
974 .formats = SND_SOC_ADV_MT_FMTS,
975 },
976 },
977 {
978 .name = MT_SOC_CODEC_RXDAI_NAME,
979 .ops = &mt6323_aif1_dai_ops,
980 .capture = {
981 .stream_name = MT_SOC_UL1_STREAM_NAME,
982 .channels_min = 1,
983 .channels_max = 2,
984 .rates = SNDRV_PCM_RATE_8000_192000,
985 .formats = SND_SOC_ADV_MT_FMTS,
986 },
987 },
988 {
989 .name = MT_SOC_CODEC_TDMRX_DAI_NAME,
990 .ops = &mt6323_aif1_dai_ops,
991 .capture = {
992 .stream_name = MT_SOC_TDM_CAPTURE_STREAM_NAME,
993 .channels_min = 2,
994 .channels_max = 8,
995 .rates = SNDRV_PCM_RATE_8000_192000,
996 .formats = (SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
997 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
998 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
999 SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_S24_LE |
1000 SNDRV_PCM_FMTBIT_U24_BE | SNDRV_PCM_FMTBIT_S24_BE |
1001 SNDRV_PCM_FMTBIT_U24_3LE | SNDRV_PCM_FMTBIT_S24_3LE |
1002 SNDRV_PCM_FMTBIT_U24_3BE | SNDRV_PCM_FMTBIT_S24_3BE |
1003 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
1004 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE),
1005 },
1006 },
1007 {
1008 .name = MT_SOC_CODEC_I2S0TXDAI_NAME,
1009 .ops = &mt6323_aif1_dai_ops,
1010 .playback = {
1011 .stream_name = MT_SOC_I2SDL1_STREAM_NAME,
1012 .channels_min = 1,
1013 .channels_max = 2,
1014 .rate_min = 8000,
1015 .rate_max = 192000,
1016 .rates = SNDRV_PCM_RATE_8000_192000,
1017 .formats = SND_SOC_ADV_MT_FMTS,
1018 }
1019 },
1020 {
1021 .name = MT_SOC_CODEC_VOICE_MD1DAI_NAME,
1022 .ops = &mt6323_aif1_dai_ops,
1023 .playback = {
1024 .stream_name = MT_SOC_VOICE_MD1_STREAM_NAME,
1025 .channels_min = 1,
1026 .channels_max = 2,
1027 .rates = SNDRV_PCM_RATE_8000_48000,
1028 .formats = SND_SOC_ADV_MT_FMTS,
1029 },
1030 .capture = {
1031 .stream_name = MT_SOC_VOICE_MD1_STREAM_NAME,
1032 .channels_min = 1,
1033 .channels_max = 2,
1034 .rates = SNDRV_PCM_RATE_8000_48000,
1035 .formats = SND_SOC_ADV_MT_FMTS,
1036 },
1037 },
1038 {
1039 .name = MT_SOC_CODEC_VOICE_MD2DAI_NAME,
1040 .ops = &mt6323_aif1_dai_ops,
1041 .playback = {
1042 .stream_name = MT_SOC_VOICE_MD2_STREAM_NAME,
1043 .channels_min = 1,
1044 .channels_max = 2,
1045 .rates = SNDRV_PCM_RATE_8000_48000,
1046 .formats = SND_SOC_ADV_MT_FMTS,
1047 },
1048 .capture = {
1049 .stream_name = MT_SOC_VOICE_MD2_STREAM_NAME,
1050 .channels_min = 1,
1051 .channels_max = 2,
1052 .rates = SNDRV_PCM_RATE_8000_48000,
1053 .formats = SND_SOC_ADV_MT_FMTS,
1054 },
1055 },
1056 {
1057 .name = MT_SOC_CODEC_FMI2S2RXDAI_NAME,
1058 .ops = &mt6323_aif1_dai_ops,
1059 .playback = {
1060 .stream_name = MT_SOC_FM_I2S2_STREAM_NAME,
1061 .channels_min = 1,
1062 .channels_max = 2,
1063 .rates = SNDRV_PCM_RATE_8000_48000,
1064 .formats = SND_SOC_ADV_MT_FMTS,
1065 },
1066 .capture = {
1067 .stream_name = MT_SOC_FM_I2S2_RECORD_STREAM_NAME,
1068 .channels_min = 1,
1069 .channels_max = 2,
1070 .rates = SNDRV_PCM_RATE_8000_48000,
1071 .formats = SND_SOC_ADV_MT_FMTS,
1072 },
1073 },
1074 {
1075 .name = MT_SOC_CODEC_FMMRGTXDAI_DUMMY_DAI_NAME,
1076 .ops = &mt6323_aif1_dai_ops,
1077 .playback = {
1078 .stream_name = MT_SOC_FM_MRGTX_STREAM_NAME,
1079 .channels_min = 1,
1080 .channels_max = 2,
1081 .rates = SNDRV_PCM_RATE_8000_48000,
1082 .formats = SND_SOC_ADV_MT_FMTS,
1083 },
1084 },
1085 {
1086 .name = MT_SOC_CODEC_ULDLLOOPBACK_NAME,
1087 .ops = &mt6323_aif1_dai_ops,
1088 .playback = {
1089 .stream_name = MT_SOC_ULDLLOOPBACK_STREAM_NAME,
1090 .channels_min = 1,
1091 .channels_max = 2,
1092 .rates = SNDRV_PCM_RATE_8000_48000,
1093 .formats = SND_SOC_ADV_MT_FMTS,
1094 },
1095 .capture = {
1096 .stream_name = MT_SOC_ULDLLOOPBACK_STREAM_NAME,
1097 .channels_min = 1,
1098 .channels_max = 2,
1099 .rates = SNDRV_PCM_RATE_8000_48000,
1100 .formats = SND_SOC_ADV_MT_FMTS,
1101 },
1102 },
1103 {
1104 .name = MT_SOC_CODEC_STUB_NAME,
1105 .ops = &mt6323_aif1_dai_ops,
1106 .playback = {
1107 .stream_name = MT_SOC_ROUTING_STREAM_NAME,
1108 .channels_min = 1,
1109 .channels_max = 2,
1110 .rates = SNDRV_PCM_RATE_8000_192000,
1111 .formats = SND_SOC_ADV_MT_FMTS,
1112 },
1113 },
1114 {
1115 .name = MT_SOC_CODEC_RXDAI2_NAME,
1116 .capture = {
1117 .stream_name = MT_SOC_UL1DATA2_STREAM_NAME,
1118 .channels_min = 1,
1119 .channels_max = 2,
1120 .rates = SNDRV_PCM_RATE_8000_192000,
1121 .formats = SND_SOC_ADV_MT_FMTS,
1122 },
1123 },
1124 {
1125 .name = MT_SOC_CODEC_MRGRX_DAI_NAME,
1126 .ops = &mt6323_aif1_dai_ops,
1127 .playback = {
1128 .stream_name = MT_SOC_MRGRX_STREAM_NAME,
1129 .channels_min = 1,
1130 .channels_max = 8,
1131 .rates = SNDRV_PCM_RATE_8000_192000,
1132 .formats = SND_SOC_ADV_MT_FMTS,
1133 },
1134 .capture = {
1135 .stream_name = MT_SOC_MRGRX_STREAM_NAME,
1136 .channels_min = 1,
1137 .channels_max = 8,
1138 .rates = SNDRV_PCM_RATE_8000_192000,
1139 .formats = SND_SOC_ADV_MT_FMTS,
1140 },
1141 },
1142 {
1143 .name = MT_SOC_CODEC_HP_IMPEDANCE_NAME,
1144 .ops = &mt6323_aif1_dai_ops,
1145 .playback = {
1146 .stream_name = MT_SOC_HP_IMPEDANCE_STREAM_NAME,
1147 .channels_min = 1,
1148 .channels_max = 2,
1149 .rates = SNDRV_PCM_RATE_8000_192000,
1150 .formats = SND_SOC_ADV_MT_FMTS,
1151 },
1152 },
1153 {
1154 .name = MT_SOC_CODEC_FM_I2S_DAI_NAME,
1155 .ops = &mt6323_aif1_dai_ops,
1156 .playback = {
1157 .stream_name = MT_SOC_FM_I2S_PLAYBACK_STREAM_NAME,
1158 .channels_min = 1,
1159 .channels_max = 8,
1160 .rates = SNDRV_PCM_RATE_8000_192000,
1161 .formats = SND_SOC_ADV_MT_FMTS,
1162 },
1163 .capture = {
1164 .stream_name = MT_SOC_FM_I2S_PLAYBACK_STREAM_NAME,
1165 .channels_min = 1,
1166 .channels_max = 8,
1167 .rates = SNDRV_PCM_RATE_8000_192000,
1168 .formats = SND_SOC_ADV_MT_FMTS,
1169 },
1170 },
1171 };
1172
1173
1174 uint32 GetDLNewIFFrequency(unsigned int frequency)
1175 {
1176 uint32 Reg_value = 0;
1177 //printk("AudioPlatformDevice ApplyDLNewIFFrequency ApplyDLNewIFFrequency = %d", frequency);
1178 switch (frequency)
1179 {
1180 case 8000:
1181 Reg_value = 0;
1182 break;
1183 case 11025:
1184 Reg_value = 1;
1185 break;
1186 case 12000:
1187 Reg_value = 2;
1188 break;
1189 case 16000:
1190 Reg_value = 3;
1191 break;
1192 case 22050:
1193 Reg_value = 4;
1194 break;
1195 case 24000:
1196 Reg_value = 5;
1197 break;
1198 case 32000:
1199 Reg_value = 6;
1200 break;
1201 case 44100:
1202 Reg_value = 7;
1203 break;
1204 case 48000:
1205 Reg_value = 8;
1206 default:
1207 printk("ApplyDLNewIFFrequency with frequency = %d", frequency);
1208 }
1209 return Reg_value;
1210 }
1211
1212 static void TurnOnDacPower(void)
1213 {
1214 printk("TurnOnDacPower\n");
1215 audckbufEnable(true);
1216 ClsqEnable(true);
1217 Topck_Enable(true);
1218 udelay(250);
1219 NvregEnable(true); //K2 moved to 0x0CEE
1220 if (GetAdcStatus() == false)
1221 {
1222 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x003a, 0xffff); //power on clock
1223 }
1224 else
1225 {
1226 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0000, 0xffff); //power on clock
1227 }
1228
1229 //set digital part
1230 Ana_Set_Reg(AFUNC_AUD_CON2, 0x0006, 0xffff); //sdm audio fifo clock power on
1231 Ana_Set_Reg(AFUNC_AUD_CON0, 0xc3a1, 0xffff); //scrambler clock on enable
1232 Ana_Set_Reg(AFUNC_AUD_CON2, 0x0003, 0xffff); //sdm power on
1233 Ana_Set_Reg(AFUNC_AUD_CON2, 0x000b, 0xffff); //sdm fifo enable
1234 Ana_Set_Reg(AFE_DL_SDM_CON1, 0x001e, 0xffff); //set attenuation gain
1235 Ana_Set_Reg(AFE_UL_DL_CON0 , 0x0001, 0xffff); //[0] afe enable
1236
1237 Ana_Set_Reg(AFE_PMIC_NEWIF_CFG0 , GetDLNewIFFrequency(mBlockSampleRate[AUDIO_ANALOG_DEVICE_OUT_DAC]) << 12 | 0x330 , 0xffff);
1238 Ana_Set_Reg(AFE_DL_SRC2_CON0_H , GetDLNewIFFrequency(mBlockSampleRate[AUDIO_ANALOG_DEVICE_OUT_DAC]) << 12 | 0x300 , 0xffff); //K2
1239
1240 Ana_Set_Reg(AFE_DL_SRC2_CON0_L , 0x0001 , 0xffff); //turn on dl
1241 Ana_Set_Reg(PMIC_AFE_TOP_CON0 , 0x0000 , 0xffff); //set DL in normal path, not from sine gen table
1242 }
1243
1244 static void TurnOffDacPower(void)
1245 {
1246 printk("TurnOffDacPower\n");
1247
1248 Ana_Set_Reg(AFE_DL_SRC2_CON0_L , 0x0000 , 0xffff); //bit0, Turn off down-link
1249 if (GetAdcStatus() == false)
1250 {
1251 Ana_Set_Reg(AFE_UL_DL_CON0, 0x0000, 0xffff); //turn off afe
1252 }
1253 udelay(250);
1254
1255 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0040, 0x0040); //down-link power down
1256
1257 Ana_Set_Reg(AUDNCP_CLKDIV_CON0, 0x0000, 0xffff); //Toggle RG_DIVCKS_CHG
1258 Ana_Set_Reg(AUDNCP_CLKDIV_CON1, 0x0000, 0xffff); //Turn off DA_600K_NCP_VA18
1259 Ana_Set_Reg(AUDNCP_CLKDIV_CON3, 0x0001, 0xffff); // Disable NCP
1260 NvregEnable(false);
1261 ClsqEnable(false);
1262 Topck_Enable(false);
1263 audckbufEnable(false);
1264 }
1265
1266 static void HeadsetVoloumeRestore(void)
1267 {
1268 int index = 0, oldindex = 0, offset = 0, count = 1;
1269 printk("%s\n", __func__);
1270 index = 8 ;
1271 oldindex = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTR];
1272 if (index > oldindex)
1273 {
1274 printk("index = %d oldindex = %d \n", index, oldindex);
1275 offset = index - oldindex;
1276 while (offset > 0)
1277 {
1278 Ana_Set_Reg(ZCD_CON2, ((oldindex + count) << 7) | (oldindex + count) , 0xf9f);
1279 offset--;
1280 count++;
1281 udelay(100);
1282 }
1283 }
1284 else
1285 {
1286 printk("index = %d oldindex = %d \n", index, oldindex);
1287 offset = oldindex - index;
1288 while (offset > 0)
1289 {
1290 Ana_Set_Reg(ZCD_CON2, ((oldindex - count) << 7) | (oldindex - count) , 0xf9f);
1291 offset--;
1292 count++;
1293 udelay(100);
1294 }
1295 }
1296 Ana_Set_Reg(ZCD_CON2, 0x0489, 0xf9f);
1297 }
1298
1299 static void HeadsetVoloumeSet(void)
1300 {
1301 int index = 0, oldindex = 0, offset = 0, count = 1;
1302 printk("%s\n", __func__);
1303 index = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTR];
1304 oldindex = 8;
1305 if (index > oldindex)
1306 {
1307 printk("index = %d oldindex = %d \n", index, oldindex);
1308 offset = index - oldindex;
1309 while (offset > 0)
1310 {
1311 Ana_Set_Reg(ZCD_CON2, ((oldindex + count) << 7) | (oldindex + count) , 0xf9f);
1312 offset--;
1313 count++;
1314 udelay(200);
1315 }
1316 }
1317 else
1318 {
1319 printk("index = %d oldindex = %d \n", index, oldindex);
1320 offset = oldindex - index;
1321 while (offset > 0)
1322 {
1323 Ana_Set_Reg(ZCD_CON2, ((oldindex - count) << 7) | (oldindex - count) , 0xf9f);
1324 offset--;
1325 count++;
1326 udelay(200);
1327 }
1328 }
1329 Ana_Set_Reg(ZCD_CON2, (index << 7) | (index), 0xf9f);
1330 }
1331
1332 static void Audio_Amp_Change(int channels , bool enable)
1333 {
1334 if (enable)
1335 {
1336 if (GetDLStatus() == false)
1337 {
1338 TurnOnDacPower();
1339 }
1340 // here pmic analog control
1341 if (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETL] == false &&
1342 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETR] == false)
1343 {
1344 printk("%s \n", __func__);
1345
1346 //set analog part (HP playback)
1347 Ana_Set_Reg(AUDNCP_CLKDIV_CON1, 0x0001, 0xffff); //Turn on DA_600K_NCP_VA18
1348 Ana_Set_Reg(AUDNCP_CLKDIV_CON2, 0x002B, 0xffff); //Set NCP clock as 604kHz // 26MHz/43 = 604KHz
1349 Ana_Set_Reg(AUDNCP_CLKDIV_CON0, 0x0001, 0xffff); //Toggle RG_DIVCKS_CHG
1350 Ana_Set_Reg(AUDNCP_CLKDIV_CON4, 0x0000, 0xffff); //Set NCP soft start mode as default mode
1351 Ana_Set_Reg(AUDNCP_CLKDIV_CON3, 0x0000, 0xffff); //Enable NCP
1352 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0A41, 0xfeeb); //Enable cap-less HC LDO (1.5V) & LDO VA33REFGEN
1353 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC1, 0xfeeb); //Enable cap-less LC LDO (1.5V)
1354 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x8000, 0x8000); //Enable NV regulator (-1.5V)
1355 Ana_Set_Reg(ZCD_CON0, 0x0000, 0xffff); //Disable AUD_ZCD
1356 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xE080, 0xffff); //Disable headphone, voice and short-ckt protection. HP MUX is opened, voice MUX is set mute
1357 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC0, 0xfeeb); //Enable IBIST
1358 Ana_Set_Reg(AUDDEC_ANA_CON4, 0x0700, 0xffff); //Enable HP & HS drivers bias circuit
1359 Ana_Set_Reg(AUDDEC_ANA_CON5, 0x5490, 0xffff); //HP/HS ibias & DR bias current optimization
1360 udelay(50);
1361 Ana_Set_Reg(ZCD_CON2, 0x0F9F, 0xffff); //Set HPR/HPL gain as minimum (~ -40dB)
1362 Ana_Set_Reg(ZCD_CON3, 0x001F, 0xffff); //Set voice gain as minimum (~ -40dB)
1363 Ana_Set_Reg(AUDDEC_ANA_CON1, 0x0480, 0xffff); //De_OSC of HP and enable output STBENH
1364 Ana_Set_Reg(AUDDEC_ANA_CON1, 0x1480, 0xffff); //De_OSC of voice, enable output STBENH
1365 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xE090, 0xffff); //Enable voice driver
1366 Ana_Set_Reg(AUDDEC_ANA_CON1, 0x14A0, 0xffff); //Enable pre-charge buffer
1367 udelay(50);
1368 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC2, 0xfeeb); //Enable AUD_CLK
1369 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xE09F, 0xffff); //Enable Audio DAC
1370
1371 //Apply digital DC compensation value to DAC
1372 Ana_Set_Reg(ZCD_CON2, 0x0489, 0xffff); //Set HPR/HPL gain to -1dB, step by step
1373 SetDcCompenSation();
1374 udelay(100);
1375 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xF49F, 0xffff); //Switch HP MUX to audio DAC
1376 // here may cause pop
1377 //msleep(1); //K2 removed
1378 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xF4FF, 0xffff); //Enable HPR/HPL
1379 udelay(50);
1380 Ana_Set_Reg(AUDDEC_ANA_CON1, 0x1480, 0xffff); //Disable pre-charge buffer
1381 Ana_Set_Reg(AUDDEC_ANA_CON1, 0x0480, 0xffff); //Disable De_OSC of voice
1382 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xF46F, 0xffff); //Disable voice buffer & Open HS input MUX
1383 Ana_Set_Reg(AUDDEC_ANA_CON4, 0x0300, 0xffff); //Disable HS drivers bias circuit
1384
1385 // apply volume setting
1386 HeadsetVoloumeSet();
1387 }
1388 else if (channels == AUDIO_ANALOG_CHANNELS_LEFT1)
1389 {
1390 }
1391 else if (channels == AUDIO_ANALOG_CHANNELS_RIGHT1)
1392 {
1393 }
1394 }
1395 else
1396 {
1397 if (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETL] == false &&
1398 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETR] == false)
1399 {
1400 printk("Audio_Amp_Change off amp\n");
1401 HeadsetVoloumeRestore();// Set HPR/HPL gain as -1dB, step by step
1402 //Ana_Set_Reg(ZCD_CON2, 0x0F9F, 0xffff); //Set HPR/HPL gain as minimum (~ -40dB)
1403 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xF40F, 0xffff); //Disable HPR/HPL
1404 }
1405 else if (channels == AUDIO_ANALOG_CHANNELS_LEFT1)
1406 {
1407 }
1408 else if (channels == AUDIO_ANALOG_CHANNELS_RIGHT1)
1409 {
1410 }
1411 if (GetDLStatus() == false)
1412 {
1413 Ana_Set_Reg(AUDDEC_ANA_CON4, 0x0000, 0xffff); //Disable drivers bias circuit
1414 Ana_Set_Reg(AUDDEC_ANA_CON0, 0x0000, 0xffff); //Disable Audio DAC
1415 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC0, 0xfeeb); //Disable AUD_CLK, bit2/4/8 is for ADC, do not set
1416 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x0000, 0x8000); //Disable NV regulator (-1.5V)
1417 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0001, 0xfeeb); //Disable cap-less LDOs (1.5V) & Disable IBIST
1418 TurnOffDacPower();
1419 }
1420 EnableDcCompensation(false);
1421 }
1422 }
1423
1424 static int Audio_AmpL_Get(struct snd_kcontrol *kcontrol,
1425 struct snd_ctl_elem_value *ucontrol)
1426 {
1427 printk("Audio_AmpL_Get = %d\n", mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETL]);
1428 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETL];
1429 return 0;
1430 }
1431
1432 static int Audio_AmpL_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1433 {
1434 mutex_lock(&Ana_Ctrl_Mutex);
1435
1436 printk("%s() gain = %ld \n ", __func__, ucontrol->value.integer.value[0]);
1437 if ((ucontrol->value.integer.value[0] == true) && (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETL] == false))
1438 {
1439 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_LEFT1 , true);
1440 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETL] = ucontrol->value.integer.value[0];
1441 }
1442 else if ((ucontrol->value.integer.value[0] == false) && (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETL] == true))
1443 {
1444 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETL] = ucontrol->value.integer.value[0];
1445 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_LEFT1 , false);
1446 }
1447 mutex_unlock(&Ana_Ctrl_Mutex);
1448 return 0;
1449 }
1450
1451 static int Audio_AmpR_Get(struct snd_kcontrol *kcontrol,
1452 struct snd_ctl_elem_value *ucontrol)
1453 {
1454 printk("Audio_AmpR_Get = %d\n", mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETR]);
1455 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETR];
1456 return 0;
1457 }
1458
1459 static int Audio_AmpR_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1460 {
1461 mutex_lock(&Ana_Ctrl_Mutex);
1462
1463 printk("%s()\n", __func__);
1464 if ((ucontrol->value.integer.value[0] == true) && (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETR] == false))
1465 {
1466 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_RIGHT1 , true);
1467 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETR] = ucontrol->value.integer.value[0];
1468 }
1469 else if ((ucontrol->value.integer.value[0] == false) && (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETR] == true))
1470 {
1471 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_HEADSETR] = ucontrol->value.integer.value[0];
1472 Audio_Amp_Change(AUDIO_ANALOG_CHANNELS_RIGHT1 , false);
1473 }
1474 mutex_unlock(&Ana_Ctrl_Mutex);
1475 return 0;
1476 }
1477
1478 #if 0 //not used
1479 static void SetVoiceAmpVolume(void)
1480 {
1481 int index;
1482 printk("%s\n", __func__);
1483 index = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HSOUTL];
1484 Ana_Set_Reg(ZCD_CON3, index , 0x001f);
1485 }
1486 #endif
1487
1488 static void Voice_Amp_Change(bool enable)
1489 {
1490 if (enable)
1491 {
1492 printk("%s \n", __func__);
1493 if (GetDLStatus() == false)
1494 {
1495 TurnOnDacPower();
1496 printk("Voice_Amp_Change on amp\n");
1497
1498 //set analog part (voice HS playback)
1499 Ana_Set_Reg(AUDNCP_CLKDIV_CON1, 0x0001, 0xffff); //Turn on DA_600K_NCP_VA18
1500 Ana_Set_Reg(AUDNCP_CLKDIV_CON2, 0x002B, 0xffff); //Set NCP clock as 604kHz // 26MHz/43 = 604KHz
1501 Ana_Set_Reg(AUDNCP_CLKDIV_CON0, 0x0001, 0xffff); //Toggle RG_DIVCKS_CHG
1502 Ana_Set_Reg(AUDNCP_CLKDIV_CON4, 0x0000, 0xffff); //Set NCP soft start mode as default mode
1503 Ana_Set_Reg(AUDNCP_CLKDIV_CON3, 0x0000, 0xffff); //Enable NCP
1504 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0A40, 0xfeeb); //Enable cap-less HC LDO (1.5V)
1505 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC0, 0xfeeb); //Enable cap-less LC LDO (1.5V)
1506 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x8000, 0x8000); //Enable NV regulator (-1.5V)
1507 Ana_Set_Reg(ZCD_CON0, 0x0000, 0xffff); //Disable AUD_ZCD
1508 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xE080, 0xffff); //Disable headphone, voice and short-ckt protection. HP MUX is opened, voice MUX is set mute
1509 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC0, 0xfeeb); //Enable IBIST
1510 Ana_Set_Reg(AUDDEC_ANA_CON4, 0x0400, 0xffff); //Enable HS drivers bias circuit
1511 Ana_Set_Reg(AUDDEC_ANA_CON5, 0x5490, 0xffff); //HP/HS ibias & DR bias current optimization
1512 udelay(50);
1513 Ana_Set_Reg(ZCD_CON3, 0x001F, 0xffff); //Set voice gain as minimum (~ -40dB)
1514 Ana_Set_Reg(AUDDEC_ANA_CON1, 0x1000, 0xffff); //De_OSC of voice, enable output STBENH
1515 //Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC2, 0xfeeb); //Enable AUD_CLK
1516 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2BC6, 0xffff); //Enable AUD_CLK
1517 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xE089, 0xffff); //Enable Audio DAC
1518
1519 //Apply digital DC compensation value to DAC
1520 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xE109, 0xffff); //Switch HS MUX to audio DAC
1521 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xE119, 0xffff); //Enable voice driver
1522 udelay(50);
1523 Ana_Set_Reg(ZCD_CON3, 0x0000, 0xffff); //Set HS gain to +8dB(for SMT), step by step
1524 }
1525 }
1526 else
1527 {
1528 printk("turn off ampL\n");
1529 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xE109 , 0xffff); //Disable voice driver
1530
1531 if (GetDLStatus() == false)
1532 {
1533 Ana_Set_Reg(AUDDEC_ANA_CON4, 0x0000, 0xffff); //Disable drivers bias circuit
1534 Ana_Set_Reg(AUDDEC_ANA_CON0, 0x0000, 0xffff); //Disable Audio DAC
1535 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC0, 0xfeeb); //Disable AUD_CLK, bit2/4/8 is for ADC, do not set
1536 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x0000, 0x8000); //Disable NV regulator (-1.5V)
1537 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0001, 0xfeeb); //Disable cap-less LDOs (1.5V) & Disable IBIST
1538
1539 TurnOffDacPower();
1540 }
1541 }
1542 }
1543
1544 static int Voice_Amp_Get(struct snd_kcontrol *kcontrol,
1545 struct snd_ctl_elem_value *ucontrol)
1546 {
1547 printk("Voice_Amp_Get = %d\n", mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_EARPIECEL]);
1548 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_EARPIECEL];
1549 return 0;
1550 }
1551
1552 static int Voice_Amp_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1553 {
1554 mutex_lock(&Ana_Ctrl_Mutex);
1555 printk("%s()\n", __func__);
1556 if ((ucontrol->value.integer.value[0] == true) && (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_EARPIECEL] == false))
1557 {
1558 Voice_Amp_Change(true);
1559 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_EARPIECEL] = ucontrol->value.integer.value[0];
1560 }
1561 else if ((ucontrol->value.integer.value[0] == false) && (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_EARPIECEL] == true))
1562 {
1563 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_EARPIECEL] = ucontrol->value.integer.value[0];
1564 Voice_Amp_Change(false);
1565 }
1566 mutex_unlock(&Ana_Ctrl_Mutex);
1567 return 0;
1568 }
1569
1570 static void Speaker_Amp_Change(bool enable)
1571 {
1572 if (enable)
1573 {
1574 if (GetDLStatus() == false)
1575 {
1576 TurnOnDacPower();
1577 }
1578 printk("%s \n", __func__);
1579 // ClassAB spk pmic analog control
1580 Ana_Set_Reg(AUDNCP_CLKDIV_CON1, 0x0001, 0xffff); //Turn on DA_600K_NCP_VA18
1581 Ana_Set_Reg(AUDNCP_CLKDIV_CON2, 0x002B, 0xffff); //Set NCP clock as 604kHz // 26MHz/43 = 604KHz
1582 Ana_Set_Reg(AUDNCP_CLKDIV_CON0, 0x0001, 0xffff); //Toggle RG_DIVCKS_CHG
1583 Ana_Set_Reg(AUDNCP_CLKDIV_CON4, 0x0000, 0xffff); //Set NCP soft start mode as default mode
1584 Ana_Set_Reg(AUDNCP_CLKDIV_CON3, 0x0000, 0xffff); //Enable NCP
1585 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0A41, 0xfeeb); //Enable cap-less HC LDO (1.5V)
1586 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC1, 0xfeeb); //Enable cap-less LC LDO (1.5V)
1587 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x8000, 0x8000); //Enable NV regulator (-1.5V)
1588 Ana_Set_Reg(ZCD_CON0, 0x0000, 0xffff); //Disable AUD_ZCD
1589
1590 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC0, 0xfeeb); //Enable IBIST
1591 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC2, 0xfeeb); //Enable AUD_CLK
1592 Ana_Set_Reg(AUDDEC_ANA_CON0, 0x0009, 0x0009); //Enable Audio DAC Lch
1593
1594 //SetDcCompenSation();
1595
1596 Ana_Set_Reg(ZCD_CON0, 0x0400, 0xffff); //Disable IVBUF_ZCD
1597 Ana_Set_Reg(ZCD_CON4, 0x0705, 0xffff); //Set 0dB IV buffer gain
1598 Ana_Set_Reg(SPK_ANA_CON3, 0x0100, 0xffff); //Set IV buffer MUX select
1599 Ana_Set_Reg(SPK_ANA_CON3, 0x0110, 0xffff); //Enable IV buffer
1600 Ana_Set_Reg(TOP_CKPDN_CON2_CLR, 0x0003, 0xffff); //Enable ClassAB/D clock
1601
1602 #ifdef CONFIG_MTK_SPEAKER
1603 if (Speaker_mode == AUDIO_SPEAKER_MODE_D)
1604 {
1605 Speaker_ClassD_Open();
1606 }
1607 else if (Speaker_mode == AUDIO_SPEAKER_MODE_AB)
1608 {
1609 Speaker_ClassAB_Open();
1610 }
1611 else if (Speaker_mode == AUDIO_SPEAKER_MODE_RECEIVER)
1612 {
1613 Speaker_ReveiverMode_Open();
1614 }
1615 #endif
1616 Apply_Speaker_Gain();
1617 }
1618 else
1619 {
1620 printk("turn off Speaker_Amp_Change \n");
1621 #ifdef CONFIG_MTK_SPEAKER
1622 if (Speaker_mode == AUDIO_SPEAKER_MODE_D)
1623 {
1624 Speaker_ClassD_close();
1625 }
1626 else if (Speaker_mode == AUDIO_SPEAKER_MODE_AB)
1627 {
1628 Speaker_ClassAB_close();
1629 }
1630 else if (Speaker_mode == AUDIO_SPEAKER_MODE_RECEIVER)
1631 {
1632 Speaker_ReveiverMode_close();
1633 }
1634 #endif
1635 Ana_Set_Reg(TOP_CKPDN_CON2_SET, 0x0003, 0xffff); //Disable ClassAB/D clock
1636 Ana_Set_Reg(SPK_ANA_CON3, 0x0, 0xffff); //Disable IV buffer, Set IV buffer MUX select open/open
1637 Ana_Set_Reg(ZCD_CON4, 0x0707, 0xffff); //Set min -2dB IV buffer gain
1638
1639 if (GetDLStatus() == false)
1640 {
1641 Ana_Set_Reg(AUDDEC_ANA_CON4, 0x0000, 0xffff); //Disable drivers bias circuit
1642 Ana_Set_Reg(AUDDEC_ANA_CON0, 0x0000, 0xffff); //Disable Audio DAC
1643 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC0, 0xfeeb); //Disable AUD_CLK, bit2/4/8 is for ADC, do not set
1644 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x0000, 0x8000); //Disable NV regulator (-1.5V)
1645 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0001, 0xfeeb); //Disable cap-less LDOs (1.5V) & Disable IBIST
1646
1647 TurnOffDacPower();
1648 }
1649 }
1650 }
1651
1652 static int Speaker_Amp_Get(struct snd_kcontrol *kcontrol,
1653 struct snd_ctl_elem_value *ucontrol)
1654 {
1655 printk("%s()\n", __func__);
1656 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_SPEAKERL] ;
1657 return 0;
1658 }
1659
1660 static int Speaker_Amp_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1661 {
1662 printk("%s() value = %ld \n ", __func__, ucontrol->value.integer.value[0]);
1663 if ((ucontrol->value.integer.value[0] == true) && (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_SPEAKERL] == false))
1664 {
1665 Speaker_Amp_Change(true);
1666 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_SPEAKERL] = ucontrol->value.integer.value[0];
1667 }
1668 else if ((ucontrol->value.integer.value[0] == false) && (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_SPEAKERL] == true))
1669 {
1670 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_SPEAKERL] = ucontrol->value.integer.value[0];
1671 Speaker_Amp_Change(false);
1672 }
1673 return 0;
1674 }
1675
1676 static unsigned int pin_extspkamp, pin_vowclk, pin_audmiso;
1677 static unsigned int pin_mode_extspkamp, pin_mode_vowclk, pin_mode_audmiso;
1678
1679 //#ifdef CONFIG_OF
1680 #if 0
1681
1682 #define GAP (2) //unit: us
1683 #define AW8736_MODE3 /*0.8w*/ \
1684 mt_set_gpio_out(pin_extspkamp,GPIO_OUT_ONE); \
1685 udelay(GAP); \
1686 mt_set_gpio_out(pin_extspkamp,GPIO_OUT_ZERO); \
1687 udelay(GAP); \
1688 mt_set_gpio_out(pin_extspkamp,GPIO_OUT_ONE); \
1689 udelay(GAP); \
1690 mt_set_gpio_out(pin_extspkamp,GPIO_OUT_ZERO); \
1691 udelay(GAP); \
1692 mt_set_gpio_out(pin_extspkamp,GPIO_OUT_ONE);
1693
1694 static void Ext_Speaker_Amp_Change(bool enable)
1695 {
1696 #define SPK_WARM_UP_TIME (25) //unit is ms
1697
1698 int ret;
1699 ret = GetGPIO_Info(5, &pin_extspkamp, &pin_mode_extspkamp);
1700 if (ret < 0)
1701 {
1702 printk("Ext_Speaker_Amp_Change GetGPIO_Info FAIL!!! \n");
1703 return;
1704 }
1705
1706 if (enable)
1707 {
1708 printk("Ext_Speaker_Amp_Change ON+ \n");
1709 #ifndef CONFIG_MTK_SPEAKER
1710 printk("Ext_Speaker_Amp_Change ON set GPIO \n");
1711 mt_set_gpio_mode(pin_extspkamp, GPIO_MODE_00); //GPIO117: DPI_D3, mode 0
1712 mt_set_gpio_pull_enable(pin_extspkamp, GPIO_PULL_ENABLE);
1713 mt_set_gpio_dir(pin_extspkamp, GPIO_DIR_OUT); // output
1714 mt_set_gpio_out(pin_extspkamp, GPIO_OUT_ZERO); // low disable
1715 udelay(1000);
1716 mt_set_gpio_dir(pin_extspkamp, GPIO_DIR_OUT); // output
1717
1718 #ifdef AW8736_MODE_CTRL
1719 AW8736_MODE3;
1720 #else
1721 mt_set_gpio_out(pin_extspkamp, GPIO_OUT_ONE); // high enable
1722 #endif
1723 msleep(SPK_WARM_UP_TIME);
1724 #endif
1725 printk("Ext_Speaker_Amp_Change ON- \n");
1726 }
1727 else
1728 {
1729 printk("Ext_Speaker_Amp_Change OFF+ \n");
1730 #ifndef CONFIG_MTK_SPEAKER
1731 //mt_set_gpio_mode(pin_extspkamp, GPIO_MODE_00); //GPIO117: DPI_D3, mode 0
1732 mt_set_gpio_dir(pin_extspkamp, GPIO_DIR_OUT); // output
1733 mt_set_gpio_out(pin_extspkamp, GPIO_OUT_ZERO); // low disbale
1734 udelay(500);
1735 #endif
1736 printk("Ext_Speaker_Amp_Change OFF- \n");
1737 }
1738 }
1739
1740 #else
1741 #ifndef CONFIG_MTK_SPEAKER
1742 #ifdef AW8736_MODE_CTRL
1743 /* 0.75us<TL<10us; 0.75us<TH<10us */
1744 #define GAP (2) //unit: us
1745 #define AW8736_MODE1 /*1.2w*/ \
1746 mt_set_gpio_out(GPIO_EXT_SPKAMP_EN_PIN,GPIO_OUT_ONE);
1747
1748 #define AW8736_MODE2 /*1.0w*/ \
1749 mt_set_gpio_out(GPIO_EXT_SPKAMP_EN_PIN,GPIO_OUT_ONE); \
1750 udelay(GAP); \
1751 mt_set_gpio_out(GPIO_EXT_SPKAMP_EN_PIN,GPIO_OUT_ZERO); \
1752 udelay(GAP); \
1753 mt_set_gpio_out(GPIO_EXT_SPKAMP_EN_PIN,GPIO_OUT_ONE);
1754
1755 #define AW8736_MODE3 /*0.8w*/ \
1756 mt_set_gpio_out(GPIO_EXT_SPKAMP_EN_PIN,GPIO_OUT_ONE); \
1757 udelay(GAP); \
1758 mt_set_gpio_out(GPIO_EXT_SPKAMP_EN_PIN,GPIO_OUT_ZERO); \
1759 udelay(GAP); \
1760 mt_set_gpio_out(GPIO_EXT_SPKAMP_EN_PIN,GPIO_OUT_ONE); \
1761 udelay(GAP); \
1762 mt_set_gpio_out(GPIO_EXT_SPKAMP_EN_PIN,GPIO_OUT_ZERO); \
1763 udelay(GAP); \
1764 mt_set_gpio_out(GPIO_EXT_SPKAMP_EN_PIN,GPIO_OUT_ONE);
1765
1766 #define AW8736_MODE4 /*it depends on THD, range: 1.5 ~ 2.0w*/ \
1767 mt_set_gpio_out(GPIO_EXT_SPKAMP_EN_PIN,GPIO_OUT_ONE); \
1768 udelay(GAP); \
1769 mt_set_gpio_out(GPIO_EXT_SPKAMP_EN_PIN,GPIO_OUT_ZERO); \
1770 udelay(GAP); \
1771 mt_set_gpio_out(GPIO_EXT_SPKAMP_EN_PIN,GPIO_OUT_ONE); \
1772 udelay(GAP); \
1773 mt_set_gpio_out(GPIO_EXT_SPKAMP_EN_PIN,GPIO_OUT_ZERO); \
1774 udelay(GAP); \
1775 mt_set_gpio_out(GPIO_EXT_SPKAMP_EN_PIN,GPIO_OUT_ONE); \
1776 udelay(GAP); \
1777 mt_set_gpio_out(GPIO_EXT_SPKAMP_EN_PIN,GPIO_OUT_ZERO); \
1778 udelay(GAP); \
1779 mt_set_gpio_out(GPIO_EXT_SPKAMP_EN_PIN,GPIO_OUT_ONE);
1780 #endif
1781 #endif
1782
1783 static void Ext_Speaker_Amp_Change(bool enable)
1784 {
1785 #define SPK_WARM_UP_TIME (25) //unit is ms
1786
1787 if (enable)
1788 {
1789 printk("Ext_Speaker_Amp_Change ON+ \n");
1790 #ifndef CONFIG_MTK_SPEAKER
1791 printk("Ext_Speaker_Amp_Change ON set GPIO \n");
1792 mt_set_gpio_mode(GPIO_EXT_SPKAMP_EN_PIN, GPIO_MODE_00); //GPIO117: DPI_D3, mode 0
1793 mt_set_gpio_pull_enable(GPIO_EXT_SPKAMP_EN_PIN, GPIO_PULL_ENABLE);
1794 mt_set_gpio_dir(GPIO_EXT_SPKAMP_EN_PIN, GPIO_DIR_OUT); // output
1795 mt_set_gpio_out(GPIO_EXT_SPKAMP_EN_PIN, GPIO_OUT_ZERO); // low disable
1796 udelay(1000);
1797 mt_set_gpio_dir(GPIO_EXT_SPKAMP_EN_PIN, GPIO_DIR_OUT); // output
1798
1799 #ifdef AW8736_MODE_CTRL
1800 AW8736_MODE3;
1801 #else
1802 mt_set_gpio_out(GPIO_EXT_SPKAMP_EN_PIN, GPIO_OUT_ONE); // high enable
1803 #endif
1804 msleep(SPK_WARM_UP_TIME);
1805 #endif
1806 printk("Ext_Speaker_Amp_Change ON- \n");
1807 }
1808 else
1809 {
1810 printk("Ext_Speaker_Amp_Change OFF+ \n");
1811 #ifndef CONFIG_MTK_SPEAKER
1812 //mt_set_gpio_mode(GPIO_EXT_SPKAMP_EN_PIN, GPIO_MODE_00); //GPIO117: DPI_D3, mode 0
1813 mt_set_gpio_dir(GPIO_EXT_SPKAMP_EN_PIN, GPIO_DIR_OUT); // output
1814 mt_set_gpio_out(GPIO_EXT_SPKAMP_EN_PIN, GPIO_OUT_ZERO); // low disbale
1815 udelay(500);
1816 #endif
1817 printk("Ext_Speaker_Amp_Change OFF- \n");
1818 }
1819 }
1820 #endif
1821
1822 static int Ext_Speaker_Amp_Get(struct snd_kcontrol *kcontrol,
1823 struct snd_ctl_elem_value *ucontrol)
1824 {
1825 printk("%s()\n", __func__);
1826 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_EXTSPKAMP] ;
1827 return 0;
1828 }
1829
1830 static int Ext_Speaker_Amp_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1831 {
1832
1833 printk("%s() gain = %ld \n ", __func__, ucontrol->value.integer.value[0]);
1834 if (ucontrol->value.integer.value[0])
1835 {
1836 Ext_Speaker_Amp_Change(true);
1837 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_EXTSPKAMP] = ucontrol->value.integer.value[0];
1838 }
1839 else
1840 {
1841 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_EXTSPKAMP] = ucontrol->value.integer.value[0];
1842 Ext_Speaker_Amp_Change(false);
1843 }
1844 return 0;
1845 }
1846
1847 static void Headset_Speaker_Amp_Change(bool enable)
1848 {
1849 if (enable)
1850 {
1851 if (GetDLStatus() == false)
1852 {
1853 TurnOnDacPower();
1854 }
1855 printk("turn on Speaker_Amp_Change \n");
1856 // here pmic analog control
1857 //set analog part (HP playback)
1858 Ana_Set_Reg(AUDNCP_CLKDIV_CON1, 0x0001, 0xffff); //Turn on DA_600K_NCP_VA18
1859 Ana_Set_Reg(AUDNCP_CLKDIV_CON2, 0x002B, 0xffff); //Set NCP clock as 604kHz // 26MHz/43 = 604KHz
1860 Ana_Set_Reg(AUDNCP_CLKDIV_CON0, 0x0001, 0xffff); //Toggle RG_DIVCKS_CHG
1861 Ana_Set_Reg(AUDNCP_CLKDIV_CON4, 0x0000, 0xffff); //Set NCP soft start mode as default mode
1862 Ana_Set_Reg(AUDNCP_CLKDIV_CON3, 0x0000, 0xffff); //Enable NCP
1863 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0A41, 0xfeeb); //Enable cap-less HC LDO (1.5V) & LDO VA33REFGEN
1864 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC1, 0xfeeb); //Enable cap-less LC LDO (1.5V)
1865 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x8000, 0x8000); //Enable NV regulator (-1.5V)
1866 Ana_Set_Reg(ZCD_CON0, 0x0000, 0xffff); //Disable AUD_ZCD
1867 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xE080, 0xffff); //Disable headphone, voice and short-ckt protection. HP MUX is opened, voice MUX is set mute
1868 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC0, 0xfeeb); //Enable IBIST
1869 Ana_Set_Reg(AUDDEC_ANA_CON4, 0x0700, 0xffff); //Enable HP & HS drivers bias circuit
1870 Ana_Set_Reg(AUDDEC_ANA_CON5, 0x5490, 0xffff); //HP/HS ibias & DR bias current optimization
1871 udelay(50);
1872 Ana_Set_Reg(ZCD_CON2, 0x0F9F, 0xffff); //Set HPR/HPL gain as minimum (~ -40dB)
1873 Ana_Set_Reg(ZCD_CON3, 0x001F, 0xffff); //Set voice gain as minimum (~ -40dB)
1874 Ana_Set_Reg(AUDDEC_ANA_CON1, 0x0480, 0xffff); //De_OSC of HP and enable output STBENH
1875 Ana_Set_Reg(AUDDEC_ANA_CON1, 0x1480, 0xffff); //De_OSC of voice, enable output STBENH
1876 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xE090, 0xffff); //Enable voice driver
1877 Ana_Set_Reg(AUDDEC_ANA_CON1, 0x14A0, 0xffff); //Enable pre-charge buffer
1878 udelay(50);
1879 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC2, 0xfeeb); //Enable AUD_CLK
1880 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xE09F, 0xffff); //Enable Audio DAC
1881
1882 //Apply digital DC compensation value to DAC
1883 Ana_Set_Reg(ZCD_CON2, 0x0489, 0xffff); //Set HPR/HPL gain to -1dB, step by step
1884 SetDcCompenSation_SPKHP();
1885 udelay(100);
1886 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xF29F, 0xffff); //R hp input mux select "Audio playback", L hp input mux select "LoudSPK playback"
1887 // here may cause pop?
1888 //msleep(1); //K2 removed
1889 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xF2FF, 0xffff); //Enable HPR/HPL
1890 udelay(50);
1891 Ana_Set_Reg(AUDDEC_ANA_CON1, 0x1480, 0xffff); //Disable pre-charge buffer
1892 Ana_Set_Reg(AUDDEC_ANA_CON1, 0x0480, 0xffff); //Disable De_OSC of voice
1893 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xF26F, 0xffff); //Disable voice buffer & Open HS input MUX
1894 Ana_Set_Reg(AUDDEC_ANA_CON4, 0x0300, 0xffff); //Disable HS drivers bias circuit
1895
1896 // ClassAB spk pmic analog control
1897 Ana_Set_Reg(ZCD_CON0, 0x0400, 0xffff); //Disable IVBUF_ZCD
1898 Ana_Set_Reg(ZCD_CON4, 0x0705, 0xffff); //Set 0dB IV buffer gain
1899 Ana_Set_Reg(SPK_ANA_CON3, 0x0100, 0xffff); //Set IV buffer MUX select
1900 Ana_Set_Reg(SPK_ANA_CON3, 0x0110, 0xffff); //Enable IV buffer
1901 Ana_Set_Reg(TOP_CKPDN_CON2_CLR, 0x0003, 0xffff); //Enable ClassAB/D clock
1902
1903 #ifdef CONFIG_MTK_SPEAKER
1904 if (Speaker_mode == AUDIO_SPEAKER_MODE_D)
1905 {
1906 Speaker_ClassD_Open();
1907 }
1908 else if (Speaker_mode == AUDIO_SPEAKER_MODE_AB)
1909 {
1910 Speaker_ClassAB_Open();
1911 }
1912 else if (Speaker_mode == AUDIO_SPEAKER_MODE_RECEIVER)
1913 {
1914 Speaker_ReveiverMode_Open();
1915 }
1916 #endif
1917 // apply volume setting
1918 HeadsetVoloumeSet();
1919 Apply_Speaker_Gain();
1920 }
1921 else
1922 {
1923 #ifdef CONFIG_MTK_SPEAKER
1924 if (Speaker_mode == AUDIO_SPEAKER_MODE_D)
1925 {
1926 Speaker_ClassD_close();
1927 }
1928 else if (Speaker_mode == AUDIO_SPEAKER_MODE_AB)
1929 {
1930 Speaker_ClassAB_close();
1931 }
1932 else if (Speaker_mode == AUDIO_SPEAKER_MODE_RECEIVER)
1933 {
1934 Speaker_ReveiverMode_close();
1935 }
1936 #endif
1937 Ana_Set_Reg(TOP_CKPDN_CON2_SET, 0x0003, 0xffff); //Disable ClassAB/D clock
1938 Ana_Set_Reg(SPK_ANA_CON3, 0x0, 0xffff); //Disable IV buffer, Set IV buffer MUX select open/open
1939 Ana_Set_Reg(ZCD_CON4, 0x0707, 0xffff); //Set min -2dB IV buffer gain
1940
1941 HeadsetVoloumeRestore();// Set HPR/HPL gain as 0dB, step by step
1942 //Ana_Set_Reg(ZCD_CON2, 0x0F9F, 0xffff); //Set HPR/HPL gain as minimum (~ -40dB)
1943 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xF20F, 0xffff); //Disable HPR/HPL
1944 if (GetDLStatus() == false)
1945 {
1946 Ana_Set_Reg(AUDDEC_ANA_CON4, 0x0000, 0xffff); //Disable drivers bias circuit
1947 Ana_Set_Reg(AUDDEC_ANA_CON0, 0x0000, 0xffff); //Disable Audio DAC
1948 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x2AC0, 0xfeeb); //Disable AUD_CLK, bit2/4/8 is for ADC, do not set
1949 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x0000, 0x8000); //Disable NV regulator (-1.5V)
1950 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0001, 0xfeeb); //Disable cap-less LDOs (1.5V) & Disable IBIST
1951
1952 TurnOffDacPower();
1953 }
1954 EnableDcCompensation(false);
1955 }
1956 }
1957
1958
1959 static int Headset_Speaker_Amp_Get(struct snd_kcontrol *kcontrol,
1960 struct snd_ctl_elem_value *ucontrol)
1961 {
1962 printk("%s()\n", __func__);
1963 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_SPEAKER_HEADSET_R] ;
1964 return 0;
1965 }
1966
1967 static int Headset_Speaker_Amp_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1968 {
1969 //struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1970
1971 printk("%s() gain = %lu \n ", __func__, ucontrol->value.integer.value[0]);
1972 if ((ucontrol->value.integer.value[0] == true) && (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_SPEAKER_HEADSET_R] == false))
1973 {
1974 Headset_Speaker_Amp_Change(true);
1975 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_SPEAKER_HEADSET_R] = ucontrol->value.integer.value[0];
1976 }
1977 else if ((ucontrol->value.integer.value[0] == false) && (mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_SPEAKER_HEADSET_R] == true))
1978 {
1979 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_OUT_SPEAKER_HEADSET_R] = ucontrol->value.integer.value[0];
1980 Headset_Speaker_Amp_Change(false);
1981 }
1982 return 0;
1983 }
1984
1985 #ifdef CONFIG_MTK_SPEAKER
1986 static const char *speaker_amp_function[] = {"CALSSD", "CLASSAB", "RECEIVER"};
1987 static const char *speaker_PGA_function[] = {"MUTE", "0Db", "4Db", "5Db", "6Db", "7Db", "8Db", "9Db", "10Db",
1988 "11Db", "12Db", "13Db", "14Db", "15Db", "16Db", "17Db"
1989 };
1990 static const char *speaker_OC_function[] = {"Off", "On"};
1991 static const char *speaker_CS_function[] = {"Off", "On"};
1992 static const char *speaker_CSPeakDetecReset_function[] = {"Off", "On"};
1993
1994 static int Audio_Speaker_Class_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1995 {
1996 mutex_lock(&Ana_Ctrl_Mutex);
1997 Speaker_mode = ucontrol->value.integer.value[0];
1998 mutex_unlock(&Ana_Ctrl_Mutex);
1999 return 0;
2000 }
2001
2002 static int Audio_Speaker_Class_Get(struct snd_kcontrol *kcontrol,
2003 struct snd_ctl_elem_value *ucontrol)
2004 {
2005 ucontrol->value.integer.value[0] = Speaker_mode ;
2006 return 0;
2007 }
2008
2009 static int Audio_Speaker_Pga_Gain_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2010 {
2011 Speaker_pga_gain = ucontrol->value.integer.value[0];
2012
2013 printk("%s Speaker_pga_gain= %d\n", __func__, Speaker_pga_gain);
2014 Ana_Set_Reg(SPK_ANA_CON0, Speaker_pga_gain << 11, 0x7800);
2015 return 0;
2016 }
2017
2018 static int Audio_Speaker_OcFlag_Get(struct snd_kcontrol *kcontrol,
2019 struct snd_ctl_elem_value *ucontrol)
2020 {
2021 mSpeaker_Ocflag = GetSpeakerOcFlag();
2022 ucontrol->value.integer.value[0] = mSpeaker_Ocflag ;
2023 return 0;
2024 }
2025
2026 static int Audio_Speaker_OcFlag_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2027 {
2028 printk("%s is not support setting \n", __func__);
2029 return 0;
2030 }
2031
2032 static int Audio_Speaker_Pga_Gain_Get(struct snd_kcontrol *kcontrol,
2033 struct snd_ctl_elem_value *ucontrol)
2034 {
2035 ucontrol->value.integer.value[0] = Speaker_pga_gain ;
2036 return 0;
2037 }
2038
2039 static int Audio_Speaker_Current_Sensing_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2040 {
2041
2042 if (ucontrol->value.integer.value[0])
2043 {
2044 Ana_Set_Reg(SPK_CON12, 0x9300, 0xff00);
2045 }
2046 else
2047 {
2048 Ana_Set_Reg(SPK_CON12, 0x1300, 0xff00);
2049 }
2050 return 0;
2051 }
2052
2053 static int Audio_Speaker_Current_Sensing_Get(struct snd_kcontrol *kcontrol,
2054 struct snd_ctl_elem_value *ucontrol)
2055 {
2056 ucontrol->value.integer.value[0] = (Ana_Get_Reg(SPK_CON12) >> 15) & 0x01;
2057 return 0;
2058 }
2059
2060 static int Audio_Speaker_Current_Sensing_Peak_Detector_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2061 {
2062
2063 if (ucontrol->value.integer.value[0])
2064 {
2065 Ana_Set_Reg(SPK_CON12, 1 << 14, 1 << 14);
2066 }
2067 else
2068 {
2069 Ana_Set_Reg(SPK_CON12, 0, 1 << 14);
2070 }
2071 return 0;
2072 }
2073
2074 static int Audio_Speaker_Current_Sensing_Peak_Detector_Get(struct snd_kcontrol *kcontrol,
2075 struct snd_ctl_elem_value *ucontrol)
2076 {
2077 ucontrol->value.integer.value[0] = (Ana_Get_Reg(SPK_CON12) >> 14) & 0x01;
2078 return 0;
2079 }
2080
2081
2082 static const struct soc_enum Audio_Speaker_Enum[] =
2083 {
2084 // speaker class setting
2085 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(speaker_amp_function), speaker_amp_function),
2086 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(speaker_PGA_function), speaker_PGA_function),
2087 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(speaker_OC_function), speaker_OC_function),
2088 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(speaker_CS_function), speaker_CS_function),
2089 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(speaker_CSPeakDetecReset_function), speaker_CSPeakDetecReset_function),
2090 };
2091
2092 static const struct snd_kcontrol_new mt6331_snd_Speaker_controls[] =
2093 {
2094 SOC_ENUM_EXT("Audio_Speaker_class_Switch", Audio_Speaker_Enum[0], Audio_Speaker_Class_Get, Audio_Speaker_Class_Set),
2095 SOC_ENUM_EXT("Audio_Speaker_PGA_gain", Audio_Speaker_Enum[1], Audio_Speaker_Pga_Gain_Get, Audio_Speaker_Pga_Gain_Set),
2096 SOC_ENUM_EXT("Audio_Speaker_OC_Falg", Audio_Speaker_Enum[2], Audio_Speaker_OcFlag_Get, Audio_Speaker_OcFlag_Set),
2097 SOC_ENUM_EXT("Audio_Speaker_CurrentSensing", Audio_Speaker_Enum[3], Audio_Speaker_Current_Sensing_Get, Audio_Speaker_Current_Sensing_Set),
2098 SOC_ENUM_EXT("Audio_Speaker_CurrentPeakDetector", Audio_Speaker_Enum[4], Audio_Speaker_Current_Sensing_Peak_Detector_Get, Audio_Speaker_Current_Sensing_Peak_Detector_Set),
2099 };
2100
2101 int Audio_AuxAdcData_Get_ext(void)
2102 {
2103 int dRetValue = PMIC_IMM_GetOneChannelValue(AUX_ICLASSAB_AP, 1, 0);
2104 printk("%s dRetValue 0x%x \n", __func__, dRetValue);
2105 return dRetValue;
2106 }
2107
2108
2109 #endif
2110
2111 static int Audio_AuxAdcData_Get(struct snd_kcontrol *kcontrol,
2112 struct snd_ctl_elem_value *ucontrol)
2113 {
2114
2115 #ifdef CONFIG_MTK_SPEAKER
2116 ucontrol->value.integer.value[0] = Audio_AuxAdcData_Get_ext();//PMIC_IMM_GetSPK_THR_IOneChannelValue(0x001B, 1, 0);
2117 #else
2118 ucontrol->value.integer.value[0] = 0;
2119 #endif
2120 printk("%s dMax = 0x%lx \n", __func__, ucontrol->value.integer.value[0]);
2121 return 0;
2122
2123 }
2124
2125 static int Audio_AuxAdcData_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2126 {
2127 dAuxAdcChannel = ucontrol->value.integer.value[0];
2128 printk("%s dAuxAdcChannel = 0x%x \n", __func__, dAuxAdcChannel);
2129 return 0;
2130 }
2131
2132
2133 static const struct snd_kcontrol_new Audio_snd_auxadc_controls[] =
2134 {
2135 SOC_SINGLE_EXT("Audio AUXADC Data", SND_SOC_NOPM, 0, 0x80000, 0, Audio_AuxAdcData_Get, Audio_AuxAdcData_Set),
2136 };
2137
2138
2139 static const char *amp_function[] = {"Off", "On"};
2140 static const char *aud_clk_buf_function[] = {"Off", "On"};
2141
2142 //static const char *DAC_SampleRate_function[] = {"8000", "11025", "16000", "24000", "32000", "44100", "48000"};
2143 static const char *DAC_DL_PGA_Headset_GAIN[] = {"8Db", "7Db", "6Db", "5Db", "4Db", "3Db", "2Db", "1Db", "0Db", "-1Db", "-2Db", "-3Db",
2144 "-4Db", "-5Db", "-6Db", "-7Db", "-8Db", "-9Db", "-10Db" , "-40Db"
2145 };
2146 static const char *DAC_DL_PGA_Handset_GAIN[] = {"8Db", "7Db", "6Db", "5Db", "4Db", "3Db", "2Db", "1Db", "0Db", "-1Db", "-2Db", "-3Db",
2147 "-4Db", "-5Db", "-6Db", "-7Db", "-8Db", "-9Db", "-10Db" , "-40Db"
2148 };
2149
2150 static const char *DAC_DL_PGA_Speaker_GAIN[] = {"8Db", "7Db", "6Db", "5Db", "4Db", "3Db", "2Db", "1Db", "0Db", "-1Db", "-2Db", "-3Db",
2151 "-4Db", "-5Db", "-6Db", "-7Db", "-8Db", "-9Db", "-10Db" , "-40Db"
2152 };
2153
2154 //static const char *Voice_Mux_function[] = {"Voice", "Speaker"};
2155
2156 static int Lineout_PGAL_Get(struct snd_kcontrol *kcontrol,
2157 struct snd_ctl_elem_value *ucontrol)
2158 {
2159 printk("Speaker_PGA_Get = %d\n", mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_SPKL]);
2160 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_SPKL];
2161 return 0;
2162 }
2163
2164 static int Lineout_PGAL_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2165 {
2166 int index = 0;
2167 printk("%s(), index = %d\n", __func__, ucontrol->value.enumerated.item[0]);
2168
2169 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(DAC_DL_PGA_Speaker_GAIN))
2170 {
2171 printk("return -EINVAL\n");
2172 return -EINVAL;
2173 }
2174 index = ucontrol->value.integer.value[0];
2175 if (ucontrol->value.enumerated.item[0] == (ARRAY_SIZE(DAC_DL_PGA_Speaker_GAIN) - 1))
2176 {
2177 index = 0x1f;
2178 }
2179 Ana_Set_Reg(ZCD_CON1, index , 0x001f);
2180 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_SPKL] = ucontrol->value.integer.value[0];
2181 return 0;
2182 }
2183
2184 static int Lineout_PGAR_Get(struct snd_kcontrol *kcontrol,
2185 struct snd_ctl_elem_value *ucontrol)
2186 {
2187 printk("%s = %d\n", __func__, mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_SPKR]);
2188 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_SPKR];
2189 return 0;
2190 }
2191
2192 static int Lineout_PGAR_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2193 {
2194 // struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
2195 int index = 0;
2196 printk("%s(), index = %d\n", __func__, ucontrol->value.enumerated.item[0]);
2197
2198 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(DAC_DL_PGA_Speaker_GAIN))
2199 {
2200 printk("return -EINVAL\n");
2201 return -EINVAL;
2202 }
2203 index = ucontrol->value.integer.value[0];
2204 if (ucontrol->value.enumerated.item[0] == (ARRAY_SIZE(DAC_DL_PGA_Speaker_GAIN) - 1))
2205 {
2206 index = 0x1f;
2207 }
2208 Ana_Set_Reg(ZCD_CON1, index << 7 , 0x0f10);
2209 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_SPKR] = ucontrol->value.integer.value[0];
2210 return 0;
2211 }
2212
2213 static int Handset_PGA_Get(struct snd_kcontrol *kcontrol,
2214 struct snd_ctl_elem_value *ucontrol)
2215 {
2216 printk("Handset_PGA_Get = %d\n", mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HSOUTL]);
2217 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HSOUTL];
2218 return 0;
2219 }
2220
2221 static int Handset_PGA_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2222 {
2223 // struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
2224 int index = 0;
2225
2226 printk("%s(), index = %d\n", __func__, ucontrol->value.enumerated.item[0]);
2227
2228 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(DAC_DL_PGA_Handset_GAIN))
2229 {
2230 printk("return -EINVAL\n");
2231 return -EINVAL;
2232 }
2233 index = ucontrol->value.integer.value[0];
2234 if (ucontrol->value.enumerated.item[0] == (ARRAY_SIZE(DAC_DL_PGA_Handset_GAIN) - 1))
2235 {
2236 index = 0x1f;
2237 }
2238 Ana_Set_Reg(ZCD_CON3, index , 0x001f);
2239 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HSOUTL] = ucontrol->value.integer.value[0];
2240 return 0;
2241 }
2242
2243 static int Headset_PGAL_Get(struct snd_kcontrol *kcontrol,
2244 struct snd_ctl_elem_value *ucontrol)
2245 {
2246 printk("Headset_PGAL_Get = %d\n", mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTL]);
2247 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTL];
2248 return 0;
2249 }
2250
2251 static int Headset_PGAL_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2252 {
2253 // struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
2254 int index = 0;
2255
2256 //printk("%s(), index = %d arraysize = %d \n", __func__, ucontrol->value.enumerated.item[0], ARRAY_SIZE(DAC_DL_PGA_Headset_GAIN)); //mark for 64bit build fail
2257
2258 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(DAC_DL_PGA_Headset_GAIN))
2259 {
2260 printk("return -EINVAL\n");
2261 return -EINVAL;
2262 }
2263 index = ucontrol->value.integer.value[0];
2264 if (ucontrol->value.enumerated.item[0] == (ARRAY_SIZE(DAC_DL_PGA_Headset_GAIN) - 1))
2265 {
2266 index = 0x1f;
2267 }
2268 Ana_Set_Reg(ZCD_CON2, index , 0x001f);
2269 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTL] = ucontrol->value.integer.value[0];
2270 return 0;
2271 }
2272
2273 static int Headset_PGAR_Get(struct snd_kcontrol *kcontrol,
2274 struct snd_ctl_elem_value *ucontrol)
2275 {
2276 printk("Headset_PGAR_Get = %d\n", mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTR]);
2277 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTR];
2278 return 0;
2279 }
2280
2281
2282 static int Headset_PGAR_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2283 {
2284 // struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
2285 int index = 0;
2286
2287 printk("%s(), index = %d\n", __func__, ucontrol->value.enumerated.item[0]);
2288
2289 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(DAC_DL_PGA_Headset_GAIN))
2290 {
2291 printk("return -EINVAL\n");
2292 return -EINVAL;
2293 }
2294 index = ucontrol->value.integer.value[0];
2295 if (ucontrol->value.enumerated.item[0] == (ARRAY_SIZE(DAC_DL_PGA_Headset_GAIN) - 1))
2296 {
2297 index = 0x1f;
2298 }
2299 Ana_Set_Reg(ZCD_CON2, index << 7, 0x0f80);
2300 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTR] = ucontrol->value.integer.value[0];
2301 return 0;
2302 }
2303
2304 static uint32 mHp_Impedance = 32;
2305
2306 static int Audio_Hp_Impedance_Get(struct snd_kcontrol *kcontrol,
2307 struct snd_ctl_elem_value *ucontrol)
2308 {
2309 printk("Audio_Hp_Impedance_Get = %d\n", mHp_Impedance);
2310 ucontrol->value.integer.value[0] = mHp_Impedance;
2311 return 0;
2312
2313 }
2314
2315 static int Audio_Hp_Impedance_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2316 {
2317 mHp_Impedance = ucontrol->value.integer.value[0];
2318 printk("%s Audio_Hp_Impedance_Set = 0x%x \n", __func__, mHp_Impedance);
2319 return 0;
2320 }
2321
2322 static int Aud_Clk_Buf_Get(struct snd_kcontrol *kcontrol,
2323 struct snd_ctl_elem_value *ucontrol)
2324 {
2325 printk("\%s n", __func__);
2326 ucontrol->value.integer.value[0] = audck_buf_Count;
2327 return 0;
2328 }
2329
2330 static int Aud_Clk_Buf_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2331 {
2332 printk("%s(), value = %d\n", __func__, ucontrol->value.enumerated.item[0]);
2333 if (ucontrol->value.integer.value[0])
2334 {
2335 audckbufEnable(true);
2336 }
2337 else
2338 {
2339 audckbufEnable(false);
2340 }
2341 return 0;
2342 }
2343
2344
2345 static const struct soc_enum Audio_DL_Enum[] =
2346 {
2347 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(amp_function), amp_function),
2348 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(amp_function), amp_function),
2349 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(amp_function), amp_function),
2350 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(amp_function), amp_function),
2351 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(amp_function), amp_function),
2352 // here comes pga gain setting
2353 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(DAC_DL_PGA_Headset_GAIN), DAC_DL_PGA_Headset_GAIN),
2354 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(DAC_DL_PGA_Headset_GAIN), DAC_DL_PGA_Headset_GAIN),
2355 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(DAC_DL_PGA_Handset_GAIN), DAC_DL_PGA_Handset_GAIN),
2356 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(DAC_DL_PGA_Speaker_GAIN), DAC_DL_PGA_Speaker_GAIN),
2357 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(DAC_DL_PGA_Speaker_GAIN), DAC_DL_PGA_Speaker_GAIN),
2358 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(aud_clk_buf_function), aud_clk_buf_function),
2359 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(amp_function), amp_function),
2360 };
2361
2362 static const struct snd_kcontrol_new mt6331_snd_controls[] =
2363 {
2364 SOC_ENUM_EXT("Audio_Amp_R_Switch", Audio_DL_Enum[0], Audio_AmpR_Get, Audio_AmpR_Set),
2365 SOC_ENUM_EXT("Audio_Amp_L_Switch", Audio_DL_Enum[1], Audio_AmpL_Get, Audio_AmpL_Set),
2366 SOC_ENUM_EXT("Voice_Amp_Switch", Audio_DL_Enum[2], Voice_Amp_Get, Voice_Amp_Set),
2367 SOC_ENUM_EXT("Speaker_Amp_Switch", Audio_DL_Enum[3], Speaker_Amp_Get, Speaker_Amp_Set),
2368 SOC_ENUM_EXT("Headset_Speaker_Amp_Switch", Audio_DL_Enum[4], Headset_Speaker_Amp_Get, Headset_Speaker_Amp_Set),
2369 SOC_ENUM_EXT("Headset_PGAL_GAIN", Audio_DL_Enum[5], Headset_PGAL_Get, Headset_PGAL_Set),
2370 SOC_ENUM_EXT("Headset_PGAR_GAIN", Audio_DL_Enum[6], Headset_PGAR_Get, Headset_PGAR_Set),
2371 SOC_ENUM_EXT("Handset_PGA_GAIN", Audio_DL_Enum[7], Handset_PGA_Get, Handset_PGA_Set),
2372 SOC_ENUM_EXT("Lineout_PGAR_GAIN", Audio_DL_Enum[8], Lineout_PGAR_Get, Lineout_PGAR_Set),
2373 SOC_ENUM_EXT("Lineout_PGAL_GAIN", Audio_DL_Enum[9], Lineout_PGAL_Get, Lineout_PGAL_Set),
2374 SOC_ENUM_EXT("AUD_CLK_BUF_Switch", Audio_DL_Enum[10], Aud_Clk_Buf_Get, Aud_Clk_Buf_Set),
2375 SOC_ENUM_EXT("Ext_Speaker_Amp_Switch", Audio_DL_Enum[11], Ext_Speaker_Amp_Get, Ext_Speaker_Amp_Set),
2376 SOC_SINGLE_EXT("Audio HP Impedance", SND_SOC_NOPM, 0, 512, 0, Audio_Hp_Impedance_Get, Audio_Hp_Impedance_Set),
2377 };
2378
2379 static const struct snd_kcontrol_new mt6331_Voice_Switch[] =
2380 {
2381 //SOC_DAPM_ENUM_EXT("Voice Mux", Audio_DL_Enum[10], Voice_Mux_Get, Voice_Mux_Set),
2382 };
2383
2384 void SetMicPGAGain(void)
2385 {
2386 int index = 0;
2387 index = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP1];
2388 Ana_Set_Reg(AUDENC_ANA_CON15, index , 0x0007);
2389 index = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP2];
2390 Ana_Set_Reg(AUDENC_ANA_CON15, index << 4, 0x0070);
2391 }
2392
2393 static bool GetAdcStatus(void)
2394 {
2395 int i = 0;
2396 for (i = AUDIO_ANALOG_DEVICE_IN_ADC1 ; i < AUDIO_ANALOG_DEVICE_MAX ; i++)
2397 {
2398 if (mCodec_data->mAudio_Ana_DevicePower[i] == true)
2399 {
2400 return true;
2401 }
2402 }
2403 return false;
2404 }
2405
2406 static bool GetDacStatus(void)
2407 {
2408 int i = 0;
2409 for (i = AUDIO_ANALOG_DEVICE_OUT_EARPIECER ; i < AUDIO_ANALOG_DEVICE_2IN1_SPK ; i++)
2410 {
2411 if (mCodec_data->mAudio_Ana_DevicePower[i] == true)
2412 {
2413 return true;
2414 }
2415 }
2416 return false;
2417 }
2418
2419
2420 static bool TurnOnADcPowerACC(int ADCType, bool enable)
2421 {
2422 bool refmic_using_ADC_L;
2423 CHIP_SW_VER ver = mt_get_chip_sw_ver();
2424 if (CHIP_SW_VER_02 <= ver)
2425 {
2426 refmic_using_ADC_L = false;
2427 }
2428 else if (CHIP_SW_VER_01 >= ver)
2429 {
2430 refmic_using_ADC_L = true;
2431 }
2432 else
2433 {
2434 refmic_using_ADC_L = false;
2435 }
2436
2437 printk("%s ADCType = %d enable = %d, ver=%d, refmic_using_ADC_L=%d \n", __func__, ADCType, enable, ver, refmic_using_ADC_L);
2438 if (enable)
2439 {
2440 //uint32 ULIndex = GetULFrequency(mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC]);
2441 uint32 SampleRate_VUL1 = mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC];
2442 //uint32 SampleRate_VUL2 = mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC_2];
2443
2444 if(GetMicbias == 0)
2445 {
2446 MicbiasRef = Ana_Get_Reg(AUDENC_ANA_CON9) & 0x0700; // save current micbias ref set by accdet
2447 printk("MicbiasRef=0x%x \n", MicbiasRef);
2448 GetMicbias = 1;
2449 }
2450 if (GetAdcStatus() == false)
2451 {
2452 audckbufEnable(true);
2453 Ana_Set_Reg(LDO_VCON1, 0x0301, 0xffff); //VA28 remote sense
2454 Ana_Set_Reg(LDO_CON2, 0x8102, 0xffff); // LDO enable control by RG_VAUD28_EN, Enable AVDD28_LDO (Default on)
2455
2456 NvregEnable(true);
2457 //ClsqAuxEnable(true);
2458 ClsqEnable(true);
2459
2460 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0004, 0x0004); //Enable audio ADC CLKGEN
2461 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0000, 0xffff); //ADC CLK from CLKGEN (13MHz)
2462 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0104, 0x0104); //Enable LCLDO_ENC 1P8V
2463 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x0006, 0x0006); //LCLDO_ENC remote sense
2464 Ana_Set_Reg(AUDENC_ANA_CON6, 0x1515, 0xffff); //default value
2465 Ana_Set_Reg(AUDENC_ANA_CON4, 0x0800, 0xffff); //default value
2466 }
2467
2468 if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC1) //main and headset mic
2469 {
2470 if (mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_1] == 0) //"ADC1", main_mic
2471 {
2472 SetDCcoupleNP(AUDIO_MIC_BIAS0, mAudio_Analog_Mic1_mode); //micbias0 DCCopuleNP
2473 //Ana_Set_Reg(AUDENC_ANA_CON9, 0x0201, 0xff09); //Enable MICBIAS0, MISBIAS0 = 1P9V
2474 Ana_Set_Reg(AUDENC_ANA_CON9, 0x0211, 0xff19); //Enable MICBIAS0, MISBIAS0 = 1P9V, also enable MICBIAS1 at the same time to avoid noise
2475 }
2476 else if (mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_1] == 1) //"ADC2", headset mic
2477 {
2478 SetDCcoupleNP(AUDIO_MIC_BIAS1, mAudio_Analog_Mic1_mode); //micbias1 DCCopuleNP
2479 Ana_Set_Reg(AUDENC_ANA_CON9, 0x0710, 0xff90); //Enable MICBIAS1, MISBIAS1 = 2P5V
2480 }
2481 Ana_Set_Reg(AUDENC_ANA_CON15, 0x0003, 0x000f); //Audio L PGA 18 dB gain(SMT)
2482 }
2483 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC2) //ref mic
2484 {
2485 SetDCcoupleNP(AUDIO_MIC_BIAS0, mAudio_Analog_Mic2_mode); //micbias0 DCCopuleNP
2486 //Ana_Set_Reg(AUDENC_ANA_CON9, 0x0201, 0xff09); //Enable MICBIAS0, MISBIAS0 = 1P9V
2487 Ana_Set_Reg(AUDENC_ANA_CON9, 0x0211, 0xff19); //Enable MICBIAS0, MISBIAS0 = 1P9V, also enable MICBIAS1 at the same time to avoid noise
2488 if (refmic_using_ADC_L == false)
2489 {
2490 Ana_Set_Reg(AUDENC_ANA_CON15, 0x0030, 0x00f0); //Audio R PGA 18 dB gain(SMT)
2491 }
2492 else
2493 {
2494 Ana_Set_Reg(AUDENC_ANA_CON15, 0x0003, 0x000f); //Audio L PGA 18 dB gain(SMT)
2495 }
2496 }
2497
2498 if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC1) //main and headset mic
2499 {
2500 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0800, 0xf900); //PGA stb enhance
2501
2502 if (mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_1] == 0) //"ADC1", main_mic
2503 {
2504 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0041, 0x00C1); //Audio L preamplifier input sel : AIN0. Enable audio L PGA
2505 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0541, 0xffff); //Audio L ADC input sel : L PGA. Enable audio L ADC
2506 }
2507 else if (mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_1] == 1) //"ADC2", headset mic
2508 {
2509 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0500, 0xffff); //Audio L ADC input sel : L PGA. Enable audio L ADC
2510 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0581, 0xffff); //Audio L preamplifier input sel : AIN1. Enable audio L PGA
2511
2512 }
2513 }
2514 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC2) //ref mic
2515 {
2516 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0800, 0xf900); //PGA stb enhance
2517 if (refmic_using_ADC_L == false)
2518 {
2519 Ana_Set_Reg(AUDENC_ANA_CON1, 0x00C1, 0x00C1); //Audio R preamplifier input sel : AIN2. Enable audio R PGA
2520 Ana_Set_Reg(AUDENC_ANA_CON1, 0x05C1, 0xffff); //Audio R ADC input sel : R PGA. Enable audio R ADC
2521 }
2522 else
2523 {
2524 Ana_Set_Reg(AUDENC_ANA_CON0, 0x00c1, 0x00C1); //Audio L preamplifier input sel : AIN2. Enable audio L PGA
2525 Ana_Set_Reg(AUDENC_ANA_CON0, 0x05c1, 0xffff); //Audio L ADC input sel : L PGA. Enable audio L ADC
2526 }
2527 }
2528
2529 SetMicPGAGain();
2530
2531 if (GetAdcStatus() == false)
2532 {
2533 //here to set digital part
2534 Topck_Enable(true);
2535 //AdcClockEnable(true);
2536 if ((GetDacStatus() == false))
2537 {
2538 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x005a, 0xffff); //power on clock
2539 }
2540 else
2541 {
2542 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0000, 0xffff); //power on clock
2543 }
2544 Ana_Set_Reg(PMIC_AFE_TOP_CON0, 0x0000, 0xffff); //configure ADC setting
2545 //Ana_Set_Reg(AFUNC_AUD_CON2, 0x0006, 0xffff); //sdm audio fifo clock power on
2546 //Ana_Set_Reg(AFUNC_AUD_CON0, 0xc3a1, 0xffff); //scrambler clock on enable
2547 //Ana_Set_Reg(AFUNC_AUD_CON2, 0x0003, 0xffff); //sdm power on
2548 //Ana_Set_Reg(AFUNC_AUD_CON2, 0x000b, 0xffff); //sdm fifo enable
2549 //Ana_Set_Reg(AFE_DL_SDM_CON1, 0x001e, 0xffff); //set attenuation gain
2550 Ana_Set_Reg(AFE_UL_DL_CON0 , 0x0001, 0xffff); //[0] afe enable
2551
2552 Ana_Set_Reg(AFE_UL_SRC0_CON0_H , (ULSampleRateTransform(SampleRate_VUL1) << 3 | ULSampleRateTransform(SampleRate_VUL1) << 1) , 0x001f); //UL sample rate and mode configure
2553 Ana_Set_Reg(AFE_UL_SRC0_CON0_L , 0x0001, 0xffff); //UL turn on
2554 }
2555 }
2556 else
2557 {
2558 if (GetAdcStatus() == false)
2559 {
2560 Ana_Set_Reg(AFE_UL_SRC0_CON0_L, 0x0000, 0xffff); //UL turn off
2561 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0020, 0x0020); //up-link power down
2562 }
2563 if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC1) //main and headset mic
2564 {
2565 if (mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_1] == 0) //"ADC1", main_mic
2566 {
2567 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0041, 0xffff); //Audio L ADC input sel : off, disable audio L ADC
2568 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0000, 0xffff); //PGA stb enhance off
2569 Ana_Set_Reg(AUDENC_ANA_CON15, 0x0000, 0x000f); //Audio L PGA 0 dB gain
2570 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0000, 0xffff); //Audio L preamplifier input sel : off, disable audio L PGA
2571 }
2572 else if (mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_1] == 1) //"ADC2", headset mic
2573 {
2574 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0500, 0xffff); //Audio L preamplifier input sel : off, disable audio L PGA
2575 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0000, 0xffff); //Audio L ADC input sel : off, disable audio L ADC
2576 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0000, 0xffff); //PGA stb enhance off
2577 Ana_Set_Reg(AUDENC_ANA_CON15, 0x0000, 0x000f); //Audio L PGA 0 dB gain
2578 }
2579
2580 Ana_Set_Reg(AUDENC_ANA_CON4, 0x0000, 0xffff); //
2581 Ana_Set_Reg(AUDENC_ANA_CON6, 0x2020, 0xffff); //
2582
2583 if (mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_1] == 0) //"ADC1", main_mic
2584 {
2585 //Ana_Set_Reg(AUDENC_ANA_CON9, (MicbiasRef|0x0000), 0xff09); //disable MICBIAS0, restore to micbias set by accdet
2586 Ana_Set_Reg(AUDENC_ANA_CON9, (MicbiasRef|0x0000), 0xff19); //disable MICBIAS0 and MICBIAS1, restore to micbias set by accdet
2587 }
2588 else if (mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_1] == 1) //"ADC2", headset mic
2589 {
2590 Ana_Set_Reg(AUDENC_ANA_CON9, (MicbiasRef|0x0000), 0xff90); //disable MICBIAS1, restore to micbias set by accdet
2591 }
2592 }
2593 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC2) //ref mic
2594 {
2595 if (refmic_using_ADC_L == false)
2596 {
2597 Ana_Set_Reg(AUDENC_ANA_CON1, 0x00C1, 0xffff); //Audio R ADC input sel : off, disable audio R ADC
2598 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0000, 0xffff); //PGA stb enhance off
2599 Ana_Set_Reg(AUDENC_ANA_CON15, 0x0000, 0x00f0); //Audio R PGA 0 dB gain
2600 Ana_Set_Reg(AUDENC_ANA_CON1, 0x0000, 0xffff); //Audio R preamplifier input sel : off, disable audio R PGA
2601 }
2602 else
2603 {
2604 Ana_Set_Reg(AUDENC_ANA_CON0, 0x00c1, 0xffff); //Audio L ADC input sel : off, disable audio L ADC
2605 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0000, 0xffff); //PGA stb enhance off
2606 Ana_Set_Reg(AUDENC_ANA_CON15, 0x0000, 0x000f); //Audio L PGA 0 dB gain
2607 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0000, 0xffff); //Audio L preamplifier input sel : off, disable audio L PGA
2608 }
2609 Ana_Set_Reg(AUDENC_ANA_CON4, 0x0000, 0xffff); //
2610 Ana_Set_Reg(AUDENC_ANA_CON6, 0x2020, 0xffff); //
2611
2612 //Ana_Set_Reg(AUDENC_ANA_CON9, (MicbiasRef|0x0000), 0xff09); //disable MICBIAS0, restore to micbias set by accdet
2613 Ana_Set_Reg(AUDENC_ANA_CON9, (MicbiasRef|0x0000), 0xff19); //disable MICBIAS0 and MICBIAS1, restore to micbias set by accdet
2614 }
2615 if (GetAdcStatus() == false)
2616 {
2617 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x0000, 0x0006); //LCLDO_ENC remote sense off
2618 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0004, 0x0104); //disable LCLDO_ENC 1P8V
2619 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0000, 0xffff); //disable ADC CLK from CLKGEN (13MHz)
2620 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0000, 0x0104); //disable audio ADC CLKGEN
2621
2622 if (GetDLStatus() == false)
2623 {
2624 Ana_Set_Reg(AFE_UL_DL_CON0, 0x0000, 0xffff); //afe disable
2625 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0084, 0x0084); //afe power down and total audio clk disable
2626 }
2627
2628 //AdcClockEnable(false);
2629 Topck_Enable(false);
2630 //ClsqAuxEnable(false);
2631 ClsqEnable(false);
2632 NvregEnable(false);
2633 audckbufEnable(false);
2634 }
2635
2636 GetMicbias = 0;
2637 }
2638 return true;
2639 }
2640
2641 static bool TurnOnADcPowerDmic(int ADCType, bool enable)
2642 {
2643 printk("%s ADCType = %d enable = %d \n", __func__, ADCType, enable);
2644 if (enable)
2645 {
2646 uint32 ULIndex = GetULFrequency(mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC]);
2647 uint32 SampleRate_VUL1 = mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC];
2648 //uint32 SampleRate_VUL2 = mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC_2];
2649
2650 if(GetMicbias == 0)
2651 {
2652 MicbiasRef = Ana_Get_Reg(AUDENC_ANA_CON9) & 0x0700; // save current micbias ref set by accdet
2653 printk("MicbiasRef=0x%x \n", MicbiasRef);
2654 GetMicbias = 1;
2655 }
2656
2657 if (GetAdcStatus() == false)
2658 {
2659 audckbufEnable(true);
2660 Ana_Set_Reg(LDO_CON2, 0x8102, 0xffff); // LDO enable control by RG_VAUD28_EN, Enable AVDD28_LDO (Default on)
2661
2662 NvregEnable(true);
2663 //ClsqAuxEnable(true);
2664 ClsqEnable(true);
2665
2666 SetDCcoupleNP(AUDIO_MIC_BIAS0, mAudio_Analog_Mic1_mode); //micbias0 DCCopuleNP
2667 //Ana_Set_Reg(AUDENC_ANA_CON9, 0x0201, 0xff09); //Enable MICBIAS0, MISBIAS0 = 1P9V
2668 Ana_Set_Reg(AUDENC_ANA_CON9, 0x0211, 0xff19); //Enable MICBIAS0 and MICBIAS1, MISBIAS0 = 1P9V
2669 Ana_Set_Reg(AUDENC_ANA_CON8, 0x0005, 0xffff); //DMIC enable
2670
2671 //here to set digital part
2672 Topck_Enable(true);
2673 //AdcClockEnable(true);
2674 if ((GetDacStatus() == false))
2675 {
2676 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x005a, 0xffff); //power on clock
2677 }
2678 else
2679 {
2680 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0000, 0xffff); //power on clock
2681 }
2682 Ana_Set_Reg(PMIC_AFE_TOP_CON0, (ULIndex << 7) | (ULIndex << 6), 0xffff); //dmic sample rate, ch1 and ch2 set to 3.25MHz 48k
2683 Ana_Set_Reg(AFE_UL_DL_CON0 , 0x0001, 0xffff); //[0] afe enable
2684
2685 Ana_Set_Reg(AFE_UL_SRC0_CON0_H , (ULSampleRateTransform(SampleRate_VUL1) << 3 | ULSampleRateTransform(SampleRate_VUL1) << 1) , 0x001f); //UL sample rate and mode configure
2686 Ana_Set_Reg(AFE_UL_SRC0_CON0_H , 0x00e0 , 0xffe0); //2-wire dmic mode, ch1 and ch2 digital mic ON
2687 Ana_Set_Reg(AFE_UL_SRC0_CON0_L , 0x0003, 0xffff); //digmic input mode 3.25MHz, select SDM 3-level mode, UL turn on
2688 }
2689 }
2690 else
2691 {
2692 if (GetAdcStatus() == false)
2693 {
2694 Ana_Set_Reg(AFE_UL_SRC0_CON0_L, 0x0000, 0xffff); //UL turn off
2695 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0020, 0x0020); //up-link power down
2696
2697 Ana_Set_Reg(AUDENC_ANA_CON8, 0x0000, 0xffff); //DMIC disable
2698
2699 //Ana_Set_Reg(AUDENC_ANA_CON9, (MicbiasRef|0x0000), 0xff09); //MICBIAS0(1.7v), powen down, restore to micbias set by accdet
2700 Ana_Set_Reg(AUDENC_ANA_CON9, (MicbiasRef|0x0000), 0xff19); //MICBIAS0(1.7v), powen down, restore to micbias set by accdet, MICBIAS1 off
2701 if (GetDLStatus() == false)
2702 {
2703 Ana_Set_Reg(AFE_UL_DL_CON0, 0x0000, 0xffff); //afe disable
2704 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0084, 0x0084); //afe power down and total audio clk disable
2705 }
2706
2707 //AdcClockEnable(false);
2708 Topck_Enable(false);
2709 //ClsqAuxEnable(false);
2710 ClsqEnable(false);
2711 NvregEnable(false);
2712 audckbufEnable(false);
2713 }
2714
2715 GetMicbias = 0;
2716 }
2717 return true;
2718 }
2719
2720 static bool TurnOnADcPowerDCC(int ADCType, bool enable)
2721 {
2722 printk("%s ADCType = %d enable = %d \n", __func__, ADCType, enable);
2723 if (enable)
2724 {
2725 //uint32 ULIndex = GetULFrequency(mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC]);
2726 uint32 SampleRate_VUL1 = mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC];
2727 //uint32 SampleRate_VUL2 = mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC_2];
2728
2729 if(GetMicbias == 0)
2730 {
2731 MicbiasRef = Ana_Get_Reg(AUDENC_ANA_CON9) & 0x0700; // save current micbias ref set by accdet
2732 printk("MicbiasRef=0x%x \n", MicbiasRef);
2733 GetMicbias = 1;
2734 }
2735
2736 if (GetAdcStatus() == false)
2737 {
2738 audckbufEnable(true);
2739 Ana_Set_Reg(LDO_VCON1, 0x0301, 0xffff); //VA28 remote sense
2740 Ana_Set_Reg(LDO_CON2, 0x8102, 0xffff); // LDO enable control by RG_VAUD28_EN, Enable AVDD28_LDO (Default on)
2741
2742 NvregEnable(true);
2743 //ClsqAuxEnable(true);
2744 ClsqEnable(true);
2745
2746 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0004, 0x0004); //Enable audio ADC CLKGEN
2747 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0000, 0xffff); //ADC CLK from CLKGEN (13MHz)
2748 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0104, 0x0104); //Enable LCLDO_ENC 1P8V
2749
2750 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x0006, 0x0006); //LCLDO_ENC remote sense
2751
2752 //DCC 50k CLK(from 26M
2753 Ana_Set_Reg(TOP_CLKSQ_SET, 0x0003, 0x0003); //
2754 Ana_Set_Reg(TOP_CKPDN_CON0, 0x0000, 0x2000); //bit[13] AUD_CK power down=0
2755
2756 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2062, 0x0002); //dcclk_div=11'b00100000011, dcclk_ref_ck_sel=2'b00
2757 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2060, 0xffff); //dcclk_pdn=1'b0
2758 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2061, 0xffff); //dcclk_gen_on=1'b1
2759 //
2760 Ana_Set_Reg(AUDENC_ANA_CON6, 0x1515, 0xffff); //default value
2761 Ana_Set_Reg(AUDENC_ANA_CON4, 0x0800, 0xffff); //default value
2762 }
2763 if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC1) //main and headset mic
2764 {
2765 if (mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_1] == 0) //"ADC1", main_mic
2766 {
2767 SetDCcoupleNP(AUDIO_MIC_BIAS0, mAudio_Analog_Mic1_mode); //micbias0 DCCopuleNP
2768 //Ana_Set_Reg(AUDENC_ANA_CON9, 0x0201, 0xff09); //Enable MICBIAS0, MISBIAS0 = 1P9V
2769 Ana_Set_Reg(AUDENC_ANA_CON9, 0x0211, 0xff19); //Enable MICBIAS0 and MICBIAS1, MISBIAS0 = 1P9V
2770 //Ana_Set_Reg(AUDENC_ANA_CON9, 0x0207, 0xff0f); //MICBIAS0 DCC SwithP/N on //DCC
2771 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0004, 0xffff); //Audio L preamplifier DCC precharge
2772 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0045, 0xffff); //Audio L preamplifier input sel : AIN0. Enable audio L PGA
2773 Ana_Set_Reg(AUDENC_ANA_CON15, 0x0002, 0x000f); //Audio L PGA 12 dB gain
2774 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0047, 0xffff); //Audio L preamplifier DCCEN
2775 }
2776 else if (mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_1] == 1) //"ADC2", headset mic
2777 {
2778 SetDCcoupleNP(AUDIO_MIC_BIAS1, mAudio_Analog_Mic1_mode); //micbias1 DCCopuleNP
2779 Ana_Set_Reg(AUDENC_ANA_CON9, 0x0710, 0xff90); //Enable MICBIAS1, MISBIAS1 = 2P5V
2780 //Ana_Set_Reg(AUDENC_ANA_CON9, 0x0770, 0xfff0); //MICBIAS1 DCC SwithP/N on //DCC
2781 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0004, 0xffff); //Audio L preamplifier DCC precharge
2782 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0085, 0xffff); //Audio L preamplifier input sel : AIN1. Enable audio L PGA
2783 Ana_Set_Reg(AUDENC_ANA_CON15, 0x0002, 0x000f); //Audio L PGA 12 dB gain
2784 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0087, 0xffff); //Audio L preamplifier DCCEN
2785 }
2786 }
2787 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC2) //ref mic
2788 {
2789 SetDCcoupleNP(AUDIO_MIC_BIAS0, mAudio_Analog_Mic2_mode); //micbias0 DCCopuleNP
2790 //Ana_Set_Reg(AUDENC_ANA_CON9, 0x0201, 0xff09); //Enable MICBIAS0, MISBIAS0 = 1P9V
2791 Ana_Set_Reg(AUDENC_ANA_CON9, 0x0211, 0xff19); //Enable MICBIAS0 and MICBIAS1, MISBIAS0 = 1P9V
2792 //Ana_Set_Reg(AUDENC_ANA_CON9, 0x0207, 0xff0f); //MICBIAS0 DCC SwithP/N on //DCC
2793 Ana_Set_Reg(AUDENC_ANA_CON1, 0x0004, 0xffff); //Audio R preamplifier DCC precharge
2794 Ana_Set_Reg(AUDENC_ANA_CON1, 0x00C5, 0xffff); //Audio R preamplifier input sel : AIN2. Enable audio R PGA
2795 Ana_Set_Reg(AUDENC_ANA_CON15, 0x0020, 0x00f0); //Audio R PGA 12 dB gain
2796 Ana_Set_Reg(AUDENC_ANA_CON1, 0x00C7, 0xffff); //Audio R preamplifier DCCEN
2797 }
2798
2799 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0800, 0xf900); //PGA stb enhance
2800
2801 if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC1) //main and headset mic
2802 {
2803
2804 if (mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_1] == 0) //"ADC1", main_mic
2805 {
2806 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0547, 0xffff); //Audio L ADC input sel : L PGA. Enable audio L ADC
2807 udelay(100);
2808 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0543, 0xffff); //Audio L preamplifier DCC precharge off
2809 }
2810 else if (mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_1] == 1) //"ADC2", headset mic
2811 {
2812 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0587, 0xffff); //Audio L ADC input sel : L PGA. Enable audio L ADC
2813 udelay(100);
2814 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0583, 0xffff); //Audio L preamplifier DCC precharge off
2815 }
2816 }
2817 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC2) //ref mic
2818 {
2819 Ana_Set_Reg(AUDENC_ANA_CON1, 0x05C7, 0xffff); //Audio R ADC input sel : R PGA. Enable audio R ADC
2820 udelay(100);
2821 Ana_Set_Reg(AUDENC_ANA_CON1, 0x05C3, 0xffff); //Audio R preamplifier DCC precharge off
2822 }
2823
2824 SetMicPGAGain();
2825
2826 if (GetAdcStatus() == false)
2827 {
2828 //here to set digital part
2829 Topck_Enable(true);
2830 //AdcClockEnable(true);
2831
2832 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0000, 0xffff); //Audio system digital clock power down release
2833 Ana_Set_Reg(PMIC_AFE_TOP_CON0, 0x0000, 0xffff); //configure ADC setting
2834 Ana_Set_Reg(AFE_UL_DL_CON0 , 0x0001, 0xffff); //[0] afe enable
2835
2836 Ana_Set_Reg(AFE_UL_SRC0_CON0_H , (ULSampleRateTransform(SampleRate_VUL1) << 3 | ULSampleRateTransform(SampleRate_VUL1) << 1) , 0x001f); //UL sample rate and mode configure
2837 Ana_Set_Reg(AFE_UL_SRC0_CON0_L , 0x0001, 0xffff); //UL turn on
2838 }
2839 }
2840 else
2841 {
2842 if (GetAdcStatus() == false)
2843 {
2844 Ana_Set_Reg(AFE_UL_SRC0_CON0_L, 0x0000, 0xffff); //UL turn off
2845 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0020, 0x0020); //up-link power down
2846 }
2847 if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC1) //main and headset mic
2848 {
2849 if (mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_1] == 0) //"ADC1", main_mic
2850 {
2851 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0043, 0xffff); //Audio L ADC input sel : off, disable audio L ADC
2852 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0000, 0xffff); //PGA stb enhance off
2853 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0041, 0xffff); //Audio L preamplifier DCCEN disable
2854 Ana_Set_Reg(AUDENC_ANA_CON15, 0x0000, 0x000f); //Audio L PGA 0 dB gain
2855 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0000, 0xffff); //Audio L preamplifier input sel : off, disable audio L PGA
2856 }
2857 else if (mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_1] == 1) //"ADC2", headset mic
2858 {
2859 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0083, 0xffff); //Audio L preamplifier input sel : off, disable audio L PGA
2860 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0000, 0xffff); //PGA stb enhance off
2861 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0081, 0xffff); //Audio L preamplifier DCCEN disable
2862 Ana_Set_Reg(AUDENC_ANA_CON15, 0x0000, 0x000f); //Audio L PGA 0 dB gain
2863 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0000, 0xffff); //Audio L ADC input sel : off, disable audio L ADC
2864 }
2865
2866 Ana_Set_Reg(AUDENC_ANA_CON4, 0x0000, 0xffff); //
2867 Ana_Set_Reg(AUDENC_ANA_CON6, 0x2020, 0xffff); //
2868
2869 if (mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_1] == 0) //"ADC1", main_mic
2870 {
2871 //Ana_Set_Reg(AUDENC_ANA_CON9, (MicbiasRef|0x0000), 0xff09); //disable MICBIAS0, restore to micbias set by accdet
2872 Ana_Set_Reg(AUDENC_ANA_CON9, (MicbiasRef|0x0000), 0xff19); //disable MICBIAS0 and MICBIAS1, restore to micbias set by accdet
2873 }
2874 else if (mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_1] == 1) //"ADC2", headset mic
2875 {
2876 Ana_Set_Reg(AUDENC_ANA_CON9, (MicbiasRef|0x0000), 0xff90); //disable MICBIAS1, restore to micbias set by accdet
2877 }
2878 }
2879 else if (ADCType == AUDIO_ANALOG_DEVICE_IN_ADC2) //ref mic
2880 {
2881 Ana_Set_Reg(AUDENC_ANA_CON1, 0x00C3, 0xffff); //Audio R ADC input sel : off, disable audio R ADC
2882 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0000, 0xffff); //PGA stb enhance off
2883 Ana_Set_Reg(AUDENC_ANA_CON1, 0x00C1, 0xffff); //Audio R preamplifier DCCEN disable
2884 Ana_Set_Reg(AUDENC_ANA_CON15, 0x0000, 0x00f0); //Audio R PGA 0 dB gain
2885 Ana_Set_Reg(AUDENC_ANA_CON1, 0x0000, 0xffff); //Audio R preamplifier input sel : off, disable audio R PGA
2886
2887 Ana_Set_Reg(AUDENC_ANA_CON4, 0x0000, 0xffff); //
2888 Ana_Set_Reg(AUDENC_ANA_CON6, 0x2020, 0xffff); //
2889 //Ana_Set_Reg(AUDENC_ANA_CON9, (MicbiasRef|0x0000), 0xff09); //disable MICBIAS0, restore to micbias set by accdet
2890 Ana_Set_Reg(AUDENC_ANA_CON9, (MicbiasRef|0x0000), 0xff19); //disable MICBIAS0 and MICBIAS1, restore to micbias set by accdet
2891 }
2892
2893 if (GetAdcStatus() == false)
2894 {
2895 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2060, 0xffff); //dcclk_gen_on=1'b0
2896 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2062, 0x0002); //dcclk_pdn=1'b0
2897
2898 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x0000, 0x0006); //LCLDO_ENC remote sense off
2899 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0004, 0x0104); //disable LCLDO_ENC 1P8V
2900 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0000, 0xffff); //disable ADC CLK from CLKGEN (13MHz)
2901 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0000, 0x0104); //disable audio ADC CLKGEN
2902
2903 if (GetDLStatus() == false)
2904 {
2905 Ana_Set_Reg(AFE_UL_DL_CON0, 0x0000, 0xffff); //afe disable
2906 Ana_Set_Reg(AFE_AUDIO_TOP_CON0, 0x0084, 0x0084); //afe power down and total audio clk disable
2907 }
2908
2909 //AdcClockEnable(false);
2910 Topck_Enable(false);
2911 //ClsqAuxEnable(false);
2912 ClsqEnable(false);
2913 NvregEnable(false);
2914 audckbufEnable(false);
2915 }
2916
2917 GetMicbias = 0;
2918 }
2919 return true;
2920 }
2921
2922
2923 static bool TurnOnADcPowerDCCECM(int ADCType, bool enable)
2924 {
2925 //use TurnOnADcPowerDCC() with SetDCcoupleNP() setting ECM or not depending on mAudio_Analog_Mic1_mode/mAudio_Analog_Mic2_mode
2926 TurnOnADcPowerDCC(ADCType, enable);
2927 return true;
2928 }
2929
2930 static bool TurnOnVOWDigitalHW(bool enable)
2931 {
2932 printk("%s enable = %d \n", __func__, enable);
2933 if (enable)
2934 {
2935 //move to vow driver
2936 #ifdef VOW_STANDALONE_CONTROL
2937 if (mAudio_VOW_Mic_type == AUDIO_VOW_MIC_TYPE_Handset_DMIC)
2938 {
2939 Ana_Set_Reg(AFE_VOW_TOP, 0x6850, 0xffff); //VOW enable
2940 }
2941 else
2942 {
2943 Ana_Set_Reg(AFE_VOW_TOP, 0x4810, 0xffff); //VOW enable
2944 }
2945 #endif
2946 }
2947 else
2948 {
2949 //disable VOW interrupt here
2950 //Ana_Set_Reg(INT_CON0, 0x0015, 0x0800); //disable VOW interrupt. BIT11
2951 #ifdef VOW_STANDALONE_CONTROL
2952 //move to vow driver
2953
2954 Ana_Set_Reg(AFE_VOW_TOP, 0x4010, 0xffff); //VOW disable
2955 Ana_Set_Reg(AFE_VOW_TOP, 0xC010, 0xffff); //VOW clock power down
2956 #endif
2957 }
2958 return true;
2959 }
2960
2961 static bool TurnOnVOWADcPowerACC(int MicType, bool enable)
2962 {
2963 int ret;
2964 printk("%s MicType = %d enable = %d, mIsVOWOn=%d, mAudio_VOW_Mic_type=%d \n", __func__, MicType, enable, mIsVOWOn, mAudio_VOW_Mic_type);
2965 //already on, no need to set again
2966 if (enable == mIsVOWOn)
2967 {
2968 return true;
2969 }
2970
2971 #ifdef CONFIG_OF
2972 ret = GetGPIO_Info(4, &pin_vowclk, &pin_mode_vowclk);
2973 if (ret < 0)
2974 {
2975 printk("TurnOnVOWADcPowerACC GetGPIO_Info FAIL1!!! \n");
2976 return false;
2977 }
2978
2979 ret = GetGPIO_Info(2, &pin_audmiso, &pin_mode_audmiso);
2980 if (ret < 0)
2981 {
2982 printk("TurnOnVOWADcPowerACC GetGPIO_Info FAIL2!!! \n");
2983 return false;
2984 }
2985 #endif
2986
2987 if (enable)
2988 {
2989 mIsVOWOn = true;
2990 SetVOWStatus(mIsVOWOn);
2991 #if defined(VOW_TONE_TEST)
2992 OpenAfeDigitaldl1(false);
2993 OpenAnalogHeadphone(false);
2994 EnableSideGenHw(Soc_Aud_InterConnectionOutput_O03, Soc_Aud_InterConnectionOutput_Num_Output, false);
2995 AudDrv_Clk_Off();
2996 #endif
2997 //uint32 ULIndex = GetULFrequency(mBlockSampleRate[AUDIO_ANALOG_DEVICE_IN_ADC]);
2998
2999 if(GetMicbias == 0)
3000 {
3001 MicbiasRef = Ana_Get_Reg(AUDENC_ANA_CON9) & 0x0700; // save current micbias ref set by accdet
3002 printk("MicbiasRef=0x%x \n", MicbiasRef);
3003 GetMicbias = 1;
3004 }
3005
3006 switch (MicType)
3007 {
3008 case AUDIO_VOW_MIC_TYPE_Headset_MIC:
3009 printk("%s, case AUDIO_VOW_MIC_TYPE_Headset_MIC \n", __func__);
3010
3011 //analog part
3012 Ana_Set_Reg(LDO_VCON1, 0x0301, 0x0200); //VA28 remote sense, only set bit9, RG_VAUD28_SENSE_SEL
3013 Ana_Set_Reg(LDO_CON2, 0x8103, 0x000f); // LDO enable control by RG_VAUD28_EN, Enable AVDD28_LDO (Default on), LPW control by VAUD28_MODE_SET Enable low power mode. bit0~3
3014 Ana_Set_Reg(AUDENC_ANA_CON2, 0x0003, 0x0003); //Enable audio uplink VOW LPW globe bias, Enable audio uplink LPW mode. bit0~1
3015 Ana_Set_Reg(AUDENC_ANA_CON12, 0x0409, 0x040D); //Enable fbdiv relatch (low jitter), Set DCKO = 1/4 F_PLL, Enable VOWPLL CLK. bit:0,2,3,10
3016 Ana_Set_Reg(AUDENC_ANA_CON14, 0x0000, 0x0038); //PLL VCOBAND. bit5:3
3017 Ana_Set_Reg(AUDENC_ANA_CON12, 0x06F9, 0x03f0); //PLL devider ratio. bit9:4
3018 Ana_Set_Reg(AUDENC_ANA_CON13, 0x8180, 0x8000); //PLL low power. bit:15
3019 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0009, 0x000D); //ADC CLK from VOWPLL (12.85/4MHz), Enable Audio ADC FBDAC 0.25FS LPW. BIT0,2,3
3020 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0100, 0x0100); //Enable LCLDO_ENC 1P8V. BIT8
3021 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x0006, 0x0006); //LCLDO_ENC remote sense.BIT1,2
3022 Ana_Set_Reg(AUDENC_ANA_CON6, 0x1515, 0xffff);
3023 Ana_Set_Reg(AUDENC_ANA_CON4, 0x0800, 0x0800);//BIT11
3024 Ana_Set_Reg(AUDENC_ANA_CON9, 0x0F10, 0x0f10); //Enable MICBIAS1 lowpower mode, MISBIAS1 = 2P5V.BIT4,10~8,11
3025 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0081, 0x00C1); //Audio L preamplifier input sel : AIN0, Enable audio L PGA. BIT0,7:6
3026 Ana_Set_Reg(AUDENC_ANA_CON15, 0x0003, 0x0007); //Audio L PGA 18 dB gain. BIT:2:0
3027 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0809, 0xf900); //PGA stb enhance. BIT:8,15:11
3028 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0581, 0x0500); //Audio L ADC input sel : L PGA, Enable audio L ADC.BIT:8,9,10
3029
3030 //here to set digital part
3031 //Ana_Set_Reg(TOP_CKPDN_CON0, 0x6EFC, 0xffff); //VOW clock power down disable
3032 VOW12MCK_Enable(true);
3033
3034 //need to enable VOW interrpt
3035 //Ana_Set_Reg(INT_CON0, 0x0815, 0x0800); //enable VOW interrupt. BIT:11
3036 //set GPIO
3037 //AP side
3038 #ifdef MTK_VOW_SUPPORT
3039 #ifdef CONFIG_OF
3040 //Enable VOW_CLK_MISO
3041 mt_set_gpio_mode(pin_vowclk, GPIO_MODE_01); //GPIO148: mode 1
3042 //Enable VOW_DAT_MISO
3043 mt_set_gpio_mode(pin_audmiso, GPIO_MODE_02); //GPIO25: mode 2
3044 #else
3045 //Enable VOW_CLK_MISO
3046 mt_set_gpio_mode(GPIO_VOW_CLK_MISO_PIN, GPIO_MODE_01); //GPIO148: mode 1
3047 //Enable VOW_DAT_MISO
3048 mt_set_gpio_mode(GPIO_AUD_DAT_MISO_PIN, GPIO_MODE_02); //GPIO25: mode 2
3049 #endif
3050 #endif
3051 //set PMIC GPIO
3052 Ana_Set_Reg(GPIO_MODE3, 0x1251, 0xffff); //GPIO Set to VOW data
3053
3054 break;
3055
3056 case AUDIO_VOW_MIC_TYPE_Handset_DMIC:
3057 case AUDIO_VOW_MIC_TYPE_Handset_DMIC_800K:
3058 printk("%s, case AUDIO_VOW_MIC_TYPE_Handset_DMIC \n", __func__);
3059
3060 //analog part
3061 Ana_Set_Reg(LDO_CON2, 0x8103, 0x000f); // LDO enable control by RG_VAUD28_EN, Enable AVDD28_LDO (Default on), LPW control by VAUD28_MODE_SET Enable low power mode. bit0~3
3062 Ana_Set_Reg(AUDENC_ANA_CON12, 0x0719, 0x040D); //Enable fbdiv relatch (low jitter), Set DCKO = 1/4 F_PLL, Enable VOWPLL CLK. bit:0,2,3,10
3063 Ana_Set_Reg(AUDENC_ANA_CON14, 0x0000, 0x0038); //PLL VCOBAND. bit5:3
3064 Ana_Set_Reg(AUDENC_ANA_CON12, 0x06F9, 0x03f0); //PLL devider ratio. bit9:4
3065 Ana_Set_Reg(AUDENC_ANA_CON13, 0x8180, 0x8000); //PLL low power. bit:15
3066 //no need to config this reg due to VOW no need
3067 //NvregEnable(false); //Disable audio globe bias (Default on)
3068 Ana_Set_Reg(AUDENC_ANA_CON2, 0x0002, 0x0002); //Enable audio uplink VOW LPW globe bias. BIT1
3069 Ana_Set_Reg(AUDENC_ANA_CON9, 0x0A01, 0x0F01); //Enable MICBIAS0 lowpower mode, MISBIAS0 = 1P9V..BIT0,10~8,11
3070 Ana_Set_Reg(AUDENC_ANA_CON8, 0x0005, 0x0007); //DMIC enable.BIT0~2
3071
3072 //here to set digital part
3073 //Ana_Set_Reg(TOP_CKPDN_CON0, 0x6EFC, 0xffff); //VOW clock power down disable
3074 VOW12MCK_Enable(true);
3075
3076 //need to enable VOW interrpt
3077 //Ana_Set_Reg(INT_CON0, 0x0815, 0x0800); //enable VOW interrupt. BIT:11
3078 //set GPIO
3079 #ifdef MTK_VOW_SUPPORT
3080 #ifdef CONFIG_OF
3081 //Enable VOW_CLK_MISO
3082 mt_set_gpio_mode(pin_vowclk, GPIO_MODE_01); //GPIO148: mode 1
3083 //Enable VOW_DAT_MISO
3084 mt_set_gpio_mode(pin_audmiso, GPIO_MODE_02); //GPIO25: mode 2
3085
3086 #else
3087 //Enable VOW_CLK_MISO
3088 mt_set_gpio_mode(GPIO_VOW_CLK_MISO_PIN, GPIO_MODE_01); //GPIO148: mode 1
3089 //Enable VOW_DAT_MISO
3090 mt_set_gpio_mode(GPIO_AUD_DAT_MISO_PIN, GPIO_MODE_02); //GPIO25: mode 2
3091 #endif
3092 #endif
3093 //set PMIC GPIO
3094 Ana_Set_Reg(GPIO_MODE3, 0x1251, 0xffff); //GPIO Set to VOW data
3095
3096 break;
3097 case AUDIO_VOW_MIC_TYPE_Handset_AMIC_DCC:
3098 case AUDIO_VOW_MIC_TYPE_Handset_AMIC_DCCECM:
3099 printk("%s, case AUDIO_VOW_MIC_TYPE_Handset_AMIC_DCC \n", __func__);
3100
3101 //analog part
3102 Ana_Set_Reg(LDO_VCON1, 0x0200, 0x0200); //VA28 remote sense, only set bit9, RG_VAUD28_SENSE_SEL
3103 Ana_Set_Reg(LDO_CON2, 0x0003, 0x000f); // LDO enable control by RG_VAUD28_EN, Enable AVDD28_LDO (Default on), LPW control by VAUD28_MODE_SET Enable low power mode. bit0~3
3104 Ana_Set_Reg(AUDENC_ANA_CON2, 0x0003, 0x0003); //Enable audio uplink VOW LPW globe bias, Enable audio uplink LPW mode. bit0~1
3105 Ana_Set_Reg(AUDENC_ANA_CON12, 0x0409, 0x040D); //Enable fbdiv relatch (low jitter), Set DCKO = 1/4 F_PLL, Enable VOWPLL CLK. bit:0,2,3,10
3106 Ana_Set_Reg(AUDENC_ANA_CON14, 0x0000, 0x0038); //PLL VCOBAND. bit5:3
3107 Ana_Set_Reg(AUDENC_ANA_CON12, 0x06F9, 0x03f0); //PLL devider ratio. bit9:4
3108 Ana_Set_Reg(AUDENC_ANA_CON13, 0x8180, 0x8000); //PLL low power. bit:15
3109
3110 //DCC 50k CLK
3111 VOW12MCK_Enable(true);
3112
3113 Ana_Set_Reg(AFE_VOW_TOP, 0x4000, 0x8000); //pdn_vow=1'b0.BIT15
3114 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2062, 0xffff);
3115 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2066, 0xffff);
3116 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2064, 0xffff);
3117 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2065, 0xffff);
3118
3119 Ana_Set_Reg(AUDENC_ANA_CON6, 0x1515, 0xffff);
3120 Ana_Set_Reg(AUDENC_ANA_CON4, 0x0800, 0x0800);//BIT11
3121 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0009, 0x000D); //ADC CLK from VOWPLL (12.85/4MHz), Enable Audio ADC FBDAC 0.25FS LPW.BIT0,2,3
3122 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0100, 0x0100); //Enable LCLDO_ENC 1P8V
3123 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x0006, 0x0006); //LCLDO_ENC remote sense
3124 Ana_Set_Reg(AUDENC_ANA_CON9, 0x0A01, 0x0f01); //Enable MICBIAS0 lowpower mode, MISBIAS0 = 1P9V.BIT0,10~8,11
3125 //Ana_Set_Reg(AUDENC_ANA_CON9, 0x0A07, 0xffff); //MICBIAS0 DCC SwithP/N on
3126 if (MicType == AUDIO_VOW_MIC_TYPE_Handset_AMIC_DCCECM) //ECM dual diff mode
3127 {
3128 Ana_Set_Reg(AUDENC_ANA_CON9, 0x0A07, 0x0006); //MICBIAS0 DCC SwithP/N on.BIT1,2
3129 }
3130 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0004, 0x0004); //Audio L preamplifier DCC precharge.BIT2
3131 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0045, 0x00C1); //Audio L preamplifier input sel : AIN0,Enable audio L PGA.BIT0,6,7
3132 Ana_Set_Reg(AUDENC_ANA_CON15, 0x0003, 0x0007); //Audio L PGA 18 dB gain.BIT0~2
3133 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0047, 0x0002); //Audio L preamplifier DCCEN.BIT1
3134 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0809, 0xf800); //PGA stb enhance. BIT11~15
3135 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0547, 0x0700); //Audio L ADC input sel : L PGA, Enable audio L ADC.BIT8,9,10
3136 //delay 100us
3137 msleep(1);
3138 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0543, 0x0004); //Audio L preamplifier DCC precharge off. BIT2=0
3139
3140 //here set digital part
3141
3142 //need to enable VOW interrpt
3143 //Ana_Set_Reg(INT_CON0, 0x0815, 0x0800); //enable VOW interrupt. BIT:11
3144 //set GPIO
3145 //AP side
3146 #ifdef MTK_VOW_SUPPORT
3147 #ifdef CONFIG_OF
3148 //Enable VOW_CLK_MISO
3149 mt_set_gpio_mode(pin_vowclk, GPIO_MODE_01); //GPIO148: mode 1
3150 //Enable VOW_DAT_MISO
3151 mt_set_gpio_mode(pin_audmiso, GPIO_MODE_02); //GPIO25: mode 2
3152
3153 #else
3154 //Enable VOW_CLK_MISO
3155 mt_set_gpio_mode(GPIO_VOW_CLK_MISO_PIN, GPIO_MODE_01); //GPIO148: mode 1
3156 //Enable VOW_DAT_MISO
3157 mt_set_gpio_mode(GPIO_AUD_DAT_MISO_PIN, GPIO_MODE_02); //GPIO25: mode 2
3158 #endif
3159 #endif
3160 //set PMIC GPIO
3161 Ana_Set_Reg(GPIO_MODE3, 0x1251, 0xffff); //GPIO Set to VOW data
3162
3163 break;
3164
3165 case AUDIO_VOW_MIC_TYPE_Headset_MIC_DCC:
3166 case AUDIO_VOW_MIC_TYPE_Headset_MIC_DCCECM:
3167 printk("%s, case AUDIO_VOW_MIC_TYPE_Headset_MIC_DCC \n", __func__);
3168
3169 //analog part
3170 Ana_Set_Reg(LDO_VCON1, 0x0200, 0x0200); //VA28 remote sense, only set bit9, RG_VAUD28_SENSE_SEL
3171 Ana_Set_Reg(LDO_CON2, 0x0003, 0x000f); // LDO enable control by RG_VAUD28_EN, Enable AVDD28_LDO (Default on), LPW control by VAUD28_MODE_SET Enable low power mode. bit0~3
3172 Ana_Set_Reg(AUDENC_ANA_CON2, 0x0003, 0x0003); //Enable audio uplink VOW LPW globe bias, Enable audio uplink LPW mode. bit0~1
3173 Ana_Set_Reg(AUDENC_ANA_CON12, 0x0409, 0x040D); //Enable fbdiv relatch (low jitter), Set DCKO = 1/4 F_PLL, Enable VOWPLL CLK. bit:0,2,3,10
3174 Ana_Set_Reg(AUDENC_ANA_CON14, 0x0000, 0x0038); //PLL VCOBAND. bit5:3
3175 Ana_Set_Reg(AUDENC_ANA_CON12, 0x06F9, 0x03f0); //PLL devider ratio. bit9:4
3176 Ana_Set_Reg(AUDENC_ANA_CON13, 0x8180, 0x8000); //PLL low power. bit:15
3177
3178 //DCC 50k CLK
3179 VOW12MCK_Enable(true);
3180
3181
3182 Ana_Set_Reg(AFE_VOW_TOP, 0x4000, 0x8000); //pdn_vow=1'b0.BIT15
3183 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2062, 0xffff);
3184 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2066, 0xffff);
3185 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2064, 0xffff);
3186 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2065, 0xffff);
3187
3188
3189 Ana_Set_Reg(AUDENC_ANA_CON6, 0x1515, 0xffff);
3190 Ana_Set_Reg(AUDENC_ANA_CON4, 0x0800, 0x0800);//BIT11
3191 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0009, 0x000D); //ADC CLK from VOWPLL (12.85/4MHz), Enable Audio ADC FBDAC 0.25FS LPW.BIT0,2,3
3192 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0100, 0x0100); //Enable LCLDO_ENC 1P8V
3193 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x0006, 0x0006); //LCLDO_ENC remote sense
3194 Ana_Set_Reg(AUDENC_ANA_CON9, 0x0F10, 0x0f10); //Enable MICBIAS1 lowpower mode, MISBIAS1 = 2P5V.BIT:4,8:11
3195
3196 if (MicType == AUDIO_VOW_MIC_TYPE_Headset_MIC_DCCECM)
3197 {
3198 Ana_Set_Reg(AUDENC_ANA_CON9, 0x0F20, 0x0060); //MICBIAS1 DCC ECM single SwithP/N on(P:1,N:0). BIT5,6
3199 }
3200 //Ana_Set_Reg(AUDENC_ANA_CON9, 0x0F70, 0xffff); //MICBIAS1 DCC SwithP/N on
3201 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0004, 0x0004); //Audio L preamplifier DCC precharge.BIT2
3202 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0045, 0x00C1); //Audio L preamplifier input sel : AIN0,Enable audio L PGA.BIT0,6,7
3203 Ana_Set_Reg(AUDENC_ANA_CON15, 0x0003, 0x0007); //Audio L PGA 18 dB gain.BIT0~2
3204 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0047, 0x0002); //Audio L preamplifier DCCEN.BIT1
3205 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0809, 0xf800); //PGA stb enhance. BIT11~15
3206 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0547, 0x0700); //Audio L ADC input sel : L PGA, Enable audio L ADC.BIT8,9,10
3207 //delay 100us
3208 msleep(1);
3209 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0543, 0x0004); //Audio L preamplifier DCC precharge off. BIT2=0
3210
3211
3212 //here set digital part
3213 VOW12MCK_Enable(true);
3214
3215 //need to enable VOW interrpt
3216 //Ana_Set_Reg(INT_CON0, 0x0815, 0x0800); //enable VOW interrupt. BIT:11
3217 //set GPIO
3218 //AP side
3219 #ifdef MTK_VOW_SUPPORT
3220 #ifdef CONFIG_OF
3221 //Enable VOW_CLK_MISO
3222 mt_set_gpio_mode(pin_vowclk, GPIO_MODE_01); //GPIO148: mode 1
3223 //Enable VOW_DAT_MISO
3224 mt_set_gpio_mode(pin_audmiso, GPIO_MODE_02); //GPIO25: mode 2
3225
3226 #else
3227 //Enable VOW_CLK_MISO
3228 mt_set_gpio_mode(GPIO_VOW_CLK_MISO_PIN, GPIO_MODE_01); //GPIO148: mode 1
3229 //Enable VOW_DAT_MISO
3230 mt_set_gpio_mode(GPIO_AUD_DAT_MISO_PIN, GPIO_MODE_02); //GPIO25: mode 2
3231 #endif
3232 #endif
3233 //set PMIC GPIO
3234 Ana_Set_Reg(GPIO_MODE3, 0x1251, 0xffff); //GPIO Set to VOW data
3235
3236 break;
3237
3238 case AUDIO_VOW_MIC_TYPE_Handset_AMIC:
3239 default:
3240 printk("%s, case AUDIO_VOW_MIC_TYPE_Handset_AMIC \n", __func__);
3241
3242 //analog part
3243 Ana_Set_Reg(LDO_VCON1, 0x0200, 0x0200); //VA28 remote sense, only set bit9, RG_VAUD28_SENSE_SEL
3244 Ana_Set_Reg(LDO_CON2, 0x0003, 0x000f); // LDO enable control by RG_VAUD28_EN, Enable AVDD28_LDO (Default on), LPW control by VAUD28_MODE_SET Enable low power mode. bit0~3
3245 Ana_Set_Reg(AUDENC_ANA_CON2, 0x0003, 0x0003); //Enable audio uplink VOW LPW globe bias, Enable audio uplink LPW mode. bit0~1
3246 Ana_Set_Reg(AUDENC_ANA_CON12, 0x0409, 0x040D); //Enable fbdiv relatch (low jitter), Set DCKO = 1/4 F_PLL, Enable VOWPLL CLK. bit:0,2,3,10
3247 Ana_Set_Reg(AUDENC_ANA_CON14, 0x0000, 0x0038); //PLL VCOBAND. bit5:3
3248 Ana_Set_Reg(AUDENC_ANA_CON12, 0x06F9, 0x03f0); //PLL devider ratio. bit9:4
3249 Ana_Set_Reg(AUDENC_ANA_CON13, 0x8180, 0x8000); //PLL low power. bit:15
3250 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0009, 0x000D); //ADC CLK from VOWPLL (12.85/4MHz), Enable Audio ADC FBDAC 0.25FS LPW. BIT0,2,3
3251 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0100, 0x0100); //Enable LCLDO_ENC 1P8V
3252 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x0006, 0x0006); //LCLDO_ENC remote sense
3253 Ana_Set_Reg(AUDENC_ANA_CON6, 0x1515, 0xffff);
3254 Ana_Set_Reg(AUDENC_ANA_CON4, 0x0800, 0x0800);//BIT11
3255 Ana_Set_Reg(AUDENC_ANA_CON9, 0x0A01, 0x0f01); //Enable MICBIAS0 lowpower mode, MISBIAS0 = 1P9V.BIT0,10~8,11
3256 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0041, 0x00C1); //Audio L preamplifier input sel : AIN0, Enable audio L PGA. BIT0,7:6
3257 Ana_Set_Reg(AUDENC_ANA_CON15, 0x0003, 0x0007); //Audio L PGA 18 dB gain. BIT:2:0
3258 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0809, 0xf900); //PGA stb enhance. BIT:8,15:11
3259 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0541, 0x0500); //Audio L ADC input sel : L PGA, Enable audio L ADC.BIT:8,9,10
3260
3261 //here to set digital part
3262 //Ana_Set_Reg(TOP_CKPDN_CON0, 0x6EFC, 0xffff); //VOW clock power down disable
3263 VOW12MCK_Enable(true);
3264
3265 //need to enable VOW interrpt
3266 //Ana_Set_Reg(INT_CON0, 0x0815, 0x0800); //enable VOW interrupt. BIT:11
3267 //set GPIO
3268 //AP side
3269 #ifdef MTK_VOW_SUPPORT
3270 #ifdef CONFIG_OF
3271 //Enable VOW_CLK_MISO
3272 mt_set_gpio_mode(pin_vowclk, GPIO_MODE_01); //GPIO148: mode 1
3273 //Enable VOW_DAT_MISO
3274 mt_set_gpio_mode(pin_audmiso, GPIO_MODE_02); //GPIO25: mode 2
3275
3276 #else
3277 //Enable VOW_CLK_MISO
3278 mt_set_gpio_mode(GPIO_VOW_CLK_MISO_PIN, GPIO_MODE_01); //GPIO148: mode 1
3279 //Enable VOW_DAT_MISO
3280 mt_set_gpio_mode(GPIO_AUD_DAT_MISO_PIN, GPIO_MODE_02); //GPIO25: mode 2
3281 #endif
3282 #endif
3283 //set PMIC GPIO
3284 Ana_Set_Reg(GPIO_MODE3, 0x1251, 0xffff); //GPIO Set to VOW data
3285
3286 break;
3287 }
3288
3289 //[Todo]Enable VOW INT (has alredy done in pmic.c)
3290 //enable VOW INT in pmic driver
3291 //~
3292 #if 1 //Set by HAL
3293 //Ana_Set_Reg(AFE_VOW_CFG0, reg_AFE_VOW_CFG0, 0xffff); //VOW AMPREF Setting, set by MD32 after DC calibration
3294 Ana_Set_Reg(AFE_VOW_CFG1, reg_AFE_VOW_CFG1, 0xffff); //VOW A,B timeout initial value
3295 if (MicType == AUDIO_VOW_MIC_TYPE_Handset_DMIC) //1p6M
3296 {
3297 Ana_Set_Reg(AFE_VOW_POSDIV_CFG0, 0x0B00, 0xffff);
3298 }
3299 else if (MicType == AUDIO_VOW_MIC_TYPE_Handset_DMIC_800K)
3300 {
3301 Ana_Set_Reg(AFE_VOW_POSDIV_CFG0, 0x0B08, 0xffff);
3302 }
3303 Ana_Set_Reg(AFE_VOW_CFG2, reg_AFE_VOW_CFG2, 0xffff); //VOW A,B value setting
3304 Ana_Set_Reg(AFE_VOW_CFG3, reg_AFE_VOW_CFG3, 0xffff); //alhpa and beta K value setting
3305 Ana_Set_Reg(AFE_VOW_CFG4, reg_AFE_VOW_CFG4, 0xffff); //gamma K value setting
3306 Ana_Set_Reg(AFE_VOW_CFG5, reg_AFE_VOW_CFG5, 0xffff); //N mini value setting
3307 #endif
3308
3309 #ifndef VOW_STANDALONE_CONTROL
3310 if (MicType == AUDIO_VOW_MIC_TYPE_Handset_DMIC)
3311 {
3312 //digital MIC need to config bit13 and bit6, (bit7 need to check) 0x6840
3313 //Ana_Set_Reg(AFE_VOW_TOP, 0x2040, 0x2040); //VOW enable
3314 #if defined (MTK_VOW_SUPPORT)
3315 VowDrv_SetDmicLowPower(false);
3316 #endif
3317 Ana_Set_Reg(AFE_VOW_TOP, 0x20C0, 0x20C0); //VOW enable, with bit7
3318 }
3319 else if (MicType == AUDIO_VOW_MIC_TYPE_Handset_DMIC_800K)
3320 {
3321 #if defined (MTK_VOW_SUPPORT)
3322 VowDrv_SetDmicLowPower(true);
3323 #endif
3324 Ana_Set_Reg(AFE_VOW_TOP, 0x20C0, 0x20C0); //VOW enable, with bit7
3325 }
3326 //others setting will do at VOW driver 0x4800
3327 else
3328 {
3329 #if defined (MTK_VOW_SUPPORT)
3330 VowDrv_SetDmicLowPower(false);
3331 #endif
3332 //Ana_Set_Reg(AFE_VOW_TOP, 0x4810, 0xffff); //VOW enable
3333 }
3334 #endif
3335
3336 #if defined (MTK_VOW_SUPPORT)
3337 //VOW enable, set AFE_VOW_TOP in VOW kernel driver
3338 //need to inform VOW driver mic type
3339 VowDrv_EnableHW(true);
3340 printk("%s, VowDrv_ChangeStatus set\n", __func__);
3341 VowDrv_ChangeStatus();
3342 #endif
3343
3344 #if defined(VOW_TONE_TEST)
3345 //test output
3346 AudDrv_Clk_On();
3347 OpenAfeDigitaldl1(true);
3348 OpenAnalogHeadphone(true);
3349 #endif
3350
3351 }
3352 else
3353 {
3354 #if defined (MTK_VOW_SUPPORT)
3355 //Set VOW driver disable, vow driver will do close all digital part setting
3356 VowDrv_EnableHW(false);
3357 printk("%s, VowDrv_ChangeStatus set\n", __func__);
3358 VowDrv_ChangeStatus();
3359 msleep(10);
3360 #endif
3361 switch (MicType)
3362 {
3363 case AUDIO_VOW_MIC_TYPE_Headset_MIC:
3364 printk("%s, case AUDIO_VOW_MIC_TYPE_Headset_MIC close\n", __func__);
3365
3366 // turn off digital first, move to vow driver
3367 //#ifdef VOW_STANDALONE_CONTROL
3368 #if 1
3369 //disable VOW interrupt here or when digital power off
3370
3371 #ifdef MTK_VOW_SUPPORT
3372 #ifdef CONFIG_OF
3373 //Enable VOW_CLK_MISO
3374 mt_set_gpio_mode(pin_vowclk, GPIO_MODE_00); //GPIO148: mode 0
3375 //Enable VOW_DAT_MISO
3376 mt_set_gpio_mode(pin_audmiso, GPIO_MODE_01); //GPIO25: mode 1
3377
3378 #else
3379 //GPIO set to back to normal record
3380 //disable VOW_CLK_MISO
3381 mt_set_gpio_mode(GPIO_VOW_CLK_MISO_PIN, GPIO_MODE_00); //GPIO148: mode 0
3382
3383 mt_set_gpio_mode(GPIO_AUD_DAT_MISO_PIN, GPIO_MODE_01); //GPIO25: mode 1
3384 #endif
3385 #endif
3386 //set PMIC GPIO
3387 Ana_Set_Reg(GPIO_MODE3, 0x1249, 0xffff); //GPIO Set to VOW data
3388 #endif
3389 VOW12MCK_Enable(false);//VOW clock power down enable
3390
3391 //turn off analog part
3392 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0500, 0x00C1); //Audio L preamplifier input sel : off, disable audio L PGA. BIT:0,6,7
3393 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0000, 0x0700); //Audio L ADC input sel : off, disable audio L ADC.BIT:8,9,10
3394 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0009, 0xf900); //PGA stb enhance off,BIT:8,15:11
3395 Ana_Set_Reg(AUDENC_ANA_CON15, 0x0000, 0x0007); //Audio L PGA 0 dB gain,BIT:0~2
3396 Ana_Set_Reg(AUDENC_ANA_CON4, 0x0000, 0x0800); //BIT11
3397 Ana_Set_Reg(AUDENC_ANA_CON6, 0x2020, 0xffff);
3398
3399 Ana_Set_Reg(AUDENC_ANA_CON9, (MicbiasRef|0x0000), 0x0f01); //disable MICBIAS0 lowpower mode, MISBIAS0 = 1P7V. BIT:0,8:10,11
3400 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x0000, 0x0006); //LCLDO_ENC remote sense off, BIT:1,2
3401 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0000, 0x0100); //disable LCLDO_ENC 1P8V
3402 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0000, 0x000D); //ADC CLK from VOWPLL (12.85/4MHz) off, Enable Audio ADC FBDAC 0.25FS LPW off. BIT:0,2,3
3403 Ana_Set_Reg(AUDENC_ANA_CON13, 0x0180, 0x8000); //PLL low power off. BIT:15
3404 Ana_Set_Reg(AUDENC_ANA_CON12, 0x02F0, 0x040D); //disable fbdiv relatch (low jitter),Set DCKO = 1/4 F_PLL off, disable VOWPLL CLK. BIT:0,2,3,10
3405 Ana_Set_Reg(AUDENC_ANA_CON2, 0x0000, 0x0003); //disable audio uplink VOW LPW globe bias, disable audio uplink LPW mode.BIT:0,1
3406 //Ana_Set_Reg(AUDDEC_ANA_CON8, 0x0000, 0xffff); //enable audio globe bias (Default on)
3407 //no need to config this reg due to VOW no need
3408 //NvregEnable(true); //enable audio globe bias (Default on)
3409 Ana_Set_Reg(LDO_CON2, 0x8102, 0x000f); //LDO enable control by RG_VAUD28_EN, Enable AVDD28_LDO (Default on), LPW control by VAUD28_MODE_SET, disable low power mode.BIT:0~3
3410
3411 break;
3412
3413 case AUDIO_VOW_MIC_TYPE_Handset_DMIC:
3414 case AUDIO_VOW_MIC_TYPE_Handset_DMIC_800K:
3415 printk("%s, case AUDIO_VOW_MIC_TYPE_Handset_DMIC close\n", __func__);
3416
3417 // turn off digital first, move to vow driver
3418 //#ifdef VOW_STANDALONE_CONTROL
3419 #if 1
3420 //disable VOW interrupt here or when digital power off
3421
3422 #ifdef MTK_VOW_SUPPORT
3423 #ifdef CONFIG_OF
3424 //Enable VOW_CLK_MISO
3425 mt_set_gpio_mode(pin_vowclk, GPIO_MODE_00); //GPIO148: mode 0
3426 //Enable VOW_DAT_MISO
3427 mt_set_gpio_mode(pin_audmiso, GPIO_MODE_01); //GPIO25: mode 1
3428
3429 #else
3430 //GPIO set to back to normal record
3431 //disable VOW_CLK_MISO
3432 mt_set_gpio_mode(GPIO_VOW_CLK_MISO_PIN, GPIO_MODE_00); //GPIO148: mode 0
3433
3434 mt_set_gpio_mode(GPIO_AUD_DAT_MISO_PIN, GPIO_MODE_01); //GPIO25: mode 1
3435 #endif
3436 #endif
3437 //set PMIC GPIO
3438 Ana_Set_Reg(GPIO_MODE3, 0x1249, 0xffff); //GPIO Set to VOW data
3439 #endif
3440
3441 VOW12MCK_Enable(false);//VOW clock power down enable
3442
3443 //turn off analog part
3444 Ana_Set_Reg(AUDENC_ANA_CON8, 0x0000, 0x0007); //DMIC disable.BIT0,1,2
3445
3446 Ana_Set_Reg(AUDENC_ANA_CON9, (MicbiasRef|0x0000), 0x0701); //disable MICBIAS0 lowpower mode, MISBIAS0 = 1P7V.BIT0,8~10
3447 Ana_Set_Reg(AUDENC_ANA_CON2, 0x0000, 0x0002); //disable audio uplink VOW LPW globe bias.BIT1
3448 //no need to config this reg due to VOW no need
3449 //NvregEnable(true); //enable audio globe bias (Default on)
3450 Ana_Set_Reg(AUDENC_ANA_CON13, 0x0180, 0x8000); //PLL low power off.BIT:15
3451 Ana_Set_Reg(AUDENC_ANA_CON12, 0x02F0, 0x040D); //disable fbdiv relatch (low jitter),Set DCKO = 1/4 F_PLL off, disable VOWPLL CLK.BIT0,2,3,10
3452 Ana_Set_Reg(LDO_CON2, 0x8102, 0x000f); //LDO enable control by RG_VAUD28_EN, Enable AVDD28_LDO (Default on), LPW control by VAUD28_MODE_SET, disable low power mode.BIT:0~3
3453
3454 break;
3455
3456 case AUDIO_VOW_MIC_TYPE_Handset_AMIC_DCC:
3457 case AUDIO_VOW_MIC_TYPE_Handset_AMIC_DCCECM:
3458 printk("%s, case AUDIO_VOW_MIC_TYPE_Handset_AMIC_DCC close\n", __func__);
3459
3460 // turn off digital first, move to vow driver
3461 //#ifdef VOW_STANDALONE_CONTROL
3462 #if 1
3463 //disable VOW interrupt here or when digital power off
3464
3465 #ifdef MTK_VOW_SUPPORT
3466 #ifdef CONFIG_OF
3467 //Enable VOW_CLK_MISO
3468 mt_set_gpio_mode(pin_vowclk, GPIO_MODE_00); //GPIO148: mode 0
3469 //Enable VOW_DAT_MISO
3470 mt_set_gpio_mode(pin_audmiso, GPIO_MODE_01); //GPIO25: mode 1
3471
3472 #else
3473 //GPIO set to back to normal record
3474 //disable VOW_CLK_MISO
3475 mt_set_gpio_mode(GPIO_VOW_CLK_MISO_PIN, GPIO_MODE_00); //GPIO148: mode 0
3476
3477 mt_set_gpio_mode(GPIO_AUD_DAT_MISO_PIN, GPIO_MODE_01); //GPIO25: mode 1
3478 #endif
3479 #endif
3480 //set PMIC GPIO
3481 Ana_Set_Reg(GPIO_MODE3, 0x1249, 0xffff); //GPIO Set to VOW data
3482 #endif
3483
3484 //turn off analog part
3485 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0502, 0x00C1); //Audio L preamplifier input sel : off, disable audio L PGA.BIT0,6,7
3486 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0000, 0x0700); //Audio L ADC input sel : off, disable audio L ADC.BIT:8,9,10
3487 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0009, 0xf800); //PGA stb enhance off.BIT11~15
3488 Ana_Set_Reg(AUDENC_ANA_CON15, 0x0000, 0x0007); //Audio L PGA 0 dB gain.BIT0~2
3489 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0000, 0x0002); //Audio L preamplifier DCCEN.BIT1
3490 Ana_Set_Reg(AUDENC_ANA_CON9, 0x0A01, 0x0006); //MICBIAS0 DCC SwithP/N on.BIT1,2
3491 Ana_Set_Reg(AUDENC_ANA_CON4, 0x0000, 0x0800); //BIT11
3492 Ana_Set_Reg(AUDENC_ANA_CON6, 0x2020, 0xffff);
3493
3494 Ana_Set_Reg(AUDENC_ANA_CON9, (MicbiasRef|0x0000), 0x0f01); //disable MICBIAS0 lowpower mode, MISBIAS0 = 1P7V. BIT:0,8:10,11
3495 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x0000, 0x0006); //LCLDO_ENC remote sense off, BIT:1,2
3496 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0000, 0x0100); //disable LCLDO_ENC 1P8V
3497 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0000, 0x000D); //ADC CLK from VOWPLL (12.85/4MHz) off, Enable Audio ADC FBDAC 0.25FS LPW off. BIT:0,2,3
3498 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2064, 0xffff);
3499 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2066, 0xffff);
3500 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2062, 0xffff);
3501 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2062, 0xffff);
3502
3503 VOW12MCK_Enable(false);//VOW clock power down enable
3504
3505 Ana_Set_Reg(AUDENC_ANA_CON13, 0x0180, 0x8000); //PLL low power off. BIT:15
3506 Ana_Set_Reg(AUDENC_ANA_CON12, 0x02F0, 0x040D); //disable fbdiv relatch (low jitter),Set DCKO = 1/4 F_PLL off, disable VOWPLL CLK. BIT:0,2,3,10
3507 Ana_Set_Reg(AUDENC_ANA_CON2, 0x0000, 0x0003); //disable audio uplink VOW LPW globe bias, disable audio uplink LPW mode.BIT:0,1
3508 //no need to config this reg due to VOW no need
3509 //NvregEnable(true); //enable audio globe bias (Default on)
3510 Ana_Set_Reg(LDO_CON2, 0x8102, 0x000f); //LDO enable control by RG_VAUD28_EN, Enable AVDD28_LDO (Default on), LPW control by VAUD28_MODE_SET, disable low power mode.BIT:0~3
3511
3512 break;
3513
3514 case AUDIO_VOW_MIC_TYPE_Headset_MIC_DCC:
3515 case AUDIO_VOW_MIC_TYPE_Headset_MIC_DCCECM:
3516 printk("%s, case AUDIO_VOW_MIC_TYPE_Headset_MIC_DCC close\n", __func__);
3517
3518 // turn off digital first, move to vow driver
3519 //#ifdef VOW_STANDALONE_CONTROL
3520 #if 1
3521 //disable VOW interrupt here or when digital power off
3522
3523 #ifdef MTK_VOW_SUPPORT
3524 #ifdef CONFIG_OF
3525 //Enable VOW_CLK_MISO
3526 mt_set_gpio_mode(pin_vowclk, GPIO_MODE_00); //GPIO148: mode 0
3527 //Enable VOW_DAT_MISO
3528 mt_set_gpio_mode(pin_audmiso, GPIO_MODE_01); //GPIO25: mode 1
3529
3530 #else
3531 //GPIO set to back to normal record
3532 //disable VOW_CLK_MISO
3533 mt_set_gpio_mode(GPIO_VOW_CLK_MISO_PIN, GPIO_MODE_00); //GPIO148: mode 0
3534
3535 mt_set_gpio_mode(GPIO_AUD_DAT_MISO_PIN, GPIO_MODE_01); //GPIO25: mode 1
3536 #endif
3537 #endif
3538 //set PMIC GPIO
3539 Ana_Set_Reg(GPIO_MODE3, 0x1249, 0xffff); //GPIO Set to VOW data
3540 #endif
3541
3542 //turn off analog part
3543 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0502, 0x00C1); //Audio L preamplifier input sel : off, disable audio L PGA.BIT0,6,7
3544 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0000, 0x0700); //Audio L ADC input sel : off, disable audio L ADC.BIT:8,9,10
3545 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0009, 0xf800); //PGA stb enhance off.BIT11~15
3546 Ana_Set_Reg(AUDENC_ANA_CON15, 0x0000, 0x0007); //Audio L PGA 0 dB gain.BIT0~2
3547 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0000, 0x0002); //Audio L preamplifier DCCEN.BIT1
3548 Ana_Set_Reg(AUDENC_ANA_CON9, 0x0F10, 0x0060); //MICBIAS1 DCC SwithP/N on. BIT5,6
3549 Ana_Set_Reg(AUDENC_ANA_CON4, 0x0000, 0x0800); //BIT11
3550 Ana_Set_Reg(AUDENC_ANA_CON6, 0x2020, 0xffff);
3551
3552 Ana_Set_Reg(AUDENC_ANA_CON9, (MicbiasRef|0x0000), 0x0f10); //disable MICBIAS0 lowpower mode, MISBIAS0 = 1P7V.BIT4,8:11
3553 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x0000, 0x0006); //LCLDO_ENC remote sense off, BIT:1,2
3554 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0000, 0x0100); //disable LCLDO_ENC 1P8V
3555 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0000, 0x000D); //ADC CLK from VOWPLL (12.85/4MHz) off, Enable Audio ADC FBDAC 0.25FS LPW off. BIT:0,2,3
3556 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2064, 0xffff);
3557 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2066, 0xffff);
3558 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2062, 0xffff);
3559 Ana_Set_Reg(AFE_DCCLK_CFG0, 0x2062, 0xffff);
3560
3561 VOW12MCK_Enable(false);//VOW clock power down enable
3562
3563 Ana_Set_Reg(AUDENC_ANA_CON13, 0x0180, 0x8000); //PLL low power off. BIT:15
3564 Ana_Set_Reg(AUDENC_ANA_CON12, 0x02F0, 0x040D); //disable fbdiv relatch (low jitter),Set DCKO = 1/4 F_PLL off, disable VOWPLL CLK. BIT:0,2,3,10
3565 Ana_Set_Reg(AUDENC_ANA_CON2, 0x0000, 0x0003); //disable audio uplink VOW LPW globe bias, disable audio uplink LPW mode.BIT:0,1
3566 //no need to config this reg due to VOW no need
3567 //NvregEnable(true); //enable audio globe bias (Default on)
3568 Ana_Set_Reg(LDO_CON2, 0x8102, 0x000f); //LDO enable control by RG_VAUD28_EN, Enable AVDD28_LDO (Default on), LPW control by VAUD28_MODE_SET, disable low power mode.BIT:0~3
3569
3570 break;
3571
3572 case AUDIO_VOW_MIC_TYPE_Handset_AMIC:
3573 default:
3574 printk("%s, case AUDIO_VOW_MIC_TYPE_Handset_AMIC close\n", __func__);
3575
3576 // turn off digital first, move to vow driver
3577 //#ifdef VOW_STANDALONE_CONTROL
3578 #if 1
3579 //disable VOW interrupt here or when digital power off
3580
3581 #ifdef MTK_VOW_SUPPORT
3582 #ifdef CONFIG_OF
3583 //Enable VOW_CLK_MISO
3584 mt_set_gpio_mode(pin_vowclk, GPIO_MODE_00); //GPIO148: mode 0
3585 //Enable VOW_DAT_MISO
3586 mt_set_gpio_mode(pin_audmiso, GPIO_MODE_01); //GPIO25: mode 1
3587
3588 #else
3589 //GPIO set to back to normal record
3590 //disable VOW_CLK_MISO
3591 mt_set_gpio_mode(GPIO_VOW_CLK_MISO_PIN, GPIO_MODE_00); //GPIO148: mode 0
3592
3593 mt_set_gpio_mode(GPIO_AUD_DAT_MISO_PIN, GPIO_MODE_01); //GPIO25: mode 1
3594 #endif
3595 #endif
3596 //set PMIC GPIO
3597 Ana_Set_Reg(GPIO_MODE3, 0x1249, 0xffff); //GPIO Set to VOW data
3598 #endif
3599 VOW12MCK_Enable(false);//VOW clock power down enable
3600
3601 //turn off analog part
3602 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0500, 0x00C1); //Audio L preamplifier input sel : off, disable audio L PGA. BIT:0,6,7
3603 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0000, 0x0700); //Audio L ADC input sel : off, disable audio L ADC.BIT:8,9,10
3604 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0009, 0xf900); //PGA stb enhance off,BIT:8,15:11
3605 Ana_Set_Reg(AUDENC_ANA_CON15, 0x0000, 0x0007); //Audio L PGA 0 dB gain,BIT:0~2
3606 Ana_Set_Reg(AUDENC_ANA_CON4, 0x0000, 0x0800); //BIT11
3607 Ana_Set_Reg(AUDENC_ANA_CON6, 0x2020, 0xffff);
3608
3609 Ana_Set_Reg(AUDENC_ANA_CON9, (MicbiasRef|0x0000), 0x0f01); //disable MICBIAS0 lowpower mode, MISBIAS0 = 1P7V. BIT:0,8:10,11
3610 Ana_Set_Reg(AUDDEC_ANA_CON7, 0x0000, 0x0006); //LCLDO_ENC remote sense off, BIT:1,2
3611 Ana_Set_Reg(AUDDEC_ANA_CON6, 0x0000, 0x0100); //disable LCLDO_ENC 1P8V
3612 Ana_Set_Reg(AUDENC_ANA_CON3, 0x0000, 0x000D); //ADC CLK from VOWPLL (12.85/4MHz) off, Enable Audio ADC FBDAC 0.25FS LPW off. BIT:0,2,3
3613 Ana_Set_Reg(AUDENC_ANA_CON13, 0x0180, 0x8000); //PLL low power off. BIT:15
3614 Ana_Set_Reg(AUDENC_ANA_CON12, 0x02F0, 0x040D); //disable fbdiv relatch (low jitter),Set DCKO = 1/4 F_PLL off, disable VOWPLL CLK. BIT:0,2,3,10
3615 Ana_Set_Reg(AUDENC_ANA_CON2, 0x0000, 0x0003); //disable audio uplink VOW LPW globe bias, disable audio uplink LPW mode.BIT:0,1
3616 //Ana_Set_Reg(AUDDEC_ANA_CON8, 0x0000, 0xffff); //enable audio globe bias (Default on)
3617 //no need to config this reg due to VOW no need
3618 //NvregEnable(true); //enable audio globe bias (Default on)
3619 Ana_Set_Reg(LDO_CON2, 0x8102, 0x000f); //LDO enable control by RG_VAUD28_EN, Enable AVDD28_LDO (Default on), LPW control by VAUD28_MODE_SET, disable low power mode.BIT:0~3
3620
3621 break;
3622 }
3623
3624 mIsVOWOn = false;
3625 SetVOWStatus(mIsVOWOn);
3626 GetMicbias = 0;
3627 }
3628 return true;
3629 }
3630
3631
3632
3633 // here start uplink power function
3634 static const char *ADC_function[] = {"Off", "On"};
3635 static const char *ADC_power_mode[] = {"normal", "lowpower"};
3636 static const char *PreAmp_Mux_function[] = {"OPEN", "IN_ADC1", "IN_ADC2", "IN_ADC3"}; //OPEN:0, IN_ADC1: 1, IN_ADC2:2, IN_ADC3:3
3637 static const char *ADC_UL_PGA_GAIN[] = { "0Db", "6Db", "12Db", "18Db", "24Db", "30Db"};
3638 static const char *Pmic_Digital_Mux[] = { "ADC1", "ADC2", "ADC3", "ADC4"};
3639 static const char *Adc_Input_Sel[] = { "idle", "AIN", "Preamp"};
3640 static const char *Audio_AnalogMic_Mode[] = { "ACCMODE", "DCCMODE", "DMIC", "DCCECMDIFFMODE", "DCCECMSINGLEMODE"};
3641 static const char *Audio_VOW_ADC_Function[] = {"Off", "On"};
3642 static const char *Audio_VOW_Digital_Function[] = {"Off", "On"};
3643 static const char *Audio_VOW_MIC_Type[] = {"HandsetAMIC", "HeadsetMIC", "HandsetDMIC", "HandsetDMIC_800K", "HandsetAMIC_DCC", "HeadsetMIC_DCC", "HandsetAMIC_DCCECM", "HeadsetMIC_DCCECM"};
3644
3645
3646 static const struct soc_enum Audio_UL_Enum[] =
3647 {
3648 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ADC_function), ADC_function),
3649 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ADC_function), ADC_function),
3650 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ADC_function), ADC_function),
3651 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ADC_function), ADC_function),
3652 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(PreAmp_Mux_function), PreAmp_Mux_function),
3653 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Adc_Input_Sel), Adc_Input_Sel),
3654 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Adc_Input_Sel), Adc_Input_Sel),
3655 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Adc_Input_Sel), Adc_Input_Sel),
3656 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Adc_Input_Sel), Adc_Input_Sel),
3657 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ADC_UL_PGA_GAIN), ADC_UL_PGA_GAIN),
3658 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ADC_UL_PGA_GAIN), ADC_UL_PGA_GAIN),
3659 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ADC_UL_PGA_GAIN), ADC_UL_PGA_GAIN),
3660 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ADC_UL_PGA_GAIN), ADC_UL_PGA_GAIN),
3661 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Pmic_Digital_Mux), Pmic_Digital_Mux),
3662 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Pmic_Digital_Mux), Pmic_Digital_Mux),
3663 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Pmic_Digital_Mux), Pmic_Digital_Mux),
3664 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Pmic_Digital_Mux), Pmic_Digital_Mux),
3665 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Audio_AnalogMic_Mode), Audio_AnalogMic_Mode),
3666 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Audio_AnalogMic_Mode), Audio_AnalogMic_Mode),
3667 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Audio_AnalogMic_Mode), Audio_AnalogMic_Mode),
3668 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Audio_AnalogMic_Mode), Audio_AnalogMic_Mode),
3669 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ADC_power_mode), ADC_power_mode),
3670 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Audio_VOW_ADC_Function), Audio_VOW_ADC_Function),
3671 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(PreAmp_Mux_function), PreAmp_Mux_function),
3672 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Audio_VOW_Digital_Function), Audio_VOW_Digital_Function),
3673 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Audio_VOW_MIC_Type), Audio_VOW_MIC_Type),
3674 };
3675
3676 static int Audio_ADC1_Get(struct snd_kcontrol *kcontrol,
3677 struct snd_ctl_elem_value *ucontrol)
3678 {
3679 printk("Audio_ADC1_Get = %d\n", mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC1]);
3680 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC1];
3681 return 0;
3682 }
3683
3684 static int Audio_ADC1_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3685 {
3686 printk("%s()\n", __func__);
3687 mutex_lock(&Ana_Power_Mutex);
3688 if (ucontrol->value.integer.value[0])
3689 {
3690 if (mAudio_Analog_Mic1_mode == AUDIO_ANALOGUL_MODE_ACC)
3691 {
3692 TurnOnADcPowerACC(AUDIO_ANALOG_DEVICE_IN_ADC1 , true);
3693 }
3694 else if (mAudio_Analog_Mic1_mode == AUDIO_ANALOGUL_MODE_DCC)
3695 {
3696 TurnOnADcPowerDCC(AUDIO_ANALOG_DEVICE_IN_ADC1 , true);
3697 }
3698 else if (mAudio_Analog_Mic1_mode == AUDIO_ANALOGUL_MODE_DMIC)
3699 {
3700 TurnOnADcPowerDmic(AUDIO_ANALOG_DEVICE_IN_ADC1, true);
3701 }
3702 else if (mAudio_Analog_Mic1_mode == AUDIO_ANALOGUL_MODE_DCCECMDIFF || mAudio_Analog_Mic1_mode == AUDIO_ANALOGUL_MODE_DCCECMSINGLE)
3703 {
3704 TurnOnADcPowerDCCECM(AUDIO_ANALOG_DEVICE_IN_ADC1 , true);
3705 }
3706 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC1] = ucontrol->value.integer.value[0];
3707 }
3708 else
3709 {
3710 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC1] = ucontrol->value.integer.value[0];
3711 if (mAudio_Analog_Mic1_mode == AUDIO_ANALOGUL_MODE_ACC)
3712 {
3713 TurnOnADcPowerACC(AUDIO_ANALOG_DEVICE_IN_ADC1 , false);
3714 }
3715 else if (mAudio_Analog_Mic1_mode == AUDIO_ANALOGUL_MODE_DCC)
3716 {
3717 TurnOnADcPowerDCC(AUDIO_ANALOG_DEVICE_IN_ADC1 , false);
3718 }
3719 else if (mAudio_Analog_Mic1_mode == AUDIO_ANALOGUL_MODE_DMIC)
3720 {
3721 TurnOnADcPowerDmic(AUDIO_ANALOG_DEVICE_IN_ADC1, false);
3722 }
3723 else if (mAudio_Analog_Mic1_mode == AUDIO_ANALOGUL_MODE_DCCECMDIFF || mAudio_Analog_Mic1_mode == AUDIO_ANALOGUL_MODE_DCCECMSINGLE)
3724 {
3725 TurnOnADcPowerDCCECM(AUDIO_ANALOG_DEVICE_IN_ADC1, false);
3726 }
3727 }
3728 mutex_unlock(&Ana_Power_Mutex);
3729 return 0;
3730 }
3731
3732 static int Audio_ADC2_Get(struct snd_kcontrol *kcontrol,
3733 struct snd_ctl_elem_value *ucontrol)
3734 {
3735 printk("Audio_ADC2_Get = %d\n", mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC2]);
3736 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC2];
3737 return 0;
3738 }
3739
3740 static int Audio_ADC2_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3741 {
3742 printk("%s()\n", __func__);
3743 mutex_lock(&Ana_Power_Mutex);
3744 if (ucontrol->value.integer.value[0])
3745 {
3746 if (mAudio_Analog_Mic2_mode == AUDIO_ANALOGUL_MODE_ACC)
3747 {
3748 TurnOnADcPowerACC(AUDIO_ANALOG_DEVICE_IN_ADC2 , true);
3749 }
3750 else if (mAudio_Analog_Mic2_mode == AUDIO_ANALOGUL_MODE_DCC)
3751 {
3752 TurnOnADcPowerDCC(AUDIO_ANALOG_DEVICE_IN_ADC2 , true);
3753 }
3754 else if (mAudio_Analog_Mic2_mode == AUDIO_ANALOGUL_MODE_DMIC)
3755 {
3756 TurnOnADcPowerDmic(AUDIO_ANALOG_DEVICE_IN_ADC2 , true);
3757 }
3758 else if (mAudio_Analog_Mic2_mode == AUDIO_ANALOGUL_MODE_DCCECMDIFF || mAudio_Analog_Mic2_mode == AUDIO_ANALOGUL_MODE_DCCECMSINGLE)
3759 {
3760 TurnOnADcPowerDCCECM(AUDIO_ANALOG_DEVICE_IN_ADC2 , true);
3761 }
3762 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC2] = ucontrol->value.integer.value[0];
3763 }
3764 else
3765 {
3766 mCodec_data->mAudio_Ana_DevicePower[AUDIO_ANALOG_DEVICE_IN_ADC2] = ucontrol->value.integer.value[0];
3767 if (mAudio_Analog_Mic2_mode == AUDIO_ANALOGUL_MODE_ACC)
3768 {
3769 TurnOnADcPowerACC(AUDIO_ANALOG_DEVICE_IN_ADC2 , false);
3770 }
3771 else if (mAudio_Analog_Mic2_mode == AUDIO_ANALOGUL_MODE_DCC)
3772 {
3773 TurnOnADcPowerDCC(AUDIO_ANALOG_DEVICE_IN_ADC2 , false);
3774 }
3775 else if (mAudio_Analog_Mic2_mode == AUDIO_ANALOGUL_MODE_DMIC)
3776 {
3777 TurnOnADcPowerDmic(AUDIO_ANALOG_DEVICE_IN_ADC2 , false);
3778 }
3779 else if (mAudio_Analog_Mic2_mode == AUDIO_ANALOGUL_MODE_DCCECMDIFF || mAudio_Analog_Mic2_mode == AUDIO_ANALOGUL_MODE_DCCECMSINGLE)
3780 {
3781 TurnOnADcPowerDCCECM(AUDIO_ANALOG_DEVICE_IN_ADC2 , false);
3782 }
3783 }
3784 mutex_unlock(&Ana_Power_Mutex);
3785 return 0;
3786 }
3787
3788 static int Audio_ADC3_Get(struct snd_kcontrol *kcontrol,
3789 struct snd_ctl_elem_value *ucontrol)
3790 {
3791 //K2 removed
3792 return 0;
3793 }
3794
3795 static int Audio_ADC3_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3796 {
3797 //K2 removed
3798 return 0;
3799 }
3800
3801 static int Audio_ADC4_Get(struct snd_kcontrol *kcontrol,
3802 struct snd_ctl_elem_value *ucontrol)
3803 {
3804 //K2 removed
3805 return 0;
3806 }
3807
3808 static int Audio_ADC4_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3809 {
3810 //K2 removed
3811 return 0;
3812 }
3813
3814 static int Audio_ADC1_Sel_Get(struct snd_kcontrol *kcontrol,
3815 struct snd_ctl_elem_value *ucontrol)
3816 {
3817 printk("%s() = %d\n", __func__, mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC1]);
3818 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC1];
3819 return 0;
3820 }
3821
3822 static int Audio_ADC1_Sel_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3823 {
3824 printk("%s()\n", __func__);
3825
3826 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Adc_Input_Sel))
3827 {
3828 printk("return -EINVAL\n");
3829 return -EINVAL;
3830 }
3831 if (ucontrol->value.integer.value[0] == 0)
3832 {
3833 Ana_Set_Reg(AUDENC_ANA_CON0, (0x0000 << 9), 0x0600); // pinumx sel
3834 }
3835 else if (ucontrol->value.integer.value[0] == 1)
3836 {
3837 Ana_Set_Reg(AUDENC_ANA_CON0, (0x0001 << 9), 0x0600); //AIN0
3838 }
3839 // ADC2
3840 else if (ucontrol->value.integer.value[0] == 2)
3841 {
3842 Ana_Set_Reg(AUDENC_ANA_CON0, (0x0002 << 9), 0x0600); //Left preamp
3843 }
3844 else
3845 {
3846 printk("%s() warning \n ", __func__);
3847 }
3848 printk("%s() done \n", __func__);
3849 mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC1] = ucontrol->value.integer.value[0];
3850 return 0;
3851 }
3852
3853 static int Audio_ADC2_Sel_Get(struct snd_kcontrol *kcontrol,
3854 struct snd_ctl_elem_value *ucontrol)
3855 {
3856 printk("%s() = %d\n", __func__, mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC2]);
3857 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC2];
3858 return 0;
3859 }
3860
3861 static int Audio_ADC2_Sel_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3862 {
3863 printk("%s()\n", __func__);
3864 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Adc_Input_Sel))
3865 {
3866 printk("return -EINVAL\n");
3867 return -EINVAL;
3868 }
3869 if (ucontrol->value.integer.value[0] == 0)
3870 {
3871 Ana_Set_Reg(AUDENC_ANA_CON1, (0x0000 << 9), 0x0600); // pinumx sel
3872 }
3873 else if (ucontrol->value.integer.value[0] == 1)
3874 {
3875 Ana_Set_Reg(AUDENC_ANA_CON1, (0x0001 << 9), 0x0600); //AIN2
3876 }
3877 else if (ucontrol->value.integer.value[0] == 2) //Right preamp
3878 {
3879 Ana_Set_Reg(AUDENC_ANA_CON1, (0x0002 << 9), 0x0600);
3880 }
3881 else
3882 {
3883 printk("%s() warning \n ", __func__);
3884 }
3885 printk("%s() done \n", __func__);
3886 mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC2] = ucontrol->value.integer.value[0];
3887 return 0;
3888 }
3889
3890 static int Audio_ADC3_Sel_Get(struct snd_kcontrol *kcontrol,
3891 struct snd_ctl_elem_value *ucontrol)
3892 {
3893 //K2 removed
3894 return 0;
3895 }
3896
3897 static int Audio_ADC3_Sel_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3898 {
3899 //K2 removed
3900 return 0;
3901 }
3902
3903 static int Audio_ADC4_Sel_Get(struct snd_kcontrol *kcontrol,
3904 struct snd_ctl_elem_value *ucontrol)
3905 {
3906 //K2 removed
3907 return 0;
3908 }
3909
3910 static int Audio_ADC4_Sel_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3911 {
3912 //K2 removed
3913 return 0;
3914 }
3915
3916
3917 static bool AudioPreAmp1_Sel(int Mul_Sel)
3918 {
3919 printk("%s Mul_Sel = %d ", __func__, Mul_Sel);
3920 if (Mul_Sel == 0)
3921 {
3922 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0000, 0x00C0); // pinumx open
3923 }
3924 else if (Mul_Sel == 1)
3925 {
3926 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0040, 0x00C0); // AIN0
3927 }
3928 else if (Mul_Sel == 2)
3929 {
3930 Ana_Set_Reg(AUDENC_ANA_CON0, 0x0080, 0x00C0); // AIN1
3931 }
3932 else if (Mul_Sel == 3)
3933 {
3934 Ana_Set_Reg(AUDENC_ANA_CON0, 0x00C0, 0x00C0); // AIN2
3935 }
3936 else
3937 {
3938 printk("AudioPreAmp1_Sel warning");
3939 }
3940 return true;
3941 }
3942
3943
3944 static int Audio_PreAmp1_Get(struct snd_kcontrol *kcontrol,
3945 struct snd_ctl_elem_value *ucontrol)
3946 {
3947 printk("%s() mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_PREAMP_1]; = %d\n", __func__, mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_PREAMP_1]);
3948 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_PREAMP_1];
3949 return 0;
3950 }
3951
3952 static int Audio_PreAmp1_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3953 {
3954 printk("%s()\n", __func__);
3955
3956 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(PreAmp_Mux_function))
3957 {
3958 printk("return -EINVAL\n");
3959 return -EINVAL;
3960 }
3961 mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_PREAMP_1] = ucontrol->value.integer.value[0];
3962 AudioPreAmp1_Sel(mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_PREAMP_1]);
3963 printk("%s() done \n", __func__);
3964 return 0;
3965 }
3966
3967 static bool AudioPreAmp2_Sel(int Mul_Sel)
3968 {
3969 printk("%s Mul_Sel = %d ", __func__, Mul_Sel);
3970 if (Mul_Sel == 0)
3971 {
3972 Ana_Set_Reg(AUDENC_ANA_CON1, 0x0000, 0x00C0); // pinumx open
3973 }
3974 else if (Mul_Sel == 1)
3975 {
3976 Ana_Set_Reg(AUDENC_ANA_CON1, 0x00C0, 0x00C0); // AIN2
3977 }
3978 else if (Mul_Sel == 2)
3979 {
3980 Ana_Set_Reg(AUDENC_ANA_CON1, 0x0080, 0x00C0); // AIN1
3981 }
3982 else if (Mul_Sel == 3)
3983 {
3984 Ana_Set_Reg(AUDENC_ANA_CON1, 0x0040, 0x00C0); // AIN0
3985 }
3986 else
3987 {
3988 printk("AudioPreAmp1_Sel warning");
3989 }
3990 return true;
3991 }
3992
3993
3994 static int Audio_PreAmp2_Get(struct snd_kcontrol *kcontrol,
3995 struct snd_ctl_elem_value *ucontrol)
3996 {
3997 printk("%s() mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_PREAMP_2]; = %d\n", __func__, mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_PREAMP_2]);
3998 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_PREAMP_2];
3999 return 0;
4000 }
4001
4002 static int Audio_PreAmp2_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4003 {
4004 printk("%s()\n", __func__);
4005
4006 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(PreAmp_Mux_function))
4007 {
4008 printk("return -EINVAL\n");
4009 return -EINVAL;
4010 }
4011 mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_PREAMP_2] = ucontrol->value.integer.value[0];
4012 AudioPreAmp2_Sel(mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_PREAMP_2]);
4013 printk("%s() done \n", __func__);
4014 return 0;
4015 }
4016
4017 //PGA1: PGA_L
4018 static int Audio_PGA1_Get(struct snd_kcontrol *kcontrol,
4019 struct snd_ctl_elem_value *ucontrol)
4020 {
4021 printk("Audio_AmpR_Get = %d\n", mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP1]);
4022 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP1];
4023 return 0;
4024 }
4025
4026 static int Audio_PGA1_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4027 {
4028 int index = 0;
4029 printk("%s()\n", __func__);
4030 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(ADC_UL_PGA_GAIN))
4031 {
4032 printk("return -EINVAL\n");
4033 return -EINVAL;
4034 }
4035 index = ucontrol->value.integer.value[0];
4036 Ana_Set_Reg(AUDENC_ANA_CON15, index , 0x0007);
4037 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP1] = ucontrol->value.integer.value[0];
4038 return 0;
4039 }
4040
4041 //PGA2: PGA_R
4042 static int Audio_PGA2_Get(struct snd_kcontrol *kcontrol,
4043 struct snd_ctl_elem_value *ucontrol)
4044 {
4045 printk("Audio_PGA2_Get = %d\n", mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP2]);
4046 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP2];
4047 return 0;
4048 }
4049
4050 static int Audio_PGA2_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4051 {
4052 int index = 0;
4053 printk("%s()\n", __func__);
4054 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(ADC_UL_PGA_GAIN))
4055 {
4056 printk("return -EINVAL\n");
4057 return -EINVAL;
4058 }
4059 index = ucontrol->value.integer.value[0];
4060 Ana_Set_Reg(AUDENC_ANA_CON15, index << 4, 0x0070);
4061 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP2] = ucontrol->value.integer.value[0];
4062 return 0;
4063 }
4064
4065 static int Audio_PGA3_Get(struct snd_kcontrol *kcontrol,
4066 struct snd_ctl_elem_value *ucontrol)
4067 {
4068 //K2 removed
4069 return 0;
4070 }
4071
4072 static int Audio_PGA3_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4073 {
4074 //K2 removed
4075 return 0;
4076 }
4077
4078 static int Audio_PGA4_Get(struct snd_kcontrol *kcontrol,
4079 struct snd_ctl_elem_value *ucontrol)
4080 {
4081 //K2 removed
4082 return 0;
4083 }
4084
4085 static int Audio_PGA4_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4086 {
4087 //K2 removed
4088 return 0;
4089 }
4090
4091 static int Audio_MicSource1_Get(struct snd_kcontrol *kcontrol,
4092 struct snd_ctl_elem_value *ucontrol)
4093 {
4094 printk("Audio_MicSource1_Get = %d\n", mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_1]);
4095 ucontrol->value.integer.value[0] = mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_1];
4096 return 0;
4097 }
4098
4099 static int Audio_MicSource1_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4100 {
4101 //K2 used for ADC1 Mic source selection, "ADC1" is main_mic, "ADC2" is headset_mic
4102 int index = 0;
4103 printk("%s()\n", __func__);
4104 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Pmic_Digital_Mux))
4105 {
4106 printk("return -EINVAL\n");
4107 return -EINVAL;
4108 }
4109 index = ucontrol->value.integer.value[0];
4110 printk("%s() index = %d done \n", __func__, index);
4111 mCodec_data->mAudio_Ana_Mux[AUDIO_MICSOURCE_MUX_IN_1] = ucontrol->value.integer.value[0];
4112
4113 return 0;
4114 }
4115
4116 static int Audio_MicSource2_Get(struct snd_kcontrol *kcontrol,
4117 struct snd_ctl_elem_value *ucontrol)
4118 {
4119 //K2 removed
4120 return 0;
4121 }
4122
4123 static int Audio_MicSource2_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4124 {
4125 //K2 removed
4126 return 0;
4127 }
4128
4129 static int Audio_MicSource3_Get(struct snd_kcontrol *kcontrol,
4130 struct snd_ctl_elem_value *ucontrol)
4131 {
4132 //K2 removed
4133 return 0;
4134 }
4135
4136 static int Audio_MicSource3_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4137 {
4138 //K2 removed
4139 return 0;
4140 }
4141
4142
4143 static int Audio_MicSource4_Get(struct snd_kcontrol *kcontrol,
4144 struct snd_ctl_elem_value *ucontrol)
4145 {
4146 //K2 removed
4147 return 0;
4148 }
4149
4150 static int Audio_MicSource4_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4151 {
4152 //K2 removed
4153 return 0;
4154 }
4155
4156 // Mic ACC/DCC Mode Setting
4157 static int Audio_Mic1_Mode_Select_Get(struct snd_kcontrol *kcontrol,
4158 struct snd_ctl_elem_value *ucontrol)
4159 {
4160 printk("%s() mAudio_Analog_Mic1_mode = %d\n", __func__, mAudio_Analog_Mic1_mode);
4161 ucontrol->value.integer.value[0] = mAudio_Analog_Mic1_mode;
4162 return 0;
4163 }
4164
4165 static int Audio_Mic1_Mode_Select_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4166 {
4167 printk("%s()\n", __func__);
4168 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Audio_AnalogMic_Mode))
4169 {
4170 printk("return -EINVAL\n");
4171 return -EINVAL;
4172 }
4173 mAudio_Analog_Mic1_mode = ucontrol->value.integer.value[0];
4174 printk("%s() mAudio_Analog_Mic1_mode = %d \n", __func__, mAudio_Analog_Mic1_mode);
4175 return 0;
4176 }
4177
4178 static int Audio_Mic2_Mode_Select_Get(struct snd_kcontrol *kcontrol,
4179 struct snd_ctl_elem_value *ucontrol)
4180 {
4181 printk("%s() = %d\n", __func__, mAudio_Analog_Mic2_mode);
4182 ucontrol->value.integer.value[0] = mAudio_Analog_Mic2_mode;
4183 return 0;
4184 }
4185
4186 static int Audio_Mic2_Mode_Select_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4187 {
4188 printk("%s()\n", __func__);
4189 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Audio_AnalogMic_Mode))
4190 {
4191 printk("return -EINVAL\n");
4192 return -EINVAL;
4193 }
4194 mAudio_Analog_Mic2_mode = ucontrol->value.integer.value[0];
4195 printk("%s() mAudio_Analog_Mic2_mode = %d \n", __func__, mAudio_Analog_Mic2_mode);
4196 return 0;
4197 }
4198
4199
4200 static int Audio_Mic3_Mode_Select_Get(struct snd_kcontrol *kcontrol,
4201 struct snd_ctl_elem_value *ucontrol)
4202 {
4203 printk("%s() = %d\n", __func__, mAudio_Analog_Mic3_mode);
4204 ucontrol->value.integer.value[0] = mAudio_Analog_Mic3_mode;
4205 return 0;
4206 }
4207
4208 static int Audio_Mic3_Mode_Select_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4209 {
4210 printk("%s()\n", __func__);
4211 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Audio_AnalogMic_Mode))
4212 {
4213 printk("return -EINVAL\n");
4214 return -EINVAL;
4215 }
4216 mAudio_Analog_Mic3_mode = ucontrol->value.integer.value[0];
4217 printk("%s() mAudio_Analog_Mic3_mode = %d \n", __func__, mAudio_Analog_Mic3_mode);
4218 return 0;
4219 }
4220
4221 static int Audio_Mic4_Mode_Select_Get(struct snd_kcontrol *kcontrol,
4222 struct snd_ctl_elem_value *ucontrol)
4223 {
4224 printk("%s() = %d\n", __func__, mAudio_Analog_Mic4_mode);
4225 ucontrol->value.integer.value[0] = mAudio_Analog_Mic4_mode;
4226 return 0;
4227 }
4228
4229 static int Audio_Mic4_Mode_Select_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4230 {
4231 printk("%s()\n", __func__);
4232 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Audio_AnalogMic_Mode))
4233 {
4234 printk("return -EINVAL\n");
4235 return -EINVAL;
4236 }
4237 mAudio_Analog_Mic4_mode = ucontrol->value.integer.value[0];
4238 printk("%s() mAudio_Analog_Mic4_mode = %d \n", __func__, mAudio_Analog_Mic4_mode);
4239 return 0;
4240 }
4241
4242 static int Audio_Adc_Power_Mode_Get(struct snd_kcontrol *kcontrol,
4243 struct snd_ctl_elem_value *ucontrol)
4244 {
4245 printk("%s() = %d\n", __func__, mAdc_Power_Mode);
4246 ucontrol->value.integer.value[0] = mAdc_Power_Mode;
4247 return 0;
4248 }
4249
4250 static int Audio_Adc_Power_Mode_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4251 {
4252 printk("%s()\n", __func__);
4253 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(ADC_power_mode))
4254 {
4255 printk("return -EINVAL\n");
4256 return -EINVAL;
4257 }
4258 mAdc_Power_Mode = ucontrol->value.integer.value[0];
4259 printk("%s() mAdc_Power_Mode = %d \n", __func__, mAdc_Power_Mode);
4260 return 0;
4261 }
4262
4263
4264 static int Audio_Vow_ADC_Func_Switch_Get(struct snd_kcontrol *kcontrol,
4265 struct snd_ctl_elem_value *ucontrol)
4266 {
4267 printk("%s() = %d\n", __func__, mAudio_Vow_Analog_Func_Enable);
4268 ucontrol->value.integer.value[0] = mAudio_Vow_Analog_Func_Enable;
4269 return 0;
4270 }
4271
4272 static int Audio_Vow_ADC_Func_Switch_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4273 {
4274 printk("%s()\n", __func__);
4275 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Audio_VOW_ADC_Function))
4276 {
4277 printk("return -EINVAL\n");
4278 return -EINVAL;
4279 }
4280
4281 if (ucontrol->value.integer.value[0])
4282 {
4283 TurnOnVOWADcPowerACC(mAudio_VOW_Mic_type, true);
4284 }
4285 else
4286 {
4287 TurnOnVOWADcPowerACC(mAudio_VOW_Mic_type, false);
4288 }
4289
4290 mAudio_Vow_Analog_Func_Enable = ucontrol->value.integer.value[0];
4291 printk("%s() mAudio_Vow_Analog_Func_Enable = %d \n", __func__, mAudio_Vow_Analog_Func_Enable);
4292 return 0;
4293 }
4294
4295 static int Audio_Vow_Digital_Func_Switch_Get(struct snd_kcontrol *kcontrol,
4296 struct snd_ctl_elem_value *ucontrol)
4297 {
4298 printk("%s() = %d\n", __func__, mAudio_Vow_Digital_Func_Enable);
4299 ucontrol->value.integer.value[0] = mAudio_Vow_Digital_Func_Enable;
4300 return 0;
4301 }
4302
4303 static int Audio_Vow_Digital_Func_Switch_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4304 {
4305 printk("%s()\n", __func__);
4306 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Audio_VOW_Digital_Function))
4307 {
4308 printk("return -EINVAL\n");
4309 return -EINVAL;
4310 }
4311
4312 if (ucontrol->value.integer.value[0])
4313 {
4314 TurnOnVOWDigitalHW(true);
4315 }
4316 else
4317 {
4318 TurnOnVOWDigitalHW(false);
4319 }
4320
4321 mAudio_Vow_Digital_Func_Enable = ucontrol->value.integer.value[0];
4322 printk("%s() mAudio_Vow_Digital_Func_Enable = %d \n", __func__, mAudio_Vow_Digital_Func_Enable);
4323 return 0;
4324 }
4325
4326
4327 static int Audio_Vow_MIC_Type_Select_Get(struct snd_kcontrol *kcontrol,
4328 struct snd_ctl_elem_value *ucontrol)
4329 {
4330 printk("%s() = %d\n", __func__, mAudio_VOW_Mic_type);
4331 ucontrol->value.integer.value[0] = mAudio_VOW_Mic_type;
4332 return 0;
4333 }
4334
4335 static int Audio_Vow_MIC_Type_Select_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4336 {
4337 printk("%s()\n", __func__);
4338 if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(Audio_VOW_MIC_Type))
4339 {
4340 printk("return -EINVAL\n");
4341 return -EINVAL;
4342 }
4343 mAudio_VOW_Mic_type = ucontrol->value.integer.value[0];
4344 printk("%s() mAudio_VOW_Mic_type = %d \n", __func__, mAudio_VOW_Mic_type);
4345 return 0;
4346 }
4347
4348
4349 static int Audio_Vow_Cfg0_Get(struct snd_kcontrol *kcontrol,
4350 struct snd_ctl_elem_value *ucontrol)
4351 {
4352 int value = /*Ana_Get_Reg(AFE_VOW_CFG0)*/reg_AFE_VOW_CFG0;
4353 printk("%s() = %d\n", __func__, value);
4354 ucontrol->value.integer.value[0] = value;
4355 return 0;
4356 }
4357
4358 static int Audio_Vow_Cfg0_Set(struct snd_kcontrol *kcontrol,
4359 struct snd_ctl_elem_value *ucontrol)
4360 {
4361 printk("%s() = %d\n", __func__, (int)(ucontrol->value.integer.value[0]));
4362 //Ana_Set_Reg(AFE_VOW_CFG0, ucontrol->value.integer.value[0], 0xffff);
4363 reg_AFE_VOW_CFG0 = ucontrol->value.integer.value[0];
4364 return 0;
4365 }
4366
4367 static int Audio_Vow_Cfg1_Get(struct snd_kcontrol *kcontrol,
4368 struct snd_ctl_elem_value *ucontrol)
4369 {
4370 int value = /*Ana_Get_Reg(AFE_VOW_CFG1)*/reg_AFE_VOW_CFG1;
4371 printk("%s() = %d\n", __func__, value);
4372 ucontrol->value.integer.value[0] = value;
4373 return 0;
4374 }
4375
4376 static int Audio_Vow_Cfg1_Set(struct snd_kcontrol *kcontrol,
4377 struct snd_ctl_elem_value *ucontrol)
4378 {
4379 printk("%s() = %ld\n", __func__, ucontrol->value.integer.value[0]);
4380 //Ana_Set_Reg(AFE_VOW_CFG1, ucontrol->value.integer.value[0], 0xffff);
4381 reg_AFE_VOW_CFG1 = ucontrol->value.integer.value[0];
4382 return 0;
4383 }
4384
4385 static int Audio_Vow_Cfg2_Get(struct snd_kcontrol *kcontrol,
4386 struct snd_ctl_elem_value *ucontrol)
4387 {
4388 int value = /*Ana_Get_Reg(AFE_VOW_CFG2)*/reg_AFE_VOW_CFG2;
4389 printk("%s() = %d\n", __func__, value);
4390 ucontrol->value.integer.value[0] = value;
4391 return 0;
4392 }
4393
4394 static int Audio_Vow_Cfg2_Set(struct snd_kcontrol *kcontrol,
4395 struct snd_ctl_elem_value *ucontrol)
4396 {
4397 printk("%s() = %ld\n", __func__, ucontrol->value.integer.value[0]);
4398 //Ana_Set_Reg(AFE_VOW_CFG2, ucontrol->value.integer.value[0], 0xffff);
4399 reg_AFE_VOW_CFG2 = ucontrol->value.integer.value[0];
4400 return 0;
4401 }
4402
4403 static int Audio_Vow_Cfg3_Get(struct snd_kcontrol *kcontrol,
4404 struct snd_ctl_elem_value *ucontrol)
4405 {
4406 int value = /*Ana_Get_Reg(AFE_VOW_CFG3)*/reg_AFE_VOW_CFG3;
4407 printk("%s() = %d\n", __func__, value);
4408 ucontrol->value.integer.value[0] = value;
4409 return 0;
4410 }
4411
4412 static int Audio_Vow_Cfg3_Set(struct snd_kcontrol *kcontrol,
4413 struct snd_ctl_elem_value *ucontrol)
4414 {
4415 printk("%s() = %ld\n", __func__, ucontrol->value.integer.value[0]);
4416 //Ana_Set_Reg(AFE_VOW_CFG3, ucontrol->value.integer.value[0], 0xffff);
4417 reg_AFE_VOW_CFG3 = ucontrol->value.integer.value[0];
4418 return 0;
4419 }
4420
4421 static int Audio_Vow_Cfg4_Get(struct snd_kcontrol *kcontrol,
4422 struct snd_ctl_elem_value *ucontrol)
4423 {
4424 int value = /*Ana_Get_Reg(AFE_VOW_CFG4)*/reg_AFE_VOW_CFG4;
4425 printk("%s() = %d\n", __func__, value);
4426 ucontrol->value.integer.value[0] = value;
4427 return 0;
4428 }
4429
4430 static int Audio_Vow_Cfg4_Set(struct snd_kcontrol *kcontrol,
4431 struct snd_ctl_elem_value *ucontrol)
4432 {
4433 printk("%s() = %ld\n", __func__, ucontrol->value.integer.value[0]);
4434 //Ana_Set_Reg(AFE_VOW_CFG4, ucontrol->value.integer.value[0], 0xffff);
4435 reg_AFE_VOW_CFG4 = ucontrol->value.integer.value[0];
4436 return 0;
4437 }
4438
4439 static int Audio_Vow_Cfg5_Get(struct snd_kcontrol *kcontrol,
4440 struct snd_ctl_elem_value *ucontrol)
4441 {
4442 int value = /*Ana_Get_Reg(AFE_VOW_CFG5)*/reg_AFE_VOW_CFG5;
4443 printk("%s() = %d\n", __func__, value);
4444 ucontrol->value.integer.value[0] = value;
4445 return 0;
4446 }
4447
4448 static int Audio_Vow_Cfg5_Set(struct snd_kcontrol *kcontrol,
4449 struct snd_ctl_elem_value *ucontrol)
4450 {
4451 printk("%s() = %ld\n", __func__, ucontrol->value.integer.value[0]);
4452 //Ana_Set_Reg(AFE_VOW_CFG5, ucontrol->value.integer.value[0], 0xffff);
4453 reg_AFE_VOW_CFG5 = ucontrol->value.integer.value[0];
4454 return 0;
4455 }
4456
4457 static int Audio_Vow_State_Get(struct snd_kcontrol *kcontrol,
4458 struct snd_ctl_elem_value *ucontrol)
4459 {
4460 int value = mIsVOWOn;
4461 printk("%s() = %d\n", __func__, value);
4462 ucontrol->value.integer.value[0] = value;
4463 return 0;
4464 }
4465
4466 static int Audio_Vow_State_Set(struct snd_kcontrol *kcontrol,
4467 struct snd_ctl_elem_value *ucontrol)
4468 {
4469 //printk("%s() = %ld\n", __func__, ucontrol->value.integer.value[0]);
4470 //reg_AFE_VOW_CFG5 = ucontrol->value.integer.value[0];
4471 return 0;
4472 }
4473
4474 static bool SineTable_DAC_HP_flag = false;
4475 static bool SineTable_UL2_flag = false;
4476
4477 static int SineTable_UL2_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4478 {
4479 if (ucontrol->value.integer.value[0])
4480 {
4481 Ana_Set_Reg(PMIC_AFE_TOP_CON0 , 0x0002 , 0x2); //set DL sine gen table
4482 Ana_Set_Reg(AFE_SGEN_CFG0 , 0x0080 , 0xffff);
4483 Ana_Set_Reg(AFE_SGEN_CFG1 , 0x0101 , 0xffff);
4484 }
4485 else
4486 {
4487 Ana_Set_Reg(PMIC_AFE_TOP_CON0 , 0x0002 , 0x2); //set DL sine gen table
4488 Ana_Set_Reg(AFE_SGEN_CFG0 , 0x0000 , 0xffff);
4489 Ana_Set_Reg(AFE_SGEN_CFG1 , 0x0101 , 0xffff);
4490 }
4491 return 0;
4492 }
4493
4494 static int SineTable_UL2_Get(struct snd_kcontrol *kcontrol,
4495 struct snd_ctl_elem_value *ucontrol)
4496 {
4497 printk("%s()\n", __func__);
4498 ucontrol->value.integer.value[0] = SineTable_UL2_flag;
4499 return 0;
4500 }
4501
4502 static int SineTable_DAC_HP_Get(struct snd_kcontrol *kcontrol,
4503 struct snd_ctl_elem_value *ucontrol)
4504 {
4505 printk("%s()\n", __func__);
4506 ucontrol->value.integer.value[0] = SineTable_DAC_HP_flag;
4507 return 0;
4508 }
4509
4510 static int SineTable_DAC_HP_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4511 {
4512 //K2 TODO?
4513 printk("%s()\n", __func__);
4514 return 0;
4515 }
4516
4517 static void ADC_LOOP_DAC_Func(int command)
4518 {
4519 //K2 TODO?
4520 }
4521
4522 static bool DAC_LOOP_DAC_HS_flag = false;
4523 static int ADC_LOOP_DAC_HS_Get(struct snd_kcontrol *kcontrol,
4524 struct snd_ctl_elem_value *ucontrol)
4525 {
4526 printk("%s()\n", __func__);
4527 ucontrol->value.integer.value[0] = DAC_LOOP_DAC_HS_flag;
4528 return 0;
4529 }
4530
4531 static int ADC_LOOP_DAC_HS_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4532 {
4533 printk("%s()\n", __func__);
4534 if (ucontrol->value.integer.value[0])
4535 {
4536 DAC_LOOP_DAC_HS_flag = ucontrol->value.integer.value[0];
4537 ADC_LOOP_DAC_Func(AUDIO_ANALOG_DAC_LOOP_DAC_HS_ON);
4538 }
4539 else
4540 {
4541 DAC_LOOP_DAC_HS_flag = ucontrol->value.integer.value[0];
4542 ADC_LOOP_DAC_Func(AUDIO_ANALOG_DAC_LOOP_DAC_HS_OFF);
4543 }
4544 return 0;
4545 }
4546
4547 static bool DAC_LOOP_DAC_HP_flag = false;
4548 static int ADC_LOOP_DAC_HP_Get(struct snd_kcontrol *kcontrol,
4549 struct snd_ctl_elem_value *ucontrol)
4550 {
4551 printk("%s()\n", __func__);
4552 ucontrol->value.integer.value[0] = DAC_LOOP_DAC_HP_flag;
4553 return 0;
4554 }
4555
4556 static int ADC_LOOP_DAC_HP_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4557 {
4558
4559 printk("%s()\n", __func__);
4560 if (ucontrol->value.integer.value[0])
4561 {
4562 DAC_LOOP_DAC_HP_flag = ucontrol->value.integer.value[0];
4563 ADC_LOOP_DAC_Func(AUDIO_ANALOG_DAC_LOOP_DAC_HP_ON);
4564 }
4565 else
4566 {
4567 DAC_LOOP_DAC_HP_flag = ucontrol->value.integer.value[0];
4568 ADC_LOOP_DAC_Func(AUDIO_ANALOG_DAC_LOOP_DAC_HP_OFF);
4569 }
4570 return 0;
4571 }
4572
4573 static bool Voice_Call_DAC_DAC_HS_flag = false;
4574 static int Voice_Call_DAC_DAC_HS_Get(struct snd_kcontrol *kcontrol,
4575 struct snd_ctl_elem_value *ucontrol)
4576 {
4577 printk("%s()\n", __func__);
4578 ucontrol->value.integer.value[0] = Voice_Call_DAC_DAC_HS_flag;
4579 return 0;
4580 }
4581
4582 static int Voice_Call_DAC_DAC_HS_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
4583 {
4584 //K2 TODO
4585 printk("%s()\n", __func__);
4586 return 0;
4587 }
4588
4589 // here start uplink power function
4590 static const char *Pmic_Test_function[] = {"Off", "On"};
4591
4592 static const struct soc_enum Pmic_Test_Enum[] =
4593 {
4594 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Pmic_Test_function), Pmic_Test_function),
4595 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Pmic_Test_function), Pmic_Test_function),
4596 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Pmic_Test_function), Pmic_Test_function),
4597 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Pmic_Test_function), Pmic_Test_function),
4598 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(Pmic_Test_function), Pmic_Test_function),
4599 };
4600
4601 static const struct snd_kcontrol_new mt6331_pmic_Test_controls[] =
4602 {
4603 SOC_ENUM_EXT("SineTable_DAC_HP", Pmic_Test_Enum[0], SineTable_DAC_HP_Get, SineTable_DAC_HP_Set),
4604 SOC_ENUM_EXT("DAC_LOOP_DAC_HS", Pmic_Test_Enum[1], ADC_LOOP_DAC_HS_Get, ADC_LOOP_DAC_HS_Set),
4605 SOC_ENUM_EXT("DAC_LOOP_DAC_HP", Pmic_Test_Enum[2], ADC_LOOP_DAC_HP_Get, ADC_LOOP_DAC_HP_Set),
4606 SOC_ENUM_EXT("Voice_Call_DAC_DAC_HS", Pmic_Test_Enum[3], Voice_Call_DAC_DAC_HS_Get, Voice_Call_DAC_DAC_HS_Set),
4607 SOC_ENUM_EXT("SineTable_UL2", Pmic_Test_Enum[4], SineTable_UL2_Get, SineTable_UL2_Set),
4608 };
4609
4610 static const struct snd_kcontrol_new mt6331_UL_Codec_controls[] =
4611 {
4612 SOC_ENUM_EXT("Audio_ADC_1_Switch", Audio_UL_Enum[0], Audio_ADC1_Get, Audio_ADC1_Set),
4613 SOC_ENUM_EXT("Audio_ADC_2_Switch", Audio_UL_Enum[1], Audio_ADC2_Get, Audio_ADC2_Set),
4614 SOC_ENUM_EXT("Audio_ADC_3_Switch", Audio_UL_Enum[2], Audio_ADC3_Get, Audio_ADC3_Set),
4615 SOC_ENUM_EXT("Audio_ADC_4_Switch", Audio_UL_Enum[3], Audio_ADC4_Get, Audio_ADC4_Set),
4616 SOC_ENUM_EXT("Audio_Preamp1_Switch", Audio_UL_Enum[4], Audio_PreAmp1_Get, Audio_PreAmp1_Set),
4617 SOC_ENUM_EXT("Audio_ADC_1_Sel", Audio_UL_Enum[5], Audio_ADC1_Sel_Get, Audio_ADC1_Sel_Set),
4618 SOC_ENUM_EXT("Audio_ADC_2_Sel", Audio_UL_Enum[6], Audio_ADC2_Sel_Get, Audio_ADC2_Sel_Set),
4619 SOC_ENUM_EXT("Audio_ADC_3_Sel", Audio_UL_Enum[7], Audio_ADC3_Sel_Get, Audio_ADC3_Sel_Set),
4620 SOC_ENUM_EXT("Audio_ADC_4_Sel", Audio_UL_Enum[8], Audio_ADC4_Sel_Get, Audio_ADC4_Sel_Set),
4621 SOC_ENUM_EXT("Audio_PGA1_Setting", Audio_UL_Enum[9], Audio_PGA1_Get, Audio_PGA1_Set),
4622 SOC_ENUM_EXT("Audio_PGA2_Setting", Audio_UL_Enum[10], Audio_PGA2_Get, Audio_PGA2_Set),
4623 SOC_ENUM_EXT("Audio_PGA3_Setting", Audio_UL_Enum[11], Audio_PGA3_Get, Audio_PGA3_Set),
4624 SOC_ENUM_EXT("Audio_PGA4_Setting", Audio_UL_Enum[12], Audio_PGA4_Get, Audio_PGA4_Set),
4625 SOC_ENUM_EXT("Audio_MicSource1_Setting", Audio_UL_Enum[13], Audio_MicSource1_Get, Audio_MicSource1_Set),
4626 SOC_ENUM_EXT("Audio_MicSource2_Setting", Audio_UL_Enum[14], Audio_MicSource2_Get, Audio_MicSource2_Set),
4627 SOC_ENUM_EXT("Audio_MicSource3_Setting", Audio_UL_Enum[15], Audio_MicSource3_Get, Audio_MicSource3_Set),
4628 SOC_ENUM_EXT("Audio_MicSource4_Setting", Audio_UL_Enum[16], Audio_MicSource4_Get, Audio_MicSource4_Set),
4629 SOC_ENUM_EXT("Audio_MIC1_Mode_Select", Audio_UL_Enum[17], Audio_Mic1_Mode_Select_Get, Audio_Mic1_Mode_Select_Set),
4630 SOC_ENUM_EXT("Audio_MIC2_Mode_Select", Audio_UL_Enum[18], Audio_Mic2_Mode_Select_Get, Audio_Mic2_Mode_Select_Set),
4631 SOC_ENUM_EXT("Audio_MIC3_Mode_Select", Audio_UL_Enum[19], Audio_Mic3_Mode_Select_Get, Audio_Mic3_Mode_Select_Set),
4632 SOC_ENUM_EXT("Audio_MIC4_Mode_Select", Audio_UL_Enum[20], Audio_Mic4_Mode_Select_Get, Audio_Mic4_Mode_Select_Set),
4633 SOC_ENUM_EXT("Audio_Mic_Power_Mode", Audio_UL_Enum[21], Audio_Adc_Power_Mode_Get, Audio_Adc_Power_Mode_Set),
4634 SOC_ENUM_EXT("Audio_Vow_ADC_Func_Switch", Audio_UL_Enum[22], Audio_Vow_ADC_Func_Switch_Get, Audio_Vow_ADC_Func_Switch_Set),
4635 SOC_ENUM_EXT("Audio_Preamp2_Switch", Audio_UL_Enum[23], Audio_PreAmp2_Get, Audio_PreAmp2_Set),
4636 SOC_ENUM_EXT("Audio_Vow_Digital_Func_Switch", Audio_UL_Enum[24], Audio_Vow_Digital_Func_Switch_Get, Audio_Vow_Digital_Func_Switch_Set),
4637 SOC_ENUM_EXT("Audio_Vow_MIC_Type_Select", Audio_UL_Enum[25], Audio_Vow_MIC_Type_Select_Get, Audio_Vow_MIC_Type_Select_Set),
4638 SOC_SINGLE_EXT("Audio VOWCFG0 Data", SND_SOC_NOPM, 0, 0x80000, 0, Audio_Vow_Cfg0_Get, Audio_Vow_Cfg0_Set),
4639 SOC_SINGLE_EXT("Audio VOWCFG1 Data", SND_SOC_NOPM, 0, 0x80000, 0, Audio_Vow_Cfg1_Get, Audio_Vow_Cfg1_Set),
4640 SOC_SINGLE_EXT("Audio VOWCFG2 Data", SND_SOC_NOPM, 0, 0x80000, 0, Audio_Vow_Cfg2_Get, Audio_Vow_Cfg2_Set),
4641 SOC_SINGLE_EXT("Audio VOWCFG3 Data", SND_SOC_NOPM, 0, 0x80000, 0, Audio_Vow_Cfg3_Get, Audio_Vow_Cfg3_Set),
4642 SOC_SINGLE_EXT("Audio VOWCFG4 Data", SND_SOC_NOPM, 0, 0x80000, 0, Audio_Vow_Cfg4_Get, Audio_Vow_Cfg4_Set),
4643 SOC_SINGLE_EXT("Audio VOWCFG5 Data", SND_SOC_NOPM, 0, 0x80000, 0, Audio_Vow_Cfg5_Get, Audio_Vow_Cfg5_Set),
4644 SOC_SINGLE_EXT("Audio_VOW_State", SND_SOC_NOPM, 0, 0x80000, 0, Audio_Vow_State_Get, Audio_Vow_State_Set),
4645 };
4646
4647 static const struct snd_soc_dapm_widget mt6331_dapm_widgets[] =
4648 {
4649 /* Outputs */
4650 SND_SOC_DAPM_OUTPUT("EARPIECE"),
4651 SND_SOC_DAPM_OUTPUT("HEADSET"),
4652 SND_SOC_DAPM_OUTPUT("SPEAKER"),
4653 /*
4654 SND_SOC_DAPM_MUX_E("VOICE_Mux_E", SND_SOC_NOPM, 0, 0 , &mt6331_Voice_Switch, codec_enable_rx_bias,
4655 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD |
4656 SND_SOC_DAPM_PRE_REG | SND_SOC_DAPM_POST_REG),
4657 */
4658
4659 };
4660
4661 static const struct snd_soc_dapm_route mtk_audio_map[] =
4662 {
4663 {"VOICE_Mux_E", "Voice Mux", "SPEAKER PGA"},
4664 };
4665
4666 static void mt6331_codec_init_reg(struct snd_soc_codec *codec)
4667 {
4668 printk("%s \n", __func__);
4669 Ana_Set_Reg(TOP_CLKSQ, 0x0 , 0x0001); //Disable CLKSQ 26MHz
4670 Ana_Set_Reg(AUDDEC_ANA_CON8, 0x0002, 0x0002); // disable AUDGLB
4671 Ana_Set_Reg(TOP_CKPDN_CON0_SET, 0x3800, 0x3800); //Turn off AUDNCP_CLKDIV engine clock,Turn off AUD 26M
4672 Ana_Set_Reg(AUDDEC_ANA_CON0, 0xe000 , 0xe000); //Disable HeadphoneL/HeadphoneR/voice short circuit protection
4673 }
4674
4675 void InitCodecDefault(void)
4676 {
4677 printk("%s\n", __func__);
4678 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP1] = 3;
4679 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP2] = 3;
4680 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP3] = 3;
4681 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_MICAMP4] = 3;
4682 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTR] = 8;
4683 mCodec_data->mAudio_Ana_Volume[AUDIO_ANALOG_VOLUME_HPOUTR] = 8;
4684
4685 mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC1] = AUDIO_ANALOG_AUDIOANALOG_INPUT_PREAMP;
4686 mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC2] = AUDIO_ANALOG_AUDIOANALOG_INPUT_PREAMP;
4687 mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC3] = AUDIO_ANALOG_AUDIOANALOG_INPUT_PREAMP;
4688 mCodec_data->mAudio_Ana_Mux[AUDIO_ANALOG_MUX_IN_MIC4] = AUDIO_ANALOG_AUDIOANALOG_INPUT_PREAMP;
4689 }
4690
4691 static int mt6331_codec_probe(struct snd_soc_codec *codec)
4692 {
4693 struct snd_soc_dapm_context *dapm = &codec->dapm;
4694 printk("%s()\n", __func__);
4695 if (mInitCodec == true)
4696 {
4697 return 0;
4698 }
4699
4700 snd_soc_dapm_new_controls(dapm, mt6331_dapm_widgets,
4701 ARRAY_SIZE(mt6331_dapm_widgets));
4702 snd_soc_dapm_add_routes(dapm, mtk_audio_map,
4703 ARRAY_SIZE(mtk_audio_map));
4704
4705 //add codec controls
4706 snd_soc_add_codec_controls(codec, mt6331_snd_controls,
4707 ARRAY_SIZE(mt6331_snd_controls));
4708 snd_soc_add_codec_controls(codec, mt6331_UL_Codec_controls,
4709 ARRAY_SIZE(mt6331_UL_Codec_controls));
4710 snd_soc_add_codec_controls(codec, mt6331_Voice_Switch,
4711 ARRAY_SIZE(mt6331_Voice_Switch));
4712 snd_soc_add_codec_controls(codec, mt6331_pmic_Test_controls,
4713 ARRAY_SIZE(mt6331_pmic_Test_controls));
4714
4715 #ifdef CONFIG_MTK_SPEAKER
4716 snd_soc_add_codec_controls(codec, mt6331_snd_Speaker_controls,
4717 ARRAY_SIZE(mt6331_snd_Speaker_controls));
4718 #endif
4719
4720 snd_soc_add_codec_controls(codec, Audio_snd_auxadc_controls,
4721 ARRAY_SIZE(Audio_snd_auxadc_controls));
4722
4723 // here to set private data
4724 mCodec_data = kzalloc(sizeof(mt6331_Codec_Data_Priv), GFP_KERNEL);
4725 if (!mCodec_data)
4726 {
4727 printk("Failed to allocate private data\n");
4728 return -ENOMEM;
4729 }
4730 snd_soc_codec_set_drvdata(codec, mCodec_data);
4731
4732 memset((void *)mCodec_data , 0 , sizeof(mt6331_Codec_Data_Priv));
4733 mt6331_codec_init_reg(codec);
4734 InitCodecDefault();
4735 mInitCodec = true;
4736
4737 return 0;
4738 }
4739
4740 static int mt6331_codec_remove(struct snd_soc_codec *codec)
4741 {
4742 printk("%s()\n", __func__);
4743 return 0;
4744 }
4745
4746 static unsigned int mt6331_read(struct snd_soc_codec *codec,
4747 unsigned int reg)
4748 {
4749 printk("mt6331_read reg = 0x%x", reg);
4750 Ana_Get_Reg(reg);
4751 return 0;
4752 }
4753
4754 static int mt6331_write(struct snd_soc_codec *codec, unsigned int reg,
4755 unsigned int value)
4756 {
4757 printk("mt6331_write reg = 0x%x value= 0x%x\n", reg, value);
4758 Ana_Set_Reg(reg , value , 0xffffffff);
4759 return 0;
4760 }
4761
4762 static int mt6331_Readable_registers(struct snd_soc_codec *codec,
4763 unsigned int reg)
4764 {
4765 return 1;
4766 }
4767
4768 static int mt6331_volatile_registers(struct snd_soc_codec *codec,
4769 unsigned int reg)
4770 {
4771 return 1;
4772 }
4773
4774 static struct snd_soc_codec_driver soc_mtk_codec =
4775 {
4776 .probe = mt6331_codec_probe,
4777 .remove = mt6331_codec_remove,
4778
4779 .read = mt6331_read,
4780 .write = mt6331_write,
4781
4782 .readable_register = mt6331_Readable_registers,
4783 .volatile_register = mt6331_volatile_registers,
4784
4785 // use add control to replace
4786 //.controls = mt6331_snd_controls,
4787 //.num_controls = ARRAY_SIZE(mt6331_snd_controls),
4788
4789 .dapm_widgets = mt6331_dapm_widgets,
4790 .num_dapm_widgets = ARRAY_SIZE(mt6331_dapm_widgets),
4791 .dapm_routes = mtk_audio_map,
4792 .num_dapm_routes = ARRAY_SIZE(mtk_audio_map),
4793
4794 };
4795
4796 static int mtk_mt6331_codec_dev_probe(struct platform_device *pdev)
4797 {
4798 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64);
4799 if (pdev->dev.dma_mask == NULL)
4800 {
4801 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
4802 }
4803
4804 if (pdev->dev.of_node)
4805 {
4806 dev_set_name(&pdev->dev, "%s", MT_SOC_CODEC_NAME);
4807 }
4808
4809 printk("%s: dev name %s\n", __func__, dev_name(&pdev->dev));
4810 return snd_soc_register_codec(&pdev->dev,
4811 &soc_mtk_codec, mtk_6331_dai_codecs, ARRAY_SIZE(mtk_6331_dai_codecs));
4812 }
4813
4814 static int mtk_mt6331_codec_dev_remove(struct platform_device *pdev)
4815 {
4816 printk("%s:\n", __func__);
4817
4818 snd_soc_unregister_codec(&pdev->dev);
4819 return 0;
4820
4821 }
4822
4823 #ifdef CONFIG_OF
4824 static const struct of_device_id mt_soc_codec_63xx_of_ids[] =
4825 {
4826 { .compatible = "mediatek,mt_soc_codec_63xx", },
4827 {}
4828 };
4829
4830 #if 0
4831 static int Auddrv_getGPIO_info(void)
4832 {
4833 struct device_node *node = NULL;
4834
4835 node = of_find_compatible_node(NULL, NULL, "mediatek,mt_soc_codec_63xx");
4836 if (node)
4837 {
4838 if (of_property_read_u32_index(node, "extspkamp-gpio", 0, &pin_extspkamp))
4839 {
4840 if_config = 0;
4841 printk("extspkamp-gpio get pin fail!!!\n");
4842 return -1;
4843 }
4844 if (of_property_read_u32_index(node, "extspkamp-gpio", 1, &pin_mode_extspkamp))
4845 {
4846 if_config = 0;
4847 printk("extspkamp-gpio get pin_mode fail!!!\n");
4848 return -1;
4849 }
4850
4851 if (of_property_read_u32_index(node, "vowclk-gpio", 0, &pin_vowclk))
4852 {
4853 if_config = 0;
4854 printk("vowclk-gpio get pin fail!!!\n");
4855 return -1;
4856 }
4857 if (of_property_read_u32_index(node, "vowclk-gpio", 1, &pin_mode_vowclk))
4858 {
4859 if_config = 0;
4860 printk("vowclk-gpio get pin_mode fail!!!\n");
4861 return -1;
4862 }
4863
4864 if (of_property_read_u32_index(node, "audmiso-gpio", 0, &pin_audmiso))
4865 {
4866 if_config = 0;
4867 printk("audmiso-gpio get pin fail!!!\n");
4868 return -1;
4869 }
4870 if (of_property_read_u32_index(node, "audmiso-gpio", 1, &pin_mode_audmiso))
4871 {
4872 if_config = 0;
4873 printk("audmiso-gpio get pin_mode fail!!!\n");
4874 return -1;
4875 }
4876 }
4877 else
4878 {
4879 printk("[mt_soc_codec_63xx] node NULL, can't Auddrv_getGPIO_info!!!\n");
4880 return -1;
4881 }
4882 return 0;
4883 }
4884 #endif
4885 #endif
4886
4887 static struct platform_driver mtk_codec_6331_driver =
4888 {
4889 .driver = {
4890 .name = MT_SOC_CODEC_NAME,
4891 .owner = THIS_MODULE,
4892 #ifdef CONFIG_OF
4893 .of_match_table = mt_soc_codec_63xx_of_ids,
4894 #endif
4895 },
4896 .probe = mtk_mt6331_codec_dev_probe,
4897 .remove = mtk_mt6331_codec_dev_remove,
4898 };
4899
4900 #ifndef CONFIG_OF
4901 static struct platform_device *soc_mtk_codec6331_dev;
4902 #endif
4903
4904 static int __init mtk_mt6331_codec_init(void)
4905 {
4906 printk("%s:\n", __func__);
4907 #ifdef CONFIG_OF
4908 //Auddrv_getGPIO_info();
4909 #else
4910 int ret = 0;
4911 soc_mtk_codec6331_dev = platform_device_alloc(MT_SOC_CODEC_NAME, -1);
4912 if (!soc_mtk_codec6331_dev)
4913 {
4914 return -ENOMEM;
4915 }
4916
4917 ret = platform_device_add(soc_mtk_codec6331_dev);
4918 if (ret != 0)
4919 {
4920 platform_device_put(soc_mtk_codec6331_dev);
4921 return ret;
4922 }
4923 #endif
4924 return platform_driver_register(&mtk_codec_6331_driver);
4925 }
4926 module_init(mtk_mt6331_codec_init);
4927
4928 static void __exit mtk_mt6331_codec_exit(void)
4929 {
4930 printk("%s:\n", __func__);
4931
4932 platform_driver_unregister(&mtk_codec_6331_driver);
4933 }
4934
4935 module_exit(mtk_mt6331_codec_exit);
4936
4937 /* Module information */
4938 MODULE_DESCRIPTION("MTK codec driver");
4939 MODULE_LICENSE("GPL v2");
4940
kernel source for telekom puls (alcatel/mediatek)