sound/soc/mediatek/mt_soc_audio_v1/mt_soc_pcm_i2s0_awb.c

   1 /*
   2  * Copyright (C) 2007 The Android Open Source Project
   3  *
   4  * Licensed under the Apache License, Version 2.0 (the "License");
   5  * you may not use this file except in compliance with the License.
   6  * You may obtain a copy of the License at
   7  *
   8  *      http://www.apache.org/licenses/LICENSE-2.0
   9  *
  10  * Unless required by applicable law or agreed to in writing, software
  11  * distributed under the License is distributed on an "AS IS" BASIS,
  12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13  * See the License for the specific language governing permissions and
  14  * limitations under the License.
  15  */
  16 /*******************************************************************************
  17  *
  18  * Filename:
  19  * ---------
  20  *   mtk_pcm_i2s0_awb.c
  21  *
  22  * Project:
  23  * --------
  24  *   Audio Driver Kernel Function
  25  *
  26  * Description:
  27  * ------------
  28  *   Audio i2s0 to  awb capture
  29  *
  30  * Author:
  31  * -------
  32  * Chipeng Chang
  33  *
  34  *------------------------------------------------------------------------------
  35  * $Revision: #1 $
  36  * $Modtime:$
  37  * $Log:$
  38  *
  39  *
  40  *******************************************************************************/
  41
  42
  43 /*****************************************************************************
  44  *                     C O M P I L E R   F L A G S
  45  *****************************************************************************/
  46
  47
  48 /*****************************************************************************
  49  *                E X T E R N A L   R E F E R E N C E S
  50  *****************************************************************************/
  51
  52 #include <linux/dma-mapping.h>
  53 #include "AudDrv_Common.h"
  54 #include "AudDrv_Def.h"
  55 #include "AudDrv_Afe.h"
  56 #include "AudDrv_Ana.h"
  57 #include "AudDrv_Clk.h"
  58 #include "AudDrv_Kernel.h"
  59 #include "mt_soc_afe_control.h"
  60 #include "mt_soc_pcm_common.h"
  61
  62 //#define DUMP_HWGAIN1_AWB
  63
  64 //information about
  65 static AFE_MEM_CONTROL_T  *I2S0_AWB_Control_context = NULL;
  66 static struct snd_dma_buffer *Awb_Capture_dma_buf  = NULL;
  67
  68 static DEFINE_SPINLOCK(auddrv_Dl1AWBInCtl_lock);
  69
  70 /*
  71  *    function implementation
  72  */
  73 static void StartAudioI2S0AWBHardware(struct snd_pcm_substream *substream);
  74 static void StopAudioI2S0AWBHardware(struct snd_pcm_substream *substream);
  75 static int mtk_i2s0_awb_probe(struct platform_device *pdev);
  76 static int mtk_i2s0_awb_pcm_close(struct snd_pcm_substream *substream);
  77 static int mtk_asoc_i2s0_awb_pcm_new(struct snd_soc_pcm_runtime *rtd);
  78 static int mtk_i2s0_dl1_awb_probe(struct snd_soc_platform *platform);
  79
  80 static struct snd_pcm_hardware mtk_I2S0_awb_hardware =
  81 {
  82     .info = (SNDRV_PCM_INFO_INTERLEAVED),
  83     .formats =      SND_SOC_STD_MT_FMTS,
  84     .rates =        SOC_HIGH_USE_RATE,
  85     .rate_min =     SOC_HIGH_USE_RATE_MIN,
  86     .rate_max =     SOC_HIGH_USE_RATE_MAX,
  87     .channels_min =     SOC_NORMAL_USE_CHANNELS_MIN,
  88     .channels_max =     SOC_NORMAL_USE_CHANNELS_MAX,
  89     .buffer_bytes_max = AWB_MAX_BUFFER_SIZE,
  90     .period_bytes_max = AWB_MAX_BUFFER_SIZE,
  91     .periods_min =     AWB_MIN_PERIOD_SIZE,
  92     .periods_max =      AWB_MAX_PERIOD_SIZE,
  93     .fifo_size =        0,
  94 };
  95
  96 static void StopAudioI2S0AWBHardware(struct snd_pcm_substream *substream)
  97 {
  98     printk("StopAudioI2S0AWBHardware \n");
  99
 100     SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_2, false);
 101     SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_AWB, false);
 102
 103     // here to set interrupt
 104     SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, false);
 105     // stop I2S
 106     Afe_Set_Reg(AFE_I2S_CON, 0x0, 0x1);
 107
 108     // here to turn off digital part
 109 #ifdef DUMP_HWGAIN1_AWB
 110     SetConnection(Soc_Aud_InterCon_DisConnect, Soc_Aud_InterConnectionInput_I10, Soc_Aud_InterConnectionOutput_O05);
 111     SetConnection(Soc_Aud_InterCon_DisConnect, Soc_Aud_InterConnectionInput_I11, Soc_Aud_InterConnectionOutput_O06);
 112 #else
 113     SetConnection(Soc_Aud_InterCon_DisConnect, Soc_Aud_InterConnectionInput_I00, Soc_Aud_InterConnectionOutput_O05);
 114     SetConnection(Soc_Aud_InterCon_DisConnect, Soc_Aud_InterConnectionInput_I01, Soc_Aud_InterConnectionOutput_O06);
 115 #endif
 116     EnableAfe(false);
 117 }
 118
 119 static void StartAudioI2S0AWBHardware(struct snd_pcm_substream *substream)
 120 {
 121     struct snd_pcm_runtime *runtime = substream->runtime;
 122
 123     uint32 Audio_I2S_Dac = 0;
 124     uint32 MclkDiv0 = 0;
 125
 126     const bool bEnablePhaseShiftFix = true;
 127
 128     printk("StartAudioI2S0AWBHardware \n");
 129
 130
 131     MclkDiv0 = SetCLkMclk(Soc_Aud_I2S0, runtime->rate); //select I2S
 132     SetCLkBclk(MclkDiv0,  runtime->rate, runtime->channels, Soc_Aud_I2S_WLEN_WLEN_32BITS);
 133
 134     // 2nd I2S In
 135     SetSampleRate(Soc_Aud_Digital_Block_MEM_I2S,  runtime->rate);
 136
 137     Audio_I2S_Dac |= (bEnablePhaseShiftFix << 31);
 138     Audio_I2S_Dac |= (Soc_Aud_I2S_IN_PAD_SEL_I2S_IN_FROM_IO_MUX << 28);//I2S in from io_mux
 139     Audio_I2S_Dac |= Soc_Aud_LOW_JITTER_CLOCK << 12 ; //Low jitter mode
 140     Audio_I2S_Dac |= (Soc_Aud_INV_LRCK_NO_INVERSE << 5);
 141     Audio_I2S_Dac |= (Soc_Aud_I2S_FORMAT_I2S << 3);
 142     Audio_I2S_Dac |= (Soc_Aud_I2S_WLEN_WLEN_32BITS << 1);
 143     Afe_Set_Reg(AFE_I2S_CON, Audio_I2S_Dac | 0x1, MASK_ALL);
 144
 145     // here to set interrupt
 146     SetIrqMcuCounter(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, substream->runtime->period_size);
 147     SetIrqMcuSampleRate(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, substream->runtime->rate);
 148     SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, true);
 149
 150     SetSampleRate(Soc_Aud_Digital_Block_MEM_AWB, substream->runtime->rate);
 151     SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_AWB, true);
 152     SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_2, true);
 153
 154     // here to turn off digital part
 155 #ifdef DUMP_HWGAIN1_AWB
 156         uint32 REG420 = 0;
 157         SetConnection(Soc_Aud_InterCon_DisConnect, Soc_Aud_InterConnectionInput_I00, Soc_Aud_InterConnectionOutput_O05);
 158         SetConnection(Soc_Aud_InterCon_DisConnect, Soc_Aud_InterConnectionInput_I01, Soc_Aud_InterConnectionOutput_O06);
 159         printk("%s() Soc_Aud_InterCon_Connection  I10  O5\n",  __func__);
 160         SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I10, Soc_Aud_InterConnectionOutput_O05);
 161         printk("%s() Soc_Aud_InterCon_Connection  I11  O6\n",  __func__);
 162         SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I11, Soc_Aud_InterConnectionOutput_O06);
 163
 164
 165         REG420 = Afe_Get_Reg(AFE_GAIN1_CONN);
 166         printk("%s() AFE_GAIN1_CONN (0X420) =0x%x\n",  __func__, REG420);
 167 #else
 168         SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I00, Soc_Aud_InterConnectionOutput_O05);
 169         SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I01, Soc_Aud_InterConnectionOutput_O06);
 170 #endif
 171
 172     EnableAfe(true);
 173 }
 174
 175 static int mtk_i2s0_awb_pcm_prepare(struct snd_pcm_substream *substream)
 176 {
 177     printk("mtk_i2s0_awb_pcm_prepare substream->rate = %d  substream->channels = %d \n", substream->runtime->rate, substream->runtime->channels);
 178     return 0;
 179 }
 180
 181 static int mtk_i2s0_awb_alsa_stop(struct snd_pcm_substream *substream)
 182 {
 183     //AFE_BLOCK_T *Awb_Block = &(I2S0_AWB_Control_context->rBlock);
 184     printk("mtk_i2s0_awb_alsa_stop \n");
 185     StopAudioI2S0AWBHardware(substream);
 186     RemoveMemifSubStream(Soc_Aud_Digital_Block_MEM_AWB,substream);
 187     return 0;
 188 }
 189
 190 static kal_int32 Previous_Hw_cur = 0;
 191 static snd_pcm_uframes_t mtk_i2s0_awb_pcm_pointer(struct snd_pcm_substream *substream)
 192 {
 193     kal_int32 HW_memory_index = 0;
 194     kal_int32 HW_Cur_ReadIdx = 0;
 195     kal_uint32 Frameidx =0;
 196     AFE_BLOCK_T *Awb_Block = &(I2S0_AWB_Control_context->rBlock);
 197     PRINTK_AUD_AWB("mtk_i2s0_awb_pcm_pointer Awb_Block->u4WriteIdx;= 0x%x \n",Awb_Block->u4WriteIdx);
 198     if (GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_AWB) == true)
 199     {
 200         // get total bytes to copysinewavetohdmi
 201         Frameidx =audio_bytes_to_frame(substream , Awb_Block->u4WriteIdx);
 202         return Frameidx;
 203
 204         HW_Cur_ReadIdx = Align64ByteSize(Afe_Get_Reg(AFE_AWB_CUR));
 205         if (HW_Cur_ReadIdx == 0)
 206         {
 207             printk("[Auddrv] mtk_awb_pcm_pointer  HW_Cur_ReadIdx ==0 \n");
 208             HW_Cur_ReadIdx = Awb_Block->pucPhysBufAddr;
 209         }
 210         HW_memory_index = (HW_Cur_ReadIdx - Awb_Block->pucPhysBufAddr);
 211         Previous_Hw_cur = HW_memory_index;
 212         PRINTK_AUD_AWB("[Auddrv] mtk_i2s0_awb_pcm_pointer =0x%x HW_memory_index = 0x%x\n", HW_Cur_ReadIdx, HW_memory_index);
 213         return audio_bytes_to_frame(substream,Previous_Hw_cur);
 214     }
 215     return 0;
 216 }
 217
 218
 219 static void SetAWBBuffer(struct snd_pcm_substream *substream,
 220                          struct snd_pcm_hw_params *hw_params)
 221 {
 222     AFE_BLOCK_T *pblock = &I2S0_AWB_Control_context->rBlock;
 223     struct snd_pcm_runtime *runtime = substream->runtime;
 224     printk("SetAWBBuffer\n");
 225     pblock->pucPhysBufAddr =  runtime->dma_addr;
 226     pblock->pucVirtBufAddr =  runtime->dma_area;
 227     pblock->u4BufferSize = runtime->dma_bytes;
 228     pblock->u4SampleNumMask = 0x001f;  // 32 byte align
 229     pblock->u4WriteIdx     = 0;
 230     pblock->u4DMAReadIdx    = 0;
 231     pblock->u4DataRemained  = 0;
 232     pblock->u4fsyncflag     = false;
 233     pblock->uResetFlag      = true;
 234     printk("dma_bytes = %d dma_area = %p dma_addr = 0x%x\n",
 235            pblock->u4BufferSize, pblock->pucVirtBufAddr, pblock->pucPhysBufAddr);
 236     // set sram address top hardware
 237     Afe_Set_Reg(AFE_AWB_BASE , pblock->pucPhysBufAddr , 0xffffffff);
 238     Afe_Set_Reg(AFE_AWB_END  , pblock->pucPhysBufAddr + (pblock->u4BufferSize - 1), 0xffffffff);
 239
 240 }
 241
 242 static int mtk_i2s0_awb_pcm_hw_params(struct snd_pcm_substream *substream,
 243                                      struct snd_pcm_hw_params *hw_params)
 244 {
 245     struct snd_pcm_runtime *runtime = substream->runtime;
 246     struct snd_dma_buffer *dma_buf = &substream->dma_buffer;
 247     int ret = 0;
 248
 249     printk("mtk_i2s0_awb_pcm_hw_params \n");
 250
 251     dma_buf->dev.type = SNDRV_DMA_TYPE_DEV;
 252     dma_buf->dev.dev = substream->pcm->card->dev;
 253     dma_buf->private_data = NULL;
 254
 255     if (Awb_Capture_dma_buf->area)
 256     {
 257         printk("mtk_i2s0_awb_pcm_hw_params Awb_Capture_dma_buf->area\n");
 258         runtime->dma_bytes = params_buffer_bytes(hw_params);
 259         runtime->dma_area = Awb_Capture_dma_buf->area;
 260         runtime->dma_addr = Awb_Capture_dma_buf->addr;
 261     }
 262     else
 263     {
 264         printk("mtk_i2s0_awb_pcm_hw_params snd_pcm_lib_malloc_pages\n");
 265         ret =  snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 266     }
 267     printk("mtk_i2s0_awb_pcm_hw_params dma_bytes = %zu dma_area = %p dma_addr = 0x%lx\n",
 268            runtime->dma_bytes, runtime->dma_area, (long)runtime->dma_addr);
 269
 270     printk("runtime->hw.buffer_bytes_max = %zu \n", runtime->hw.buffer_bytes_max);
 271     SetAWBBuffer(substream, hw_params);
 272
 273     printk("dma_bytes = %zu dma_area = %p dma_addr = 0x%lx\n",
 274            substream->runtime->dma_bytes, substream->runtime->dma_area, (long)substream->runtime->dma_addr);
 275     return ret;
 276 }
 277
 278 static int mtk_i2s0_capture_pcm_hw_free(struct snd_pcm_substream *substream)
 279 {
 280     printk("mtk_i2s0_capture_pcm_hw_free \n");
 281     if (Awb_Capture_dma_buf->area)
 282     {
 283         return 0;
 284     }
 285     else
 286     {
 287         return snd_pcm_lib_free_pages(substream);
 288     }
 289 }
 290
 291 static struct snd_pcm_hw_constraint_list dl1_awb_constraints_sample_rates =
 292 {
 293     .count = ARRAY_SIZE(soc_high_supported_sample_rates),
 294     .list = soc_high_supported_sample_rates,
 295 };
 296
 297 static int mtk_i2s0_awb_pcm_open(struct snd_pcm_substream *substream)
 298 {
 299     struct snd_pcm_runtime *runtime = substream->runtime;
 300     int ret = 0;
 301     printk("mtk_i2s0_awb_pcm_open\n");
 302     I2S0_AWB_Control_context = Get_Mem_ControlT(Soc_Aud_Digital_Block_MEM_AWB);
 303     runtime->hw = mtk_I2S0_awb_hardware;
 304     memcpy((void *)(&(runtime->hw)), (void *)&mtk_I2S0_awb_hardware , sizeof(struct snd_pcm_hardware));
 305
 306     ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
 307                                      &dl1_awb_constraints_sample_rates);
 308     ret = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
 309
 310     if (ret < 0)
 311     {
 312         printk("snd_pcm_hw_constraint_integer failed\n");
 313     }
 314
 315     // here open audio clocks
 316     AudDrv_Clk_On();
 317
 318     //print for hw pcm information
 319     printk("mtk_i2s0_awb_pcm_open runtime rate = %d channels = %d \n", runtime->rate, runtime->channels);
 320     runtime->hw.info |= SNDRV_PCM_INFO_INTERLEAVED;
 321     runtime->hw.info |= SNDRV_PCM_INFO_NONINTERLEAVED;
 322     runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
 323
 324     if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 325     {
 326         printk("SNDRV_PCM_STREAM_CAPTURE \n");
 327     }
 328     else
 329     {
 330         return -1;
 331     }
 332
 333     if (ret < 0)
 334     {
 335         printk("mtk_i2s0_awb_pcm_close\n");
 336         mtk_i2s0_awb_pcm_close(substream);
 337         return ret;
 338     }
 339     AudDrv_Emi_Clk_On();
 340     printk("mtk_i2s0_awb_pcm_open return\n");
 341     return 0;
 342 }
 343
 344 static int mtk_i2s0_awb_pcm_close(struct snd_pcm_substream *substream)
 345 {
 346     AudDrv_Emi_Clk_Off();
 347     return 0;
 348 }
 349
 350 static int mtk_i2s0_awb_alsa_start(struct snd_pcm_substream *substream)
 351 {
 352     printk("mtk_i2s0_awb_alsa_start \n");
 353     SetMemifSubStream(Soc_Aud_Digital_Block_MEM_AWB, substream);
 354     StartAudioI2S0AWBHardware(substream);
 355     return 0;
 356 }
 357
 358 static int mtk_i2s0_awb_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 359 {
 360     printk("mtk_i2s0_awb_pcm_trigger cmd = %d\n", cmd);
 361
 362     switch (cmd)
 363     {
 364         case SNDRV_PCM_TRIGGER_START:
 365         case SNDRV_PCM_TRIGGER_RESUME:
 366             return mtk_i2s0_awb_alsa_start(substream);
 367         case SNDRV_PCM_TRIGGER_STOP:
 368         case SNDRV_PCM_TRIGGER_SUSPEND:
 369             return mtk_i2s0_awb_alsa_stop(substream);
 370     }
 371     return -EINVAL;
 372 }
 373
 374 static bool CheckNullPointer(void *pointer)
 375 {
 376     if (pointer == NULL)
 377     {
 378         printk("CheckNullPointer pointer = NULL");
 379         return true;
 380     }
 381     return false;
 382 }
 383
 384 static int mtk_i2s0_awb_pcm_copy(struct snd_pcm_substream *substream,
 385                                 int channel, snd_pcm_uframes_t pos,
 386                                 void __user *dst, snd_pcm_uframes_t count)
 387 {
 388     AFE_MEM_CONTROL_T *pAWB_MEM_ConTrol = NULL;
 389     AFE_BLOCK_T  *Awb_Block = NULL;
 390     char *Read_Data_Ptr = (char *)dst;
 391     ssize_t DMA_Read_Ptr = 0 , read_size = 0, read_count = 0;
 392     unsigned long flags;
 393
 394     // get total bytes to copy
 395     count = Align64ByteSize(audio_frame_to_bytes(substream , count));
 396
 397     printk("%s  pos = %lu count = %lu\n ", __func__, pos, count);
 398
 399     // check which memif nned to be write
 400     pAWB_MEM_ConTrol = I2S0_AWB_Control_context;
 401     Awb_Block = &(pAWB_MEM_ConTrol->rBlock);
 402
 403     if (pAWB_MEM_ConTrol == NULL)
 404     {
 405         printk("cannot find MEM control !!!!!!!\n");
 406         msleep(50);
 407         return 0;
 408     }
 409
 410     if (Awb_Block->u4BufferSize <= 0)
 411     {
 412         msleep(50);
 413         return 0;
 414     }
 415
 416     if (CheckNullPointer((void *)Awb_Block->pucVirtBufAddr))
 417     {
 418         printk("CheckNullPointer  pucVirtBufAddr = %p\n", Awb_Block->pucVirtBufAddr);
 419         return 0;
 420     }
 421
 422     spin_lock_irqsave(&auddrv_Dl1AWBInCtl_lock, flags);
 423     if (Awb_Block->u4DataRemained >  Awb_Block->u4BufferSize)
 424     {
 425         printk("AudDrv_MEMIF_Read u4DataRemained=%x > u4BufferSize=%x" , Awb_Block->u4DataRemained, Awb_Block->u4BufferSize);
 426         Awb_Block->u4DataRemained = 0;
 427         Awb_Block->u4DMAReadIdx   = Awb_Block->u4WriteIdx;
 428     }
 429     if (count >  Awb_Block->u4DataRemained)
 430     {
 431         read_size = Awb_Block->u4DataRemained;
 432     }
 433     else
 434     {
 435         read_size = count;
 436     }
 437
 438     DMA_Read_Ptr = Awb_Block->u4DMAReadIdx;
 439     spin_unlock_irqrestore(&auddrv_Dl1AWBInCtl_lock, flags);
 440
 441     PRINTK_AUD_AWB("AudDrv_MEMIF_Read finish0, read_count:0x%x, read_size:0x%x, u4DataRemained:0x%x, u4DMAReadIdx:0x%x, u4WriteIdx:0x%x \r\n",
 442            read_count, read_size, Awb_Block->u4DataRemained, Awb_Block->u4DMAReadIdx, Awb_Block->u4WriteIdx);
 443
 444     if (DMA_Read_Ptr + read_size < Awb_Block->u4BufferSize)
 445     {
 446         if (DMA_Read_Ptr != Awb_Block->u4DMAReadIdx)
 447         {
 448             printk("AudDrv_MEMIF_Read 1, read_size:%zu, DataRemained:0x%x, DMA_Read_Ptr:%zu, DMAReadIdx:0x%x \r\n",
 449                    read_size, Awb_Block->u4DataRemained, DMA_Read_Ptr, Awb_Block->u4DMAReadIdx);
 450         }
 451
 452         if (copy_to_user((void __user *)Read_Data_Ptr, (Awb_Block->pucVirtBufAddr + DMA_Read_Ptr), read_size))
 453         {
 454
 455             printk("AudDrv_MEMIF_Read Fail 1 copy to user Read_Data_Ptr:%p, pucVirtBufAddr:%p, u4DMAReadIdx:0x%x, DMA_Read_Ptr:%zu,read_size:%zu", Read_Data_Ptr, Awb_Block->pucVirtBufAddr, Awb_Block->u4DMAReadIdx, DMA_Read_Ptr, read_size);
 456             return 0;
 457         }
 458
 459         read_count += read_size;
 460         spin_lock(&auddrv_Dl1AWBInCtl_lock);
 461         Awb_Block->u4DataRemained -= read_size;
 462         Awb_Block->u4DMAReadIdx += read_size;
 463         Awb_Block->u4DMAReadIdx %= Awb_Block->u4BufferSize;
 464         DMA_Read_Ptr = Awb_Block->u4DMAReadIdx;
 465         spin_unlock(&auddrv_Dl1AWBInCtl_lock);
 466
 467         Read_Data_Ptr += read_size;
 468         count -= read_size;
 469
 470         PRINTK_AUD_AWB("AudDrv_MEMIF_Read finish1, copy size:0x%x, u4DMAReadIdx:0x%x, u4WriteIdx:0x%x, u4DataRemained:0x%x \r\n",
 471                read_size, Awb_Block->u4DMAReadIdx, Awb_Block->u4WriteIdx, Awb_Block->u4DataRemained);
 472     }
 473
 474     else
 475     {
 476         uint32 size_1 = Awb_Block->u4BufferSize - DMA_Read_Ptr;
 477         uint32 size_2 = read_size - size_1;
 478
 479         if (DMA_Read_Ptr != Awb_Block->u4DMAReadIdx)
 480         {
 481
 482             printk("AudDrv_MEMIF_Read 2, read_size1:0x%x, DataRemained:0x%x, DMA_Read_Ptr:%zu, DMAReadIdx:0x%x \r\n",
 483                    size_1, Awb_Block->u4DataRemained, DMA_Read_Ptr, Awb_Block->u4DMAReadIdx);
 484         }
 485         if (copy_to_user((void __user *)Read_Data_Ptr, (Awb_Block->pucVirtBufAddr + DMA_Read_Ptr), size_1))
 486         {
 487
 488             printk("AudDrv_MEMIF_Read Fail 2 copy to user Read_Data_Ptr:%p, pucVirtBufAddr:%p, u4DMAReadIdx:0x%x, DMA_Read_Ptr:%zu,read_size:%zu",
 489                    Read_Data_Ptr, Awb_Block->pucVirtBufAddr, Awb_Block->u4DMAReadIdx, DMA_Read_Ptr, read_size);
 490             return 0;
 491         }
 492
 493         read_count += size_1;
 494         spin_lock(&auddrv_Dl1AWBInCtl_lock);
 495         Awb_Block->u4DataRemained -= size_1;
 496         Awb_Block->u4DMAReadIdx += size_1;
 497         Awb_Block->u4DMAReadIdx %= Awb_Block->u4BufferSize;
 498         DMA_Read_Ptr = Awb_Block->u4DMAReadIdx;
 499         spin_unlock(&auddrv_Dl1AWBInCtl_lock);
 500
 501         PRINTK_AUD_AWB("AudDrv_MEMIF_Read finish2, copy size_1:0x%x, u4DMAReadIdx:0x%x, u4WriteIdx:0x%x, u4DataRemained:0x%x \r\n",
 502                size_1, Awb_Block->u4DMAReadIdx, Awb_Block->u4WriteIdx, Awb_Block->u4DataRemained);
 503
 504         if (DMA_Read_Ptr != Awb_Block->u4DMAReadIdx)
 505         {
 506
 507             printk("AudDrv_AWB_Read 3, read_size2:%x, DataRemained:%x, DMA_Read_Ptr:%zu, DMAReadIdx:%x \r\n",
 508                    size_2, Awb_Block->u4DataRemained, DMA_Read_Ptr, Awb_Block->u4DMAReadIdx);
 509         }
 510         if (copy_to_user((void __user *)(Read_Data_Ptr + size_1), (Awb_Block->pucVirtBufAddr + DMA_Read_Ptr), size_2))
 511         {
 512
 513             printk("AudDrv_MEMIF_Read Fail 3 copy to user Read_Data_Ptr:%p, pucVirtBufAddr:%p, u4DMAReadIdx:0x%x , DMA_Read_Ptr:%zu, read_size:%zu", Read_Data_Ptr, Awb_Block->pucVirtBufAddr, Awb_Block->u4DMAReadIdx, DMA_Read_Ptr, read_size);
 514             return read_count << 2;
 515         }
 516
 517         read_count += size_2;
 518         spin_lock(&auddrv_Dl1AWBInCtl_lock);
 519         Awb_Block->u4DataRemained -= size_2;
 520         Awb_Block->u4DMAReadIdx += size_2;
 521         DMA_Read_Ptr = Awb_Block->u4DMAReadIdx;
 522         spin_unlock(&auddrv_Dl1AWBInCtl_lock);
 523
 524         count -= read_size;
 525         Read_Data_Ptr += read_size;
 526
 527         PRINTK_AUD_AWB("AudDrv_MEMIF_Read finish3, copy size_2:0x%x, u4DMAReadIdx:0x%x, u4WriteIdx:0x%x u4DataRemained:0x%x \r\n",
 528                size_2, Awb_Block->u4DMAReadIdx, Awb_Block->u4WriteIdx, Awb_Block->u4DataRemained);
 529     }
 530
 531     return read_count >> 2;
 532 }
 533
 534 static int mtk_capture_pcm_silence(struct snd_pcm_substream *substream,
 535                                    int channel, snd_pcm_uframes_t pos,
 536                                    snd_pcm_uframes_t count)
 537 {
 538     printk("dummy_pcm_silence \n");
 539     return 0; /* do nothing */
 540 }
 541
 542
 543 static void *dummy_page[2];
 544
 545 static struct page *mtk_i2s0_capture_pcm_page(struct snd_pcm_substream *substream,
 546                                              unsigned long offset)
 547 {
 548     printk("dummy_pcm_page \n");
 549     return virt_to_page(dummy_page[substream->stream]); /* the same page */
 550 }
 551
 552
 553 static struct snd_pcm_ops mtk_i2s0_awb_ops =
 554 {
 555     .open =     mtk_i2s0_awb_pcm_open,
 556     .close =    mtk_i2s0_awb_pcm_close,
 557     .ioctl =    snd_pcm_lib_ioctl,
 558     .hw_params =    mtk_i2s0_awb_pcm_hw_params,
 559     .hw_free =  mtk_i2s0_capture_pcm_hw_free,
 560     .prepare =  mtk_i2s0_awb_pcm_prepare,
 561     .trigger =  mtk_i2s0_awb_pcm_trigger,
 562     .pointer =  mtk_i2s0_awb_pcm_pointer,
 563     .copy =     mtk_i2s0_awb_pcm_copy,
 564     .silence =  mtk_capture_pcm_silence,
 565     .page =     mtk_i2s0_capture_pcm_page,
 566 };
 567
 568 static struct snd_soc_platform_driver mtk_soc_platform =
 569 {
 570     .ops        = &mtk_i2s0_awb_ops,
 571     .pcm_new    = mtk_asoc_i2s0_awb_pcm_new,
 572     .probe      = mtk_i2s0_dl1_awb_probe,
 573 };
 574
 575 static int mtk_i2s0_awb_probe(struct platform_device *pdev)
 576 {
 577     printk("mtk_i2s0_awb_probe\n");
 578
 579     pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64);
 580     if (!pdev->dev.dma_mask)
 581     {
 582         pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
 583     }
 584
 585     if (pdev->dev.of_node)
 586     {
 587         dev_set_name(&pdev->dev, "%s", MT_SOC_I2S0_AWB_PCM);
 588     }
 589
 590     printk("%s: dev name %s\n", __func__, dev_name(&pdev->dev));
 591     return snd_soc_register_platform(&pdev->dev,
 592                                      &mtk_soc_platform);
 593 }
 594
 595 static int mtk_asoc_i2s0_awb_pcm_new(struct snd_soc_pcm_runtime *rtd)
 596 {
 597     printk("mtk_asoc_i2s0_awb_pcm_new \n");
 598     return 0;
 599 }
 600
 601 static int mtk_i2s0_dl1_awb_probe(struct snd_soc_platform *platform)
 602 {
 603     printk("mtk_i2s0_dl1_awb_probe\n");
 604     AudDrv_Allocate_mem_Buffer(platform->dev, Soc_Aud_Digital_Block_MEM_AWB, AWB_MAX_BUFFER_SIZE);
 605     Awb_Capture_dma_buf =  Get_Mem_Buffer(Soc_Aud_Digital_Block_MEM_AWB);
 606     return 0;
 607 }
 608
 609 static int mtk_dl1_awb_remove(struct platform_device *pdev)
 610 {
 611     pr_debug("%s\n", __func__);
 612     snd_soc_unregister_platform(&pdev->dev);
 613     return 0;
 614 }
 615
 616 #ifdef CONFIG_OF
 617 static const struct of_device_id mt_soc_pcm_i2s0_awb_of_ids[] =
 618 {
 619     { .compatible = "mediatek,mt_soc_pcm_i2s0_awb", },
 620     {}
 621 };
 622 #endif
 623
 624 static struct platform_driver mtk_i2s0_awb_capture_driver =
 625 {
 626     .driver = {
 627         .name = MT_SOC_I2S0_AWB_PCM,
 628         .owner = THIS_MODULE,
 629         #ifdef CONFIG_OF
 630         .of_match_table = mt_soc_pcm_i2s0_awb_of_ids,
 631         #endif
 632     },
 633     .probe = mtk_i2s0_awb_probe,
 634     .remove = mtk_dl1_awb_remove,
 635 };
 636
 637 #ifndef CONFIG_OF
 638 static struct platform_device *soc_i2s0_awb_capture_dev;
 639 #endif
 640
 641 static int __init mtk_soc_i2s0_awb_platform_init(void)
 642 {
 643     int ret = 0;
 644     printk("%s\n", __func__);
 645         #ifndef CONFIG_OF
 646     soc_i2s0_awb_capture_dev = platform_device_alloc(MT_SOC_I2S0_AWB_PCM, -1);
 647     if (!soc_i2s0_awb_capture_dev)
 648     {
 649         return -ENOMEM;
 650     }
 651
 652     ret = platform_device_add(soc_i2s0_awb_capture_dev);
 653     if (ret != 0)
 654     {
 655         platform_device_put(soc_i2s0_awb_capture_dev);
 656         return ret;
 657     }
 658         #endif
 659     ret = platform_driver_register(&mtk_i2s0_awb_capture_driver);
 660     return ret;
 661 }
 662
 663 static void __exit mtk_soc_i2s0_awb_platform_exit(void)
 664 {
 665     printk("%s\n", __func__);
 666     platform_driver_unregister(&mtk_i2s0_awb_capture_driver);
 667 }
 668
 669 module_init(mtk_soc_i2s0_awb_platform_init);
 670 module_exit(mtk_soc_i2s0_awb_platform_exit);
 671
 672 MODULE_DESCRIPTION("I2S0 AWB module platform driver");
 673 MODULE_LICENSE("GPL");
 674
 675