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import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / mediatek / mt_soc_audio_v1 / mt_soc_afe_control.c
1 /*
2 * Copyright (C) 2007 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16 /*******************************************************************************
17 *
18 * Filename:
19 * ---------
20 * mt_sco_afe_control.c
21 *
22 * Project:
23 * --------
24 * MT6583 Audio Driver Kernel Function
25 *
26 * Description:
27 * ------------
28 * Audio register
29 *
30 * Author:
31 * -------
32 * Chipeng Chang
33 *
34 *------------------------------------------------------------------------------
35 * $Revision: #1 $
36 * $Modtime:$
37 * $Log:$
38 *
39 *
40 *******************************************************************************/
41
42
43 /*****************************************************************************
44 * C O M P I L E R F L A G S
45 *****************************************************************************/
46
47
48 /*****************************************************************************
49 * E X T E R N A L R E F E R E N C E S
50 *****************************************************************************/
51
52 #include "AudDrv_Def.h"
53 #include "AudDrv_Afe.h"
54 #include "AudDrv_Ana.h"
55 #include "AudDrv_Clk.h"
56 #include "mt_soc_digital_type.h"
57 #include "AudDrv_Def.h"
58 #include "AudDrv_Kernel.h"
59 #include "mt_soc_afe_control.h"
60 #include "mt_soc_afe_connection.h"
61
62 #include <linux/kernel.h>
63 #include <linux/module.h>
64 #include <linux/init.h>
65 #include <linux/device.h>
66 #include <linux/slab.h>
67 #include <linux/fs.h>
68 #include <linux/completion.h>
69 #include <linux/mm.h>
70 #include <linux/delay.h>
71 #include <linux/interrupt.h>
72 #include <linux/dma-mapping.h>
73 #include <linux/vmalloc.h>
74 #include <linux/platform_device.h>
75 #include <linux/miscdevice.h>
76 #include <linux/wait.h>
77 #include <linux/spinlock.h>
78 #include <linux/sched.h>
79 #include <linux/wakelock.h>
80 #include <linux/semaphore.h>
81 #include <linux/jiffies.h>
82 #include <linux/proc_fs.h>
83 #include <linux/string.h>
84 #include <linux/mutex.h>
85 #include <linux/xlog.h>
86 #include <mach/irqs.h>
87 #include <asm/uaccess.h>
88 #include <asm/irq.h>
89 #include <asm/io.h>
90 #include <mach/mt_reg_base.h>
91 #include <asm/div64.h>
92 #include <linux/aee.h>
93 #include <mach/pmic_mt6320_sw.h>
94 #include <mach/upmu_common.h>
95 #include <mach/upmu_hw.h>
96 #include <mach/mt_gpio.h>
97 #include <mach/mt_typedefs.h>
98
99 #include <linux/clk.h>
100 #include <linux/delay.h>
101 #include <linux/gpio.h>
102 #include <linux/platform_device.h>
103 #include <linux/slab.h>
104 #include <sound/core.h>
105 #include <sound/soc.h>
106 #include <sound/soc-dapm.h>
107 #include <sound/pcm.h>
108 #include <sound/jack.h>
109 //#include <asm/mach-types.h>
110
111 #include <mach/mt_gpio.h>
112 #include <mach/mt_boot.h>
113 #include <cust_eint.h>
114 #include <cust_gpio_usage.h>
115 #include <mach/eint.h>
116 #include "AudDrv_Common.h"
117
118 static DEFINE_SPINLOCK(afe_control_lock);
119 static DEFINE_SPINLOCK(afe_sram_control_lock);
120 static DEFINE_SPINLOCK(afe_mem_lock);
121 static DEFINE_MUTEX(Apll_mutex);
122
123
124 // static variable
125 static bool AudioDaiBtStatus = false;
126 static bool AudioAdcI2SStatus = false;
127 static bool Audio2ndAdcI2SStatus = false;
128 static bool AudioMrgStatus = false;
129 static bool mAudioInit = false;
130 static bool mPcm2AsyncFifoSel = true;
131 static bool AudioSpeakerProtectUsingSram = false;
132
133 static AudioDigtalI2S *AudioAdcI2S = NULL;
134 static AudioDigtalI2S *m2ndI2S = NULL; // input
135 static AudioDigtalI2S *m2ndI2Sout = NULL; // output
136
137 static AudioHdmi *mHDMIOutput = NULL;
138 static AudioMrgIf *mAudioMrg = NULL;
139 static AudioDigitalDAIBT *AudioDaiBt = NULL;
140
141 static AFE_MEM_CONTROL_T *AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_HDMI + 1] = {NULL};
142 static struct snd_dma_buffer *Audio_dma_buf[Soc_Aud_Digital_Block_MEM_HDMI + 1] = {NULL};
143
144 static AudioIrqMcuMode *mAudioMcuMode[Soc_Aud_IRQ_MCU_MODE_NUM_OF_IRQ_MODE] = {NULL};
145 static AudioMemIFAttribute *mAudioMEMIF[Soc_Aud_Digital_Block_NUM_OF_DIGITAL_BLOCK] = {NULL};
146
147 static AudioAfeRegCache mAudioRegCache;
148
149 static AudioSramManager mAudioSramManager;
150 const unsigned int AudioSramPlaybackFullSize = 1024 * 24;
151 const unsigned int AudioSramPlaybackPartialSize = 1024 * 16;
152 const unsigned int AudioDramPlaybackSize = 1024 * 24;
153 const size_t AudioSramCaptureSize = 1024 * 24;
154 const size_t AudioDramCaptureSize = 1024 * 24;
155 const size_t AudioInterruptLimiter = 100;
156
157 static bool mExternalModemStatus = false;
158
159 extern bool get_voice_bt_status(void);
160 extern bool get_voice_status(void);
161
162 // mutex lock
163 static DEFINE_MUTEX(afe_control_mutex);
164 //static DEFINE_SPINLOCK(auddrv_irqstatus_lock);
165 static DEFINE_SPINLOCK(auddrv_dl1_lock);
166 static DEFINE_SPINLOCK(auddrv_ul1_lock);
167 void Clear_Mem_CopySize(Soc_Aud_Digital_Block MemBlock);
168
169 static const uint16_t kSideToneCoefficientTable16k[] =
170 {
171 0x049C, 0x09E8, 0x09E0, 0x089C,
172 0xFF54, 0xF488, 0xEAFC, 0xEBAC,
173 0xfA40, 0x17AC, 0x3D1C, 0x6028,
174 0x7538
175 };
176
177 static const uint16_t kSideToneCoefficientTable32k[] =
178 {
179 0xff58, 0x0063, 0x0086, 0x00bf,
180 0x0100, 0x013d, 0x0169, 0x0178,
181 0x0160, 0x011c, 0x00aa, 0x0011,
182 0xff5d, 0xfea1, 0xfdf6, 0xfd75,
183 0xfd39, 0xfd5a, 0xfde8, 0xfeea,
184 0x005f, 0x0237, 0x0458, 0x069f,
185 0x08e2, 0x0af7, 0x0cb2, 0x0df0,
186 0x0e96
187 };
188
189 /*
190 * function implementation
191 */
192 static irqreturn_t AudDrv_IRQ_handler(int irq, void *dev_id);
193
194 static bool CheckSize(uint32 size)
195 {
196 if (size == 0)
197 {
198 printk("CheckSize size = 0\n");
199 return true;
200 }
201 return false;
202 }
203
204 void AfeControlMutexLock(void)
205 {
206 mutex_lock(&afe_control_mutex);
207 }
208
209 void AfeControlMutexUnLock(void)
210 {
211 mutex_unlock(&afe_control_mutex);
212 }
213
214 void AfeControlSramLock(void)
215 {
216 spin_lock(&afe_sram_control_lock);
217 }
218
219 void AfeControlSramUnLock(void)
220 {
221 spin_unlock(&afe_sram_control_lock);
222 }
223
224
225 unsigned int GetSramState(void)
226 {
227 return mAudioSramManager.mMemoryState;
228 }
229
230 void SetSramState(unsigned int State)
231 {
232 printk("%s state= %d, %d\n", __func__, mAudioSramManager.mMemoryState, State);
233 mAudioSramManager.mMemoryState |= State;
234 }
235
236 void ClearSramState(unsigned int State)
237 {
238 printk("%s state= %d, %d\n", __func__, mAudioSramManager.mMemoryState, State);
239 mAudioSramManager.mMemoryState &= (~State);
240 }
241
242 unsigned int GetPLaybackSramFullSize(void)
243 {
244 if(AudioSpeakerProtectUsingSram)
245 return AudioSramPlaybackPartialSize;
246 else
247 return AudioSramPlaybackFullSize;
248 }
249
250 unsigned int GetPLaybackSramPartial(void)
251 {
252 return AudioSramPlaybackPartialSize;
253 }
254
255 unsigned int GetPLaybackDramSize(void)
256 {
257 return AudioSramCaptureSize;
258 }
259
260 size_t GetCaptureSramSize(void)
261 {
262 return AudioSramCaptureSize;
263 }
264
265 size_t GetCaptureDramSize(void)
266 {
267 return AudioDramCaptureSize;
268 }
269
270 void SetAudioSpeakerProtectSram(bool enable)
271 {
272 // todo :: fix for this issue for buffer size
273 AudioSpeakerProtectUsingSram = false;
274 //AudioSpeakerProtectUsingSram = enable;
275 }
276
277 bool GetAudioSpeakerProtectSram(void)
278 {
279 return AudioSpeakerProtectUsingSram;
280 }
281
282 // function get internal mode status.
283 bool get_internalmd_status(void)
284 {
285 bool ret = (get_voice_bt_status() || get_voice_status());
286 return ret;
287 }
288
289 void DumpMemifSubStream(void)
290 {
291 int i=0;
292 //printk("+%s \n ", __func__);
293 for(i=0 ; i <= Soc_Aud_Digital_Block_MEM_HDMI ; i++ )
294 {
295 substreamList *head = AFE_Mem_Control_context[i]->substreamL;
296 while(head != NULL)
297 {
298 //printk("%s AFE_Mem_Control_context[%d] head = %p head->substream = %p \n ", __func__,i, head,head->substream);
299 head = (substreamList *)head->next;
300 }
301 }
302 //printk("-%s \n ", __func__);
303 }
304
305
306 static void FillDatatoDlmemory(volatile unsigned int *memorypointer, unsigned int fillsize, unsigned short value)
307 {
308 int addr = 0;
309 unsigned int tempvalue = value;
310 tempvalue = tempvalue << 16;
311 tempvalue |= value;
312 // set memory to DC value
313 for (addr = 0; addr < (fillsize >> 2) ; addr++)
314 {
315 *memorypointer = tempvalue;
316 memorypointer++;
317 }
318 }
319
320 static struct snd_dma_buffer *Dl1_Playback_dma_buf = NULL;
321
322 static void SetDL1BufferwithBuf(void)
323 {
324 //AudDrv_Allocate_mem_Buffer(NULL, Soc_Aud_Digital_Block_MEM_DL1, (24*1024));
325 Dl1_Playback_dma_buf = Get_Mem_Buffer(Soc_Aud_Digital_Block_MEM_DL1);
326 // TODO: check Dl1_Playback_dma_buf->addr != NULL!!
327
328 Afe_Set_Reg(AFE_DL1_BASE , Dl1_Playback_dma_buf->addr, 0xffffffff);
329 Afe_Set_Reg(AFE_DL1_END ,Dl1_Playback_dma_buf->addr + ((24*1024) - 1), 0xffffffff);
330 }
331
332
333 void OpenAfeDigitaldl1(bool bEnable)
334 {
335 volatile unsigned int *Sramdata;
336
337 if (bEnable == true)
338 {
339 SetDL1BufferwithBuf();
340 SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL1, AFE_WLEN_16_BIT);
341 SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL2, AFE_WLEN_16_BIT);
342 SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O03);
343 SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O04);
344 SetSampleRate(Soc_Aud_Digital_Block_MEM_I2S, 44100);
345 SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I05, Soc_Aud_InterConnectionOutput_O03);
346 SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I06, Soc_Aud_InterConnectionOutput_O04);
347 SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DL1, true);
348
349 Sramdata = (volatile unsigned int *)Dl1_Playback_dma_buf->area;
350 FillDatatoDlmemory(Sramdata , Dl1_Playback_dma_buf->bytes , 0);
351 msleep(5);
352
353 if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC) == false)
354 {
355 SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, true);
356 SetI2SDacOut(44100);
357 SetI2SDacEnable(true);
358 }
359 else
360 {
361 SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, true);
362 }
363 EnableAfe(true);
364 }
365 else
366 {
367 SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, false);
368 SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DL1, false);
369 if (GetI2SDacEnable() == false)
370 {
371 SetI2SDacEnable(false);
372 }
373 EnableAfe(false);
374 }
375 }
376
377 void SetExternalModemStatus(const bool bEnable)
378 {
379 printk("%s(), mExternalModemStatus : %d => %d\n", __func__, mExternalModemStatus, bEnable);
380 mExternalModemStatus = bEnable;
381 }
382
383 bool GetExternalModemStatus(void)
384 {
385 return mExternalModemStatus ;
386 }
387
388 /*****************************************************************************
389 * FUNCTION
390 * InitAfeControl ,ResetAfeControl
391 *
392 * DESCRIPTION
393 * afe init function
394 *
395 *****************************************************************************
396 */
397
398 bool InitAfeControl(void)
399 {
400 int i = 0;
401 printk("InitAfeControl \n");
402 // first time to init , reg init.
403 Auddrv_Reg_map();
404 AudDrv_Clk_Power_On();
405 Auddrv_Bus_Init();
406 AfeControlMutexLock();
407 // allocate memory for pointers
408 if (mAudioInit == false)
409 {
410 mAudioInit = true;
411 mAudioMrg = kzalloc(sizeof(AudioMrgIf), GFP_KERNEL);
412 AudioDaiBt = kzalloc(sizeof(AudioDigitalDAIBT), GFP_KERNEL);
413 AudioAdcI2S = kzalloc(sizeof(AudioDigtalI2S), GFP_KERNEL);
414 m2ndI2S = kzalloc(sizeof(AudioDigtalI2S), GFP_KERNEL);
415 m2ndI2Sout = kzalloc(sizeof(AudioDigtalI2S), GFP_KERNEL);
416 mHDMIOutput = kzalloc(sizeof(AudioHdmi), GFP_KERNEL);
417 for (i = 0; i < Soc_Aud_IRQ_MCU_MODE_NUM_OF_IRQ_MODE ; i ++)
418 {
419 mAudioMcuMode[i] = kzalloc(sizeof(AudioIrqMcuMode) , GFP_KERNEL);
420 }
421 for (i = 0; i < Soc_Aud_Digital_Block_NUM_OF_DIGITAL_BLOCK ; i ++)
422 {
423 mAudioMEMIF[i] = kzalloc(sizeof(AudioMemIFAttribute), GFP_KERNEL);
424 }
425 for (i = 0; i <= Soc_Aud_Digital_Block_MEM_HDMI ; i ++)
426 {
427 AFE_Mem_Control_context[i] = kzalloc(sizeof(AFE_MEM_CONTROL_T), GFP_KERNEL);
428 AFE_Mem_Control_context[i]->substreamL = NULL;
429 }
430 for (i = 0; i <= Soc_Aud_Digital_Block_MEM_HDMI ; i ++)
431 {
432 Audio_dma_buf[i] = kzalloc(sizeof(Audio_dma_buf), GFP_KERNEL);
433 }
434 }
435 AudioDaiBtStatus = false;
436 AudioAdcI2SStatus = false;
437 Audio2ndAdcI2SStatus = false;
438 AudioMrgStatus = false;
439 memset((void *)&mAudioSramManager, 0, sizeof(AudioSramManager));
440
441 mAudioMrg->Mrg_I2S_SampleRate = SampleRateTransform(44100);
442
443 for (i = AUDIO_APLL1_DIV0 ; i <= AUDIO_APLL2_DIV5 ; i++)
444 {
445 EnableI2SDivPower(i , false);
446 }
447
448 // set APLL clock setting
449 AfeControlMutexUnLock();
450 mt_set_gpio_mode(GPIO_AUD_CLK_MOSI_PIN , GPIO_MODE_00);
451 return true;
452 }
453
454 bool ResetAfeControl(void)
455 {
456 int i = 0;
457 printk("ResetAfeControl \n");
458 AfeControlMutexLock();
459 mAudioInit = false;
460 memset((void *)(mAudioMrg), 0, sizeof(AudioMrgIf));
461 memset((void *)(AudioDaiBt), 0, sizeof(AudioDigitalDAIBT));
462 for (i = 0; i < Soc_Aud_IRQ_MCU_MODE_NUM_OF_IRQ_MODE ; i ++)
463 {
464 memset((void *)(mAudioMcuMode[i]), 0, sizeof(AudioIrqMcuMode));
465 }
466 for (i = 0; i < Soc_Aud_Digital_Block_NUM_OF_DIGITAL_BLOCK ; i ++)
467 {
468 memset((void *)(mAudioMEMIF[i]), 0, sizeof(AudioMemIFAttribute));
469 }
470 for (i = 0; i < Soc_Aud_Digital_Block_NUM_OF_DIGITAL_BLOCK ; i ++)
471 {
472 memset((void *)(AFE_Mem_Control_context[i]), 0, sizeof(AFE_MEM_CONTROL_T));
473 }
474 AfeControlMutexUnLock();
475 return true;
476 }
477
478
479 /*****************************************************************************
480 * FUNCTION
481 * Register_aud_irq
482 *
483 * DESCRIPTION
484 * IRQ handler
485 *
486 *****************************************************************************
487 */
488
489 bool Register_Aud_Irq(void *dev, uint32 afe_irq_number)
490 {
491 int ret = 0;
492 #ifdef CONFIG_OF
493 ret = request_irq(afe_irq_number, AudDrv_IRQ_handler, IRQF_TRIGGER_LOW, "Afe_ISR_Handle", dev);
494 if (ret)
495 {
496 printk("Register_Aud_Irq AFE IRQ register fail!!!\n");
497 }
498 #else
499 printk("%s dev name =%s \n", __func__, dev_name(dev));
500 ret = request_irq(MT6595_AFE_MCU_IRQ_LINE, AudDrv_IRQ_handler, IRQF_TRIGGER_LOW/*IRQF_TRIGGER_FALLING*/, "Afe_ISR_Handle", dev);
501 #endif
502 return ret;
503 }
504
505 static int irqcount = 0;
506 /*****************************************************************************
507 * FUNCTION
508 * AudDrv_IRQ_handler / AudDrv_magic_tasklet
509 *
510 * DESCRIPTION
511 * IRQ handler
512 *
513 *****************************************************************************
514 */
515 irqreturn_t AudDrv_IRQ_handler(int irq, void *dev_id)
516 {
517 //unsigned long flags;
518 kal_uint32 volatile u4RegValue;
519 kal_uint32 volatile u4tmpValue;
520 kal_uint32 volatile u4tmpValue1;
521 kal_uint32 volatile u4tmpValue2;
522
523 AudDrv_Clk_On();
524 u4RegValue = Afe_Get_Reg(AFE_IRQ_MCU_STATUS);
525 u4RegValue &= 0xff;
526
527 u4tmpValue = Afe_Get_Reg(AFE_IRQ_MCU_EN);
528 u4tmpValue &= 0xff;
529
530 u4tmpValue1 = Afe_Get_Reg(AFE_IRQ_CNT5);
531 u4tmpValue1 &= 0x0003ffff;
532
533 u4tmpValue2 = Afe_Get_Reg(AFE_IRQ_DEBUG);
534 u4tmpValue2 &= 0x0003ffff;
535
536 // here is error handle , for interrupt is trigger but not status , clear all interrupt with bit 6
537 if (u4RegValue == 0)
538 {
539 printk("u4RegValue == 0 irqcount =0\n");
540 Afe_Set_Reg(AFE_IRQ_MCU_CLR, 1 << 6 , 0xff);
541 Afe_Set_Reg(AFE_IRQ_MCU_CLR, 1 , 0xff);
542 Afe_Set_Reg(AFE_IRQ_MCU_CLR, 1 << 1 , 0xff);
543 Afe_Set_Reg(AFE_IRQ_MCU_CLR, 1 << 2 , 0xff);
544 Afe_Set_Reg(AFE_IRQ_MCU_CLR, 1 << 3 , 0xff);
545 Afe_Set_Reg(AFE_IRQ_MCU_CLR, 1 << 4 , 0xff);
546 Afe_Set_Reg(AFE_IRQ_MCU_CLR, 1 << 5 , 0xff);
547 irqcount++;
548 if (irqcount > AudioInterruptLimiter)
549 {
550 SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, false);
551 SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, false);
552 irqcount = 0;
553 }
554 goto AudDrv_IRQ_handler_exit;
555 }
556
557 if (u4RegValue & INTERRUPT_IRQ1_MCU)
558 {
559 if (mAudioMEMIF[Soc_Aud_Digital_Block_MEM_DL1]->mState == true)
560 {
561 Auddrv_DL1_Interrupt_Handler();
562 }
563 }
564 if (u4RegValue & INTERRUPT_IRQ2_MCU)
565 {
566 if (mAudioMEMIF[Soc_Aud_Digital_Block_MEM_VUL]->mState == true)
567 {
568 Auddrv_UL1_Interrupt_Handler();
569 }
570 if (mAudioMEMIF[Soc_Aud_Digital_Block_MEM_AWB]->mState == true)
571 {
572 Auddrv_AWB_Interrupt_Handler();
573 }
574 if (mAudioMEMIF[Soc_Aud_Digital_Block_MEM_DAI]->mState == true)
575 {
576 Auddrv_DAI_Interrupt_Handler();
577 }
578 if (mAudioMEMIF[Soc_Aud_Digital_Block_MEM_VUL_DATA2]->mState == true)
579 {
580 Auddrv_UL2_Interrupt_Handler();
581 }
582 if (mAudioMEMIF[Soc_Aud_Digital_Block_MEM_MOD_DAI]->mState == true)
583 {
584 Auddrv_MOD_DAI_Interrupt_Handler();
585 }
586 }
587 if (u4RegValue & INTERRUPT_IRQ3_MCU)
588 {
589 }
590 if (u4RegValue & INTERRUPT_IRQ4_MCU)
591 {
592 }
593 if (u4RegValue & INTERRUPT_IRQ5_MCU)
594 {
595 Auddrv_HDMI_Interrupt_Handler();
596 }
597 // clear irq
598 Afe_Set_Reg(AFE_IRQ_MCU_CLR, u4RegValue , 0xff);
599 AudDrv_IRQ_handler_exit:
600 AudDrv_Clk_Off();
601 return IRQ_HANDLED;
602 }
603
604 uint32 GetApllbySampleRate(uint32 SampleRate)
605 {
606 if (SampleRate == 176400 || SampleRate == 88200 || SampleRate == 44100 || SampleRate == 22050 || SampleRate == 11025)
607 {
608 return Soc_Aud_APLL1;
609 }
610 else
611 {
612 return Soc_Aud_APLL2;
613 }
614 }
615
616 void SetckSel(uint32 I2snum, uint32 SampleRate)
617 {
618 uint32 ApllSource = GetApllbySampleRate(SampleRate);
619 switch (I2snum)
620 {
621 case Soc_Aud_I2S0:
622 SetClkCfg(AUDIO_CLK_AUDDIV_0, ApllSource << 4, 1 << 4);
623 break;
624 case Soc_Aud_I2S1:
625 SetClkCfg(AUDIO_CLK_AUDDIV_0, ApllSource << 5, 1 << 5);
626 break;
627 case Soc_Aud_I2S2:
628 SetClkCfg(AUDIO_CLK_AUDDIV_0, ApllSource << 6, 1 << 6);
629 break;
630 case Soc_Aud_I2S3:
631 SetClkCfg(AUDIO_CLK_AUDDIV_0, ApllSource << 7, 1 << 7);
632 SetClkCfg(AUDIO_CLK_AUDDIV_0, ApllSource << 8, 1 << 8);
633 break;
634 }
635 printk("%s ApllSource = %d \n", __func__, ApllSource);
636
637 }
638
639 uint32 SetCLkMclk(uint32 I2snum, uint32 SampleRate)
640 {
641 uint32 I2S_APll = 0;
642 uint32 I2s_ck_div = 0;
643 if (GetApllbySampleRate(SampleRate) == Soc_Aud_APLL1)
644 {
645 I2S_APll = 22579200 * 8;
646 }
647 else
648 {
649 I2S_APll = 24576000 * 8 ;
650 }
651
652 SetckSel(I2snum, SampleRate); // set I2Sx mck source
653
654 switch (I2snum)
655 {
656 case Soc_Aud_I2S0:
657 I2s_ck_div = (I2S_APll / 256 / SampleRate) - 1;
658 SetClkCfg(AUDIO_CLK_AUDDIV_1, I2s_ck_div, 0x000000ff);
659 SetClkCfg(AUDIO_CLK_AUDDIV_2, I2s_ck_div, 0x000000ff);
660 break;
661 case Soc_Aud_I2S1:
662 I2s_ck_div = (I2S_APll / 256 / SampleRate) - 1;
663 SetClkCfg(AUDIO_CLK_AUDDIV_1, I2s_ck_div << 8, 0x0000ff00);
664 SetClkCfg(AUDIO_CLK_AUDDIV_2, I2s_ck_div << 8, 0x0000ff00);
665 break;
666 case Soc_Aud_I2S2:
667 I2s_ck_div = (I2S_APll / 256 / SampleRate) - 1;
668 SetClkCfg(AUDIO_CLK_AUDDIV_1, I2s_ck_div << 16, 0x00ff0000);
669 SetClkCfg(AUDIO_CLK_AUDDIV_2, I2s_ck_div << 16, 0x00ff0000);
670 break;
671 case Soc_Aud_I2S3:
672 I2s_ck_div = (I2S_APll / 256 / SampleRate) - 1;
673 SetClkCfg(AUDIO_CLK_AUDDIV_1, I2s_ck_div << 24, 0xff000000);
674 SetClkCfg(AUDIO_CLK_AUDDIV_2, I2s_ck_div << 24, 0xff000000);
675 break;
676 }
677 printk("%s I2s_ck_div = %d I2S_APll = %d\n", __func__, I2s_ck_div, I2S_APll);
678 return I2s_ck_div;
679 }
680
681 void SetCLkBclk(uint32 MckDiv, uint32 SampleRate, uint32 Channels , uint32 Wlength)
682 {
683 uint32 I2S_APll = 0;
684 uint32 I2S_Bclk = 0;
685 uint32 I2s_Bck_div = 0;
686 printk("%s MckDiv = %dv SampleRate = %d Channels = %d Wlength = %d\n", __func__, MckDiv, SampleRate, Channels, Wlength);
687 MckDiv++;
688
689 if (GetApllbySampleRate(SampleRate) == Soc_Aud_APLL1)
690 {
691 I2S_APll = 22579200 * 8;
692 }
693 else
694 {
695 I2S_APll = 24576000 * 8 ;
696 }
697 I2S_Bclk = SampleRate * Channels * (Wlength + 1) * 16;
698 I2s_Bck_div = (I2S_APll / MckDiv) / I2S_Bclk;
699
700 printk("%s I2S_APll = %dv I2S_Bclk = %d I2s_Bck_div = %d\n", __func__, I2S_APll, I2S_Bclk, I2s_Bck_div);
701 I2s_Bck_div--;
702 SetClkCfg(AUDIO_CLK_AUDDIV_3, I2s_Bck_div, 0x0000000f);
703 SetClkCfg(AUDIO_CLK_AUDDIV_3, I2s_Bck_div << 4, 0x000000f0);
704 }
705
706
707 void EnableI2SDivPower(uint32 Diveder_name, bool bEnable)
708 {
709 if (bEnable)
710 {
711 //AUDIO_APLL1_DIV0
712 SetClkCfg(AUDIO_CLK_AUDDIV_3, 0 << Diveder_name, 1 << Diveder_name);
713 }
714 else
715 {
716 SetClkCfg(AUDIO_CLK_AUDDIV_3, 1 << Diveder_name , 1 << Diveder_name);
717 }
718 }
719
720 static bool APLL1State = false;
721 void EnableApll1(bool bEnable)
722 {
723 printk("+%s bEnable = %d\n",__func__,bEnable);
724 if ((bEnable== true) && (APLL1State == false))
725 {
726 SetClkCfg(AUDIO_CLK_AUDDIV_0, 0x07000000, 0x0f000000);
727 AudDrv_APLL22M_Clk_On();
728 SetClkCfg(AUDIO_CLK_AUDDIV_0, 0x0, 0x3);
729 enable_mux(MT_MUX_AUD1, "AUDIO");
730 APLL1State = true;
731 }
732 else if((bEnable == false) && (APLL1State == true))
733 {
734 disable_mux(MT_MUX_AUD1, "AUDIO");
735 AudDrv_APLL22M_Clk_Off();
736 SetClkCfg(AUDIO_CLK_AUDDIV_0, 0x3, 0x3);
737 SetClkCfg(AUDIO_CLK_AUDDIV_0, 0x07000000, 0x0f000000);
738 APLL1State = false;
739 }
740 printk("-%s bEnable = %d\n",__func__,bEnable);
741 }
742
743 static bool APLL2State = false;
744 void EnableApll2(bool bEnable)
745 {
746 printk("+%s bEnable = %d\n",__func__,bEnable);
747 if ((bEnable== true) && (APLL2State == false))
748 {
749 SetClkCfg(AUDIO_CLK_AUDDIV_0, 0x70000000, 0xf0000000);
750 AudDrv_APLL24M_Clk_On();
751 SetClkCfg(AUDIO_CLK_AUDDIV_0, 0x0, 0xc);
752 enable_mux(MT_MUX_AUD2, "AUDIO");
753 APLL2State = true;
754 }
755 else if((bEnable == false) && (APLL2State == true))
756 {
757 disable_mux(MT_MUX_AUD2, "AUDIO");
758 AudDrv_APLL24M_Clk_Off();
759 SetClkCfg(AUDIO_CLK_AUDDIV_0, 0xc, 0xc);
760 SetClkCfg(AUDIO_CLK_AUDDIV_0, 0x70000000, 0xf0000000);
761 APLL2State = false;
762 }
763 printk("-%s bEnable = %d\n",__func__,bEnable);
764 }
765
766 static bool CheckMemIfEnable(void)
767 {
768 int i = 0;
769 for (i = 0 ; i < Soc_Aud_Digital_Block_NUM_OF_DIGITAL_BLOCK ; i++)
770 {
771 if ((mAudioMEMIF[i]->mState) == true)
772 {
773 //printk("CheckMemIfEnable == true\n");
774 return true;
775 }
776 }
777 //printk("CheckMemIfEnable == false\n");
778 return false;
779 }
780
781
782 /*****************************************************************************
783 * FUNCTION
784 * Auddrv_Reg_map
785 *
786 * DESCRIPTION
787 * Auddrv_Reg_map
788 *
789 *****************************************************************************
790 */
791 void EnableAfe(bool bEnable)
792 {
793 unsigned int flags;
794 bool MemEnable = false;
795 spin_lock_irqsave(&afe_control_lock, flags);
796 MemEnable = CheckMemIfEnable();
797 if (false == bEnable && false == MemEnable)
798 {
799 Afe_Set_Reg(AFE_DAC_CON0, 0x0, 0x0); // TODO(Chipeng, Harvey): check open/close in pairs
800 mt_set_gpio_mode(GPIO_AUD_CLK_MOSI_PIN , GPIO_MODE_00);
801 }
802 else if (true == bEnable && true == MemEnable)
803 {
804 mt_set_gpio_mode(GPIO_AUD_CLK_MOSI_PIN , GPIO_MODE_01);
805 Afe_Set_Reg(AFE_DAC_CON0, 0x1, 0x1);
806 }
807 spin_unlock_irqrestore(&afe_control_lock, flags);
808 }
809
810 uint32 SampleRateTransform(uint32 SampleRate)
811 {
812 switch (SampleRate)
813 {
814 case 8000:
815 return Soc_Aud_I2S_SAMPLERATE_I2S_8K;
816 case 11025:
817 return Soc_Aud_I2S_SAMPLERATE_I2S_11K;
818 case 12000:
819 return Soc_Aud_I2S_SAMPLERATE_I2S_12K;
820 case 16000:
821 return Soc_Aud_I2S_SAMPLERATE_I2S_16K;
822 case 22050:
823 return Soc_Aud_I2S_SAMPLERATE_I2S_22K;
824 case 24000:
825 return Soc_Aud_I2S_SAMPLERATE_I2S_24K;
826 case 32000:
827 return Soc_Aud_I2S_SAMPLERATE_I2S_32K;
828 case 44100:
829 return Soc_Aud_I2S_SAMPLERATE_I2S_44K;
830 case 48000:
831 return Soc_Aud_I2S_SAMPLERATE_I2S_48K;
832 case 88000:
833 return Soc_Aud_I2S_SAMPLERATE_I2S_88K;
834 case 96000:
835 return Soc_Aud_I2S_SAMPLERATE_I2S_96K;
836 case 174000:
837 return Soc_Aud_I2S_SAMPLERATE_I2S_174K;
838 case 192000:
839 return Soc_Aud_I2S_SAMPLERATE_I2S_192K;
840 case 260000:
841 return Soc_Aud_I2S_SAMPLERATE_I2S_260K;
842 default:
843 break;
844 }
845 return Soc_Aud_I2S_SAMPLERATE_I2S_44K;
846 }
847
848 bool SetSampleRate(uint32 Aud_block, uint32 SampleRate)
849 {
850 //printk("%s Aud_block = %d SampleRate = %d\n", __func__, Aud_block, SampleRate);
851 SampleRate = SampleRateTransform(SampleRate);
852 switch (Aud_block)
853 {
854 case Soc_Aud_Digital_Block_MEM_DL1:
855 {
856 Afe_Set_Reg(AFE_DAC_CON1, SampleRate , 0x0000000f);
857 break;
858 }
859 case Soc_Aud_Digital_Block_MEM_DL2:
860 {
861 Afe_Set_Reg(AFE_DAC_CON1, SampleRate << 4 , 0x000000f0);
862 break;
863 }
864 case Soc_Aud_Digital_Block_MEM_I2S:
865 {
866 Afe_Set_Reg(AFE_DAC_CON1, SampleRate << 8 , 0x00000f00);
867 break;
868 }
869 case Soc_Aud_Digital_Block_MEM_AWB:
870 {
871 Afe_Set_Reg(AFE_DAC_CON1, SampleRate << 12, 0x0000f000);
872 break;
873 }
874 case Soc_Aud_Digital_Block_MEM_VUL:
875 {
876 Afe_Set_Reg(AFE_DAC_CON1, SampleRate << 16, 0x000f0000);
877 break;
878 }
879 case Soc_Aud_Digital_Block_MEM_DAI:
880 {
881 if (SampleRate == Soc_Aud_I2S_SAMPLERATE_I2S_8K)
882 {
883 Afe_Set_Reg(AFE_DAC_CON0, 0 << 24 , 3 << 24);
884 }
885 else if (SampleRate == Soc_Aud_I2S_SAMPLERATE_I2S_16K)
886 {
887 Afe_Set_Reg(AFE_DAC_CON0, 1 << 24 , 3 << 24);
888 }
889 else if (SampleRate == Soc_Aud_I2S_SAMPLERATE_I2S_32K)
890 {
891 Afe_Set_Reg(AFE_DAC_CON0, 2 << 24 , 3 << 24);
892 }
893 else
894 {
895 return false;
896 }
897 break;
898 }
899 case Soc_Aud_Digital_Block_MEM_MOD_DAI:
900 {
901 if (SampleRate == Soc_Aud_I2S_SAMPLERATE_I2S_8K)
902 {
903 Afe_Set_Reg(AFE_DAC_CON1, 0 << 30, 3 << 30);
904 }
905 else if (SampleRate == Soc_Aud_I2S_SAMPLERATE_I2S_16K)
906 {
907 Afe_Set_Reg(AFE_DAC_CON1, 1 << 30, 3 << 30);
908 }
909 else
910 {
911 return false;
912 }
913 break;
914 }
915 case Soc_Aud_Digital_Block_MEM_VUL_DATA2:
916 {
917 Afe_Set_Reg(AFE_DAC_CON0, SampleRate << 20, 0x00f00000);
918 break;
919 }
920 return true;
921 }
922 return false;
923 }
924
925 bool SetChannels(uint32 Memory_Interface, uint32 channel)
926 {
927 const bool bMono = (channel == 1) ? true : false;
928
929 //printk("SetChannels Memory_Interface = %d channels = %d\n", Memory_Interface, channel);
930
931 switch (Memory_Interface)
932 {
933 case Soc_Aud_Digital_Block_MEM_DL1:
934 {
935 Afe_Set_Reg(AFE_DAC_CON1, bMono << 21, 1 << 21);
936 break;
937 }
938 case Soc_Aud_Digital_Block_MEM_AWB:
939 {
940 Afe_Set_Reg(AFE_DAC_CON1, bMono << 24, 1 << 24);
941 break;
942 }
943 case Soc_Aud_Digital_Block_MEM_VUL:
944 {
945 Afe_Set_Reg(AFE_DAC_CON1, bMono << 27, 1 << 27);
946 break;
947 }
948 case Soc_Aud_Digital_Block_MEM_VUL_DATA2:
949 {
950 Afe_Set_Reg(AFE_DAC_CON0, bMono << 10, 1 << 10);
951 break;
952 }
953 default:
954 printk("SetChannels Memory_Interface = %d, channel = %d, bMono = %d\n", Memory_Interface, channel, bMono);
955 return false;
956 }
957 return true;
958 }
959
960
961 bool Set2ndI2SOutAttribute(uint32_t sampleRate)
962 {
963 printk("+%s(), sampleRate = %d\n", __FUNCTION__, sampleRate);
964 m2ndI2Sout->mLR_SWAP = Soc_Aud_LR_SWAP_NO_SWAP;
965 m2ndI2Sout->mI2S_SLAVE = Soc_Aud_I2S_SRC_MASTER_MODE;
966 m2ndI2Sout->mINV_LRCK = Soc_Aud_INV_LRCK_NO_INVERSE;
967 m2ndI2Sout->mI2S_FMT = Soc_Aud_I2S_FORMAT_I2S;
968 m2ndI2Sout->mI2S_WLEN = Soc_Aud_I2S_WLEN_WLEN_16BITS;
969 m2ndI2Sout->mI2S_HDEN = Soc_Aud_NORMAL_CLOCK;
970 m2ndI2Sout->mI2S_SAMPLERATE = sampleRate;
971 Set2ndI2SOut(m2ndI2Sout);
972 return true;
973 }
974
975 bool Set2ndI2SOut(AudioDigtalI2S *DigtalI2S)
976 {
977 uint32 u32AudioI2S = 0;
978 memcpy((void *)m2ndI2Sout, (void *)DigtalI2S, sizeof(AudioDigtalI2S));
979 u32AudioI2S = SampleRateTransform(m2ndI2Sout->mI2S_SAMPLERATE) << 8;
980 u32AudioI2S |= m2ndI2Sout->mLR_SWAP << 31;
981 u32AudioI2S |= m2ndI2Sout->mI2S_HDEN << 12;
982 u32AudioI2S |= m2ndI2Sout->mINV_LRCK << 5;
983 u32AudioI2S |= m2ndI2Sout->mI2S_FMT << 3;
984 u32AudioI2S |= m2ndI2Sout->mI2S_WLEN << 1;
985 Afe_Set_Reg(AFE_I2S_CON3, u32AudioI2S, AFE_MASK_ALL);
986 return true;
987 }
988
989 bool Set2ndI2SOutEnable(bool benable)
990 {
991 if (benable)
992 {
993 Afe_Set_Reg(AFE_I2S_CON3, 0x1, 0x1);
994 }
995 else
996 {
997 Afe_Set_Reg(AFE_I2S_CON3, 0x0, 0x1);
998 }
999 return true;
1000 }
1001
1002 bool SetDaiBt(AudioDigitalDAIBT *mAudioDaiBt)
1003 {
1004 AudioDaiBt->mBT_LEN = mAudioDaiBt->mBT_LEN;
1005 AudioDaiBt->mUSE_MRGIF_INPUT = mAudioDaiBt->mUSE_MRGIF_INPUT;
1006 AudioDaiBt->mDAI_BT_MODE = mAudioDaiBt->mDAI_BT_MODE;
1007 AudioDaiBt->mDAI_DEL = mAudioDaiBt->mDAI_DEL;
1008 AudioDaiBt->mBT_LEN = mAudioDaiBt->mBT_LEN;
1009 AudioDaiBt->mDATA_RDY = mAudioDaiBt->mDATA_RDY;
1010 AudioDaiBt->mBT_SYNC = mAudioDaiBt->mBT_SYNC;
1011 return true;
1012 }
1013
1014 bool SetDaiBtEnable(bool bEanble)
1015 {
1016 printk("%s bEanble = %d\n", __func__, bEanble);
1017 if (bEanble == true) // turn on dai bt
1018 {
1019 Afe_Set_Reg(AFE_DAIBT_CON0, AudioDaiBt->mDAI_BT_MODE << 9, 0x1 << 9);
1020 if (mAudioMrg->MrgIf_En == true)
1021 {
1022 Afe_Set_Reg(AFE_DAIBT_CON0, 0x1 << 12, 0x1 << 12); // use merge
1023 Afe_Set_Reg(AFE_DAIBT_CON0, 0x1 << 3, 0x1 << 3); // data ready
1024 Afe_Set_Reg(AFE_DAIBT_CON0, 0x3, 0x3); //Turn on DAIBT
1025 }
1026 else // turn on merge and daiBT
1027 {
1028 Afe_Set_Reg(AFE_MRGIF_CON, mAudioMrg->Mrg_I2S_SampleRate << 20, 0xF00000); // set Mrg_I2S Samping Rate
1029 Afe_Set_Reg(AFE_MRGIF_CON, 1 << 16, 1 << 16); // set Mrg_I2S enable
1030 Afe_Set_Reg(AFE_MRGIF_CON, 1, 0x1); // Turn on Merge Interface
1031 udelay(100);
1032 Afe_Set_Reg(AFE_DAIBT_CON0, 0x1 << 12, 0x1 << 12); // use merge
1033 Afe_Set_Reg(AFE_DAIBT_CON0, 0x1 << 3, 0x1 << 3); // data ready
1034 Afe_Set_Reg(AFE_DAIBT_CON0, 0x3, 0x3); //Turn on DAIBT
1035 }
1036 AudioDaiBt->mBT_ON = true;
1037 AudioDaiBt->mDAIBT_ON = true;
1038 mAudioMrg->MrgIf_En = true;
1039 }
1040 else
1041 {
1042 if (mAudioMrg->Mergeif_I2S_Enable == true)
1043 {
1044 Afe_Set_Reg(AFE_DAIBT_CON0, 0, 0x3); //Turn off DAIBT
1045 }
1046 else
1047 {
1048 Afe_Set_Reg(AFE_DAIBT_CON0, 0, 0x3); //Turn on DAIBT
1049 udelay(100);
1050 Afe_Set_Reg(AFE_MRGIF_CON, 0 << 16, 1 << 16); // set Mrg_I2S enable
1051 Afe_Set_Reg(AFE_MRGIF_CON, 0, 0x1); // Turn on Merge Interface
1052 mAudioMrg->MrgIf_En = false;
1053 }
1054 AudioDaiBt->mBT_ON = false;
1055 AudioDaiBt->mDAIBT_ON = false;
1056 }
1057 return true;
1058 }
1059
1060 bool GetMrgI2SEnable()
1061 {
1062 return mAudioMEMIF[Soc_Aud_Digital_Block_MRG_I2S_OUT]->mState ;
1063 }
1064
1065 bool SetMrgI2SEnable(bool bEnable, unsigned int sampleRate)
1066 {
1067 printk("%s bEnable = %d\n", __func__, bEnable);
1068 if (bEnable == true)
1069 {
1070 // To enable MrgI2S
1071 if (mAudioMrg->MrgIf_En == true)
1072 {
1073 // Merge Interface already turn on.
1074 //if sample Rate change, then it need to restart with new setting; else do nothing.
1075 if (mAudioMrg->Mrg_I2S_SampleRate != SampleRateTransform(sampleRate))
1076 {
1077 //Turn off Merge Interface first to switch I2S sampling rate
1078 Afe_Set_Reg(AFE_MRGIF_CON, 0, 1 << 16); // Turn off I2S
1079 if (AudioDaiBt->mDAIBT_ON == true)
1080 {
1081 Afe_Set_Reg(AFE_DAIBT_CON0, 0, 0x1); //Turn off DAIBT first
1082 }
1083 udelay(100);
1084 Afe_Set_Reg(AFE_MRGIF_CON, 0, 0x1); // Turn off Merge Interface
1085 udelay(100);
1086 Afe_Set_Reg(AFE_MRGIF_CON, 1, 0x1); // Turn on Merge Interface
1087 if (AudioDaiBt->mDAIBT_ON == true)
1088 {
1089 Afe_Set_Reg(AFE_DAIBT_CON0, AudioDaiBt->mDAI_BT_MODE << 9, 0x1 << 9); // use merge
1090 Afe_Set_Reg(AFE_DAIBT_CON0, 0x1 << 12, 0x1 << 12); // use merge
1091 Afe_Set_Reg(AFE_DAIBT_CON0, 0x1 << 3, 0x1 << 3); // data ready
1092 Afe_Set_Reg(AFE_DAIBT_CON0, 0x3, 0x3); //Turn on DAIBT
1093 }
1094 mAudioMrg->Mrg_I2S_SampleRate = SampleRateTransform(sampleRate);
1095 Afe_Set_Reg(AFE_MRGIF_CON, mAudioMrg->Mrg_I2S_SampleRate << 20, 0xF00000); // set Mrg_I2S Samping Rate
1096 Afe_Set_Reg(AFE_MRGIF_CON, 1 << 16, 1 << 16); // set Mrg_I2S enable
1097 }
1098 }
1099 else
1100 {
1101 // turn on merge Interface from off state
1102 mAudioMrg->Mrg_I2S_SampleRate = SampleRateTransform(sampleRate);
1103 Afe_Set_Reg(AFE_MRGIF_CON, mAudioMrg->Mrg_I2S_SampleRate << 20, 0xF00000); // set Mrg_I2S Samping rates
1104 Afe_Set_Reg(AFE_MRGIF_CON, 1 << 16, 1 << 16); // set Mrg_I2S enable
1105 udelay(100);
1106 Afe_Set_Reg(AFE_MRGIF_CON, 1, 0x1); // Turn on Merge Interface
1107 udelay(100);
1108 if (AudioDaiBt->mDAIBT_ON == true)
1109 {
1110 Afe_Set_Reg(AFE_DAIBT_CON0, AudioDaiBt->mDAI_BT_MODE << 9, 0x1 << 9); // use merge
1111 Afe_Set_Reg(AFE_DAIBT_CON0, 0x1 << 12, 0x1 << 12); // use merge
1112 Afe_Set_Reg(AFE_DAIBT_CON0, 0x1 << 3, 0x1 << 3); // data ready
1113 Afe_Set_Reg(AFE_DAIBT_CON0, 0x3, 0x3); //Turn on DAIBT
1114 }
1115 }
1116 mAudioMrg->MrgIf_En = true;
1117 mAudioMrg->Mergeif_I2S_Enable = true;
1118 }
1119 else
1120 {
1121 if (mAudioMrg->MrgIf_En == true)
1122 {
1123 Afe_Set_Reg(AFE_MRGIF_CON, 0, 1 << 16); // Turn off I2S
1124 if (AudioDaiBt->mDAIBT_ON == false)
1125 {
1126 udelay(100);
1127 // DAIBT also not using, then it's OK to disable Merge Interface
1128 Afe_Set_Reg(AFE_MRGIF_CON, 0, 0x1); // Turn off Merge Interface
1129 mAudioMrg->MrgIf_En = false;
1130 }
1131 }
1132 mAudioMrg->Mergeif_I2S_Enable = false;
1133 }
1134 return true;
1135 }
1136 bool Set2ndI2SAdcIn(AudioDigtalI2S *DigtalI2S)
1137 {
1138 uint32 Audio_I2S_Adc = 0;
1139 memcpy((void *)AudioAdcI2S, (void *)DigtalI2S, sizeof(AudioDigtalI2S));
1140
1141 if (false == Audio2ndAdcI2SStatus)
1142 {
1143 uint32 eSamplingRate = SampleRateTransform(AudioAdcI2S->mI2S_SAMPLERATE);
1144 uint32 dVoiceModeSelect = 0;
1145 Afe_Set_Reg(AFE_ADDA_TOP_CON0, 0, 0x1); //Using Internal ADC
1146 if (eSamplingRate == Soc_Aud_I2S_SAMPLERATE_I2S_8K)
1147 {
1148 dVoiceModeSelect = 0;
1149 }
1150 else if (eSamplingRate == Soc_Aud_I2S_SAMPLERATE_I2S_16K)
1151 {
1152 dVoiceModeSelect = 1;
1153 }
1154 else if (eSamplingRate == Soc_Aud_I2S_SAMPLERATE_I2S_32K)
1155 {
1156 dVoiceModeSelect = 2;
1157 }
1158 else if (eSamplingRate == Soc_Aud_I2S_SAMPLERATE_I2S_48K)
1159 {
1160 dVoiceModeSelect = 3;
1161 }
1162 else
1163 {
1164 }
1165 Afe_Set_Reg(AFE_ADDA2_UL_SRC_CON0, (dVoiceModeSelect << 19) | (dVoiceModeSelect << 17), 0x001E0000);
1166 //Test Sine Tone
1167 //Afe_Set_Reg(AFE_ADDA2_UL_SRC_CON1, (8 << 12) | (8) | 0x8000000, 0x0C00F00F);
1168 //Afe_Set_Reg(AFE_ADDA2_UL_SRC_CON0, 0xC0000000, 0xC0000000);
1169 //Afe_Set_Reg(AFE_ADDA2_TOP_CON0, (8 << 12) | (8) | 0x8000000, 0x0C00F00F);
1170 //Test Sine Tone
1171 Afe_Set_Reg(AFE_ADDA2_NEWIF_CFG0, 0x03F87201, 0xFFFFFFFF); // up8x txif sat on
1172 }
1173 else
1174 {
1175 Afe_Set_Reg(AFE_ADDA_TOP_CON0, 1, 0x1); //Using External ADC
1176 Audio_I2S_Adc |= (AudioAdcI2S->mLR_SWAP << 31);
1177 Audio_I2S_Adc |= (AudioAdcI2S->mBuffer_Update_word << 24);
1178 Audio_I2S_Adc |= (AudioAdcI2S->mINV_LRCK << 23);
1179 Audio_I2S_Adc |= (AudioAdcI2S->mFpga_bit_test << 22);
1180 Audio_I2S_Adc |= (AudioAdcI2S->mFpga_bit << 21);
1181 Audio_I2S_Adc |= (AudioAdcI2S->mloopback << 20);
1182 Audio_I2S_Adc |= (SampleRateTransform(AudioAdcI2S->mI2S_SAMPLERATE) << 8);
1183 Audio_I2S_Adc |= (AudioAdcI2S->mI2S_FMT << 3);
1184 Audio_I2S_Adc |= (AudioAdcI2S->mI2S_WLEN << 1);
1185 printk("%s Audio_I2S_Adc = 0x%x", __FUNCTION__, Audio_I2S_Adc);
1186 Afe_Set_Reg(AFE_I2S_CON2, Audio_I2S_Adc, MASK_ALL);
1187 }
1188 return true;
1189 }
1190
1191 bool SetI2SAdcIn(AudioDigtalI2S *DigtalI2S)
1192 {
1193 uint32 Audio_I2S_Adc = 0;
1194 memcpy((void *)AudioAdcI2S, (void *)DigtalI2S, sizeof(AudioDigtalI2S));
1195
1196 if (false == AudioAdcI2SStatus)
1197 {
1198 uint32 eSamplingRate = SampleRateTransform(AudioAdcI2S->mI2S_SAMPLERATE);
1199 uint32 dVoiceModeSelect = 0;
1200 Afe_Set_Reg(AFE_ADDA_TOP_CON0, 0, 0x1); //Using Internal ADC
1201 if (eSamplingRate == Soc_Aud_I2S_SAMPLERATE_I2S_8K)
1202 {
1203 dVoiceModeSelect = 0;
1204 }
1205 else if (eSamplingRate == Soc_Aud_I2S_SAMPLERATE_I2S_16K)
1206 {
1207 dVoiceModeSelect = 1;
1208 }
1209 else if (eSamplingRate == Soc_Aud_I2S_SAMPLERATE_I2S_32K)
1210 {
1211 dVoiceModeSelect = 2;
1212 }
1213 else if (eSamplingRate == Soc_Aud_I2S_SAMPLERATE_I2S_48K)
1214 {
1215 dVoiceModeSelect = 3;
1216 }
1217 else
1218 {
1219 }
1220 Afe_Set_Reg(AFE_ADDA_UL_SRC_CON0, (dVoiceModeSelect << 19) | (dVoiceModeSelect << 17), 0x001E0000);
1221 Afe_Set_Reg(AFE_ADDA_NEWIF_CFG0, 0x03F87201, 0xFFFFFFFF); // up8x txif sat on
1222 Afe_Set_Reg(AFE_ADDA_NEWIF_CFG1, ((dVoiceModeSelect < 3) ? 1 : 3) << 10, 0x00000C00);
1223 }
1224 else
1225 {
1226 Afe_Set_Reg(AFE_ADDA_TOP_CON0, 1, 0x1); //Using External ADC
1227 Audio_I2S_Adc |= (AudioAdcI2S->mLR_SWAP << 31);
1228 Audio_I2S_Adc |= (AudioAdcI2S->mBuffer_Update_word << 24);
1229 Audio_I2S_Adc |= (AudioAdcI2S->mINV_LRCK << 23);
1230 Audio_I2S_Adc |= (AudioAdcI2S->mFpga_bit_test << 22);
1231 Audio_I2S_Adc |= (AudioAdcI2S->mFpga_bit << 21);
1232 Audio_I2S_Adc |= (AudioAdcI2S->mloopback << 20);
1233 Audio_I2S_Adc |= (SampleRateTransform(AudioAdcI2S->mI2S_SAMPLERATE) << 8);
1234 Audio_I2S_Adc |= (AudioAdcI2S->mI2S_FMT << 3);
1235 Audio_I2S_Adc |= (AudioAdcI2S->mI2S_WLEN << 1);
1236 printk("%s Audio_I2S_Adc = 0x%x", __FUNCTION__, Audio_I2S_Adc);
1237 Afe_Set_Reg(AFE_I2S_CON2, Audio_I2S_Adc, MASK_ALL);
1238 }
1239 return true;
1240 }
1241
1242 bool Audio_ModemPcm2_ASRC_Set(bool Enable)
1243 {
1244 printk("+%s(), Enable=%d\n", __func__, Enable);
1245 if (Enable)
1246 {
1247 mPcm2AsyncFifoSel = false;
1248 }
1249 else
1250 {
1251 mPcm2AsyncFifoSel = true;
1252 }
1253 printk("-%s(), mPcm2AsyncFifoSel=%d\n", __func__, mPcm2AsyncFifoSel);
1254 return 0;
1255 }
1256
1257 bool EnableSideGenHw(uint32 connection , bool direction , bool Enable)
1258 {
1259 printk("+%s(), connection = %d, direction = %d, Enable= %d\n", __FUNCTION__, connection, direction, Enable);
1260 if (Enable && direction)
1261 {
1262 switch (connection)
1263 {
1264 case Soc_Aud_InterConnectionInput_I00:
1265 case Soc_Aud_InterConnectionInput_I01:
1266 Afe_Set_Reg(AFE_SGEN_CON0, 0x048C2762, 0xffffffff);
1267 break;
1268 case Soc_Aud_InterConnectionInput_I02:
1269 Afe_Set_Reg(AFE_SGEN_CON0, 0x146C2662, 0xffffffff);
1270 break;
1271 case Soc_Aud_InterConnectionInput_I03:
1272 case Soc_Aud_InterConnectionInput_I04:
1273 Afe_Set_Reg(AFE_SGEN_CON0, 0x24862862, 0xffffffff);
1274 break;
1275 case Soc_Aud_InterConnectionInput_I05:
1276 case Soc_Aud_InterConnectionInput_I06:
1277 Afe_Set_Reg(AFE_SGEN_CON0, 0x346C2662, 0xffffffff);
1278 break;
1279 case Soc_Aud_InterConnectionInput_I07:
1280 case Soc_Aud_InterConnectionInput_I08:
1281 Afe_Set_Reg(AFE_SGEN_CON0, 0x446C2662, 0xffffffff);
1282 break;
1283 case Soc_Aud_InterConnectionInput_I09:
1284 Afe_Set_Reg(AFE_SGEN_CON0, 0x546C2662, 0xffffffff);
1285 case Soc_Aud_InterConnectionInput_I10:
1286 case Soc_Aud_InterConnectionInput_I11:
1287 Afe_Set_Reg(AFE_SGEN_CON0, 0x646C2662, 0xffffffff);
1288 break;
1289 case Soc_Aud_InterConnectionInput_I12:
1290 case Soc_Aud_InterConnectionInput_I13:
1291 Afe_Set_Reg(AFE_SGEN_CON0, 0x746C2662, 0xffffffff);
1292 break;
1293 case Soc_Aud_InterConnectionInput_I14:
1294 Afe_Set_Reg(AFE_SGEN_CON0, 0x846C2662, 0xffffffff);
1295 break;
1296 case Soc_Aud_InterConnectionInput_I15:
1297 case Soc_Aud_InterConnectionInput_I16:
1298 Afe_Set_Reg(AFE_SGEN_CON0, 0x946C2662, 0xffffffff);
1299 break;
1300 case Soc_Aud_InterConnectionInput_I17:
1301 case Soc_Aud_InterConnectionInput_I18:
1302 Afe_Set_Reg(AFE_SGEN_CON0, 0xa46C2662, 0xffffffff);
1303 break;
1304 case Soc_Aud_InterConnectionInput_I19:
1305 case Soc_Aud_InterConnectionInput_I20:
1306 Afe_Set_Reg(AFE_SGEN_CON0, 0xb46C2662, 0xffffffff);
1307 break;
1308 case Soc_Aud_InterConnectionInput_I21:
1309 case Soc_Aud_InterConnectionInput_I22:
1310 break;
1311 Afe_Set_Reg(AFE_SGEN_CON0, 0xc46C2662, 0xffffffff);
1312 default:
1313 break;
1314 }
1315 }
1316 else if (Enable)
1317 {
1318 switch (connection)
1319 {
1320 case Soc_Aud_InterConnectionOutput_O00:
1321 case Soc_Aud_InterConnectionOutput_O01:
1322 Afe_Set_Reg(AFE_SGEN_CON0, 0x0c7c27c2, 0xffffffff);
1323 break;
1324 case Soc_Aud_InterConnectionOutput_O02:
1325 Afe_Set_Reg(AFE_SGEN_CON0, 0x1c6c26c2, 0xffffffff);
1326 break;
1327 case Soc_Aud_InterConnectionOutput_O03:
1328 case Soc_Aud_InterConnectionOutput_O04:
1329 Afe_Set_Reg(AFE_SGEN_CON0, 0x2c8c28c2, 0xffffffff);
1330 break;
1331 case Soc_Aud_InterConnectionOutput_O05:
1332 case Soc_Aud_InterConnectionOutput_O06:
1333 Afe_Set_Reg(AFE_SGEN_CON0, 0x3c6c26c2, 0xffffffff);
1334 break;
1335 case Soc_Aud_InterConnectionOutput_O07:
1336 case Soc_Aud_InterConnectionOutput_O08:
1337 Afe_Set_Reg(AFE_SGEN_CON0, 0x4c6c26c2, 0xffffffff);
1338 break;
1339 case Soc_Aud_InterConnectionOutput_O09:
1340 case Soc_Aud_InterConnectionOutput_O10:
1341 Afe_Set_Reg(AFE_SGEN_CON0, 0x5c6c26c2, 0xffffffff);
1342 break;
1343 case Soc_Aud_InterConnectionOutput_O11:
1344 Afe_Set_Reg(AFE_SGEN_CON0, 0x6c6c26c2, 0xffffffff);
1345 break;
1346 case Soc_Aud_InterConnectionOutput_O12:
1347 if (Soc_Aud_I2S_SAMPLERATE_I2S_8K == mAudioMEMIF[Soc_Aud_Digital_Block_MEM_MOD_DAI]->mSampleRate) //MD connect BT Verify (8K SamplingRate)
1348 {
1349 Afe_Set_Reg(AFE_SGEN_CON0, 0x7c0e80e8, 0xffffffff);
1350 }
1351 else if (Soc_Aud_I2S_SAMPLERATE_I2S_16K == mAudioMEMIF[Soc_Aud_Digital_Block_MEM_MOD_DAI]->mSampleRate)
1352 {
1353 Afe_Set_Reg(AFE_SGEN_CON0, 0x7c0f00f0, 0xffffffff);
1354 }
1355 else
1356 {
1357 Afe_Set_Reg(AFE_SGEN_CON0, 0x7c6c26c2, 0xffffffff); //Default
1358 }
1359 break;
1360 case Soc_Aud_InterConnectionOutput_O13:
1361 case Soc_Aud_InterConnectionOutput_O14:
1362 Afe_Set_Reg(AFE_SGEN_CON0, 0x8c6c26c2, 0xffffffff);
1363 break;
1364 case Soc_Aud_InterConnectionOutput_O15:
1365 case Soc_Aud_InterConnectionOutput_O16:
1366 Afe_Set_Reg(AFE_SGEN_CON0, 0x9c6c26c2, 0xffffffff);
1367 break;
1368 case Soc_Aud_InterConnectionOutput_O17:
1369 case Soc_Aud_InterConnectionOutput_O18:
1370 Afe_Set_Reg(AFE_SGEN_CON0, 0xac6c26c2, 0xffffffff);
1371 break;
1372 case Soc_Aud_InterConnectionOutput_O19:
1373 case Soc_Aud_InterConnectionOutput_O20:
1374 Afe_Set_Reg(AFE_SGEN_CON0, 0xbc6c26c2, 0xffffffff);
1375 break;
1376 case Soc_Aud_InterConnectionOutput_O21:
1377 case Soc_Aud_InterConnectionOutput_O22:
1378 Afe_Set_Reg(AFE_SGEN_CON0, 0xcc6c26c2, 0xffffffff);
1379 break;
1380 case Soc_Aud_InterConnectionOutput_O23:
1381 case Soc_Aud_InterConnectionOutput_O24:
1382 Afe_Set_Reg(AFE_SGEN_CON0, 0xdc6c26c2, 0xffffffff);
1383 break;
1384 case Soc_Aud_InterConnectionOutput_O25:
1385 Afe_Set_Reg(AFE_SGEN_CON0, 0xec6c26c2, 0xffffffff);
1386 default:
1387 break;
1388 }
1389 }
1390 else
1391 {
1392 //don't set [31:28] as 0 when disable sinetone HW, because it will repalce i00/i01 input with sine gen output.
1393 //Set 0xf is correct way to disconnect sinetone HW to any I/O.
1394 Afe_Set_Reg(AFE_SGEN_CON0, 0xf0000000 , 0xffffffff);
1395 }
1396 return true;
1397 }
1398
1399 bool Set2ndI2SAdcEnable(bool bEnable)
1400 {
1401 Afe_Set_Reg(AFE_ADDA2_UL_SRC_CON0, bEnable ? 1 : 0, 0x01);
1402 mAudioMEMIF[Soc_Aud_Digital_Block_I2S_IN_ADC_2]->mState = bEnable;
1403 if (bEnable == true)
1404 {
1405 Afe_Set_Reg(AFE_ADDA_UL_DL_CON0, 0x0001, 0x0001);
1406 }
1407 else if (mAudioMEMIF[Soc_Aud_Digital_Block_I2S_OUT_DAC]->mState == false &&
1408 mAudioMEMIF[Soc_Aud_Digital_Block_I2S_IN_ADC]->mState == false &&
1409 mAudioMEMIF[Soc_Aud_Digital_Block_I2S_IN_ADC_2]->mState == false)
1410 {
1411 Afe_Set_Reg(AFE_ADDA_UL_DL_CON0, 0x0000, 0x0001);
1412 }
1413 return true;
1414 }
1415
1416 bool SetI2SAdcEnable(bool bEnable)
1417 {
1418 Afe_Set_Reg(AFE_ADDA_UL_SRC_CON0, bEnable ? 1 : 0, 0x01);
1419 mAudioMEMIF[Soc_Aud_Digital_Block_I2S_IN_ADC]->mState = bEnable;
1420 if (bEnable == true)
1421 {
1422 Afe_Set_Reg(AFE_ADDA_UL_DL_CON0, 0x0001, 0x0001);
1423 }
1424 else if (mAudioMEMIF[Soc_Aud_Digital_Block_I2S_OUT_DAC]->mState == false &&
1425 mAudioMEMIF[Soc_Aud_Digital_Block_I2S_IN_ADC]->mState == false &&
1426 mAudioMEMIF[Soc_Aud_Digital_Block_I2S_IN_ADC_2]->mState == false)
1427 {
1428 Afe_Set_Reg(AFE_ADDA_UL_DL_CON0, 0x0000, 0x0001);
1429 }
1430 return true;
1431 }
1432
1433 bool Set2ndI2SEnable(bool bEnable)
1434 {
1435 Afe_Set_Reg(AFE_I2S_CON, bEnable, 0x1);
1436 return true;
1437 }
1438
1439 bool CleanPreDistortion()
1440 {
1441 //printk("%s \n", __FUNCTION__);
1442 Afe_Set_Reg(AFE_ADDA_PREDIS_CON0, 0, MASK_ALL);
1443 Afe_Set_Reg(AFE_ADDA_PREDIS_CON1, 0, MASK_ALL);
1444 return true;
1445 }
1446
1447 bool SetDLSrc2(uint32 SampleRate)
1448 {
1449 uint32 AfeAddaDLSrc2Con0, AfeAddaDLSrc2Con1;
1450 if (SampleRate == 8000)
1451 {
1452 AfeAddaDLSrc2Con0 = 0;
1453 }
1454 else if (SampleRate == 11025)
1455 {
1456 AfeAddaDLSrc2Con0 = 1;
1457 }
1458 else if (SampleRate == 12000)
1459 {
1460 AfeAddaDLSrc2Con0 = 2;
1461 }
1462 else if (SampleRate == 16000)
1463 {
1464 AfeAddaDLSrc2Con0 = 3;
1465 }
1466 else if (SampleRate == 22050)
1467 {
1468 AfeAddaDLSrc2Con0 = 4;
1469 }
1470 else if (SampleRate == 24000)
1471 {
1472 AfeAddaDLSrc2Con0 = 5;
1473 }
1474 else if (SampleRate == 32000)
1475 {
1476 AfeAddaDLSrc2Con0 = 6;
1477 }
1478 else if (SampleRate == 44100)
1479 {
1480 AfeAddaDLSrc2Con0 = 7;
1481 }
1482 else if (SampleRate == 48000)
1483 {
1484 AfeAddaDLSrc2Con0 = 8;
1485 }
1486 else
1487 {
1488 AfeAddaDLSrc2Con0 = 7; //Default 44100
1489 }
1490 //ASSERT(0);
1491 if (AfeAddaDLSrc2Con0 == 0 || AfeAddaDLSrc2Con0 == 3) //8k or 16k voice mode
1492 {
1493 AfeAddaDLSrc2Con0 = (AfeAddaDLSrc2Con0 << 28) | (0x03 << 24) | (0x03 << 11) | (0x01 << 5);
1494 }
1495 else
1496 {
1497 AfeAddaDLSrc2Con0 = (AfeAddaDLSrc2Con0 << 28) | (0x03 << 24) | (0x03 << 11);
1498 }
1499 //SA suggest apply -0.3db to audio/speech path
1500 AfeAddaDLSrc2Con0 = AfeAddaDLSrc2Con0 | (0x01 << 1); //2013.02.22 for voice mode degrade 0.3 db
1501 AfeAddaDLSrc2Con1 = 0xf74f0000;
1502
1503 Afe_Set_Reg(AFE_ADDA_DL_SRC2_CON0, AfeAddaDLSrc2Con0, MASK_ALL);
1504 Afe_Set_Reg(AFE_ADDA_DL_SRC2_CON1, AfeAddaDLSrc2Con1, MASK_ALL);
1505 return true;
1506
1507 }
1508
1509 bool SetI2SDacOut(uint32 SampleRate)
1510 {
1511 uint32 Audio_I2S_Dac = 0;
1512 printk("SetI2SDacOut \n");
1513 CleanPreDistortion();
1514 SetDLSrc2(SampleRate);
1515 Audio_I2S_Dac |= (Soc_Aud_LR_SWAP_NO_SWAP << 31);
1516 Audio_I2S_Dac |= (SampleRateTransform(SampleRate) << 8);
1517 Audio_I2S_Dac |= (Soc_Aud_INV_LRCK_NO_INVERSE << 5);
1518 Audio_I2S_Dac |= (Soc_Aud_I2S_FORMAT_I2S << 3);
1519 Audio_I2S_Dac |= (Soc_Aud_I2S_WLEN_WLEN_16BITS << 1);
1520 Audio_I2S_Dac |= (0 << 12); // low gitter mode
1521 Afe_Set_Reg(AFE_I2S_CON1, Audio_I2S_Dac, MASK_ALL);
1522 return true;
1523 }
1524
1525 bool SetHwDigitalGainMode(uint32 GainType, uint32 SampleRate, uint32 SamplePerStep)
1526 {
1527 //printk("SetHwDigitalGainMode GainType = %d, SampleRate = %d, SamplePerStep= %d\n", GainType, SampleRate, SamplePerStep);
1528 uint32 value = 0;
1529 value = (SamplePerStep << 8) | (SampleRateTransform(SampleRate) << 4);
1530 switch (GainType)
1531 {
1532 case Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN1:
1533 Afe_Set_Reg(AFE_GAIN1_CON0, value, 0xfff0);
1534 break;
1535 case Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN2:
1536 Afe_Set_Reg(AFE_GAIN2_CON0, value, 0xfff0);
1537 break;
1538 default:
1539 return false;
1540 }
1541 return true;
1542 }
1543
1544 bool SetHwDigitalGainEnable(int GainType, bool Enable)
1545 {
1546 printk("+%s(), GainType = %d, Enable = %d\n", __FUNCTION__, GainType, Enable);
1547 switch (GainType)
1548 {
1549 case Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN1:
1550 if (Enable)
1551 {
1552 Afe_Set_Reg(AFE_GAIN1_CUR, 0, 0xFFFFFFFF); //Let current gain be 0 to ramp up
1553 }
1554 Afe_Set_Reg(AFE_GAIN1_CON0, Enable, 0x1);
1555 break;
1556 case Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN2:
1557 if (Enable)
1558 {
1559 Afe_Set_Reg(AFE_GAIN2_CUR, 0, 0xFFFFFFFF); //Let current gain be 0 to ramp up
1560 }
1561 Afe_Set_Reg(AFE_GAIN2_CON0, Enable, 0x1);
1562 break;
1563 default:
1564 printk("%s with no match type\n", __func__);
1565 return false;
1566 }
1567 return true;
1568 }
1569
1570 bool SetHwDigitalGain(uint32 Gain , int GainType)
1571 {
1572 printk("+%s(), Gain = 0x%x, gain type = %d\n", __func__, Gain, GainType);
1573 switch (GainType)
1574 {
1575 case Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN1:
1576 Afe_Set_Reg(AFE_GAIN1_CON1, Gain, 0xffffffff);
1577 break;
1578 case Soc_Aud_Hw_Digital_Gain_HW_DIGITAL_GAIN2:
1579 Afe_Set_Reg(AFE_GAIN2_CON1, Gain, 0xffffffff);
1580 break;
1581 default:
1582 printk("%s with no match type\n", __func__);
1583 return false;
1584 }
1585 return true;
1586 }
1587
1588 bool SetModemPcmConfig(int modem_index , AudioDigitalPCM p_modem_pcm_attribute)
1589 {
1590 uint32 reg_pcm2_intf_con = 0;
1591 uint32 reg_pcm_intf_con1 = 0;
1592 printk("+%s()\n", __func__);
1593 if (modem_index == MODEM_1)
1594 {
1595 p_modem_pcm_attribute.mAsyncFifoSel = mPcm2AsyncFifoSel;
1596 reg_pcm2_intf_con |= (p_modem_pcm_attribute.mTxLchRepeatSel & 0x1) << 13;
1597 reg_pcm2_intf_con |= (p_modem_pcm_attribute.mVbt16kModeSel & 0x1) << 12;
1598 reg_pcm2_intf_con |= (p_modem_pcm_attribute.mSingelMicSel & 0x1) << 7;
1599 reg_pcm2_intf_con |= (p_modem_pcm_attribute.mAsyncFifoSel & 0x1) << 6;
1600 reg_pcm2_intf_con |= (p_modem_pcm_attribute.mPcmWordLength & 0x1) << 4;
1601 reg_pcm2_intf_con |= (p_modem_pcm_attribute.mPcmModeWidebandSel & 0x1) << 3;
1602 reg_pcm2_intf_con |= (p_modem_pcm_attribute.mPcmFormat & 0x3) << 1;
1603 printk("%s(), PCM2_INTF_CON(0x%x) = 0x%x\n", __FUNCTION__, PCM2_INTF_CON, reg_pcm2_intf_con);
1604 Afe_Set_Reg(PCM2_INTF_CON, reg_pcm2_intf_con, MASK_ALL);
1605 if (p_modem_pcm_attribute.mPcmModeWidebandSel == Soc_Aud_PCM_MODE_PCM_MODE_8K)
1606 {
1607 Afe_Set_Reg(AFE_ASRC2_CON1, 0x00098580, 0xffffffff);
1608 Afe_Set_Reg(AFE_ASRC2_CON2, 0x00400000, 0xffffffff);
1609 Afe_Set_Reg(AFE_ASRC2_CON3, 0x00400000, 0xffffffff);
1610 Afe_Set_Reg(AFE_ASRC2_CON4, 0x00098580, 0xffffffff);
1611 Afe_Set_Reg(AFE_ASRC2_CON7, 0x0004c2c0, 0xffffffff);
1612 Afe_Set_Reg(AFE_ASRC3_CON1, 0x00098580, 0xffffffff);
1613 Afe_Set_Reg(AFE_ASRC3_CON2, 0x00400000, 0xffffffff);
1614 Afe_Set_Reg(AFE_ASRC3_CON3, 0x00400000, 0xffffffff);
1615 Afe_Set_Reg(AFE_ASRC3_CON4, 0x00098580, 0xffffffff);
1616 Afe_Set_Reg(AFE_ASRC3_CON7, 0x0004c2c0, 0xffffffff);
1617 }
1618 else if (p_modem_pcm_attribute.mPcmModeWidebandSel == Soc_Aud_PCM_MODE_PCM_MODE_16K)
1619 {
1620 Afe_Set_Reg(AFE_ASRC2_CON1, 0x0004c2c0, 0xffffffff);
1621 Afe_Set_Reg(AFE_ASRC2_CON2, 0x00400000, 0xffffffff);
1622 Afe_Set_Reg(AFE_ASRC2_CON3, 0x00400000, 0xffffffff);
1623 Afe_Set_Reg(AFE_ASRC2_CON4, 0x0004c2c0, 0xffffffff);
1624 Afe_Set_Reg(AFE_ASRC2_CON7, 0x00026160, 0xffffffff);
1625 Afe_Set_Reg(AFE_ASRC3_CON1, 0x0004c2c0, 0xffffffff);
1626 Afe_Set_Reg(AFE_ASRC3_CON2, 0x00400000, 0xffffffff);
1627 Afe_Set_Reg(AFE_ASRC3_CON3, 0x00400000, 0xffffffff);
1628 Afe_Set_Reg(AFE_ASRC3_CON4, 0x0004c2c0, 0xffffffff);
1629 Afe_Set_Reg(AFE_ASRC3_CON7, 0x00026160, 0xffffffff);
1630 }
1631 else if (p_modem_pcm_attribute.mPcmModeWidebandSel == Soc_Aud_PCM_MODE_PCM_MODE_32K)
1632 {
1633 Afe_Set_Reg(AFE_ASRC2_CON1, 0x00026160, 0xffffffff);
1634 Afe_Set_Reg(AFE_ASRC2_CON2, 0x00400000, 0xffffffff);
1635 Afe_Set_Reg(AFE_ASRC2_CON3, 0x00400000, 0xffffffff);
1636 Afe_Set_Reg(AFE_ASRC2_CON4, 0x00026160, 0xffffffff);
1637 Afe_Set_Reg(AFE_ASRC2_CON7, 0x000130b0, 0xffffffff);
1638 Afe_Set_Reg(AFE_ASRC3_CON1, 0x00026160, 0xffffffff);
1639 Afe_Set_Reg(AFE_ASRC3_CON2, 0x00400000, 0xffffffff);
1640 Afe_Set_Reg(AFE_ASRC3_CON3, 0x00400000, 0xffffffff);
1641 Afe_Set_Reg(AFE_ASRC3_CON4, 0x00026160, 0xffffffff);
1642 Afe_Set_Reg(AFE_ASRC3_CON7, 0x000130b0, 0xffffffff);
1643 }
1644
1645 }
1646 else if (modem_index == MODEM_2 || modem_index == MODEM_EXTERNAL) // MODEM_2 use PCM_INTF_CON1 (0x530) !!!
1647 {
1648 if (p_modem_pcm_attribute.mPcmModeWidebandSel == Soc_Aud_PCM_MODE_PCM_MODE_8K)
1649 {
1650 Afe_Set_Reg(AFE_ASRC_CON1, 0x00098580, 0xffffffff);
1651 Afe_Set_Reg(AFE_ASRC_CON2, 0x00400000, 0xffffffff);
1652 Afe_Set_Reg(AFE_ASRC_CON3, 0x00400000, 0xffffffff);
1653 Afe_Set_Reg(AFE_ASRC_CON4, 0x00098580, 0xffffffff);
1654 Afe_Set_Reg(AFE_ASRC_CON7, 0x0004c2c0, 0xffffffff);
1655 }
1656 else if (p_modem_pcm_attribute.mPcmModeWidebandSel == Soc_Aud_PCM_MODE_PCM_MODE_16K)
1657 {
1658 Afe_Set_Reg(AFE_ASRC_CON1, 0x0004c2c0, 0xffffffff);
1659 Afe_Set_Reg(AFE_ASRC_CON2, 0x00400000, 0xffffffff);
1660 Afe_Set_Reg(AFE_ASRC_CON3, 0x00400000, 0xffffffff);
1661 Afe_Set_Reg(AFE_ASRC_CON4, 0x0004c2c0, 0xffffffff);
1662 Afe_Set_Reg(AFE_ASRC_CON7, 0x00026160, 0xffffffff);
1663 }
1664 else if (p_modem_pcm_attribute.mPcmModeWidebandSel == Soc_Aud_PCM_MODE_PCM_MODE_32K)
1665 {
1666 Afe_Set_Reg(AFE_ASRC_CON1, 0x00026160, 0xffffffff);
1667 Afe_Set_Reg(AFE_ASRC_CON2, 0x00400000, 0xffffffff);
1668 Afe_Set_Reg(AFE_ASRC_CON3, 0x00400000, 0xffffffff);
1669 Afe_Set_Reg(AFE_ASRC_CON4, 0x00026160, 0xffffffff);
1670 Afe_Set_Reg(AFE_ASRC_CON7, 0x000130b0, 0xffffffff);
1671 }
1672
1673 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mBclkInInv & 0x01) << 20;
1674 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mTxLchRepeatSel & 0x01) << 19;
1675 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mVbt16kModeSel & 0x01) << 18;
1676 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mExtModemSel & 0x01) << 17;
1677 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mExtendBckSyncLength & 0x1F) << 9;
1678 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mExtendBckSyncTypeSel & 0x01) << 8;
1679 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mSingelMicSel & 0x01) << 7;
1680 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mAsyncFifoSel & 0x01) << 6;
1681 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mSlaveModeSel & 0x01) << 5;
1682 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mPcmWordLength & 0x01) << 4;
1683 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mPcmModeWidebandSel & 0x01) << 3;
1684 reg_pcm_intf_con1 |= (p_modem_pcm_attribute.mPcmFormat & 0x03) << 1;
1685
1686 printk("%s(), PCM_INTF_CON1(0x%x) = 0x%x", __FUNCTION__, PCM_INTF_CON, reg_pcm_intf_con1);
1687 Afe_Set_Reg(PCM_INTF_CON, reg_pcm_intf_con1, MASK_ALL);
1688
1689 }
1690 return true;
1691 }
1692
1693 bool SetModemPcmEnable(int modem_index, bool modem_pcm_on)
1694 {
1695 uint32 dNeedDisableASM = 0;
1696 printk("+%s(), modem_index = %d, modem_pcm_on = %d\n", __FUNCTION__, modem_index, modem_pcm_on);
1697
1698 if (modem_index == MODEM_1) // MODEM_1 use PCM2_INTF_CON (0x53C) !!!
1699 {
1700 if (modem_pcm_on == true)
1701 {
1702 printk("%s(), modem_index(%d), modem_pcm_on = %d, mPcm2AsyncFifoSel = %d\n", __FUNCTION__, modem_index, modem_pcm_on, mPcm2AsyncFifoSel);
1703 if (mPcm2AsyncFifoSel == false) // turn on ASRC before Modem PCM on
1704 {
1705 Afe_Set_Reg(AFE_ASRC2_CON6, 0x00bf188f, MASK_ALL);
1706 Afe_Set_Reg(AFE_ASRC2_CON0, 0x06003031, MASK_ALL);
1707 Afe_Set_Reg(AFE_ASRC3_CON6, 0x00bf188f, MASK_ALL);
1708 Afe_Set_Reg(AFE_ASRC3_CON0, 0x03003031, MASK_ALL);
1709 }
1710 Afe_Set_Reg(PCM2_INTF_CON, modem_pcm_on, 0x1);
1711 }
1712 else if (modem_pcm_on == false)
1713 {
1714 Afe_Set_Reg(PCM2_INTF_CON, modem_pcm_on, 0x1);
1715 dNeedDisableASM = Afe_Get_Reg(AFE_ASRC2_CON0) & 0x1;
1716 printk("%s(), modem_index(%d), modem_pcm_on = %d, dNeedDisableASM=%d\n", __FUNCTION__, modem_index, modem_pcm_on, dNeedDisableASM);
1717 if (dNeedDisableASM) // turn off ASRC after Modem PCM off
1718 {
1719 Afe_Set_Reg(AFE_ASRC2_CON6, 0x00000000, MASK_ALL);
1720 Afe_Set_Reg(AFE_ASRC2_CON0, 0x06003030, MASK_ALL);
1721 Afe_Set_Reg(AFE_ASRC3_CON6, 0x00000000, MASK_ALL);
1722 Afe_Set_Reg(AFE_ASRC3_CON0, 0x03003030, MASK_ALL);
1723 }
1724 mPcm2AsyncFifoSel = true;//reset to default value
1725 }
1726 mAudioMEMIF[Soc_Aud_Digital_Block_MODEM_PCM_1_O]->mState = modem_pcm_on;
1727 }
1728 else if (modem_index == MODEM_2 || modem_index == MODEM_EXTERNAL) // MODEM_2 use PCM_INTF_CON1 (0x530) !!!
1729 {
1730 if (modem_pcm_on == true) // turn on ASRC before Modem PCM on
1731 {
1732 Afe_Set_Reg(AFE_ASRC_CON6, 0x005f188f, MASK_ALL); // pre ver. 0x0001188F
1733 Afe_Set_Reg(AFE_ASRC_CON0, 0x86083031, MASK_ALL);
1734 Afe_Set_Reg(PCM_INTF_CON, 0x1, 0x1);
1735 }
1736 else if (modem_pcm_on == false) // turn off ASRC after Modem PCM off
1737 {
1738 Afe_Set_Reg(PCM_INTF_CON, 0x0, 0x1);
1739 Afe_Set_Reg(AFE_ASRC_CON6, 0x00000000, MASK_ALL);
1740 dNeedDisableASM = (Afe_Get_Reg(AFE_ASRC_CON0) & 0x0040) ? 1 : 0;
1741 Afe_Set_Reg(AFE_ASRC_CON0, 0, (1 << 4 | 1 << 5 | dNeedDisableASM));
1742 Afe_Set_Reg(AFE_ASRC_CON0, 0x0, 0x1);
1743 }
1744 mAudioMEMIF[Soc_Aud_Digital_Block_MODEM_PCM_2_O]->mState = modem_pcm_on;
1745 }
1746 else
1747 {
1748 printk("%s(), no such modem_index: %d!!", __FUNCTION__, modem_index);
1749 return false;
1750 }
1751 return true;
1752 }
1753
1754
1755 bool EnableSideToneFilter(bool stf_on)
1756 {
1757
1758 // MD max support 16K sampling rate
1759 const uint8_t kSideToneHalfTapNum = sizeof(kSideToneCoefficientTable16k) / sizeof(uint16_t);
1760 printk("+%s(), stf_on = %d\n", __func__, stf_on);
1761 AudDrv_Clk_On();
1762
1763 if (stf_on == false)
1764 {
1765 // bypass STF result & disable
1766 const bool bypass_stf_on = true;
1767 uint32_t reg_value = (bypass_stf_on << 31) | (stf_on << 8);
1768 Afe_Set_Reg(AFE_SIDETONE_CON1, reg_value, MASK_ALL);
1769 printk("%s(), AFE_SIDETONE_CON1[0x%x] = 0x%x\n", __FUNCTION__, AFE_SIDETONE_CON1, reg_value);
1770
1771 // set side tone gain = 0
1772 Afe_Set_Reg(AFE_SIDETONE_GAIN, 0, MASK_ALL);
1773 printk("%s(), AFE_SIDETONE_GAIN[0x%x] = 0x%x\n", __FUNCTION__, AFE_SIDETONE_GAIN, 0);
1774 }
1775 else
1776 {
1777 const bool bypass_stf_on = false;
1778 // using STF result & enable & set half tap num
1779 uint32_t write_reg_value = (bypass_stf_on << 31) | (stf_on << 8) | kSideToneHalfTapNum;
1780
1781 // set side tone coefficient
1782 const bool enable_read_write = true; // enable read/write side tone coefficient
1783 const bool read_write_sel = true; // for write case
1784 const bool sel_ch2 = false; // using uplink ch1 as STF input
1785 uint32_t read_reg_value = Afe_Get_Reg(AFE_SIDETONE_CON0);
1786 size_t coef_addr = 0;
1787
1788 printk("%s(), AFE_SIDETONE_GAIN[0x%x] = 0x%x\n", __FUNCTION__, AFE_SIDETONE_GAIN, 0);
1789 // set side tone gain
1790 Afe_Set_Reg(AFE_SIDETONE_GAIN, 0, MASK_ALL);
1791 Afe_Set_Reg(AFE_SIDETONE_CON1, write_reg_value, MASK_ALL);
1792 printk("%s(), AFE_SIDETONE_CON1[0x%x] = 0x%x\n", __FUNCTION__, AFE_SIDETONE_CON1, write_reg_value);
1793
1794 for (coef_addr = 0; coef_addr < kSideToneHalfTapNum; coef_addr++)
1795 {
1796 bool old_write_ready = (read_reg_value >> 29) & 0x1;
1797 bool new_write_ready = 0;
1798 int try_cnt = 0;
1799 write_reg_value = enable_read_write << 25 |
1800 read_write_sel << 24 |
1801 sel_ch2 << 23 |
1802 coef_addr << 16 |
1803 kSideToneCoefficientTable16k[coef_addr];
1804 Afe_Set_Reg(AFE_SIDETONE_CON0, write_reg_value, 0x39FFFFF);
1805 printk("%s(), AFE_SIDETONE_CON0[0x%x] = 0x%x\n", __FUNCTION__, AFE_SIDETONE_CON0, write_reg_value);
1806
1807 // wait until flag write_ready changed (means write done)
1808 for (try_cnt = 0; try_cnt < 10; try_cnt++) // max try 10 times
1809 {
1810 msleep(3);
1811 read_reg_value = Afe_Get_Reg(AFE_SIDETONE_CON0);
1812 new_write_ready = (read_reg_value >> 29) & 0x1;
1813 if (new_write_ready != old_write_ready) // flip => ok
1814 {
1815 break;
1816 }
1817 else
1818 {
1819 BUG_ON(new_write_ready != old_write_ready);
1820 return false;
1821 }
1822 }
1823 }
1824 }
1825 AudDrv_Clk_Off();
1826 printk("-%s(), stf_on = %d\n", __FUNCTION__, stf_on);
1827 return true;
1828 }
1829
1830
1831 bool SetMemoryPathEnable(uint32 Aud_block, bool bEnable)
1832 {
1833 printk("%s Aud_block = %d bEnable = %d \n", __func__, Aud_block, bEnable);
1834 if (Aud_block >= Soc_Aud_Digital_Block_NUM_OF_DIGITAL_BLOCK)
1835 {
1836 return false;
1837 }
1838 // set for counter
1839 if (bEnable == true)
1840 {
1841 if (mAudioMEMIF[Aud_block]->mUserCount == 0)
1842 {
1843 mAudioMEMIF[Aud_block]->mState = true;
1844 }
1845 mAudioMEMIF[Aud_block]->mUserCount++;
1846 }
1847 else
1848 {
1849 mAudioMEMIF[Aud_block]->mUserCount--;
1850 if (mAudioMEMIF[Aud_block]->mUserCount == 0)
1851 {
1852 mAudioMEMIF[Aud_block]->mState = false;
1853 }
1854 if (mAudioMEMIF[Aud_block]->mUserCount < 0)
1855 {
1856 mAudioMEMIF[Aud_block]->mUserCount = 0;
1857 printk("warning , user count <0 \n");
1858 }
1859 }
1860 printk("%s Aud_block = %d mAudioMEMIF[Aud_block]->mUserCount = %d \n", __func__, Aud_block, mAudioMEMIF[Aud_block]->mUserCount);
1861
1862 if (Aud_block > Soc_Aud_Digital_Block_NUM_OF_MEM_INTERFACE)
1863 {
1864 return true;
1865 }
1866
1867 if ((bEnable == true) && (mAudioMEMIF[Aud_block]->mUserCount == 1))
1868 {
1869 Afe_Set_Reg(AFE_DAC_CON0, bEnable << (Aud_block + 1) , 1 << (Aud_block + 1));
1870 }
1871 else if ((bEnable == false) && (mAudioMEMIF[Aud_block]->mUserCount == 0))
1872 {
1873 Afe_Set_Reg(AFE_DAC_CON0, bEnable << (Aud_block + 1), 1 << (Aud_block + 1));
1874 }
1875
1876 return true;
1877 }
1878
1879 bool GetMemoryPathEnable(uint32 Aud_block)
1880 {
1881 if (Aud_block < Soc_Aud_Digital_Block_NUM_OF_DIGITAL_BLOCK)
1882 {
1883 return mAudioMEMIF[Aud_block]->mState;
1884 }
1885 return false;
1886 }
1887
1888 bool SetI2SDacEnable(bool bEnable)
1889 {
1890 printk("%s bEnable = %d", __func__, bEnable);
1891 if (bEnable)
1892 {
1893 Afe_Set_Reg(AFE_ADDA_DL_SRC2_CON0, bEnable, 0x01);
1894 Afe_Set_Reg(AFE_I2S_CON1, bEnable, 0x1);
1895 Afe_Set_Reg(AFE_ADDA_UL_DL_CON0, bEnable, 0x0001);
1896 Afe_Set_Reg(FPGA_CFG1, 0, 0x10); //For FPGA Pin the same with DAC
1897 }
1898 else
1899 {
1900 Afe_Set_Reg(AFE_ADDA_DL_SRC2_CON0, bEnable, 0x01);
1901 Afe_Set_Reg(AFE_I2S_CON1, bEnable, 0x1);
1902
1903 if (mAudioMEMIF[Soc_Aud_Digital_Block_I2S_OUT_DAC]->mState == false &&
1904 mAudioMEMIF[Soc_Aud_Digital_Block_I2S_IN_ADC]->mState == false)
1905 {
1906 Afe_Set_Reg(AFE_ADDA_UL_DL_CON0, bEnable, 0x0001);
1907 }
1908 Afe_Set_Reg(FPGA_CFG1, 1 << 4, 0x10); //For FPGA Pin the same with DAC
1909 }
1910 return true;
1911 }
1912
1913 bool GetI2SDacEnable()
1914 {
1915 return mAudioMEMIF[Soc_Aud_Digital_Block_I2S_OUT_DAC]->mState ;
1916 }
1917
1918 bool checkUplinkMEMIfStatus()
1919 {
1920 int i = 0;
1921 for (i = Soc_Aud_Digital_Block_MEM_VUL ; i <= Soc_Aud_Digital_Block_MEM_VUL_DATA2 ; i ++)
1922 {
1923 if (mAudioMEMIF[i]->mState == true)
1924 {
1925 return true;
1926 }
1927 }
1928 return false;
1929 }
1930
1931 bool SetHDMIChannels(uint32 Channels)
1932 {
1933 printk("+%s(), Channels = %d\n", __func__, Channels);
1934 mHDMIOutput->mChannels = Channels;
1935 Afe_Set_Reg(AFE_HDMI_OUT_CON0, (Channels << 4), 0x00f0);
1936
1937 Afe_Set_Reg(AFE_HDMI_OUT_CON0, 0, 0x0100);
1938
1939 return true;
1940 }
1941
1942 bool SetHDMIEnable(bool bEnable)
1943 {
1944 printk("+%s(), bEnable = %d \n", __func__, bEnable);
1945 Afe_Set_Reg(AFE_HDMI_OUT_CON0, bEnable , 0x0001);
1946 return true;
1947 }
1948
1949 bool SetHDMIConnection(uint32 ConnectionState, uint32 Input , uint32 Output)
1950 {
1951 printk("+%s(), Input = %d, Output = %d\n", __FUNCTION__, Input, Output);
1952 switch (Output)
1953 {
1954 case Soc_Aud_InterConnectionOutput_O30:
1955 Afe_Set_Reg(AFE_HDMI_CONN0, Input , 0x0007);
1956 break;
1957 case Soc_Aud_InterConnectionOutput_O31:
1958 Afe_Set_Reg(AFE_HDMI_CONN0, (Input << 3), (0x0007 << 3));
1959 break;
1960 case Soc_Aud_InterConnectionOutput_O32:
1961 Afe_Set_Reg(AFE_HDMI_CONN0, (Input << 6), (0x0007 << 6));
1962 break;
1963 case Soc_Aud_InterConnectionOutput_O33:
1964 Afe_Set_Reg(AFE_HDMI_CONN0, (Input << 9), (0x0007 << 9));
1965 break;
1966 case Soc_Aud_InterConnectionOutput_O34:
1967 Afe_Set_Reg(AFE_HDMI_CONN0, (Input << 12), (0x0007 << 12));
1968 break;
1969 case Soc_Aud_InterConnectionOutput_O35:
1970 Afe_Set_Reg(AFE_HDMI_CONN0, (Input << 15), (0x0007 << 15));
1971 break;
1972 case Soc_Aud_InterConnectionOutput_O36:
1973 Afe_Set_Reg(AFE_HDMI_CONN0, (Input << 18), (0x0007 << 18));
1974 break;
1975 case Soc_Aud_InterConnectionOutput_O37:
1976 Afe_Set_Reg(AFE_HDMI_CONN0, (Input << 21), (0x0007 << 21));
1977 break;
1978 default:
1979 break;
1980 }
1981 return true;
1982 }
1983
1984 bool SetConnection(uint32 ConnectionState, uint32 Input , uint32 Output)
1985 {
1986 return SetConnectionState(ConnectionState, Input, Output);
1987 }
1988
1989 bool SetIrqEnable(uint32 Irqmode, bool bEnable)
1990 {
1991 //printk("+%s(), Irqmode = %d, bEnable = %d\n", __FUNCTION__, Irqmode, bEnable);
1992 switch (Irqmode)
1993 {
1994 case Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE:
1995 {
1996 Afe_Set_Reg(AFE_IRQ_MCU_CON, (bEnable << Irqmode), (1 << Irqmode));
1997 break;
1998 }
1999 case Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE:
2000 {
2001 if (checkUplinkMEMIfStatus() == false)
2002 {
2003 Afe_Set_Reg(AFE_IRQ_MCU_CON, (bEnable << Irqmode), (1 << Irqmode));
2004 }
2005 break;
2006 }
2007 case Soc_Aud_IRQ_MCU_MODE_IRQ3_MCU_MODE:
2008 {
2009 Afe_Set_Reg(AFE_IRQ_MCU_EN, (bEnable << Irqmode), (1 << Irqmode));
2010
2011 Afe_Set_Reg(AFE_IRQ_MCU_CON, (bEnable << Irqmode), (1 << Irqmode));
2012 break;
2013 }
2014 case Soc_Aud_IRQ_MCU_MODE_IRQ5_MCU_MODE:
2015 {
2016 Afe_Set_Reg(AFE_IRQ_MCU_EN, (bEnable << Irqmode), (1 << Irqmode));
2017
2018 Afe_Set_Reg(AFE_IRQ_MCU_CON, (bEnable << 12), (1 << 12));
2019 break;
2020 }
2021 default:
2022 break;
2023 }
2024 //printk("-%s(), Irqmode = %d, bEnable = %d\n", __FUNCTION__, Irqmode, bEnable);
2025 return true;
2026 }
2027
2028 bool SetIrqMcuSampleRate(uint32 Irqmode, uint32 SampleRate)
2029 {
2030 switch (Irqmode)
2031 {
2032 case Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE:
2033 {
2034 Afe_Set_Reg(AFE_IRQ_MCU_CON, (SampleRateTransform(SampleRate) << 4), 0x000000f0);
2035 break;
2036 }
2037 case Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE:
2038 {
2039 Afe_Set_Reg(AFE_IRQ_MCU_CON, (SampleRateTransform(SampleRate) << 8), 0x00000f00);
2040 break;
2041 }
2042 case Soc_Aud_IRQ_MCU_MODE_IRQ3_MCU_MODE:
2043 {
2044 Afe_Set_Reg(AFE_IRQ_MCU_CON, (SampleRateTransform(SampleRate) << 16), 0x000f0000);
2045 break;
2046 }
2047
2048 default:
2049 return false;
2050 }
2051 return true;
2052 }
2053
2054 bool SetIrqMcuCounter(uint32 Irqmode, uint32 Counter)
2055 {
2056 //printk(" %s Irqmode = %d Counter = %d ", __func__, Irqmode, Counter);
2057 uint32 CurrentCount = 0;
2058 switch (Irqmode)
2059 {
2060 case Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE:
2061 {
2062 Afe_Set_Reg(AFE_IRQ_MCU_CNT1, Counter, 0xffffffff);
2063 break;
2064 }
2065 case Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE:
2066 {
2067 CurrentCount = Afe_Get_Reg(AFE_IRQ_MCU_CNT2);
2068 if (CurrentCount == 0)
2069 {
2070 Afe_Set_Reg(AFE_IRQ_MCU_CNT2, Counter, 0xffffffff);
2071 }
2072 else if ((Counter < CurrentCount))
2073 {
2074 printk("update counter latency CurrentCount = %d Counter = %d", CurrentCount, Counter);
2075 Afe_Set_Reg(AFE_IRQ_MCU_CNT2, Counter, 0xffffffff);
2076 }
2077 else
2078 {
2079 printk("not to add counter latency CurrentCount = %d Counter = %d", CurrentCount, Counter);
2080 }
2081 break;
2082 }
2083 case Soc_Aud_IRQ_MCU_MODE_IRQ3_MCU_MODE:
2084 {
2085 Afe_Set_Reg(AFE_IRQ_MCU_CNT1, Counter << 20, 0xfff00000);
2086 break;
2087 }
2088 case Soc_Aud_IRQ_MCU_MODE_IRQ5_MCU_MODE:
2089 {
2090 Afe_Set_Reg(AFE_IRQ_CNT5, Counter , 0x0003ffff); // ox3BC [0~17] , ex 24bit , stereo, 48BCKs @CNT
2091
2092 break;
2093 }
2094 default:
2095 return false;
2096 }
2097 return true;
2098 }
2099
2100 bool SetMemDuplicateWrite(uint32 InterfaceType, int dupwrite)
2101 {
2102 switch (InterfaceType)
2103 {
2104 case Soc_Aud_Digital_Block_MEM_DAI:
2105 {
2106 Afe_Set_Reg(AFE_DAC_CON1, dupwrite << 29, 1 << 29);
2107 break;
2108 }
2109 case Soc_Aud_Digital_Block_MEM_MOD_DAI:
2110 {
2111 Afe_Set_Reg(AFE_DAC_CON1, dupwrite << 31, 1 << 31);
2112 break;
2113 }
2114 default:
2115 return false;
2116 }
2117 return true;
2118 }
2119
2120
2121 bool Set2ndI2SInConfig(unsigned int sampleRate, bool bIsSlaveMode)
2122 {
2123 AudioDigtalI2S I2S2ndIn_attribute;
2124 memset((void *)&I2S2ndIn_attribute, 0, sizeof(I2S2ndIn_attribute));
2125 I2S2ndIn_attribute.mLR_SWAP = Soc_Aud_LR_SWAP_NO_SWAP;
2126 I2S2ndIn_attribute.mI2S_SLAVE = bIsSlaveMode;
2127 I2S2ndIn_attribute.mI2S_SAMPLERATE = sampleRate;
2128 I2S2ndIn_attribute.mINV_LRCK = Soc_Aud_INV_LRCK_NO_INVERSE;
2129 I2S2ndIn_attribute.mI2S_FMT = Soc_Aud_I2S_FORMAT_I2S;
2130 I2S2ndIn_attribute.mI2S_WLEN = Soc_Aud_I2S_WLEN_WLEN_16BITS;
2131 Set2ndI2SIn(&I2S2ndIn_attribute);
2132 return true;
2133 }
2134
2135 bool Set2ndI2SIn(AudioDigtalI2S *mDigitalI2S)
2136 {
2137 uint32 Audio_I2S_Adc = 0;
2138 memcpy((void *)m2ndI2S, (void *)mDigitalI2S, sizeof(AudioDigtalI2S));
2139 if (!m2ndI2S->mI2S_SLAVE) //Master setting SampleRate only
2140 {
2141 SetSampleRate(Soc_Aud_Digital_Block_MEM_I2S, m2ndI2S->mI2S_SAMPLERATE);
2142 }
2143 Audio_I2S_Adc |= (m2ndI2S->mINV_LRCK << 5);
2144 Audio_I2S_Adc |= (m2ndI2S->mI2S_FMT << 3);
2145 Audio_I2S_Adc |= (m2ndI2S->mI2S_SLAVE << 2);
2146 Audio_I2S_Adc |= (m2ndI2S->mI2S_WLEN << 1);
2147 Audio_I2S_Adc |= (m2ndI2S->mI2S_IN_PAD_SEL << 28);
2148 Audio_I2S_Adc |= 1 << 31;//Default enable phase_shift_fix for better quality
2149 printk("Set2ndI2SIn Audio_I2S_Adc= 0x%x", Audio_I2S_Adc);
2150 Afe_Set_Reg(AFE_I2S_CON, Audio_I2S_Adc, 0xfffffffe);
2151 if (!m2ndI2S->mI2S_SLAVE)
2152 {
2153 Afe_Set_Reg(FPGA_CFG1, 1 << 8, 0x0100);
2154 }
2155 else
2156 {
2157 Afe_Set_Reg(FPGA_CFG1, 0, 0x0100);
2158 }
2159 return true;
2160 }
2161
2162 bool Set2ndI2SInEnable(bool bEnable)
2163 {
2164 printk("Set2ndI2SInEnable bEnable = %d", bEnable);
2165 m2ndI2S->mI2S_EN = bEnable;
2166 Afe_Set_Reg(AFE_I2S_CON, bEnable, 0x1);
2167 mAudioMEMIF[Soc_Aud_Digital_Block_I2S_IN_2]->mState = bEnable;
2168 return true;
2169 }
2170
2171 bool SetI2SASRCConfig(bool bIsUseASRC, unsigned int dToSampleRate)
2172 {
2173 printk("+%s() bIsUseASRC [%d] dToSampleRate [%d]\n", __FUNCTION__, bIsUseASRC, dToSampleRate);
2174 if (true == bIsUseASRC)
2175 {
2176 BUG_ON(!(dToSampleRate == 44100 || dToSampleRate == 48000));
2177 Afe_Set_Reg(AFE_CONN4, 0, 1 << 30);
2178 SetSampleRate(Soc_Aud_Digital_Block_MEM_I2S, dToSampleRate);//To target sample rate
2179 Afe_Set_Reg(AFE_ASRC_CON13, 0, 1 << 16); //0:Stereo 1:Mono
2180 if (dToSampleRate == 44100)
2181 {
2182 Afe_Set_Reg(AFE_ASRC_CON14, 0xDC8000, AFE_MASK_ALL);
2183 Afe_Set_Reg(AFE_ASRC_CON15, 0xA00000, AFE_MASK_ALL);
2184 Afe_Set_Reg(AFE_ASRC_CON17, 0x1FBD, AFE_MASK_ALL);
2185 }
2186 else
2187 {
2188 Afe_Set_Reg(AFE_ASRC_CON14, 0x600000, AFE_MASK_ALL);
2189 Afe_Set_Reg(AFE_ASRC_CON15, 0x400000, AFE_MASK_ALL);
2190 Afe_Set_Reg(AFE_ASRC_CON17, 0xCB2, AFE_MASK_ALL);
2191 }
2192
2193 Afe_Set_Reg(AFE_ASRC_CON16, 0x00075987, AFE_MASK_ALL);//Calibration setting
2194 Afe_Set_Reg(AFE_ASRC_CON20, 0x00001b00, AFE_MASK_ALL);//Calibration setting
2195 }
2196 else
2197 {
2198 Afe_Set_Reg(AFE_CONN4, 1 << 30, 1 << 30);
2199 }
2200 return true;
2201 }
2202
2203 bool SetI2SASRCEnable(bool bEnable)
2204 {
2205 if (true == bEnable)
2206 {
2207 Afe_Set_Reg(AFE_ASRC_CON0, ((1 << 6) | (1 << 0)), ((1 << 6) | (1 << 0)));
2208 }
2209 else
2210 {
2211 uint32 dNeedDisableASM = (Afe_Get_Reg(AFE_ASRC_CON0) & 0x0030) ? 1 : 0;
2212 Afe_Set_Reg(AFE_ASRC_CON0, 0, (1 << 6 | dNeedDisableASM));
2213 }
2214 return true;
2215 }
2216
2217 bool SetMemIfFetchFormatPerSample(uint32 InterfaceType, uint32 eFetchFormat)
2218 {
2219 mAudioMEMIF[InterfaceType]->mFetchFormatPerSample = eFetchFormat;
2220 /*
2221 printk("+%s(), InterfaceType = %d, eFetchFormat = %d, mAudioMEMIF[InterfaceType].mFetchFormatPerSample = %d\n", __FUNCTION__
2222 , InterfaceType, eFetchFormat, mAudioMEMIF[InterfaceType]->mFetchFormatPerSample);*/
2223 switch (InterfaceType)
2224 {
2225 case Soc_Aud_Digital_Block_MEM_DL1:
2226 {
2227 Afe_Set_Reg(AFE_MEMIF_PBUF_SIZE, mAudioMEMIF[InterfaceType]->mFetchFormatPerSample << 16 , 0x00030000);
2228 break;
2229 }
2230 case Soc_Aud_Digital_Block_MEM_DL1_DATA2:
2231 {
2232 Afe_Set_Reg(AFE_MEMIF_PBUF_SIZE, mAudioMEMIF[InterfaceType]->mFetchFormatPerSample << 12 , 0x00003000);
2233 break;
2234 }
2235 case Soc_Aud_Digital_Block_MEM_DL2:
2236 {
2237 Afe_Set_Reg(AFE_MEMIF_PBUF_SIZE, mAudioMEMIF[InterfaceType]->mFetchFormatPerSample << 18 , 0x0000c000);
2238 break;
2239 }
2240 case Soc_Aud_Digital_Block_MEM_I2S:
2241 {
2242 //Afe_Set_Reg(AFE_DAC_CON1, mAudioMEMIF[InterfaceType].mSampleRate << 8 , 0x00000f00);
2243 printk("Unsupport MEM_I2S");
2244 break;
2245 }
2246 case Soc_Aud_Digital_Block_MEM_AWB:
2247 {
2248 Afe_Set_Reg(AFE_MEMIF_PBUF_SIZE, mAudioMEMIF[InterfaceType]->mFetchFormatPerSample << 20, 0x00300000);
2249 break;
2250 }
2251 case Soc_Aud_Digital_Block_MEM_VUL:
2252 {
2253 Afe_Set_Reg(AFE_MEMIF_PBUF_SIZE, mAudioMEMIF[InterfaceType]->mFetchFormatPerSample << 22, 0x00C00000);
2254 break;
2255 }
2256 case Soc_Aud_Digital_Block_MEM_VUL_DATA2:
2257 {
2258 Afe_Set_Reg(AFE_MEMIF_PBUF_SIZE, mAudioMEMIF[InterfaceType]->mFetchFormatPerSample << 14, 0x000C0000);
2259 break;
2260 }
2261 case Soc_Aud_Digital_Block_MEM_DAI:
2262 {
2263 Afe_Set_Reg(AFE_MEMIF_PBUF_SIZE, mAudioMEMIF[InterfaceType]->mFetchFormatPerSample << 24, 0x03000000);
2264 break;
2265 }
2266 case Soc_Aud_Digital_Block_MEM_MOD_DAI:
2267 {
2268 Afe_Set_Reg(AFE_MEMIF_PBUF_SIZE, mAudioMEMIF[InterfaceType]->mFetchFormatPerSample << 26, 0x0C000000);
2269 break;
2270 }
2271 case Soc_Aud_Digital_Block_MEM_HDMI:
2272 {
2273 Afe_Set_Reg(AFE_MEMIF_PBUF_SIZE, mAudioMEMIF[InterfaceType]->mFetchFormatPerSample << 28, 0x30000000);
2274 break;
2275 }
2276 default:
2277 return false;
2278 }
2279 return true;
2280 }
2281
2282 bool SetoutputConnectionFormat(uint32 ConnectionFormat, uint32 Output)
2283 {
2284 //printk("+%s(), Data Format = %d, Output = %d\n", __FUNCTION__, ConnectionFormat, Output);
2285 Afe_Set_Reg(AFE_CONN_24BIT, (ConnectionFormat << Output), (1 << Output));
2286 return true;
2287 }
2288
2289 bool SetHDMIMCLK()
2290 {
2291 uint32 mclksamplerate = mHDMIOutput->mSampleRate * 256;
2292 uint32 hdmi_APll = GetHDMIApLLSource();
2293 uint32 hdmi_mclk_div = 0;
2294 printk("%s \n", __func__);
2295 if (hdmi_APll == APLL_SOURCE_24576)
2296 {
2297 hdmi_APll = 24576000;
2298 }
2299 else
2300 {
2301 hdmi_APll = 22579200;
2302 }
2303 printk("%s hdmi_mclk_div = %d mclksamplerate = %d\n", __func__, hdmi_mclk_div, mclksamplerate);
2304 hdmi_mclk_div = (hdmi_APll / mclksamplerate / 2) - 1;
2305 mHDMIOutput->mHdmiMckDiv = hdmi_mclk_div;
2306 printk("%s hdmi_mclk_div = %d\n", __func__, hdmi_mclk_div);
2307 Afe_Set_Reg(FPGA_CFG1, hdmi_mclk_div << 24, 0x3f000000);
2308
2309 SetCLkMclk(Soc_Aud_I2S3, mHDMIOutput->mSampleRate);
2310 return true;
2311 }
2312
2313 bool SetHDMIBCLK()
2314 {
2315 mHDMIOutput->mBckSamplerate = mHDMIOutput->mSampleRate * mHDMIOutput->mChannels;
2316 printk("%s mBckSamplerate = %d mSampleRate = %d mChannels = %d\n", __func__, mHDMIOutput->mBckSamplerate, mHDMIOutput->mSampleRate , mHDMIOutput->mChannels);
2317 mHDMIOutput->mBckSamplerate *= (mHDMIOutput->mI2S_WLEN + 1) * 16;
2318 printk("%s mBckSamplerate = %d mApllSamplerate = %d\n", __func__, mHDMIOutput->mBckSamplerate, mHDMIOutput->mApllSamplerate);
2319 mHDMIOutput->mHdmiBckDiv = (mHDMIOutput->mApllSamplerate / mHDMIOutput->mBckSamplerate / 2) - 1;
2320 printk("%s mHdmiBckDiv = %d\n", __func__, mHDMIOutput->mHdmiBckDiv);
2321 Afe_Set_Reg(FPGA_CFG1, (mHDMIOutput->mHdmiBckDiv) << 16, 0x00ff0000);
2322 return true;
2323 }
2324
2325 uint32 GetHDMIApLLSource()
2326 {
2327 printk("%s ApllSource = %d \n", __func__, mHDMIOutput->mApllSource);
2328 return mHDMIOutput->mApllSource ;
2329 }
2330
2331 bool SetHDMIApLL(uint32 ApllSource)
2332 {
2333 printk("%s ApllSource = %d", __func__, ApllSource);
2334 if (ApllSource == APLL_SOURCE_24576)
2335 {
2336 Afe_Set_Reg(FPGA_CFG1, 0 << 31, 1 << 31);
2337 mHDMIOutput->mApllSource = APLL_SOURCE_24576;
2338 mHDMIOutput->mApllSamplerate = 24576000;
2339 }
2340 else if (ApllSource == APLL_SOURCE_225792)
2341 {
2342 Afe_Set_Reg(FPGA_CFG1, 1 << 31, 1 << 31);
2343 mHDMIOutput->mApllSource = APLL_SOURCE_225792;
2344 mHDMIOutput->mApllSamplerate = 22579200;
2345 }
2346 return true;
2347 }
2348
2349 bool SetHDMIdatalength(uint32 length)
2350 {
2351 printk("%s length = %d\n ", __func__, length);
2352 mHDMIOutput->mI2S_WLEN = length;
2353 return true;
2354 }
2355
2356 bool SetHDMIsamplerate(uint32 samplerate)
2357 {
2358 uint32 SampleRateinedx = SampleRateTransform(samplerate);
2359 mHDMIOutput->mSampleRate = samplerate;
2360 printk("%s samplerate = %d \n", __func__, samplerate);
2361 switch (SampleRateinedx)
2362 {
2363 case Soc_Aud_I2S_SAMPLERATE_I2S_8K:
2364 SetHDMIApLL(APLL_SOURCE_24576);
2365 break;
2366 case Soc_Aud_I2S_SAMPLERATE_I2S_11K:
2367 SetHDMIApLL(APLL_SOURCE_225792);
2368 break;
2369 case Soc_Aud_I2S_SAMPLERATE_I2S_12K:
2370 SetHDMIApLL(APLL_SOURCE_24576);
2371 break;
2372 case Soc_Aud_I2S_SAMPLERATE_I2S_16K:
2373 SetHDMIApLL(APLL_SOURCE_24576);
2374 break;
2375 case Soc_Aud_I2S_SAMPLERATE_I2S_22K:
2376 SetHDMIApLL(APLL_SOURCE_225792);
2377 break;
2378 case Soc_Aud_I2S_SAMPLERATE_I2S_24K:
2379 SetHDMIApLL(APLL_SOURCE_24576);
2380 break;
2381 case Soc_Aud_I2S_SAMPLERATE_I2S_32K:
2382 SetHDMIApLL(APLL_SOURCE_24576);
2383 break;
2384 case Soc_Aud_I2S_SAMPLERATE_I2S_44K:
2385 SetHDMIApLL(APLL_SOURCE_225792);
2386 break;
2387 case Soc_Aud_I2S_SAMPLERATE_I2S_48K:
2388 SetHDMIApLL(APLL_SOURCE_24576);
2389 break;
2390 case Soc_Aud_I2S_SAMPLERATE_I2S_88K:
2391 SetHDMIApLL(APLL_SOURCE_225792);
2392 break;
2393 case Soc_Aud_I2S_SAMPLERATE_I2S_96K:
2394 SetHDMIApLL(APLL_SOURCE_24576);
2395 break;
2396 default:
2397 break;
2398 }
2399 return true;
2400 }
2401
2402 bool SetTDMLrckWidth(uint32 cycles)
2403 {
2404 printk("%s cycles = %d", __func__, cycles);
2405 Afe_Set_Reg(AFE_TDM_CON1, cycles << 24, 0xff000000);
2406 return true;
2407 }
2408
2409 bool SetTDMbckcycle(uint32 cycles)
2410 {
2411 uint32 index = 0;
2412 printk("%s cycles = %d \n", __func__, cycles);
2413 switch (cycles)
2414 {
2415 case Soc_Aud_I2S_WLEN_WLEN_16BITS:
2416 {
2417 index = 0;
2418 }
2419 break;
2420 case Soc_Aud_I2S_WLEN_WLEN_32BITS:
2421 {
2422 index = 2;
2423 }
2424 default:
2425 break;
2426 break;
2427 }
2428 Afe_Set_Reg(AFE_TDM_CON1, index << 12, 0x0000f000);
2429 return true;
2430 }
2431
2432 bool SetTDMChannelsSdata(uint32 channels)
2433 {
2434 uint32 index = 0;
2435 printk("%s channels = %d", __func__, channels);
2436 switch (channels)
2437 {
2438 case 2:
2439 index = 0;
2440 break;
2441 case 4:
2442 index = 1;
2443 break;
2444 case 8:
2445 index = 2;
2446 break;
2447 }
2448 Afe_Set_Reg(AFE_TDM_CON1, index << 10, 0x00000c00);
2449 return true;
2450 }
2451
2452 bool SetTDMDatalength(uint32 length)
2453 {
2454 printk("%s length = %d\n", __func__, length);
2455 if (length == Soc_Aud_I2S_WLEN_WLEN_16BITS)
2456 {
2457 Afe_Set_Reg(AFE_TDM_CON1, 1 << 8, 0x00000300);
2458 }
2459 else if (length == Soc_Aud_I2S_WLEN_WLEN_32BITS)
2460 {
2461 Afe_Set_Reg(AFE_TDM_CON1, 2 << 8, 0x00000300);
2462 }
2463 return true;
2464 }
2465
2466 bool SetTDMI2Smode(uint32 mode)
2467 {
2468 printk("%s mode = %d", __func__, mode);
2469 if (mode == Soc_Aud_I2S_FORMAT_EIAJ)
2470 {
2471 Afe_Set_Reg(AFE_TDM_CON1, 0 << 3, 1 << 3);
2472 }
2473 else if (mode == Soc_Aud_I2S_FORMAT_I2S)
2474 {
2475 Afe_Set_Reg(AFE_TDM_CON1, 1 << 3, 1 << 3);
2476 }
2477 Afe_Set_Reg(AFE_TDM_CON1, 1 << 4, 1 << 4); // LEFT_ALIGN
2478 return true;
2479 }
2480
2481 bool SetTDMLrckInverse(bool enable)
2482 {
2483 printk("%s enable = %d", __func__, enable);
2484 if (enable)
2485 {
2486 Afe_Set_Reg(AFE_TDM_CON1, 1 << 2, 1 << 2);
2487 }
2488 else
2489 {
2490 Afe_Set_Reg(AFE_TDM_CON1, 0, 1 << 2);
2491 }
2492 return true;
2493
2494 }
2495 bool SetTDMBckInverse(bool enable)
2496 {
2497 printk("%s enable = %d", __func__, enable);
2498 if (enable)
2499 {
2500 Afe_Set_Reg(AFE_TDM_CON1, 1 << 1, 1 << 1);
2501 }
2502 else
2503 {
2504 Afe_Set_Reg(AFE_TDM_CON1, 0, 1 << 1);
2505 }
2506 return true;
2507 }
2508
2509 bool SetTDMEnable(bool enable)
2510 {
2511 printk("%s enable = %d", __func__, enable);
2512 if (enable)
2513 {
2514 Afe_Set_Reg(AFE_TDM_CON1, 1, 1);
2515 }
2516 else
2517 {
2518 Afe_Set_Reg(AFE_TDM_CON1, 0, 1);
2519 }
2520 return true;
2521 }
2522
2523 bool SetTDMDataChannels(uint32 SData , uint32 SDataChannels)
2524 {
2525 int index = 0;
2526 printk("%s SData = %d SDataChannels = %d", __func__, SData, SDataChannels);
2527 switch (SData)
2528 {
2529 case HDMI_SDATA0:
2530 index = 0;
2531 break;
2532 case HDMI_SDATA1:
2533 index = 4;
2534 break;
2535 case HDMI_SDATA2:
2536 index = 8;
2537 break;
2538 case HDMI_SDATA3:
2539 index = 12;
2540 break;
2541 default:
2542 break;
2543 }
2544 Afe_Set_Reg(AFE_TDM_CON2, SDataChannels << index, 1 << 0xf << index);
2545 return true;
2546 }
2547
2548 bool SetTDMtoI2SEnable(bool enable)
2549 {
2550 printk("%s enable = %d", __func__, enable);
2551 if (enable)
2552 {
2553 Afe_Set_Reg(AFE_TDM_CON2, 1 << 20, 1 << 20);
2554 }
2555 else
2556 {
2557 Afe_Set_Reg(AFE_TDM_CON2, 0, 1 << 20);
2558 }
2559 return true;
2560 }
2561
2562 bool SetModemSpeechDAIBTAttribute(int sample_rate)
2563 {
2564 AudioDigitalDAIBT daibt_attribute;
2565 memset((void *)&daibt_attribute, 0, sizeof(daibt_attribute));
2566
2567 #if 0 // temp for merge only support
2568 daibt_attribute.mUSE_MRGIF_INPUT = Soc_Aud_BT_DAI_INPUT_FROM_BT;
2569 #else
2570 daibt_attribute.mUSE_MRGIF_INPUT = Soc_Aud_BT_DAI_INPUT_FROM_MGRIF;
2571 #endif
2572 daibt_attribute.mDAI_BT_MODE = (sample_rate == 8000) ? Soc_Aud_DATBT_MODE_Mode8K : Soc_Aud_DATBT_MODE_Mode16K;
2573 daibt_attribute.mDAI_DEL = Soc_Aud_DAI_DEL_HighWord; // suggest always HighWord
2574 daibt_attribute.mBT_LEN = 0;
2575 daibt_attribute.mDATA_RDY = true;
2576 daibt_attribute.mBT_SYNC = Soc_Aud_BTSYNC_Short_Sync;
2577 daibt_attribute.mBT_ON = true;
2578 daibt_attribute.mDAIBT_ON = false;
2579 SetDaiBt(&daibt_attribute);
2580 return true;
2581 }
2582
2583 /*****************************************************************************
2584 * FUNCTION
2585 * AudDrv_Allocate_DL1_Buffer / AudDrv_Free_DL1_Buffer
2586 *
2587 * DESCRIPTION
2588 * allocate DL1 Buffer
2589 *
2590
2591 ******************************************************************************/
2592 int AudDrv_Allocate_DL1_Buffer(struct device *pDev, kal_uint32 Afe_Buf_Length)
2593 {
2594 #ifdef AUDIO_MEMORY_SRAM
2595 kal_uint32 u4PhyAddr = 0;
2596 #endif
2597 AFE_BLOCK_T *pblock = &(AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_DL1]->rBlock);
2598
2599 printk("%s Afe_Buf_Length = %d \n ", __func__, Afe_Buf_Length);
2600
2601 pblock->u4BufferSize = Afe_Buf_Length;
2602
2603 if (Afe_Buf_Length > AFE_INTERNAL_SRAM_SIZE)
2604 {
2605 PRINTK_AUDDRV("Afe_Buf_Length > AUDDRV_DL1_MAX_BUFFER_LENGTH \n");
2606 return -1;
2607 }
2608
2609 // allocate memory
2610 {
2611 #ifdef AUDIO_MEMORY_SRAM
2612 // todo , there should be a sram manager to allocate memory for low power.
2613 u4PhyAddr = AFE_INTERNAL_SRAM_PHY_BASE;
2614 pblock->pucPhysBufAddr = u4PhyAddr;
2615
2616 #ifdef AUDIO_MEM_IOREMAP
2617 PRINTK_AUDDRV("AudDrv_Allocate_DL1_Buffer length AUDIO_MEM_IOREMAP = %d\n",
2618 Afe_Buf_Length);
2619 pblock->pucVirtBufAddr = (kal_uint8 *)Get_Afe_SramBase_Pointer();
2620 #else
2621 pblock->pucVirtBufAddr = AFE_INTERNAL_SRAM_VIR_BASE;
2622 #endif
2623
2624 #else
2625 PRINTK_AUDDRV("AudDrv_Allocate_DL1_Buffer use dram");
2626 pblock->pucVirtBufAddr = dma_alloc_coherent(pDev, pblock->u4BufferSize, &pblock->pucPhysBufAddr, GFP_KERNEL);
2627 #endif
2628 }
2629 PRINTK_AUDDRV("AudDrv_Allocate_DL1_Buffer Afe_Buf_Length = %dpucVirtBufAddr = %p\n", Afe_Buf_Length, pblock->pucVirtBufAddr);
2630
2631 // check 32 bytes align
2632 if ((pblock->pucPhysBufAddr & 0x1f) != 0)
2633 {
2634 PRINTK_AUDDRV("[Auddrv] AudDrv_Allocate_DL1_Buffer is not aligned (0x%x) \n", pblock->pucPhysBufAddr);
2635 }
2636
2637 pblock->u4SampleNumMask = 0x001f; // 32 byte align
2638 pblock->u4WriteIdx = 0;
2639 pblock->u4DMAReadIdx = 0;
2640 pblock->u4DataRemained = 0;
2641 pblock->u4fsyncflag = false;
2642 pblock->uResetFlag = true;
2643
2644 // set sram address top hardware
2645 Afe_Set_Reg(AFE_DL1_BASE , pblock->pucPhysBufAddr , 0xffffffff);
2646 Afe_Set_Reg(AFE_DL1_END , pblock->pucPhysBufAddr + (Afe_Buf_Length - 1), 0xffffffff);
2647 memset(pblock->pucVirtBufAddr, 0, pblock->u4BufferSize);
2648 return 0;
2649 }
2650
2651 int AudDrv_Allocate_mem_Buffer(struct device *pDev, Soc_Aud_Digital_Block MemBlock, uint32 Buffer_length)
2652 {
2653 switch (MemBlock)
2654 {
2655 case Soc_Aud_Digital_Block_MEM_DL1:
2656 case Soc_Aud_Digital_Block_MEM_DL2:
2657 case Soc_Aud_Digital_Block_MEM_DAI:
2658 case Soc_Aud_Digital_Block_MEM_AWB:
2659 case Soc_Aud_Digital_Block_MEM_MOD_DAI:
2660 case Soc_Aud_Digital_Block_MEM_DL1_DATA2:
2661 case Soc_Aud_Digital_Block_MEM_VUL_DATA2:
2662 case Soc_Aud_Digital_Block_MEM_HDMI:
2663 {
2664 printk("%s MemBlock =%d Buffer_length = %d\n ", __func__, MemBlock, Buffer_length);
2665 if (Audio_dma_buf[MemBlock] != NULL)
2666 {
2667 printk("AudDrv_Allocate_mem_Buffer MemBlock = %d dma_alloc_coherent\n", MemBlock);
2668 if (Audio_dma_buf[MemBlock] ->area == NULL)
2669 {
2670 printk("dma_alloc_coherent\n");
2671 Audio_dma_buf[MemBlock] ->area = dma_alloc_coherent(pDev, Buffer_length,
2672 &Audio_dma_buf[MemBlock] ->addr, GFP_KERNEL);
2673 if (Audio_dma_buf[MemBlock] ->area)
2674 {
2675 Audio_dma_buf[MemBlock] ->bytes = Buffer_length;
2676 }
2677 }
2678 printk("area = %p \n", Audio_dma_buf[MemBlock] ->area);
2679 }
2680 }
2681 break;
2682 case Soc_Aud_Digital_Block_MEM_VUL:
2683 {
2684 printk("%s MemBlock =%d Buffer_length = %d\n ", __func__, MemBlock, Buffer_length);
2685 if (Audio_dma_buf[MemBlock] != NULL)
2686 {
2687 printk("AudDrv_Allocate_mem_Buffer MemBlock = %d dma_alloc_coherent\n", MemBlock);
2688 if (Audio_dma_buf[MemBlock] ->area == NULL)
2689 {
2690 printk("dma_alloc_coherent\n");
2691 Audio_dma_buf[MemBlock] ->area = dma_alloc_coherent(pDev, Buffer_length,
2692 &Audio_dma_buf[MemBlock] ->addr, GFP_KERNEL);
2693 if (Audio_dma_buf[MemBlock] ->area)
2694 {
2695 Audio_dma_buf[MemBlock] ->bytes = Buffer_length;
2696 }
2697 }
2698 printk("area = %p \n", Audio_dma_buf[MemBlock] ->area);
2699 }
2700 break;
2701 }
2702 case Soc_Aud_Digital_Block_MEM_I2S:
2703 printk("currently not support \n");
2704 default:
2705 printk("%s not support \n", __func__);
2706 }
2707 return true;
2708 }
2709
2710 AFE_MEM_CONTROL_T *Get_Mem_ControlT(Soc_Aud_Digital_Block MemBlock)
2711 {
2712 if (MemBlock >= 0 && MemBlock <= Soc_Aud_Digital_Block_MEM_HDMI)
2713 {
2714 return AFE_Mem_Control_context[MemBlock];
2715 }
2716 else
2717 {
2718 printk("%s error \n", __func__);
2719 return NULL;
2720 }
2721 }
2722
2723 bool SetMemifSubStream(Soc_Aud_Digital_Block MemBlock , struct snd_pcm_substream *substream)
2724 {
2725 substreamList *head;
2726 substreamList *temp = NULL;
2727 unsigned long flags;
2728 printk("+%s MemBlock = %d substream = %p \n ", __func__, MemBlock, substream);
2729 spin_lock_irqsave(&afe_mem_lock, flags);
2730 head = AFE_Mem_Control_context[MemBlock]->substreamL;
2731 if (head == NULL) // frst item is NULL
2732 {
2733 //printk("%s head == NULL\n ", __func__);
2734 temp = kzalloc(sizeof(substreamList), GFP_ATOMIC);
2735 temp->substream = substream;
2736 temp->next = NULL;
2737 AFE_Mem_Control_context[MemBlock]->substreamL = temp;
2738 }
2739 else // find out Null pointer
2740 {
2741 while (head->next != NULL)
2742 {
2743 head = (substreamList *)head->next;
2744 }
2745 // head->next is NULL
2746 temp = kzalloc(sizeof(substreamList), GFP_ATOMIC);
2747 temp->substream = substream;
2748 temp->next = NULL;
2749 head->next = (struct substreamList *)temp;
2750 }
2751 spin_unlock_irqrestore(&afe_mem_lock, flags);
2752 printk("-%s MemBlock = %d \n ", __func__, MemBlock);
2753 //DumpMemifSubStream();
2754 return true;
2755 }
2756
2757 bool ClearMemBlock(Soc_Aud_Digital_Block MemBlock)
2758 {
2759 if (MemBlock >= 0 && MemBlock <= Soc_Aud_Digital_Block_MEM_HDMI)
2760 {
2761 AFE_BLOCK_T *pBlock = &AFE_Mem_Control_context[MemBlock]->rBlock;
2762 memset(pBlock->pucVirtBufAddr, 0, pBlock->u4BufferSize);
2763 pBlock->u4WriteIdx = 0;
2764 pBlock->u4DMAReadIdx = 0;
2765 pBlock->u4DataRemained = 0;
2766 pBlock->u4fsyncflag = false;
2767 pBlock->uResetFlag = true;
2768 }
2769 else
2770 {
2771 printk("%s error \n", __func__);
2772 return NULL;
2773 }
2774 return true;
2775 }
2776
2777 bool RemoveMemifSubStream(Soc_Aud_Digital_Block MemBlock, struct snd_pcm_substream *substream)
2778 {
2779 substreamList *head = NULL;
2780 substreamList *temp = NULL;
2781 unsigned long flags;
2782 spin_lock_irqsave(&afe_mem_lock, flags);
2783 head = AFE_Mem_Control_context[MemBlock]->substreamL;
2784 printk("+ %s MemBlock = %d substream = %p \n ", __func__, MemBlock,substream);
2785 if (head == NULL) // no object
2786 {
2787 // do nothing
2788 }
2789 else
2790 {
2791 // condition for first item hit and ony 1 item
2792 if (head->substream == substream)
2793 {
2794 //printk("%s head->substream = %p \n ", __func__, head->substream);
2795 AFE_Mem_Control_context[MemBlock]->substreamL = (substreamList *)head->next;
2796 spin_unlock_irqrestore(&afe_mem_lock, flags);
2797 kfree(head);
2798 //DumpMemifSubStream();
2799 return true;
2800 }
2801 temp = head;
2802 head = (substreamList *)head->next;
2803 while (head)
2804 {
2805 if (head->substream == substream)
2806 {
2807 temp->next = head->next;
2808 if (head)
2809 {
2810 kfree(head);
2811 head = NULL;
2812 }
2813 break;
2814 }
2815 temp = head;
2816 head = (substreamList *)head->next;
2817 }
2818 }
2819 spin_unlock_irqrestore(&afe_mem_lock, flags);
2820 //DumpMemifSubStream();
2821
2822 if (AFE_Mem_Control_context[MemBlock]->substreamL == NULL)
2823 {
2824 ClearMemBlock(MemBlock);
2825 return true;
2826 }
2827 else
2828 {
2829 printk("%s substreram is not NULL MemBlock = %d \n", __func__, MemBlock);
2830 return true;
2831 }
2832 printk("- %s MemBlock = %d \n ", __func__, MemBlock);
2833 }
2834
2835 static unsigned long dl1_flags = 0;
2836 void Auddrv_Dl1_Spinlock_lock(void)
2837 {
2838 spin_lock_irqsave(&auddrv_dl1_lock, dl1_flags);
2839 }
2840
2841 void Auddrv_Dl1_Spinlock_unlock(void)
2842 {
2843 spin_unlock_irqrestore(&auddrv_dl1_lock, dl1_flags);
2844 }
2845
2846 static unsigned long ul1_flags = 0;
2847 void Auddrv_UL1_Spinlock_lock(void)
2848 {
2849 spin_lock_irqsave(&auddrv_ul1_lock, ul1_flags);
2850 }
2851 void Auddrv_UL1_Spinlock_unlock(void)
2852 {
2853 spin_unlock_irqrestore(&auddrv_ul1_lock, ul1_flags);
2854 }
2855
2856 void Auddrv_HDMI_Interrupt_Handler(void) // irq5 ISR handler
2857 {
2858 kal_int32 Afe_consumed_bytes = 0;
2859 kal_int32 HW_memory_index = 0;
2860 kal_int32 HW_Cur_ReadIdx = 0;
2861 substreamList *Temp = NULL;
2862 unsigned long flags;
2863 AFE_BLOCK_T *Afe_Block = &(AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_HDMI]->rBlock);
2864
2865 if (GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_HDMI) == false)
2866 {
2867 //printk("%s(), GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_HDMI) == false, return\n ", __func__);
2868 return;
2869 }
2870
2871 HW_Cur_ReadIdx = Afe_Get_Reg(AFE_HDMI_CUR);
2872 if (HW_Cur_ReadIdx == 0)
2873 {
2874 PRINTK_AUDDRV("[Auddrv_HDMI_Interrupt] HW_Cur_ReadIdx ==0 \n");
2875 HW_Cur_ReadIdx = Afe_Block->pucPhysBufAddr;
2876 }
2877 HW_memory_index = (HW_Cur_ReadIdx - Afe_Block->pucPhysBufAddr);
2878
2879 PRINTK_AUD_HDMI("[Auddrv_HDMI_Interrupt]0 HW_Cur_ReadIdx=0x%x HW_memory_index = 0x%x Afe_Block->pucPhysBufAddr = 0x%x\n",
2880 HW_Cur_ReadIdx, HW_memory_index, Afe_Block->pucPhysBufAddr);
2881
2882 // get hw consume bytes
2883 if (HW_memory_index > Afe_Block->u4DMAReadIdx)
2884 {
2885 Afe_consumed_bytes = HW_memory_index - Afe_Block->u4DMAReadIdx;
2886 }
2887 else
2888 {
2889 Afe_consumed_bytes = Afe_Block->u4BufferSize + HW_memory_index - Afe_Block->u4DMAReadIdx ;
2890 }
2891
2892 if ((Afe_consumed_bytes & 0x1f) != 0)
2893 {
2894 printk("[Auddrv_HDMI_Interrupt] DMA address is not aligned 32 bytes \n");
2895 }
2896
2897 PRINTK_AUD_HDMI("+[Auddrv_HDMI_Interrupt]1 ReadIdx:%x WriteIdx:%x, DataRemained:%x, Afe_consumed_bytes:%x HW_memory_index = %x \n",
2898 Afe_Block->u4DMAReadIdx, Afe_Block->u4WriteIdx, Afe_Block->u4DataRemained, Afe_consumed_bytes, HW_memory_index);
2899
2900 if (Afe_Block->u4DataRemained < Afe_consumed_bytes || Afe_Block->u4DataRemained <= 0 || Afe_Block->u4DataRemained > Afe_Block->u4BufferSize)
2901 {
2902 // buffer underflow --> clear whole buffer
2903 //memset(Afe_Block->pucVirtBufAddr, 0, Afe_Block->u4BufferSize);
2904
2905 PRINTK_AUD_HDMI("+[Auddrv_HDMI_Interrupt]2 underflow ReadIdx:%x WriteIdx:%x, DataRemained:%x, Afe_consumed_bytes:%x HW_memory_index = 0x%x\n",
2906 Afe_Block->u4DMAReadIdx, Afe_Block->u4WriteIdx, Afe_Block->u4DataRemained, Afe_consumed_bytes, HW_memory_index);
2907 Afe_Block->u4DMAReadIdx = HW_memory_index;
2908 Afe_Block->u4WriteIdx = Afe_Block->u4DMAReadIdx;
2909 Afe_Block->u4DataRemained = Afe_Block->u4BufferSize;
2910
2911 PRINTK_AUD_HDMI("-[Auddrv_HDMI_Interrupt]2 underflow ReadIdx:%x WriteIdx:%x, DataRemained:%x, Afe_consumed_bytes %x \n",
2912 Afe_Block->u4DMAReadIdx, Afe_Block->u4WriteIdx, Afe_Block->u4DataRemained, Afe_consumed_bytes);
2913 }
2914 else
2915 {
2916
2917 PRINTK_AUD_HDMI("+[Auddrv_HDMI_Interrupt]3 normal ReadIdx:%x ,DataRemained:%x, WriteIdx:%x \n",
2918 Afe_Block->u4DMAReadIdx, Afe_Block->u4DataRemained, Afe_Block->u4WriteIdx);
2919 Afe_Block->u4DataRemained -= Afe_consumed_bytes;
2920 Afe_Block->u4DMAReadIdx += Afe_consumed_bytes;
2921 Afe_Block->u4DMAReadIdx %= Afe_Block->u4BufferSize;
2922
2923 PRINTK_AUD_HDMI("-[Auddrv_HDMI_Interrupt]3 normal ReadIdx:%x ,DataRemained:%x, WriteIdx:%x \n",
2924 Afe_Block->u4DMAReadIdx, Afe_Block->u4DataRemained, Afe_Block->u4WriteIdx);
2925 }
2926 AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_HDMI]->interruptTrigger = 1 ;
2927
2928 spin_lock_irqsave(&afe_mem_lock, flags);
2929 Temp = AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_HDMI]->substreamL;
2930 spin_unlock_irqrestore(&afe_mem_lock, flags);
2931 if(Temp != NULL)
2932 {
2933 if (Temp->substream != NULL)
2934 {
2935 snd_pcm_period_elapsed(Temp->substream);
2936 }
2937 }
2938 PRINTK_AUD_HDMI("-[Auddrv_HDMI_Interrupt]4 ReadIdx:%x ,DataRemained:%x, WriteIdx:%x \n",
2939 Afe_Block->u4DMAReadIdx, Afe_Block->u4DataRemained, Afe_Block->u4WriteIdx);
2940 }
2941
2942 static void TraverseAllSubStream(substreamList *Head)
2943 {
2944 //printk("+%s\n",__func__);
2945 substreamList *temp = Head;
2946 while (temp != NULL)
2947 {
2948 //printk("temp = %p temp->substream = %p\n", temp, temp->substream);
2949 if (temp->substream != NULL)
2950 {
2951 snd_pcm_period_elapsed(temp->substream);
2952 }
2953 temp = (substreamList *)temp->next;
2954 }
2955 //printk("-%s\n",__func__);
2956 }
2957
2958 void Auddrv_AWB_Interrupt_Handler(void)
2959 {
2960 AFE_MEM_CONTROL_T *Mem_Block = AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_AWB];
2961 kal_uint32 HW_Cur_ReadIdx = 0;
2962 kal_uint32 MaxCopySize = 0;
2963 kal_int32 Hw_Get_bytes = 0;
2964 substreamList *Temp = NULL;
2965 AFE_BLOCK_T *mBlock = NULL;
2966 unsigned long flags;
2967
2968 if (Mem_Block == NULL)
2969 {
2970 return;
2971 }
2972
2973 if (GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_AWB) == false)
2974 {
2975 //printk("%s(), GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_AWB) == false, return\n ", __func__);
2976 return;
2977 }
2978
2979 mBlock = &Mem_Block->rBlock;
2980 HW_Cur_ReadIdx = Align64ByteSize(Afe_Get_Reg(AFE_AWB_CUR));
2981 PRINTK_AUD_AWB("Auddrv_AWB_Interrupt_Handler HW_Cur_ReadIdx = 0x%x\n ", HW_Cur_ReadIdx);
2982
2983 if (CheckSize(HW_Cur_ReadIdx))
2984 {
2985 return;
2986 }
2987 if (mBlock->pucVirtBufAddr == NULL)
2988 {
2989 return;
2990 }
2991
2992 MaxCopySize = Get_Mem_MaxCopySize(Soc_Aud_Digital_Block_MEM_AWB);
2993 PRINTK_AUD_AWB("1 mBlock = %p MaxCopySize = 0x%x u4BufferSize = 0x%x \n", mBlock, MaxCopySize, mBlock->u4BufferSize);
2994 if (MaxCopySize)
2995 {
2996 if (MaxCopySize > mBlock->u4BufferSize)
2997 {
2998 MaxCopySize = mBlock->u4BufferSize;
2999 }
3000 mBlock->u4DataRemained -= MaxCopySize;
3001 mBlock->u4DMAReadIdx += MaxCopySize;
3002 mBlock->u4DMAReadIdx %= mBlock->u4BufferSize;
3003 Clear_Mem_CopySize(Soc_Aud_Digital_Block_MEM_AWB);
3004 PRINTK_AUD_AWB("update read pointer u4DMAReadIdx:0x%x, u4WriteIdx:0x%x, pucPhysBufAddr:0x%x mBlock->u4MaxCopySize =0x%x\n",
3005 mBlock->u4DMAReadIdx, mBlock->u4WriteIdx, mBlock->pucPhysBufAddr, mBlock->u4MaxCopySize);
3006 }
3007
3008 // HW already fill in
3009 Hw_Get_bytes = (HW_Cur_ReadIdx - mBlock->pucPhysBufAddr) - mBlock->u4WriteIdx;
3010 if (Hw_Get_bytes < 0)
3011 {
3012 Hw_Get_bytes += mBlock->u4BufferSize;
3013 }
3014
3015 PRINTK_AUD_AWB("+Auddrv_Handle_Mem_context Hw_Get_bytes:0x%x, HW_Cur_ReadIdx:0x%x, u4DMAReadIdx:0x%x, u4WriteIdx:0x%x, pucPhysBufAddr:0x%x mBlock->u4MaxCopySize =0x%x mBlock->u4DataRemained = 0x%x\n",
3016 Hw_Get_bytes, HW_Cur_ReadIdx, mBlock->u4DMAReadIdx, mBlock->u4WriteIdx, mBlock->pucPhysBufAddr, mBlock->u4MaxCopySize, mBlock->u4DataRemained);
3017
3018 mBlock->u4WriteIdx += Hw_Get_bytes;
3019 mBlock->u4WriteIdx %= mBlock->u4BufferSize;
3020 mBlock->u4DataRemained += Hw_Get_bytes;
3021 // buffer overflow
3022 if (mBlock->u4DataRemained > mBlock->u4BufferSize)
3023 {
3024 printk("Auddrv_Handle_Mem_context buffer overflow u4DMAReadIdx:%x, u4WriteIdx:%x, u4DataRemained:%x, u4BufferSize:%x \n",
3025 mBlock->u4DMAReadIdx, mBlock->u4WriteIdx, mBlock->u4DataRemained, mBlock->u4BufferSize);
3026 mBlock->u4DataRemained -= mBlock->u4BufferSize;
3027 }
3028 Mem_Block->interruptTrigger = 1;
3029
3030 spin_lock_irqsave(&afe_mem_lock, flags);
3031 Temp = Mem_Block->substreamL;
3032 spin_unlock_irqrestore(&afe_mem_lock, flags);
3033 if (Temp != NULL)
3034 {
3035 TraverseAllSubStream(Temp);
3036 }
3037
3038 PRINTK_AUD_AWB("-Auddrv_Handle_Mem_context u4DMAReadIdx:0x%x, u4WriteIdx:0x%x mBlock->u4DataRemained = 0x%x \n", mBlock->u4DMAReadIdx, mBlock->u4WriteIdx, mBlock->u4DataRemained);
3039
3040 }
3041
3042 void Auddrv_DAI_Interrupt_Handler(void)
3043 {
3044 AFE_MEM_CONTROL_T *Mem_Block = AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_DAI];
3045 kal_uint32 HW_Cur_ReadIdx = 0;
3046 kal_int32 Hw_Get_bytes = 0;
3047 AFE_BLOCK_T *mBlock = NULL;
3048 substreamList *Temp = NULL;
3049 unsigned long flags;
3050
3051 if (Mem_Block == NULL)
3052 {
3053 return;
3054 }
3055
3056 if (GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DAI) == false)
3057 {
3058 //printk("%s(), GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DAI) == false, return\n ", __func__);
3059 return;
3060 }
3061
3062 mBlock = &Mem_Block->rBlock;
3063 HW_Cur_ReadIdx = Align64ByteSize(Afe_Get_Reg(AFE_DAI_CUR));
3064
3065 if (CheckSize(HW_Cur_ReadIdx))
3066 {
3067 return;
3068 }
3069 if (mBlock->pucVirtBufAddr == NULL)
3070 {
3071 return;
3072 }
3073
3074 // HW already fill in
3075 Hw_Get_bytes = (HW_Cur_ReadIdx - mBlock->pucPhysBufAddr) - mBlock->u4WriteIdx;
3076 if (Hw_Get_bytes < 0)
3077 {
3078 Hw_Get_bytes += mBlock->u4BufferSize;
3079 }
3080
3081 PRINTK_AUD_DAI("Auddrv_DAI_Interrupt_Handler Hw_Get_bytes:0x%x, HW_Cur_ReadIdx:0x%x, u4DMAReadIdx:0x%x, u4WriteIdx:0x%x, pucPhysBufAddr:0x%x Mem_Block->MemIfNum = %d \n",
3082 Hw_Get_bytes, HW_Cur_ReadIdx, mBlock->u4DMAReadIdx, mBlock->u4WriteIdx, mBlock->pucPhysBufAddr, Mem_Block->MemIfNum);
3083
3084 mBlock->u4WriteIdx += Hw_Get_bytes;
3085 mBlock->u4WriteIdx %= mBlock->u4BufferSize;
3086 mBlock->u4DataRemained += Hw_Get_bytes;
3087
3088 // buffer overflow
3089 if (mBlock->u4DataRemained > mBlock->u4BufferSize)
3090 {
3091 PRINTK_AUD_DAI("Auddrv_DAI_Interrupt_Handler buffer overflow u4DMAReadIdx:%x, u4WriteIdx:%x, u4DataRemained:%x, u4BufferSize:%x \n",
3092 mBlock->u4DMAReadIdx, mBlock->u4WriteIdx, mBlock->u4DataRemained, mBlock->u4BufferSize);
3093 /*
3094 mBlock->u4DataRemained = mBlock->u4BufferSize / 2;
3095 mBlock->u4DMAReadIdx = mBlock->u4WriteIdx - mBlock->u4BufferSize / 2;
3096 if (mBlock->u4DMAReadIdx < 0)
3097 {
3098 mBlock->u4DMAReadIdx += mBlock->u4BufferSize;
3099 }*/
3100 }
3101 Mem_Block->interruptTrigger = 1;
3102
3103 spin_lock_irqsave(&afe_mem_lock, flags);
3104 Temp = Mem_Block->substreamL;
3105 spin_unlock_irqrestore(&afe_mem_lock, flags);
3106 if (Temp != NULL)
3107 {
3108 if (Temp->substream != NULL)
3109 {
3110 snd_pcm_period_elapsed(Temp->substream);
3111 }
3112 }
3113 }
3114
3115 void Auddrv_MOD_DAI_Interrupt_Handler(void)
3116 {
3117 AFE_MEM_CONTROL_T *Mem_Block = AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_MOD_DAI];
3118 kal_uint32 HW_Cur_ReadIdx = 0;
3119 kal_int32 Hw_Get_bytes = 0;
3120 AFE_BLOCK_T *mBlock = NULL;
3121 substreamList *Temp = NULL;
3122 unsigned long flags;
3123
3124 if (Mem_Block == NULL)
3125 {
3126 return;
3127 }
3128
3129 if (GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_MOD_DAI) == false)
3130 {
3131 //printk("%s(), GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_MOD_DAI) == false, return\n ", __func__);
3132 return;
3133 }
3134
3135 mBlock = &Mem_Block->rBlock;
3136 HW_Cur_ReadIdx = Align64ByteSize(Afe_Get_Reg(AFE_MOD_DAI_CUR));
3137
3138 if (CheckSize(HW_Cur_ReadIdx))
3139 {
3140 return;
3141 }
3142 if (mBlock->pucVirtBufAddr == NULL)
3143 {
3144 return;
3145 }
3146
3147 // HW already fill in
3148 Hw_Get_bytes = (HW_Cur_ReadIdx - mBlock->pucPhysBufAddr) - mBlock->u4WriteIdx;
3149 if (Hw_Get_bytes < 0)
3150 {
3151 Hw_Get_bytes += mBlock->u4BufferSize;
3152 }
3153
3154 PRINTK_AUD_MODDAI("Auddrv_MOD_DAI_Interrupt_Handler Hw_Get_bytes:0x%x, HW_Cur_ReadIdx:0x%x, u4DMAReadIdx:0x%x, u4WriteIdx:0x%x, pucPhysBufAddr:0x%x Mem_Block->MemIfNum = %d \n",
3155 Hw_Get_bytes, HW_Cur_ReadIdx, mBlock->u4DMAReadIdx, mBlock->u4WriteIdx, mBlock->pucPhysBufAddr, Mem_Block->MemIfNum);
3156
3157 mBlock->u4WriteIdx += Hw_Get_bytes;
3158 mBlock->u4WriteIdx %= mBlock->u4BufferSize;
3159 mBlock->u4DataRemained += Hw_Get_bytes;
3160
3161 // buffer overflow
3162 if (mBlock->u4DataRemained > mBlock->u4BufferSize)
3163 {
3164 PRINTK_AUD_MODDAI("Auddrv_MOD_DAI_Interrupt_Handler buffer overflow u4DMAReadIdx:%x, u4WriteIdx:%x, u4DataRemained:%x, u4BufferSize:%x \n",
3165 mBlock->u4DMAReadIdx, mBlock->u4WriteIdx, mBlock->u4DataRemained, mBlock->u4BufferSize);
3166 /*
3167 mBlock->u4DataRemained = mBlock->u4BufferSize / 2;
3168 mBlock->u4DMAReadIdx = mBlock->u4WriteIdx - mBlock->u4BufferSize / 2;
3169 if (mBlock->u4DMAReadIdx < 0)
3170 {
3171 mBlock->u4DMAReadIdx += mBlock->u4BufferSize;
3172 }*/
3173 }
3174 Mem_Block->interruptTrigger = 1;
3175
3176 spin_lock_irqsave(&afe_mem_lock, flags);
3177 Temp = AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_MOD_DAI]->substreamL;
3178 spin_unlock_irqrestore(&afe_mem_lock, flags);
3179 if(Temp != NULL)
3180 {
3181 if(Temp->substream != NULL)
3182 {
3183 snd_pcm_period_elapsed(Temp->substream);
3184 }
3185 }
3186 }
3187
3188 void Auddrv_DL1_Interrupt_Handler(void) // irq1 ISR handler
3189 {
3190 #define MAGIC_NUMBER 0xFFFFFFC0
3191
3192 kal_int32 Afe_consumed_bytes = 0;
3193 kal_int32 HW_memory_index = 0;
3194 kal_int32 HW_Cur_ReadIdx = 0;
3195 AFE_BLOCK_T *Afe_Block = &(AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_DL1]->rBlock);
3196 substreamList *Temp = NULL;
3197 unsigned long flags;
3198
3199 if (GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DL1) == false)
3200 {
3201 //printk("%s(), GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DL1) == false, return\n ", __func__);
3202 return;
3203 }
3204
3205 HW_Cur_ReadIdx = Afe_Get_Reg(AFE_DL1_CUR);
3206 if (HW_Cur_ReadIdx == 0)
3207 {
3208 PRINTK_AUDDRV("[Auddrv] HW_Cur_ReadIdx ==0 \n");
3209 HW_Cur_ReadIdx = Afe_Block->pucPhysBufAddr;
3210 }
3211 HW_memory_index = (HW_Cur_ReadIdx - Afe_Block->pucPhysBufAddr);
3212
3213 PRINTK_AUD_DL1("[Auddrv] HW_Cur_ReadIdx=0x%x HW_memory_index = 0x%x Afe_Block->pucPhysBufAddr = 0x%x\n",
3214 HW_Cur_ReadIdx, HW_memory_index, Afe_Block->pucPhysBufAddr);
3215
3216
3217 // get hw consume bytes
3218 if (HW_memory_index > Afe_Block->u4DMAReadIdx)
3219 {
3220 Afe_consumed_bytes = HW_memory_index - Afe_Block->u4DMAReadIdx;
3221 }
3222 else
3223 {
3224 Afe_consumed_bytes = Afe_Block->u4BufferSize + HW_memory_index - Afe_Block->u4DMAReadIdx ;
3225 }
3226
3227 Afe_consumed_bytes = Afe_consumed_bytes & MAGIC_NUMBER; //64 bytes align
3228
3229 /*
3230 if ((Afe_consumed_bytes & 0x1f) != 0)
3231 {
3232 printk("[Auddrv] DMA address is not aligned 32 bytes \n");
3233 }*/
3234
3235 PRINTK_AUD_DL1("+Auddrv_DL1_Interrupt_Handler ReadIdx:%x WriteIdx:%x, DataRemained:%x, Afe_consumed_bytes:%x HW_memory_index = %x \n",
3236 Afe_Block->u4DMAReadIdx, Afe_Block->u4WriteIdx, Afe_Block->u4DataRemained, Afe_consumed_bytes, HW_memory_index);
3237
3238 if (Afe_Block->u4DataRemained < Afe_consumed_bytes || Afe_Block->u4DataRemained <= 0 || Afe_Block->u4DataRemained > Afe_Block->u4BufferSize)
3239 {
3240 printk("DL_Handling underflow \n");
3241 }
3242 else
3243 {
3244
3245 PRINTK_AUD_DL1("+DL_Handling normal ReadIdx:%x ,DataRemained:%x, WriteIdx:%x \n",
3246 Afe_Block->u4DMAReadIdx, Afe_Block->u4DataRemained, Afe_Block->u4WriteIdx);
3247 Afe_Block->u4DataRemained -= Afe_consumed_bytes;
3248 Afe_Block->u4DMAReadIdx += Afe_consumed_bytes;
3249 Afe_Block->u4DMAReadIdx %= Afe_Block->u4BufferSize;
3250 }
3251 AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_DL1]->interruptTrigger = 1 ;
3252 PRINTK_AUD_DL1("-DL_Handling normal ReadIdx:%x ,DataRemained:%x, WriteIdx:%x \n",
3253 Afe_Block->u4DMAReadIdx, Afe_Block->u4DataRemained, Afe_Block->u4WriteIdx);
3254 spin_lock_irqsave(&afe_mem_lock, flags);
3255 Temp = AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_DL1]->substreamL;
3256 spin_unlock_irqrestore(&afe_mem_lock, flags);
3257 if (Temp != NULL)
3258 {
3259 if (Temp->substream != NULL)
3260 {
3261 snd_pcm_period_elapsed(Temp->substream);
3262 }
3263 }
3264 }
3265
3266 struct snd_dma_buffer *Get_Mem_Buffer(Soc_Aud_Digital_Block MemBlock)
3267 {
3268 printk("%s MemBlock = %d\n", __func__, MemBlock);
3269 switch (MemBlock)
3270 {
3271 case Soc_Aud_Digital_Block_MEM_DL1:
3272 return Audio_dma_buf[MemBlock] ;
3273 case Soc_Aud_Digital_Block_MEM_DL2:
3274 return Audio_dma_buf[MemBlock] ;
3275 case Soc_Aud_Digital_Block_MEM_VUL:
3276 return Audio_dma_buf[MemBlock] ;
3277 case Soc_Aud_Digital_Block_MEM_DAI:
3278 return Audio_dma_buf[MemBlock] ;
3279 case Soc_Aud_Digital_Block_MEM_AWB:
3280 return Audio_dma_buf[MemBlock] ;
3281 case Soc_Aud_Digital_Block_MEM_MOD_DAI:
3282 return Audio_dma_buf[MemBlock] ;
3283 case Soc_Aud_Digital_Block_MEM_DL1_DATA2:
3284 return Audio_dma_buf[MemBlock] ;
3285 case Soc_Aud_Digital_Block_MEM_VUL_DATA2:
3286 return Audio_dma_buf[MemBlock] ;
3287 case Soc_Aud_Digital_Block_MEM_HDMI:
3288 return Audio_dma_buf[MemBlock];
3289 case Soc_Aud_Digital_Block_MEM_I2S:
3290 printk("currently not support \n");
3291 break;
3292 default:
3293 break;
3294 }
3295 return NULL;
3296 }
3297
3298 void Auddrv_UL1_Interrupt_Handler(void)
3299 {
3300 AFE_MEM_CONTROL_T *Mem_Block = AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_VUL];
3301
3302 kal_uint32 HW_Cur_ReadIdx = 0;
3303 kal_int32 Hw_Get_bytes = 0;
3304 AFE_BLOCK_T *mBlock = NULL;
3305 substreamList *Temp = NULL;
3306 unsigned long flags;
3307 if (Mem_Block == NULL)
3308 {
3309 printk("Mem_Block == NULL \n ");
3310 return;
3311 }
3312
3313 if (GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_VUL) == false)
3314 {
3315 //printk("%s(), GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_VUL) == false, return\n ", __func__);
3316 return;
3317 }
3318
3319 mBlock = &Mem_Block->rBlock;
3320 HW_Cur_ReadIdx = Align64ByteSize(Afe_Get_Reg(AFE_VUL_CUR));
3321 if (CheckSize(HW_Cur_ReadIdx))
3322 {
3323 return;
3324 }
3325 if (mBlock->pucVirtBufAddr == NULL)
3326 {
3327 return;
3328 }
3329
3330 // HW already fill in
3331 Hw_Get_bytes = (HW_Cur_ReadIdx - mBlock->pucPhysBufAddr) - mBlock->u4WriteIdx;
3332 if (Hw_Get_bytes < 0)
3333 {
3334 Hw_Get_bytes += mBlock->u4BufferSize;
3335 }
3336
3337 PRINTK_AUD_UL1("Auddrv_Handle_Mem_context Hw_Get_bytes:%x, HW_Cur_ReadIdx:%x, u4DMAReadIdx:%x, u4WriteIdx:0x%x, pucPhysBufAddr:%x Mem_Block->MemIfNum = %d \n",
3338 Hw_Get_bytes, HW_Cur_ReadIdx, mBlock->u4DMAReadIdx, mBlock->u4WriteIdx, mBlock->pucPhysBufAddr, Mem_Block->MemIfNum);
3339
3340 mBlock->u4WriteIdx += Hw_Get_bytes;
3341 mBlock->u4WriteIdx %= mBlock->u4BufferSize;
3342 mBlock->u4DataRemained += Hw_Get_bytes;
3343
3344 // buffer overflow
3345 if (mBlock->u4DataRemained > mBlock->u4BufferSize)
3346 {
3347 printk("Auddrv_Handle_Mem_context buffer overflow u4DMAReadIdx:%x, u4WriteIdx:%x, u4DataRemained:%x, u4BufferSize:%x \n",
3348 mBlock->u4DMAReadIdx, mBlock->u4WriteIdx, mBlock->u4DataRemained, mBlock->u4BufferSize);
3349 }
3350 AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_VUL]->interruptTrigger = 1;
3351
3352 spin_lock_irqsave(&afe_mem_lock, flags);
3353 Temp = AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_VUL]->substreamL;
3354 spin_unlock_irqrestore(&afe_mem_lock, flags);
3355 if (Temp != NULL)
3356 {
3357 if (Temp->substream != NULL)
3358 {
3359 snd_pcm_period_elapsed(Temp->substream);
3360 }
3361 }
3362 }
3363
3364 void Clear_Mem_CopySize(Soc_Aud_Digital_Block MemBlock)
3365 {
3366 substreamList *head;
3367 unsigned long flags;
3368 spin_lock_irqsave(&afe_mem_lock, flags);
3369 head = AFE_Mem_Control_context[MemBlock]->substreamL;
3370 //printk("+%s MemBlock = %d \n ", __func__, MemBlock);
3371 while (head != NULL) // frst item is NULL
3372 {
3373 head->u4MaxCopySize = 0;
3374 head = (substreamList *)head->next;
3375 }
3376 spin_unlock_irqrestore(&afe_mem_lock, flags);
3377 //printk("-%s MemBlock = %d \n ", __func__, MemBlock);
3378 }
3379
3380 kal_uint32 Get_Mem_CopySizeByStream(Soc_Aud_Digital_Block MemBlock, struct snd_pcm_substream *substream)
3381 {
3382 substreamList *head;
3383 unsigned long flags;
3384 kal_uint32 MaxCopySize;
3385 spin_lock_irqsave(&afe_mem_lock, flags);
3386 head = AFE_Mem_Control_context[MemBlock]->substreamL;
3387 //printk("+%s MemBlock = %d \n ", __func__, MemBlock);
3388 while (head != NULL) // frst item is NULL
3389 {
3390 if (head->substream == substream)
3391 {
3392 MaxCopySize = head->u4MaxCopySize;
3393 spin_unlock_irqrestore(&afe_mem_lock, flags);
3394 return MaxCopySize;
3395 }
3396 head = (substreamList *)head->next;
3397 }
3398 spin_unlock_irqrestore(&afe_mem_lock, flags);
3399 //printk("-%s MemBlock = %d \n ", __func__, MemBlock);
3400 return 0;
3401 }
3402
3403 kal_uint32 Get_Mem_MaxCopySize(Soc_Aud_Digital_Block MemBlock)
3404 {
3405 substreamList *head;
3406 unsigned long flags;
3407 kal_uint32 MaxCopySize;
3408 spin_lock_irqsave(&afe_mem_lock, flags);
3409 head = AFE_Mem_Control_context[MemBlock]->substreamL;
3410 MaxCopySize = 0;
3411 //printk("+%s MemBlock = %d \n ", __func__, MemBlock);
3412 while (head != NULL) // frst item is NULL
3413 {
3414 if (MaxCopySize < head->u4MaxCopySize)
3415 {
3416 MaxCopySize = head->u4MaxCopySize;
3417 }
3418 head = (substreamList *)head->next;
3419 }
3420 spin_unlock_irqrestore(&afe_mem_lock, flags);
3421 //printk("-%s MemBlock = %d \n ", __func__, MemBlock);
3422 return MaxCopySize;
3423 }
3424
3425 void Set_Mem_CopySizeByStream(Soc_Aud_Digital_Block MemBlock, struct snd_pcm_substream *substream, uint32 size)
3426 {
3427 substreamList *head;
3428 unsigned long flags;
3429 spin_lock_irqsave(&afe_mem_lock, flags);
3430 head = AFE_Mem_Control_context[MemBlock]->substreamL;
3431 //printk("+%s MemBlock = %d \n ", __func__, MemBlock);
3432 while (head != NULL) // frst item is NULL
3433 {
3434 if (head->substream == substream)
3435 {
3436 head->u4MaxCopySize += size;
3437 break;
3438 }
3439 head = (substreamList *)head->next;
3440 }
3441 spin_unlock_irqrestore(&afe_mem_lock, flags);
3442 //printk("-%s MemBlock = %d \n ", __func__, MemBlock);
3443 }
3444
3445 void Auddrv_UL2_Interrupt_Handler(void)
3446 {
3447 AFE_MEM_CONTROL_T *Mem_Block = AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_VUL_DATA2];
3448
3449 kal_uint32 HW_Cur_ReadIdx = 0;
3450 kal_int32 Hw_Get_bytes = 0;
3451 AFE_BLOCK_T *mBlock = NULL;
3452 substreamList *Temp = NULL;
3453 unsigned long flags;
3454
3455 PRINTK_AUD_UL2("Auddrv_UL2_Interrupt_Handler \n ");
3456
3457 if (Mem_Block == NULL)
3458 {
3459 printk("Mem_Block == NULL \n ");
3460 return;
3461 }
3462
3463 if (GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_VUL_DATA2) == false)
3464 {
3465 //printk("%s(), GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_VUL_DATA2) == false, return\n ", __func__);
3466 return;
3467 }
3468
3469 mBlock = &Mem_Block->rBlock;
3470 HW_Cur_ReadIdx = Align64ByteSize(Afe_Get_Reg(AFE_VUL_D2_CUR));
3471 PRINTK_AUD_UL2("Auddrv_UL2_Interrupt_Handler HW_Cur_ReadIdx = 0x%x\n ", HW_Cur_ReadIdx);
3472
3473 if (CheckSize(HW_Cur_ReadIdx))
3474 {
3475 return;
3476 }
3477 if (mBlock->pucVirtBufAddr == NULL)
3478 {
3479 return;
3480 }
3481
3482 // HW already fill in
3483 Hw_Get_bytes = (HW_Cur_ReadIdx - mBlock->pucPhysBufAddr) - mBlock->u4WriteIdx;
3484 if (Hw_Get_bytes < 0)
3485 {
3486 Hw_Get_bytes += mBlock->u4BufferSize;
3487 }
3488
3489 PRINTK_AUD_UL2("Auddrv_UL2_Interrupt_Handler Hw_Get_bytes:%x, HW_Cur_ReadIdx:%x, u4DMAReadIdx:%x, u4WriteIdx:0x%x, pucPhysBufAddr:%x Mem_Block->MemIfNum = %d \n",
3490 Hw_Get_bytes, HW_Cur_ReadIdx, mBlock->u4DMAReadIdx, mBlock->u4WriteIdx, mBlock->pucPhysBufAddr, Mem_Block->MemIfNum);
3491
3492 mBlock->u4WriteIdx += Hw_Get_bytes;
3493 mBlock->u4WriteIdx %= mBlock->u4BufferSize;
3494 mBlock->u4DataRemained += Hw_Get_bytes;
3495
3496 // buffer overflow
3497 if (mBlock->u4DataRemained > mBlock->u4BufferSize)
3498 {
3499 PRINTK_AUD_UL1("Auddrv_UL2_Interrupt_Handler buffer overflow u4DMAReadIdx:%x, u4WriteIdx:%x, u4DataRemained:%x, u4BufferSize:%x \n",
3500 mBlock->u4DMAReadIdx, mBlock->u4WriteIdx, mBlock->u4DataRemained, mBlock->u4BufferSize);
3501 mBlock->u4DataRemained = mBlock->u4BufferSize / 2;
3502 mBlock->u4DMAReadIdx = mBlock->u4WriteIdx - mBlock->u4BufferSize / 2;
3503 if (mBlock->u4DMAReadIdx < 0)
3504 {
3505 mBlock->u4DMAReadIdx += mBlock->u4BufferSize;
3506 }
3507 }
3508 AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_VUL_DATA2]->interruptTrigger = 1;
3509 spin_lock_irqsave(&afe_mem_lock, flags);
3510 Temp = AFE_Mem_Control_context[Soc_Aud_Digital_Block_MEM_VUL_DATA2]->substreamL;
3511 spin_unlock_irqrestore(&afe_mem_lock, flags);
3512 if (Temp != NULL)
3513 {
3514 if (Temp->substream != NULL)
3515 {
3516 snd_pcm_period_elapsed(Temp->substream);
3517 }
3518 }
3519 }
3520
3521 bool BackUp_Audio_Register(void)
3522 {
3523 AudDrv_Clk_On();
3524 mAudioRegCache.REG_AUDIO_TOP_CON1 = Afe_Get_Reg(AUDIO_TOP_CON1);
3525 mAudioRegCache.REG_AUDIO_TOP_CON2 = Afe_Get_Reg(AUDIO_TOP_CON2);
3526 mAudioRegCache.REG_AUDIO_TOP_CON3 = Afe_Get_Reg(AUDIO_TOP_CON3);
3527 mAudioRegCache.REG_AFE_DAC_CON0 = Afe_Get_Reg(AFE_DAC_CON0);
3528 mAudioRegCache.REG_AFE_DAC_CON1 = Afe_Get_Reg(AFE_DAC_CON1);
3529 mAudioRegCache.REG_AFE_I2S_CON = Afe_Get_Reg(AFE_I2S_CON);
3530 mAudioRegCache.REG_AFE_DAIBT_CON0 = Afe_Get_Reg(AFE_DAIBT_CON0);
3531 mAudioRegCache.REG_AFE_CONN0 = Afe_Get_Reg(AFE_CONN0);
3532 mAudioRegCache.REG_AFE_CONN1 = Afe_Get_Reg(AFE_CONN1);
3533 mAudioRegCache.REG_AFE_CONN2 = Afe_Get_Reg(AFE_CONN2);
3534 mAudioRegCache.REG_AFE_CONN3 = Afe_Get_Reg(AFE_CONN3);
3535 mAudioRegCache.REG_AFE_CONN4 = Afe_Get_Reg(AFE_CONN4);
3536 mAudioRegCache.REG_AFE_I2S_CON1 = Afe_Get_Reg(AFE_I2S_CON1);
3537 mAudioRegCache.REG_AFE_I2S_CON2 = Afe_Get_Reg(AFE_I2S_CON2);
3538 mAudioRegCache.REG_AFE_MRGIF_CON = Afe_Get_Reg(AFE_MRGIF_CON);
3539 mAudioRegCache.REG_AFE_DL1_D2_BASE = Afe_Get_Reg(AFE_DL1_D2_BASE);
3540 mAudioRegCache.REG_AFE_DL1_D2_CUR = Afe_Get_Reg(AFE_DL1_D2_CUR);
3541 mAudioRegCache.REG_AFE_DL1_D2_END = Afe_Get_Reg(AFE_DL1_D2_END);
3542 mAudioRegCache.REG_AFE_VUL_D2_BASE = Afe_Get_Reg(AFE_VUL_D2_BASE);
3543 mAudioRegCache.REG_AFE_VUL_D2_END = Afe_Get_Reg(AFE_VUL_D2_END);
3544 mAudioRegCache.REG_AFE_VUL_D2_CUR = Afe_Get_Reg(AFE_VUL_D2_CUR);
3545 mAudioRegCache.REG_AFE_I2S_CON3 = Afe_Get_Reg(AFE_I2S_CON3);
3546 mAudioRegCache.REG_AFE_DL2_BASE = Afe_Get_Reg(AFE_DL2_BASE);
3547 mAudioRegCache.REG_AFE_DL2_CUR = Afe_Get_Reg(AFE_DL2_CUR);
3548 mAudioRegCache.REG_AFE_DL2_END = Afe_Get_Reg(AFE_DL2_END);
3549 mAudioRegCache.REG_AFE_CONN5 = Afe_Get_Reg(AFE_CONN5);
3550 mAudioRegCache.REG_AFE_CONN_24BIT = Afe_Get_Reg(AFE_CONN_24BIT);
3551 mAudioRegCache.REG_AFE_AWB_BASE = Afe_Get_Reg(AFE_AWB_BASE);
3552 mAudioRegCache.REG_AFE_AWB_END = Afe_Get_Reg(AFE_AWB_END);
3553 mAudioRegCache.REG_AFE_AWB_CUR = Afe_Get_Reg(AFE_AWB_CUR);
3554 mAudioRegCache.REG_AFE_DAI_BASE = Afe_Get_Reg(AFE_DAI_BASE);
3555 mAudioRegCache.REG_AFE_DAI_END = Afe_Get_Reg(AFE_DAI_END);
3556 mAudioRegCache.REG_AFE_DAI_CUR = Afe_Get_Reg(AFE_DAI_CUR);
3557 mAudioRegCache.REG_AFE_CONN6 = Afe_Get_Reg(AFE_CONN6);
3558
3559 mAudioRegCache.REG_AFE_MEMIF_MSB = Afe_Get_Reg(AFE_MEMIF_MSB);
3560
3561 mAudioRegCache.REG_AFE_ADDA_DL_SRC2_CON0 = Afe_Get_Reg(AFE_ADDA_DL_SRC2_CON0);
3562 mAudioRegCache.REG_AFE_ADDA_DL_SRC2_CON1 = Afe_Get_Reg(AFE_ADDA_DL_SRC2_CON1);
3563 mAudioRegCache.REG_AFE_ADDA_UL_SRC_CON0 = Afe_Get_Reg(AFE_ADDA_UL_SRC_CON0);
3564 mAudioRegCache.REG_AFE_ADDA_UL_SRC_CON1 = Afe_Get_Reg(AFE_ADDA_UL_SRC_CON1);
3565 mAudioRegCache.REG_AFE_ADDA_TOP_CON0 = Afe_Get_Reg(AFE_ADDA_TOP_CON0);
3566 mAudioRegCache.REG_AFE_ADDA_UL_DL_CON0 = Afe_Get_Reg(AFE_ADDA_UL_DL_CON0);
3567
3568 mAudioRegCache.REG_AFE_ADDA_NEWIF_CFG0 = Afe_Get_Reg(AFE_ADDA_NEWIF_CFG0);
3569 mAudioRegCache.REG_AFE_ADDA_NEWIF_CFG1 = Afe_Get_Reg(AFE_ADDA_NEWIF_CFG1);
3570
3571 mAudioRegCache.REG_AFE_SIDETONE_CON0 = Afe_Get_Reg(AFE_SIDETONE_CON0);
3572 mAudioRegCache.REG_AFE_SIDETONE_COEFF = Afe_Get_Reg(AFE_SIDETONE_COEFF);
3573 mAudioRegCache.REG_AFE_SIDETONE_CON1 = Afe_Get_Reg(AFE_SIDETONE_CON1);
3574 mAudioRegCache.REG_AFE_SIDETONE_GAIN = Afe_Get_Reg(AFE_SIDETONE_GAIN);
3575 mAudioRegCache.REG_AFE_SGEN_CON0 = Afe_Get_Reg(AFE_SGEN_CON0);
3576 mAudioRegCache.REG_AFE_SGEN_CON1 = Afe_Get_Reg(AFE_SGEN_CON1);
3577 mAudioRegCache.REG_AFE_TOP_CON0 = Afe_Get_Reg(AFE_TOP_CON0);
3578 mAudioRegCache.REG_AFE_ADDA_PREDIS_CON0 = Afe_Get_Reg(AFE_ADDA_PREDIS_CON0);
3579 mAudioRegCache.REG_AFE_ADDA_PREDIS_CON1 = Afe_Get_Reg(AFE_ADDA_PREDIS_CON1);
3580
3581 mAudioRegCache.REG_AFE_MOD_DAI_BASE = Afe_Get_Reg(AFE_MOD_DAI_BASE);
3582 mAudioRegCache.REG_AFE_MOD_DAI_END = Afe_Get_Reg(AFE_MOD_DAI_END);
3583 mAudioRegCache.REG_AFE_MOD_DAI_CUR = Afe_Get_Reg(AFE_MOD_DAI_CUR);
3584 mAudioRegCache.REG_AFE_HDMI_OUT_CON0 = Afe_Get_Reg(AFE_HDMI_OUT_CON0);
3585 mAudioRegCache.REG_AFE_HDMI_BASE = Afe_Get_Reg(AFE_HDMI_BASE);
3586 mAudioRegCache.REG_AFE_HDMI_CUR = Afe_Get_Reg(AFE_HDMI_CUR);
3587 mAudioRegCache.REG_AFE_HDMI_END = Afe_Get_Reg(AFE_HDMI_END);
3588 mAudioRegCache.REG_AFE_HDMI_CONN0 = Afe_Get_Reg(AFE_HDMI_CONN0);
3589 mAudioRegCache.REG_AFE_IRQ_MCU_CON = Afe_Get_Reg(AFE_IRQ_MCU_CON);
3590 mAudioRegCache.REG_AFE_IRQ_MCU_CNT1 = Afe_Get_Reg(AFE_IRQ_MCU_CNT1);
3591 mAudioRegCache.REG_AFE_IRQ_MCU_CNT2 = Afe_Get_Reg(AFE_IRQ_MCU_CNT2);
3592 mAudioRegCache.REG_AFE_IRQ_MCU_EN = Afe_Get_Reg(AFE_IRQ_MCU_EN);
3593 mAudioRegCache.REG_AFE_MEMIF_MAXLEN = Afe_Get_Reg(AFE_MEMIF_MAXLEN);
3594 mAudioRegCache.REG_AFE_MEMIF_PBUF_SIZE = Afe_Get_Reg(AFE_MEMIF_PBUF_SIZE);
3595 mAudioRegCache.REG_AFE_APLL1_TUNER_CFG = Afe_Get_Reg(AFE_APLL1_TUNER_CFG);
3596 mAudioRegCache.REG_AFE_APLL2_TUNER_CFG = Afe_Get_Reg(AFE_APLL2_TUNER_CFG);
3597 mAudioRegCache.REG_AFE_GAIN1_CON0 = Afe_Get_Reg(AFE_GAIN1_CON0);
3598 mAudioRegCache.REG_AFE_GAIN1_CON1 = Afe_Get_Reg(AFE_GAIN1_CON1);
3599 mAudioRegCache.REG_AFE_GAIN1_CON2 = Afe_Get_Reg(AFE_GAIN1_CON2);
3600 mAudioRegCache.REG_AFE_GAIN1_CON3 = Afe_Get_Reg(AFE_GAIN1_CON3);
3601 mAudioRegCache.REG_AFE_GAIN1_CONN = Afe_Get_Reg(AFE_GAIN1_CONN);
3602 mAudioRegCache.REG_AFE_GAIN1_CUR = Afe_Get_Reg(AFE_GAIN1_CUR);
3603 mAudioRegCache.REG_AFE_GAIN2_CON0 = Afe_Get_Reg(AFE_GAIN1_CON0);
3604 mAudioRegCache.REG_AFE_GAIN2_CON1 = Afe_Get_Reg(AFE_GAIN1_CON1);
3605 mAudioRegCache.REG_AFE_GAIN2_CON2 = Afe_Get_Reg(AFE_GAIN1_CON2);
3606 mAudioRegCache.REG_AFE_GAIN2_CON3 = Afe_Get_Reg(AFE_GAIN1_CON3);
3607 mAudioRegCache.REG_AFE_GAIN2_CONN = Afe_Get_Reg(AFE_GAIN1_CONN);
3608 mAudioRegCache.REG_AFE_GAIN2_CUR = Afe_Get_Reg(AFE_GAIN2_CUR);
3609 mAudioRegCache.REG_AFE_GAIN2_CONN2 = Afe_Get_Reg(AFE_GAIN2_CONN2);
3610 mAudioRegCache.REG_AFE_GAIN2_CONN3 = Afe_Get_Reg(AFE_GAIN2_CONN3);
3611 mAudioRegCache.REG_AFE_GAIN1_CONN2 = Afe_Get_Reg(AFE_GAIN1_CONN2);
3612 mAudioRegCache.REG_AFE_GAIN1_CONN3 = Afe_Get_Reg(AFE_GAIN1_CONN3);
3613 mAudioRegCache.REG_AFE_CONN7 = Afe_Get_Reg(AFE_CONN7);
3614 mAudioRegCache.REG_AFE_CONN8 = Afe_Get_Reg(AFE_CONN8);
3615 mAudioRegCache.REG_AFE_CONN9 = Afe_Get_Reg(AFE_CONN9);
3616 mAudioRegCache.REG_FPGA_CFG2 = Afe_Get_Reg(FPGA_CFG2);
3617 mAudioRegCache.REG_FPGA_CFG3 = Afe_Get_Reg(FPGA_CFG3);
3618 mAudioRegCache.REG_FPGA_CFG0 = Afe_Get_Reg(FPGA_CFG0);
3619 mAudioRegCache.REG_FPGA_CFG1 = Afe_Get_Reg(FPGA_CFG1);
3620
3621 mAudioRegCache.REG_AFE_ASRC_CON0 = Afe_Get_Reg(AFE_ASRC_CON0);
3622 mAudioRegCache.REG_AFE_ASRC_CON1 = Afe_Get_Reg(AFE_ASRC_CON1);
3623 mAudioRegCache.REG_AFE_ASRC_CON2 = Afe_Get_Reg(AFE_ASRC_CON2);
3624 mAudioRegCache.REG_AFE_ASRC_CON3 = Afe_Get_Reg(AFE_ASRC_CON3);
3625 mAudioRegCache.REG_AFE_ASRC_CON4 = Afe_Get_Reg(AFE_ASRC_CON4);
3626 mAudioRegCache.REG_AFE_ASRC_CON5 = Afe_Get_Reg(AFE_ASRC_CON5);
3627 mAudioRegCache.REG_AFE_ASRC_CON6 = Afe_Get_Reg(AFE_ASRC_CON6);
3628 mAudioRegCache.REG_AFE_ASRC_CON7 = Afe_Get_Reg(AFE_ASRC_CON7);
3629 mAudioRegCache.REG_AFE_ASRC_CON8 = Afe_Get_Reg(AFE_ASRC_CON8);
3630 mAudioRegCache.REG_AFE_ASRC_CON9 = Afe_Get_Reg(AFE_ASRC_CON9);
3631 mAudioRegCache.REG_AFE_ASRC_CON10 = Afe_Get_Reg(AFE_ASRC_CON10);
3632 mAudioRegCache.REG_AFE_ASRC_CON11 = Afe_Get_Reg(AFE_ASRC_CON11);
3633 mAudioRegCache.REG_PCM_INTF_CON = Afe_Get_Reg(PCM_INTF_CON);
3634 mAudioRegCache.REG_PCM_INTF_CON2 = Afe_Get_Reg(PCM_INTF_CON2);
3635 mAudioRegCache.REG_PCM2_INTF_CON = Afe_Get_Reg(PCM2_INTF_CON);
3636 mAudioRegCache.REG_AFE_TDM_CON1 = Afe_Get_Reg(AFE_TDM_CON1);
3637 mAudioRegCache.REG_AFE_TDM_CON2 = Afe_Get_Reg(AFE_TDM_CON2);
3638 mAudioRegCache.REG_AFE_ASRC_CON13 = Afe_Get_Reg(AFE_ASRC_CON13);
3639 mAudioRegCache.REG_AFE_ASRC_CON14 = Afe_Get_Reg(AFE_ASRC_CON14);
3640 mAudioRegCache.REG_AFE_ASRC_CON15 = Afe_Get_Reg(AFE_ASRC_CON15);
3641 mAudioRegCache.REG_AFE_ASRC_CON16 = Afe_Get_Reg(AFE_ASRC_CON16);
3642 mAudioRegCache.REG_AFE_ASRC_CON17 = Afe_Get_Reg(AFE_ASRC_CON17);
3643 mAudioRegCache.REG_AFE_ASRC_CON18 = Afe_Get_Reg(AFE_ASRC_CON18);
3644 mAudioRegCache.REG_AFE_ASRC_CON19 = Afe_Get_Reg(AFE_ASRC_CON19);
3645 mAudioRegCache.REG_AFE_ASRC_CON20 = Afe_Get_Reg(AFE_ASRC_CON20);
3646 mAudioRegCache.REG_AFE_ASRC_CON21 = Afe_Get_Reg(AFE_ASRC_CON21);
3647 mAudioRegCache.REG_AFE_ADDA2_TOP_CON0 = Afe_Get_Reg(AFE_ADDA2_TOP_CON0);
3648 mAudioRegCache.REG_AFE_ADDA2_UL_SRC_CON0 = Afe_Get_Reg(AFE_ADDA2_UL_SRC_CON0);
3649 mAudioRegCache.REG_AFE_ADDA2_UL_SRC_CON1 = Afe_Get_Reg(AFE_ADDA2_UL_SRC_CON1);
3650
3651 mAudioRegCache.REG_AFE_ADDA2_NEWIF_CFG0 = Afe_Get_Reg(AFE_ADDA2_NEWIF_CFG0);
3652 mAudioRegCache.REG_AFE_ADDA2_NEWIF_CFG1 = Afe_Get_Reg(AFE_ADDA2_NEWIF_CFG1);
3653 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_02_01 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_02_01);
3654 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_04_03 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_04_03);
3655 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_06_05 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_06_05);
3656 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_08_07 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_08_07);
3657 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_10_09 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_10_09);
3658 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_12_11 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_12_11);
3659 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_14_13 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_14_13);
3660 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_16_15 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_16_15);
3661 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_18_17 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_18_17);
3662 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_20_19 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_20_19);
3663 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_22_21 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_22_21);
3664 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_24_23 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_24_23);
3665 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_26_25 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_26_25);
3666 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_28_27 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_28_27);
3667 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_30_29 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_30_29);
3668 mAudioRegCache.REG_AFE_ADDA3_UL_SRC_CON0 = Afe_Get_Reg(AFE_ADDA3_UL_SRC_CON0);
3669 mAudioRegCache.REG_AFE_ADDA3_UL_SRC_CON1 = Afe_Get_Reg(AFE_ADDA3_UL_SRC_CON1);
3670 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_02_01 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_02_01);
3671 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_04_03 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_04_03);
3672 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_06_05 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_06_05);
3673 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_08_07 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_08_07);
3674 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_10_09 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_10_09);
3675 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_12_11 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_12_11);
3676 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_14_13 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_14_13);
3677 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_16_15 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_16_15);
3678 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_18_17 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_18_17);
3679 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_20_19 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_20_19);
3680 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_22_21 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_22_21);
3681 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_24_23 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_24_23);
3682 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_26_25 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_26_25);
3683 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_28_27 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_28_27);
3684 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_30_29 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_30_29);
3685 mAudioRegCache.REG_AFE_ASRC2_CON0 = Afe_Get_Reg(AFE_ASRC2_CON0);
3686 mAudioRegCache.REG_AFE_ASRC2_CON1 = Afe_Get_Reg(AFE_ASRC2_CON1);
3687 mAudioRegCache.REG_AFE_ASRC2_CON2 = Afe_Get_Reg(AFE_ASRC2_CON2);
3688 mAudioRegCache.REG_AFE_ASRC2_CON3 = Afe_Get_Reg(AFE_ASRC2_CON3);
3689 mAudioRegCache.REG_AFE_ASRC2_CON4 = Afe_Get_Reg(AFE_ASRC2_CON4);
3690 mAudioRegCache.REG_AFE_ASRC2_CON5 = Afe_Get_Reg(AFE_ASRC2_CON5);
3691 mAudioRegCache.REG_AFE_ASRC2_CON6 = Afe_Get_Reg(AFE_ASRC2_CON6);
3692 mAudioRegCache.REG_AFE_ASRC2_CON7 = Afe_Get_Reg(AFE_ASRC2_CON7);
3693 mAudioRegCache.REG_AFE_ASRC2_CON8 = Afe_Get_Reg(AFE_ASRC2_CON8);
3694 mAudioRegCache.REG_AFE_ASRC2_CON9 = Afe_Get_Reg(AFE_ASRC2_CON9);
3695 mAudioRegCache.REG_AFE_ASRC2_CON10 = Afe_Get_Reg(AFE_ASRC2_CON10);
3696 mAudioRegCache.REG_AFE_ASRC2_CON11 = Afe_Get_Reg(AFE_ASRC2_CON11);
3697 mAudioRegCache.REG_AFE_ASRC2_CON12 = Afe_Get_Reg(AFE_ASRC2_CON12);
3698 mAudioRegCache.REG_AFE_ASRC2_CON13 = Afe_Get_Reg(AFE_ASRC2_CON13);
3699 mAudioRegCache.REG_AFE_ASRC2_CON14 = Afe_Get_Reg(AFE_ASRC2_CON14);
3700 mAudioRegCache.REG_AFE_ASRC3_CON0 = Afe_Get_Reg(AFE_ASRC3_CON0);
3701 mAudioRegCache.REG_AFE_ASRC3_CON1 = Afe_Get_Reg(AFE_ASRC3_CON1);
3702 mAudioRegCache.REG_AFE_ASRC3_CON2 = Afe_Get_Reg(AFE_ASRC3_CON2);
3703 mAudioRegCache.REG_AFE_ASRC3_CON3 = Afe_Get_Reg(AFE_ASRC3_CON3);
3704 mAudioRegCache.REG_AFE_ASRC3_CON4 = Afe_Get_Reg(AFE_ASRC3_CON4);
3705 mAudioRegCache.REG_AFE_ASRC3_CON5 = Afe_Get_Reg(AFE_ASRC3_CON5);
3706 mAudioRegCache.REG_AFE_ASRC3_CON6 = Afe_Get_Reg(AFE_ASRC3_CON6);
3707 mAudioRegCache.REG_AFE_ASRC3_CON7 = Afe_Get_Reg(AFE_ASRC3_CON7);
3708 mAudioRegCache.REG_AFE_ASRC3_CON8 = Afe_Get_Reg(AFE_ASRC3_CON8);
3709 mAudioRegCache.REG_AFE_ASRC3_CON9 = Afe_Get_Reg(AFE_ASRC3_CON9);
3710 mAudioRegCache.REG_AFE_ASRC3_CON10 = Afe_Get_Reg(AFE_ASRC3_CON10);
3711 mAudioRegCache.REG_AFE_ASRC3_CON11 = Afe_Get_Reg(AFE_ASRC3_CON11);
3712 mAudioRegCache.REG_AFE_ASRC3_CON12 = Afe_Get_Reg(AFE_ASRC3_CON12);
3713 mAudioRegCache.REG_AFE_ASRC3_CON13 = Afe_Get_Reg(AFE_ASRC3_CON13);
3714 mAudioRegCache.REG_AFE_ASRC3_CON14 = Afe_Get_Reg(AFE_ASRC3_CON14);
3715 AudDrv_Clk_Off();
3716 return true;
3717 }
3718
3719
3720 bool Restore_Audio_Register(void)
3721 {
3722 AudDrv_Clk_On();
3723 mAudioRegCache.REG_AUDIO_TOP_CON1 = Afe_Get_Reg(AUDIO_TOP_CON1);
3724 mAudioRegCache.REG_AUDIO_TOP_CON2 = Afe_Get_Reg(AUDIO_TOP_CON2);
3725 mAudioRegCache.REG_AUDIO_TOP_CON3 = Afe_Get_Reg(AUDIO_TOP_CON3);
3726 mAudioRegCache.REG_AFE_DAC_CON0 = Afe_Get_Reg(AFE_DAC_CON0);
3727 mAudioRegCache.REG_AFE_DAC_CON1 = Afe_Get_Reg(AFE_DAC_CON1);
3728 mAudioRegCache.REG_AFE_I2S_CON = Afe_Get_Reg(AFE_I2S_CON);
3729 mAudioRegCache.REG_AFE_DAIBT_CON0 = Afe_Get_Reg(AFE_DAIBT_CON0);
3730 mAudioRegCache.REG_AFE_CONN0 = Afe_Get_Reg(AFE_CONN0);
3731 mAudioRegCache.REG_AFE_CONN1 = Afe_Get_Reg(AFE_CONN1);
3732 mAudioRegCache.REG_AFE_CONN2 = Afe_Get_Reg(AFE_CONN2);
3733 mAudioRegCache.REG_AFE_CONN3 = Afe_Get_Reg(AFE_CONN3);
3734 mAudioRegCache.REG_AFE_CONN4 = Afe_Get_Reg(AFE_CONN4);
3735 mAudioRegCache.REG_AFE_I2S_CON1 = Afe_Get_Reg(AFE_I2S_CON1);
3736 mAudioRegCache.REG_AFE_I2S_CON2 = Afe_Get_Reg(AFE_I2S_CON2);
3737 mAudioRegCache.REG_AFE_MRGIF_CON = Afe_Get_Reg(AFE_MRGIF_CON);
3738 mAudioRegCache.REG_AFE_DL1_D2_BASE = Afe_Get_Reg(AFE_DL1_D2_BASE);
3739 mAudioRegCache.REG_AFE_DL1_D2_CUR = Afe_Get_Reg(AFE_DL1_D2_CUR);
3740 mAudioRegCache.REG_AFE_DL1_D2_END = Afe_Get_Reg(AFE_DL1_D2_END);
3741 mAudioRegCache.REG_AFE_VUL_D2_BASE = Afe_Get_Reg(AFE_VUL_D2_BASE);
3742 mAudioRegCache.REG_AFE_VUL_D2_END = Afe_Get_Reg(AFE_VUL_D2_END);
3743 mAudioRegCache.REG_AFE_VUL_D2_CUR = Afe_Get_Reg(AFE_VUL_D2_CUR);
3744 mAudioRegCache.REG_AFE_I2S_CON3 = Afe_Get_Reg(AFE_I2S_CON3);
3745 mAudioRegCache.REG_AFE_DL2_BASE = Afe_Get_Reg(AFE_DL2_BASE);
3746 mAudioRegCache.REG_AFE_DL2_CUR = Afe_Get_Reg(AFE_DL2_CUR);
3747 mAudioRegCache.REG_AFE_DL2_END = Afe_Get_Reg(AFE_DL2_END);
3748 mAudioRegCache.REG_AFE_CONN5 = Afe_Get_Reg(AFE_CONN5);
3749 mAudioRegCache.REG_AFE_CONN_24BIT = Afe_Get_Reg(AFE_CONN_24BIT);
3750 mAudioRegCache.REG_AFE_AWB_BASE = Afe_Get_Reg(AFE_AWB_BASE);
3751 mAudioRegCache.REG_AFE_AWB_END = Afe_Get_Reg(AFE_AWB_END);
3752 mAudioRegCache.REG_AFE_AWB_CUR = Afe_Get_Reg(AFE_AWB_CUR);
3753 mAudioRegCache.REG_AFE_DAI_BASE = Afe_Get_Reg(AFE_DAI_BASE);
3754 mAudioRegCache.REG_AFE_DAI_END = Afe_Get_Reg(AFE_DAI_END);
3755 mAudioRegCache.REG_AFE_DAI_CUR = Afe_Get_Reg(AFE_DAI_CUR);
3756 mAudioRegCache.REG_AFE_CONN6 = Afe_Get_Reg(AFE_CONN6);
3757
3758 mAudioRegCache.REG_AFE_MEMIF_MSB = Afe_Get_Reg(AFE_MEMIF_MSB);
3759
3760 mAudioRegCache.REG_AFE_ADDA_DL_SRC2_CON0 = Afe_Get_Reg(AFE_ADDA_DL_SRC2_CON0);
3761 mAudioRegCache.REG_AFE_ADDA_DL_SRC2_CON1 = Afe_Get_Reg(AFE_ADDA_DL_SRC2_CON1);
3762 mAudioRegCache.REG_AFE_ADDA_UL_SRC_CON0 = Afe_Get_Reg(AFE_ADDA_UL_SRC_CON0);
3763 mAudioRegCache.REG_AFE_ADDA_UL_SRC_CON1 = Afe_Get_Reg(AFE_ADDA_UL_SRC_CON1);
3764 mAudioRegCache.REG_AFE_ADDA_TOP_CON0 = Afe_Get_Reg(AFE_ADDA_TOP_CON0);
3765 mAudioRegCache.REG_AFE_ADDA_UL_DL_CON0 = Afe_Get_Reg(AFE_ADDA_UL_DL_CON0);
3766
3767 mAudioRegCache.REG_AFE_ADDA_NEWIF_CFG0 = Afe_Get_Reg(AFE_ADDA_NEWIF_CFG0);
3768 mAudioRegCache.REG_AFE_ADDA_NEWIF_CFG1 = Afe_Get_Reg(AFE_ADDA_NEWIF_CFG1);
3769
3770 mAudioRegCache.REG_AFE_SIDETONE_CON0 = Afe_Get_Reg(AFE_SIDETONE_CON0);
3771 mAudioRegCache.REG_AFE_SIDETONE_COEFF = Afe_Get_Reg(AFE_SIDETONE_COEFF);
3772 mAudioRegCache.REG_AFE_SIDETONE_CON1 = Afe_Get_Reg(AFE_SIDETONE_CON1);
3773 mAudioRegCache.REG_AFE_SIDETONE_GAIN = Afe_Get_Reg(AFE_SIDETONE_GAIN);
3774 mAudioRegCache.REG_AFE_SGEN_CON0 = Afe_Get_Reg(AFE_SGEN_CON0);
3775 mAudioRegCache.REG_AFE_SGEN_CON1 = Afe_Get_Reg(AFE_SGEN_CON1);
3776 mAudioRegCache.REG_AFE_TOP_CON0 = Afe_Get_Reg(AFE_TOP_CON0);
3777 mAudioRegCache.REG_AFE_ADDA_PREDIS_CON0 = Afe_Get_Reg(AFE_ADDA_PREDIS_CON0);
3778 mAudioRegCache.REG_AFE_ADDA_PREDIS_CON1 = Afe_Get_Reg(AFE_ADDA_PREDIS_CON1);
3779
3780 mAudioRegCache.REG_AFE_MOD_DAI_BASE = Afe_Get_Reg(AFE_MOD_DAI_BASE);
3781 mAudioRegCache.REG_AFE_MOD_DAI_END = Afe_Get_Reg(AFE_MOD_DAI_END);
3782 mAudioRegCache.REG_AFE_MOD_DAI_CUR = Afe_Get_Reg(AFE_MOD_DAI_CUR);
3783 mAudioRegCache.REG_AFE_HDMI_OUT_CON0 = Afe_Get_Reg(AFE_HDMI_OUT_CON0);
3784 mAudioRegCache.REG_AFE_HDMI_BASE = Afe_Get_Reg(AFE_HDMI_BASE);
3785 mAudioRegCache.REG_AFE_HDMI_CUR = Afe_Get_Reg(AFE_HDMI_CUR);
3786 mAudioRegCache.REG_AFE_HDMI_END = Afe_Get_Reg(AFE_HDMI_END);
3787 mAudioRegCache.REG_AFE_HDMI_CONN0 = Afe_Get_Reg(AFE_HDMI_CONN0);
3788 mAudioRegCache.REG_AFE_IRQ_MCU_CON = Afe_Get_Reg(AFE_IRQ_MCU_CON);
3789 mAudioRegCache.REG_AFE_IRQ_MCU_CNT1 = Afe_Get_Reg(AFE_IRQ_MCU_CNT1);
3790 mAudioRegCache.REG_AFE_IRQ_MCU_CNT2 = Afe_Get_Reg(AFE_IRQ_MCU_CNT2);
3791 mAudioRegCache.REG_AFE_IRQ_MCU_EN = Afe_Get_Reg(AFE_IRQ_MCU_EN);
3792 mAudioRegCache.REG_AFE_MEMIF_MAXLEN = Afe_Get_Reg(AFE_MEMIF_MAXLEN);
3793 mAudioRegCache.REG_AFE_MEMIF_PBUF_SIZE = Afe_Get_Reg(AFE_MEMIF_PBUF_SIZE);
3794 mAudioRegCache.REG_AFE_APLL1_TUNER_CFG = Afe_Get_Reg(AFE_APLL1_TUNER_CFG);
3795 mAudioRegCache.REG_AFE_APLL2_TUNER_CFG = Afe_Get_Reg(AFE_APLL2_TUNER_CFG);
3796 mAudioRegCache.REG_AFE_GAIN1_CON0 = Afe_Get_Reg(AFE_GAIN1_CON0);
3797 mAudioRegCache.REG_AFE_GAIN1_CON1 = Afe_Get_Reg(AFE_GAIN1_CON1);
3798 mAudioRegCache.REG_AFE_GAIN1_CON2 = Afe_Get_Reg(AFE_GAIN1_CON2);
3799 mAudioRegCache.REG_AFE_GAIN1_CON3 = Afe_Get_Reg(AFE_GAIN1_CON3);
3800 mAudioRegCache.REG_AFE_GAIN1_CONN = Afe_Get_Reg(AFE_GAIN1_CONN);
3801 mAudioRegCache.REG_AFE_GAIN1_CUR = Afe_Get_Reg(AFE_GAIN1_CUR);
3802 mAudioRegCache.REG_AFE_GAIN2_CON0 = Afe_Get_Reg(AFE_GAIN1_CON0);
3803 mAudioRegCache.REG_AFE_GAIN2_CON1 = Afe_Get_Reg(AFE_GAIN1_CON1);
3804 mAudioRegCache.REG_AFE_GAIN2_CON2 = Afe_Get_Reg(AFE_GAIN1_CON2);
3805 mAudioRegCache.REG_AFE_GAIN2_CON3 = Afe_Get_Reg(AFE_GAIN1_CON3);
3806 mAudioRegCache.REG_AFE_GAIN2_CONN = Afe_Get_Reg(AFE_GAIN1_CONN);
3807 mAudioRegCache.REG_AFE_GAIN2_CUR = Afe_Get_Reg(AFE_GAIN2_CUR);
3808 mAudioRegCache.REG_AFE_GAIN2_CONN2 = Afe_Get_Reg(AFE_GAIN2_CONN2);
3809 mAudioRegCache.REG_AFE_GAIN2_CONN3 = Afe_Get_Reg(AFE_GAIN2_CONN3);
3810 mAudioRegCache.REG_AFE_GAIN1_CONN2 = Afe_Get_Reg(AFE_GAIN1_CONN2);
3811 mAudioRegCache.REG_AFE_GAIN1_CONN3 = Afe_Get_Reg(AFE_GAIN1_CONN3);
3812 mAudioRegCache.REG_AFE_CONN7 = Afe_Get_Reg(AFE_CONN7);
3813 mAudioRegCache.REG_AFE_CONN8 = Afe_Get_Reg(AFE_CONN8);
3814 mAudioRegCache.REG_AFE_CONN9 = Afe_Get_Reg(AFE_CONN9);
3815 mAudioRegCache.REG_FPGA_CFG2 = Afe_Get_Reg(FPGA_CFG2);
3816 mAudioRegCache.REG_FPGA_CFG3 = Afe_Get_Reg(FPGA_CFG3);
3817 mAudioRegCache.REG_FPGA_CFG0 = Afe_Get_Reg(FPGA_CFG0);
3818 mAudioRegCache.REG_FPGA_CFG1 = Afe_Get_Reg(FPGA_CFG1);
3819
3820 mAudioRegCache.REG_AFE_ASRC_CON0 = Afe_Get_Reg(AFE_ASRC_CON0);
3821 mAudioRegCache.REG_AFE_ASRC_CON1 = Afe_Get_Reg(AFE_ASRC_CON1);
3822 mAudioRegCache.REG_AFE_ASRC_CON2 = Afe_Get_Reg(AFE_ASRC_CON2);
3823 mAudioRegCache.REG_AFE_ASRC_CON3 = Afe_Get_Reg(AFE_ASRC_CON3);
3824 mAudioRegCache.REG_AFE_ASRC_CON4 = Afe_Get_Reg(AFE_ASRC_CON4);
3825 mAudioRegCache.REG_AFE_ASRC_CON5 = Afe_Get_Reg(AFE_ASRC_CON5);
3826 mAudioRegCache.REG_AFE_ASRC_CON6 = Afe_Get_Reg(AFE_ASRC_CON6);
3827 mAudioRegCache.REG_AFE_ASRC_CON7 = Afe_Get_Reg(AFE_ASRC_CON7);
3828 mAudioRegCache.REG_AFE_ASRC_CON8 = Afe_Get_Reg(AFE_ASRC_CON8);
3829 mAudioRegCache.REG_AFE_ASRC_CON9 = Afe_Get_Reg(AFE_ASRC_CON9);
3830 mAudioRegCache.REG_AFE_ASRC_CON10 = Afe_Get_Reg(AFE_ASRC_CON10);
3831 mAudioRegCache.REG_AFE_ASRC_CON11 = Afe_Get_Reg(AFE_ASRC_CON11);
3832 mAudioRegCache.REG_PCM_INTF_CON = Afe_Get_Reg(PCM_INTF_CON);
3833 mAudioRegCache.REG_PCM_INTF_CON2 = Afe_Get_Reg(PCM_INTF_CON2);
3834 mAudioRegCache.REG_PCM2_INTF_CON = Afe_Get_Reg(PCM2_INTF_CON);
3835 mAudioRegCache.REG_AFE_TDM_CON1 = Afe_Get_Reg(AFE_TDM_CON1);
3836 mAudioRegCache.REG_AFE_TDM_CON2 = Afe_Get_Reg(AFE_TDM_CON2);
3837 mAudioRegCache.REG_AFE_ASRC_CON13 = Afe_Get_Reg(AFE_ASRC_CON13);
3838 mAudioRegCache.REG_AFE_ASRC_CON14 = Afe_Get_Reg(AFE_ASRC_CON14);
3839 mAudioRegCache.REG_AFE_ASRC_CON15 = Afe_Get_Reg(AFE_ASRC_CON15);
3840 mAudioRegCache.REG_AFE_ASRC_CON16 = Afe_Get_Reg(AFE_ASRC_CON16);
3841 mAudioRegCache.REG_AFE_ASRC_CON17 = Afe_Get_Reg(AFE_ASRC_CON17);
3842 mAudioRegCache.REG_AFE_ASRC_CON18 = Afe_Get_Reg(AFE_ASRC_CON18);
3843 mAudioRegCache.REG_AFE_ASRC_CON19 = Afe_Get_Reg(AFE_ASRC_CON19);
3844 mAudioRegCache.REG_AFE_ASRC_CON20 = Afe_Get_Reg(AFE_ASRC_CON20);
3845 mAudioRegCache.REG_AFE_ASRC_CON21 = Afe_Get_Reg(AFE_ASRC_CON21);
3846 mAudioRegCache.REG_AFE_ADDA2_TOP_CON0 = Afe_Get_Reg(AFE_ADDA2_TOP_CON0);
3847 mAudioRegCache.REG_AFE_ADDA2_UL_SRC_CON0 = Afe_Get_Reg(AFE_ADDA2_UL_SRC_CON0);
3848 mAudioRegCache.REG_AFE_ADDA2_UL_SRC_CON1 = Afe_Get_Reg(AFE_ADDA2_UL_SRC_CON1);
3849
3850 mAudioRegCache.REG_AFE_ADDA2_NEWIF_CFG0 = Afe_Get_Reg(AFE_ADDA2_NEWIF_CFG0);
3851 mAudioRegCache.REG_AFE_ADDA2_NEWIF_CFG1 = Afe_Get_Reg(AFE_ADDA2_NEWIF_CFG1);
3852 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_02_01 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_02_01);
3853 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_04_03 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_04_03);
3854 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_06_05 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_06_05);
3855 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_08_07 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_08_07);
3856 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_10_09 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_10_09);
3857 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_12_11 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_12_11);
3858 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_14_13 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_14_13);
3859 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_16_15 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_16_15);
3860 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_18_17 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_18_17);
3861 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_20_19 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_20_19);
3862 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_22_21 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_22_21);
3863 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_24_23 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_24_23);
3864 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_26_25 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_26_25);
3865 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_28_27 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_28_27);
3866 mAudioRegCache.REG_AFE_ADDA2_ULCF_CFG_30_29 = Afe_Get_Reg(AFE_ADDA2_ULCF_CFG_30_29);
3867 mAudioRegCache.REG_AFE_ADDA3_UL_SRC_CON0 = Afe_Get_Reg(AFE_ADDA3_UL_SRC_CON0);
3868 mAudioRegCache.REG_AFE_ADDA3_UL_SRC_CON1 = Afe_Get_Reg(AFE_ADDA3_UL_SRC_CON1);
3869 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_02_01 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_02_01);
3870 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_04_03 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_04_03);
3871 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_06_05 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_06_05);
3872 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_08_07 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_08_07);
3873 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_10_09 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_10_09);
3874 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_12_11 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_12_11);
3875 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_14_13 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_14_13);
3876 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_16_15 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_16_15);
3877 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_18_17 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_18_17);
3878 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_20_19 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_20_19);
3879 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_22_21 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_22_21);
3880 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_24_23 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_24_23);
3881 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_26_25 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_26_25);
3882 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_28_27 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_28_27);
3883 mAudioRegCache.REG_AFE_ADDA3_ULCF_CFG_30_29 = Afe_Get_Reg(AFE_ADDA3_ULCF_CFG_30_29);
3884 mAudioRegCache.REG_AFE_ASRC2_CON0 = Afe_Get_Reg(AFE_ASRC2_CON0);
3885 mAudioRegCache.REG_AFE_ASRC2_CON1 = Afe_Get_Reg(AFE_ASRC2_CON1);
3886 mAudioRegCache.REG_AFE_ASRC2_CON2 = Afe_Get_Reg(AFE_ASRC2_CON2);
3887 mAudioRegCache.REG_AFE_ASRC2_CON3 = Afe_Get_Reg(AFE_ASRC2_CON3);
3888 mAudioRegCache.REG_AFE_ASRC2_CON4 = Afe_Get_Reg(AFE_ASRC2_CON4);
3889 mAudioRegCache.REG_AFE_ASRC2_CON5 = Afe_Get_Reg(AFE_ASRC2_CON5);
3890 mAudioRegCache.REG_AFE_ASRC2_CON6 = Afe_Get_Reg(AFE_ASRC2_CON6);
3891 mAudioRegCache.REG_AFE_ASRC2_CON7 = Afe_Get_Reg(AFE_ASRC2_CON7);
3892 mAudioRegCache.REG_AFE_ASRC2_CON8 = Afe_Get_Reg(AFE_ASRC2_CON8);
3893 mAudioRegCache.REG_AFE_ASRC2_CON9 = Afe_Get_Reg(AFE_ASRC2_CON9);
3894 mAudioRegCache.REG_AFE_ASRC2_CON10 = Afe_Get_Reg(AFE_ASRC2_CON10);
3895 mAudioRegCache.REG_AFE_ASRC2_CON11 = Afe_Get_Reg(AFE_ASRC2_CON11);
3896 mAudioRegCache.REG_AFE_ASRC2_CON12 = Afe_Get_Reg(AFE_ASRC2_CON12);
3897 mAudioRegCache.REG_AFE_ASRC2_CON13 = Afe_Get_Reg(AFE_ASRC2_CON13);
3898 mAudioRegCache.REG_AFE_ASRC2_CON14 = Afe_Get_Reg(AFE_ASRC2_CON14);
3899 mAudioRegCache.REG_AFE_ASRC3_CON0 = Afe_Get_Reg(AFE_ASRC3_CON0);
3900 mAudioRegCache.REG_AFE_ASRC3_CON1 = Afe_Get_Reg(AFE_ASRC3_CON1);
3901 mAudioRegCache.REG_AFE_ASRC3_CON2 = Afe_Get_Reg(AFE_ASRC3_CON2);
3902 mAudioRegCache.REG_AFE_ASRC3_CON3 = Afe_Get_Reg(AFE_ASRC3_CON3);
3903 mAudioRegCache.REG_AFE_ASRC3_CON4 = Afe_Get_Reg(AFE_ASRC3_CON4);
3904 mAudioRegCache.REG_AFE_ASRC3_CON5 = Afe_Get_Reg(AFE_ASRC3_CON5);
3905 mAudioRegCache.REG_AFE_ASRC3_CON6 = Afe_Get_Reg(AFE_ASRC3_CON6);
3906 mAudioRegCache.REG_AFE_ASRC3_CON7 = Afe_Get_Reg(AFE_ASRC3_CON7);
3907 mAudioRegCache.REG_AFE_ASRC3_CON8 = Afe_Get_Reg(AFE_ASRC3_CON8);
3908 mAudioRegCache.REG_AFE_ASRC3_CON9 = Afe_Get_Reg(AFE_ASRC3_CON9);
3909 mAudioRegCache.REG_AFE_ASRC3_CON10 = Afe_Get_Reg(AFE_ASRC3_CON10);
3910 mAudioRegCache.REG_AFE_ASRC3_CON11 = Afe_Get_Reg(AFE_ASRC3_CON11);
3911 mAudioRegCache.REG_AFE_ASRC3_CON12 = Afe_Get_Reg(AFE_ASRC3_CON12);
3912 mAudioRegCache.REG_AFE_ASRC3_CON13 = Afe_Get_Reg(AFE_ASRC3_CON13);
3913 mAudioRegCache.REG_AFE_ASRC3_CON14 = Afe_Get_Reg(AFE_ASRC3_CON14);
3914 AudDrv_Clk_Off();
3915 return true;
3916 }
3917
3918
3919 unsigned int Align64ByteSize(unsigned int insize)
3920 {
3921 #define MAGIC_NUMBER 0xFFFFFFC0
3922
3923 unsigned int align_size;
3924 align_size = insize & MAGIC_NUMBER;
3925 return align_size;
3926 }
3927
3928
kernel source for telekom puls (alcatel/mediatek)