sound/soc/fsl/fsl_ssi.c

   1 /*
   2  * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
   3  *
   4  * Author: Timur Tabi <timur@freescale.com>
   5  *
   6  * Copyright 2007-2008 Freescale Semiconductor, Inc.  This file is licensed
   7  * under the terms of the GNU General Public License version 2.  This
   8  * program is licensed "as is" without any warranty of any kind, whether
   9  * express or implied.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/device.h>
  16 #include <linux/delay.h>
  17
  18 #include <sound/core.h>
  19 #include <sound/pcm.h>
  20 #include <sound/pcm_params.h>
  21 #include <sound/initval.h>
  22 #include <sound/soc.h>
  23
  24 #include <asm/immap_86xx.h>
  25
  26 #include "fsl_ssi.h"
  27
  28 /**
  29  * FSLSSI_I2S_RATES: sample rates supported by the I2S
  30  *
  31  * This driver currently only supports the SSI running in I2S slave mode,
  32  * which means the codec determines the sample rate.  Therefore, we tell
  33  * ALSA that we support all rates and let the codec driver decide what rates
  34  * are really supported.
  35  */
  36 #define FSLSSI_I2S_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \
  37                           SNDRV_PCM_RATE_CONTINUOUS)
  38
  39 /**
  40  * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
  41  *
  42  * This driver currently only supports the SSI running in I2S slave mode.
  43  *
  44  * The SSI has a limitation in that the samples must be in the same byte
  45  * order as the host CPU.  This is because when multiple bytes are written
  46  * to the STX register, the bytes and bits must be written in the same
  47  * order.  The STX is a shift register, so all the bits need to be aligned
  48  * (bit-endianness must match byte-endianness).  Processors typically write
  49  * the bits within a byte in the same order that the bytes of a word are
  50  * written in.  So if the host CPU is big-endian, then only big-endian
  51  * samples will be written to STX properly.
  52  */
  53 #ifdef __BIG_ENDIAN
  54 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
  55          SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
  56          SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
  57 #else
  58 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
  59          SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  60          SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
  61 #endif
  62
  63 /**
  64  * fsl_ssi_private: per-SSI private data
  65  *
  66  * @name: short name for this device ("SSI0", "SSI1", etc)
  67  * @ssi: pointer to the SSI's registers
  68  * @ssi_phys: physical address of the SSI registers
  69  * @irq: IRQ of this SSI
  70  * @first_stream: pointer to the stream that was opened first
  71  * @second_stream: pointer to second stream
  72  * @dev: struct device pointer
  73  * @playback: the number of playback streams opened
  74  * @capture: the number of capture streams opened
  75  * @cpu_dai: the CPU DAI for this device
  76  * @dev_attr: the sysfs device attribute structure
  77  * @stats: SSI statistics
  78  */
  79 struct fsl_ssi_private {
  80         char name[8];
  81         struct ccsr_ssi __iomem *ssi;
  82         dma_addr_t ssi_phys;
  83         unsigned int irq;
  84         struct snd_pcm_substream *first_stream;
  85         struct snd_pcm_substream *second_stream;
  86         struct device *dev;
  87         unsigned int playback;
  88         unsigned int capture;
  89         struct snd_soc_dai cpu_dai;
  90         struct device_attribute dev_attr;
  91
  92         struct {
  93                 unsigned int rfrc;
  94                 unsigned int tfrc;
  95                 unsigned int cmdau;
  96                 unsigned int cmddu;
  97                 unsigned int rxt;
  98                 unsigned int rdr1;
  99                 unsigned int rdr0;
 100                 unsigned int tde1;
 101                 unsigned int tde0;
 102                 unsigned int roe1;
 103                 unsigned int roe0;
 104                 unsigned int tue1;
 105                 unsigned int tue0;
 106                 unsigned int tfs;
 107                 unsigned int rfs;
 108                 unsigned int tls;
 109                 unsigned int rls;
 110                 unsigned int rff1;
 111                 unsigned int rff0;
 112                 unsigned int tfe1;
 113                 unsigned int tfe0;
 114         } stats;
 115 };
 116
 117 /**
 118  * fsl_ssi_isr: SSI interrupt handler
 119  *
 120  * Although it's possible to use the interrupt handler to send and receive
 121  * data to/from the SSI, we use the DMA instead.  Programming is more
 122  * complicated, but the performance is much better.
 123  *
 124  * This interrupt handler is used only to gather statistics.
 125  *
 126  * @irq: IRQ of the SSI device
 127  * @dev_id: pointer to the ssi_private structure for this SSI device
 128  */
 129 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
 130 {
 131         struct fsl_ssi_private *ssi_private = dev_id;
 132         struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
 133         irqreturn_t ret = IRQ_NONE;
 134         __be32 sisr;
 135         __be32 sisr2 = 0;
 136
 137         /* We got an interrupt, so read the status register to see what we
 138            were interrupted for.  We mask it with the Interrupt Enable register
 139            so that we only check for events that we're interested in.
 140          */
 141         sisr = in_be32(&ssi->sisr) & in_be32(&ssi->sier);
 142
 143         if (sisr & CCSR_SSI_SISR_RFRC) {
 144                 ssi_private->stats.rfrc++;
 145                 sisr2 |= CCSR_SSI_SISR_RFRC;
 146                 ret = IRQ_HANDLED;
 147         }
 148
 149         if (sisr & CCSR_SSI_SISR_TFRC) {
 150                 ssi_private->stats.tfrc++;
 151                 sisr2 |= CCSR_SSI_SISR_TFRC;
 152                 ret = IRQ_HANDLED;
 153         }
 154
 155         if (sisr & CCSR_SSI_SISR_CMDAU) {
 156                 ssi_private->stats.cmdau++;
 157                 ret = IRQ_HANDLED;
 158         }
 159
 160         if (sisr & CCSR_SSI_SISR_CMDDU) {
 161                 ssi_private->stats.cmddu++;
 162                 ret = IRQ_HANDLED;
 163         }
 164
 165         if (sisr & CCSR_SSI_SISR_RXT) {
 166                 ssi_private->stats.rxt++;
 167                 ret = IRQ_HANDLED;
 168         }
 169
 170         if (sisr & CCSR_SSI_SISR_RDR1) {
 171                 ssi_private->stats.rdr1++;
 172                 ret = IRQ_HANDLED;
 173         }
 174
 175         if (sisr & CCSR_SSI_SISR_RDR0) {
 176                 ssi_private->stats.rdr0++;
 177                 ret = IRQ_HANDLED;
 178         }
 179
 180         if (sisr & CCSR_SSI_SISR_TDE1) {
 181                 ssi_private->stats.tde1++;
 182                 ret = IRQ_HANDLED;
 183         }
 184
 185         if (sisr & CCSR_SSI_SISR_TDE0) {
 186                 ssi_private->stats.tde0++;
 187                 ret = IRQ_HANDLED;
 188         }
 189
 190         if (sisr & CCSR_SSI_SISR_ROE1) {
 191                 ssi_private->stats.roe1++;
 192                 sisr2 |= CCSR_SSI_SISR_ROE1;
 193                 ret = IRQ_HANDLED;
 194         }
 195
 196         if (sisr & CCSR_SSI_SISR_ROE0) {
 197                 ssi_private->stats.roe0++;
 198                 sisr2 |= CCSR_SSI_SISR_ROE0;
 199                 ret = IRQ_HANDLED;
 200         }
 201
 202         if (sisr & CCSR_SSI_SISR_TUE1) {
 203                 ssi_private->stats.tue1++;
 204                 sisr2 |= CCSR_SSI_SISR_TUE1;
 205                 ret = IRQ_HANDLED;
 206         }
 207
 208         if (sisr & CCSR_SSI_SISR_TUE0) {
 209                 ssi_private->stats.tue0++;
 210                 sisr2 |= CCSR_SSI_SISR_TUE0;
 211                 ret = IRQ_HANDLED;
 212         }
 213
 214         if (sisr & CCSR_SSI_SISR_TFS) {
 215                 ssi_private->stats.tfs++;
 216                 ret = IRQ_HANDLED;
 217         }
 218
 219         if (sisr & CCSR_SSI_SISR_RFS) {
 220                 ssi_private->stats.rfs++;
 221                 ret = IRQ_HANDLED;
 222         }
 223
 224         if (sisr & CCSR_SSI_SISR_TLS) {
 225                 ssi_private->stats.tls++;
 226                 ret = IRQ_HANDLED;
 227         }
 228
 229         if (sisr & CCSR_SSI_SISR_RLS) {
 230                 ssi_private->stats.rls++;
 231                 ret = IRQ_HANDLED;
 232         }
 233
 234         if (sisr & CCSR_SSI_SISR_RFF1) {
 235                 ssi_private->stats.rff1++;
 236                 ret = IRQ_HANDLED;
 237         }
 238
 239         if (sisr & CCSR_SSI_SISR_RFF0) {
 240                 ssi_private->stats.rff0++;
 241                 ret = IRQ_HANDLED;
 242         }
 243
 244         if (sisr & CCSR_SSI_SISR_TFE1) {
 245                 ssi_private->stats.tfe1++;
 246                 ret = IRQ_HANDLED;
 247         }
 248
 249         if (sisr & CCSR_SSI_SISR_TFE0) {
 250                 ssi_private->stats.tfe0++;
 251                 ret = IRQ_HANDLED;
 252         }
 253
 254         /* Clear the bits that we set */
 255         if (sisr2)
 256                 out_be32(&ssi->sisr, sisr2);
 257
 258         return ret;
 259 }
 260
 261 /**
 262  * fsl_ssi_startup: create a new substream
 263  *
 264  * This is the first function called when a stream is opened.
 265  *
 266  * If this is the first stream open, then grab the IRQ and program most of
 267  * the SSI registers.
 268  */
 269 static int fsl_ssi_startup(struct snd_pcm_substream *substream)
 270 {
 271         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 272         struct fsl_ssi_private *ssi_private = rtd->dai->cpu_dai->private_data;
 273
 274         /*
 275          * If this is the first stream opened, then request the IRQ
 276          * and initialize the SSI registers.
 277          */
 278         if (!ssi_private->playback && !ssi_private->capture) {
 279                 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
 280                 int ret;
 281
 282                 ret = request_irq(ssi_private->irq, fsl_ssi_isr, 0,
 283                                   ssi_private->name, ssi_private);
 284                 if (ret < 0) {
 285                         dev_err(substream->pcm->card->dev,
 286                                 "could not claim irq %u\n", ssi_private->irq);
 287                         return ret;
 288                 }
 289
 290                 /*
 291                  * Section 16.5 of the MPC8610 reference manual says that the
 292                  * SSI needs to be disabled before updating the registers we set
 293                  * here.
 294                  */
 295                 clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN);
 296
 297                 /*
 298                  * Program the SSI into I2S Slave Non-Network Synchronous mode.
 299                  * Also enable the transmit and receive FIFO.
 300                  *
 301                  * FIXME: Little-endian samples require a different shift dir
 302                  */
 303                 clrsetbits_be32(&ssi->scr, CCSR_SSI_SCR_I2S_MODE_MASK,
 304                         CCSR_SSI_SCR_TFR_CLK_DIS |
 305                         CCSR_SSI_SCR_I2S_MODE_SLAVE | CCSR_SSI_SCR_SYN);
 306
 307                 out_be32(&ssi->stcr,
 308                          CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
 309                          CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS |
 310                          CCSR_SSI_STCR_TSCKP);
 311
 312                 out_be32(&ssi->srcr,
 313                          CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
 314                          CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS |
 315                          CCSR_SSI_SRCR_RSCKP);
 316
 317                 /*
 318                  * The DC and PM bits are only used if the SSI is the clock
 319                  * master.
 320                  */
 321
 322                 /* 4. Enable the interrupts and DMA requests */
 323                 out_be32(&ssi->sier,
 324                          CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE |
 325                          CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN |
 326                          CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN |
 327                          CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE |
 328                          CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN);
 329
 330                 /*
 331                  * Set the watermark for transmit FIFI 0 and receive FIFO 0. We
 332                  * don't use FIFO 1.  Since the SSI only supports stereo, the
 333                  * watermark should never be an odd number.
 334                  */
 335                 out_be32(&ssi->sfcsr,
 336                          CCSR_SSI_SFCSR_TFWM0(6) | CCSR_SSI_SFCSR_RFWM0(2));
 337
 338                 /*
 339                  * We keep the SSI disabled because if we enable it, then the
 340                  * DMA controller will start.  It's not supposed to start until
 341                  * the SCR.TE (or SCR.RE) bit is set, but it does anyway.  The
 342                  * DMA controller will transfer one "BWC" of data (i.e. the
 343                  * amount of data that the MR.BWC bits are set to).  The reason
 344                  * this is bad is because at this point, the PCM driver has not
 345                  * finished initializing the DMA controller.
 346                  */
 347         }
 348
 349         if (!ssi_private->first_stream)
 350                 ssi_private->first_stream = substream;
 351         else {
 352                 /* This is the second stream open, so we need to impose sample
 353                  * rate and maybe sample size constraints.  Note that this can
 354                  * cause a race condition if the second stream is opened before
 355                  * the first stream is fully initialized.
 356                  *
 357                  * We provide some protection by checking to make sure the first
 358                  * stream is initialized, but it's not perfect.  ALSA sometimes
 359                  * re-initializes the driver with a different sample rate or
 360                  * size.  If the second stream is opened before the first stream
 361                  * has received its final parameters, then the second stream may
 362                  * be constrained to the wrong sample rate or size.
 363                  *
 364                  * FIXME: This code does not handle opening and closing streams
 365                  * repeatedly.  If you open two streams and then close the first
 366                  * one, you may not be able to open another stream until you
 367                  * close the second one as well.
 368                  */
 369                 struct snd_pcm_runtime *first_runtime =
 370                         ssi_private->first_stream->runtime;
 371
 372                 if (!first_runtime->rate || !first_runtime->sample_bits) {
 373                         dev_err(substream->pcm->card->dev,
 374                                 "set sample rate and size in %s stream first\n",
 375                                 substream->stream == SNDRV_PCM_STREAM_PLAYBACK
 376                                 ? "capture" : "playback");
 377                         return -EAGAIN;
 378                 }
 379
 380                 snd_pcm_hw_constraint_minmax(substream->runtime,
 381                         SNDRV_PCM_HW_PARAM_RATE,
 382                         first_runtime->rate, first_runtime->rate);
 383
 384                 snd_pcm_hw_constraint_minmax(substream->runtime,
 385                         SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
 386                         first_runtime->sample_bits,
 387                         first_runtime->sample_bits);
 388
 389                 ssi_private->second_stream = substream;
 390         }
 391
 392         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 393                 ssi_private->playback++;
 394
 395         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 396                 ssi_private->capture++;
 397
 398         return 0;
 399 }
 400
 401 /**
 402  * fsl_ssi_prepare: prepare the SSI.
 403  *
 404  * Most of the SSI registers have been programmed in the startup function,
 405  * but the word length must be programmed here.  Unfortunately, programming
 406  * the SxCCR.WL bits requires the SSI to be temporarily disabled.  This can
 407  * cause a problem with supporting simultaneous playback and capture.  If
 408  * the SSI is already playing a stream, then that stream may be temporarily
 409  * stopped when you start capture.
 410  *
 411  * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
 412  * clock master.
 413  */
 414 static int fsl_ssi_prepare(struct snd_pcm_substream *substream)
 415 {
 416         struct snd_pcm_runtime *runtime = substream->runtime;
 417         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 418         struct fsl_ssi_private *ssi_private = rtd->dai->cpu_dai->private_data;
 419
 420         struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
 421
 422         if (substream == ssi_private->first_stream) {
 423                 u32 wl;
 424
 425                 /* The SSI should always be disabled at this points (SSIEN=0) */
 426                 wl = CCSR_SSI_SxCCR_WL(snd_pcm_format_width(runtime->format));
 427
 428                 /* In synchronous mode, the SSI uses STCCR for capture */
 429                 clrsetbits_be32(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
 430         }
 431
 432         return 0;
 433 }
 434
 435 /**
 436  * fsl_ssi_trigger: start and stop the DMA transfer.
 437  *
 438  * This function is called by ALSA to start, stop, pause, and resume the DMA
 439  * transfer of data.
 440  *
 441  * The DMA channel is in external master start and pause mode, which
 442  * means the SSI completely controls the flow of data.
 443  */
 444 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd)
 445 {
 446         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 447         struct fsl_ssi_private *ssi_private = rtd->dai->cpu_dai->private_data;
 448         struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
 449
 450         switch (cmd) {
 451         case SNDRV_PCM_TRIGGER_START:
 452         case SNDRV_PCM_TRIGGER_RESUME:
 453         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 454                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 455                         clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN);
 456                         setbits32(&ssi->scr,
 457                                 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE);
 458                 } else {
 459                         clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN);
 460                         setbits32(&ssi->scr,
 461                                 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE);
 462
 463                         /*
 464                          * I think we need this delay to allow time for the SSI
 465                          * to put data into its FIFO.  Without it, ALSA starts
 466                          * to complain about overruns.
 467                          */
 468                         mdelay(1);
 469                 }
 470                 break;
 471
 472         case SNDRV_PCM_TRIGGER_STOP:
 473         case SNDRV_PCM_TRIGGER_SUSPEND:
 474         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 475                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 476                         clrbits32(&ssi->scr, CCSR_SSI_SCR_TE);
 477                 else
 478                         clrbits32(&ssi->scr, CCSR_SSI_SCR_RE);
 479                 break;
 480
 481         default:
 482                 return -EINVAL;
 483         }
 484
 485         return 0;
 486 }
 487
 488 /**
 489  * fsl_ssi_shutdown: shutdown the SSI
 490  *
 491  * Shutdown the SSI if there are no other substreams open.
 492  */
 493 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream)
 494 {
 495         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 496         struct fsl_ssi_private *ssi_private = rtd->dai->cpu_dai->private_data;
 497
 498         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 499                 ssi_private->playback--;
 500
 501         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 502                 ssi_private->capture--;
 503
 504         if (ssi_private->first_stream == substream)
 505                 ssi_private->first_stream = ssi_private->second_stream;
 506
 507         ssi_private->second_stream = NULL;
 508
 509         /*
 510          * If this is the last active substream, disable the SSI and release
 511          * the IRQ.
 512          */
 513         if (!ssi_private->playback && !ssi_private->capture) {
 514                 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
 515
 516                 clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN);
 517
 518                 free_irq(ssi_private->irq, ssi_private);
 519         }
 520 }
 521
 522 /**
 523  * fsl_ssi_set_sysclk: set the clock frequency and direction
 524  *
 525  * This function is called by the machine driver to tell us what the clock
 526  * frequency and direction are.
 527  *
 528  * Currently, we only support operating as a clock slave (SND_SOC_CLOCK_IN),
 529  * and we don't care about the frequency.  Return an error if the direction
 530  * is not SND_SOC_CLOCK_IN.
 531  *
 532  * @clk_id: reserved, should be zero
 533  * @freq: the frequency of the given clock ID, currently ignored
 534  * @dir: SND_SOC_CLOCK_IN (clock slave) or SND_SOC_CLOCK_OUT (clock master)
 535  */
 536 static int fsl_ssi_set_sysclk(struct snd_soc_dai *cpu_dai,
 537                               int clk_id, unsigned int freq, int dir)
 538 {
 539
 540         return (dir == SND_SOC_CLOCK_IN) ? 0 : -EINVAL;
 541 }
 542
 543 /**
 544  * fsl_ssi_set_fmt: set the serial format.
 545  *
 546  * This function is called by the machine driver to tell us what serial
 547  * format to use.
 548  *
 549  * Currently, we only support I2S mode.  Return an error if the format is
 550  * not SND_SOC_DAIFMT_I2S.
 551  *
 552  * @format: one of SND_SOC_DAIFMT_xxx
 553  */
 554 static int fsl_ssi_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int format)
 555 {
 556         return (format == SND_SOC_DAIFMT_I2S) ? 0 : -EINVAL;
 557 }
 558
 559 /**
 560  * fsl_ssi_dai_template: template CPU DAI for the SSI
 561  */
 562 static struct snd_soc_dai fsl_ssi_dai_template = {
 563         .playback = {
 564                 /* The SSI does not support monaural audio. */
 565                 .channels_min = 2,
 566                 .channels_max = 2,
 567                 .rates = FSLSSI_I2S_RATES,
 568                 .formats = FSLSSI_I2S_FORMATS,
 569         },
 570         .capture = {
 571                 .channels_min = 2,
 572                 .channels_max = 2,
 573                 .rates = FSLSSI_I2S_RATES,
 574                 .formats = FSLSSI_I2S_FORMATS,
 575         },
 576         .ops = {
 577                 .startup = fsl_ssi_startup,
 578                 .prepare = fsl_ssi_prepare,
 579                 .shutdown = fsl_ssi_shutdown,
 580                 .trigger = fsl_ssi_trigger,
 581         },
 582         .dai_ops = {
 583                 .set_sysclk = fsl_ssi_set_sysclk,
 584                 .set_fmt = fsl_ssi_set_fmt,
 585         },
 586 };
 587
 588 /**
 589  * fsl_sysfs_ssi_show: display SSI statistics
 590  *
 591  * Display the statistics for the current SSI device.
 592  */
 593 static ssize_t fsl_sysfs_ssi_show(struct device *dev,
 594         struct device_attribute *attr, char *buf)
 595 {
 596         struct fsl_ssi_private *ssi_private =
 597         container_of(attr, struct fsl_ssi_private, dev_attr);
 598         ssize_t length;
 599
 600         length = sprintf(buf, "rfrc=%u", ssi_private->stats.rfrc);
 601         length += sprintf(buf + length, "\ttfrc=%u", ssi_private->stats.tfrc);
 602         length += sprintf(buf + length, "\tcmdau=%u", ssi_private->stats.cmdau);
 603         length += sprintf(buf + length, "\tcmddu=%u", ssi_private->stats.cmddu);
 604         length += sprintf(buf + length, "\trxt=%u", ssi_private->stats.rxt);
 605         length += sprintf(buf + length, "\trdr1=%u", ssi_private->stats.rdr1);
 606         length += sprintf(buf + length, "\trdr0=%u", ssi_private->stats.rdr0);
 607         length += sprintf(buf + length, "\ttde1=%u", ssi_private->stats.tde1);
 608         length += sprintf(buf + length, "\ttde0=%u", ssi_private->stats.tde0);
 609         length += sprintf(buf + length, "\troe1=%u", ssi_private->stats.roe1);
 610         length += sprintf(buf + length, "\troe0=%u", ssi_private->stats.roe0);
 611         length += sprintf(buf + length, "\ttue1=%u", ssi_private->stats.tue1);
 612         length += sprintf(buf + length, "\ttue0=%u", ssi_private->stats.tue0);
 613         length += sprintf(buf + length, "\ttfs=%u", ssi_private->stats.tfs);
 614         length += sprintf(buf + length, "\trfs=%u", ssi_private->stats.rfs);
 615         length += sprintf(buf + length, "\ttls=%u", ssi_private->stats.tls);
 616         length += sprintf(buf + length, "\trls=%u", ssi_private->stats.rls);
 617         length += sprintf(buf + length, "\trff1=%u", ssi_private->stats.rff1);
 618         length += sprintf(buf + length, "\trff0=%u", ssi_private->stats.rff0);
 619         length += sprintf(buf + length, "\ttfe1=%u", ssi_private->stats.tfe1);
 620         length += sprintf(buf + length, "\ttfe0=%u\n", ssi_private->stats.tfe0);
 621
 622         return length;
 623 }
 624
 625 /**
 626  * fsl_ssi_create_dai: create a snd_soc_dai structure
 627  *
 628  * This function is called by the machine driver to create a snd_soc_dai
 629  * structure.  The function creates an ssi_private object, which contains
 630  * the snd_soc_dai.  It also creates the sysfs statistics device.
 631  */
 632 struct snd_soc_dai *fsl_ssi_create_dai(struct fsl_ssi_info *ssi_info)
 633 {
 634         struct snd_soc_dai *fsl_ssi_dai;
 635         struct fsl_ssi_private *ssi_private;
 636         int ret = 0;
 637         struct device_attribute *dev_attr;
 638
 639         ssi_private = kzalloc(sizeof(struct fsl_ssi_private), GFP_KERNEL);
 640         if (!ssi_private) {
 641                 dev_err(ssi_info->dev, "could not allocate DAI object\n");
 642                 return NULL;
 643         }
 644         memcpy(&ssi_private->cpu_dai, &fsl_ssi_dai_template,
 645                sizeof(struct snd_soc_dai));
 646
 647         fsl_ssi_dai = &ssi_private->cpu_dai;
 648         dev_attr = &ssi_private->dev_attr;
 649
 650         sprintf(ssi_private->name, "ssi%u", (u8) ssi_info->id);
 651         ssi_private->ssi = ssi_info->ssi;
 652         ssi_private->ssi_phys = ssi_info->ssi_phys;
 653         ssi_private->irq = ssi_info->irq;
 654         ssi_private->dev = ssi_info->dev;
 655
 656         ssi_private->dev->driver_data = fsl_ssi_dai;
 657
 658         /* Initialize the the device_attribute structure */
 659         dev_attr->attr.name = "ssi-stats";
 660         dev_attr->attr.mode = S_IRUGO;
 661         dev_attr->show = fsl_sysfs_ssi_show;
 662
 663         ret = device_create_file(ssi_private->dev, dev_attr);
 664         if (ret) {
 665                 dev_err(ssi_info->dev, "could not create sysfs %s file\n",
 666                         ssi_private->dev_attr.attr.name);
 667                 kfree(fsl_ssi_dai);
 668                 return NULL;
 669         }
 670
 671         fsl_ssi_dai->private_data = ssi_private;
 672         fsl_ssi_dai->name = ssi_private->name;
 673         fsl_ssi_dai->id = ssi_info->id;
 674
 675         return fsl_ssi_dai;
 676 }
 677 EXPORT_SYMBOL_GPL(fsl_ssi_create_dai);
 678
 679 /**
 680  * fsl_ssi_destroy_dai: destroy the snd_soc_dai object
 681  *
 682  * This function undoes the operations of fsl_ssi_create_dai()
 683  */
 684 void fsl_ssi_destroy_dai(struct snd_soc_dai *fsl_ssi_dai)
 685 {
 686         struct fsl_ssi_private *ssi_private =
 687         container_of(fsl_ssi_dai, struct fsl_ssi_private, cpu_dai);
 688
 689         device_remove_file(ssi_private->dev, &ssi_private->dev_attr);
 690
 691         kfree(ssi_private);
 692 }
 693 EXPORT_SYMBOL_GPL(fsl_ssi_destroy_dai);
 694
 695 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
 696 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
 697 MODULE_LICENSE("GPL");