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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / davinci / davinci-i2s.c
1 /*
2 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/device.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/io.h>
18 #include <linux/clk.h>
19
20 #include <sound/core.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/initval.h>
24 #include <sound/soc.h>
25
26 #include <mach/asp.h>
27
28 #include "davinci-pcm.h"
29 #include "davinci-i2s.h"
30
31
32 /*
33 * NOTE: terminology here is confusing.
34 *
35 * - This driver supports the "Audio Serial Port" (ASP),
36 * found on dm6446, dm355, and other DaVinci chips.
37 *
38 * - But it labels it a "Multi-channel Buffered Serial Port"
39 * (McBSP) as on older chips like the dm642 ... which was
40 * backward-compatible, possibly explaining that confusion.
41 *
42 * - OMAP chips have a controller called McBSP, which is
43 * incompatible with the DaVinci flavor of McBSP.
44 *
45 * - Newer DaVinci chips have a controller called McASP,
46 * incompatible with ASP and with either McBSP.
47 *
48 * In short: this uses ASP to implement I2S, not McBSP.
49 * And it won't be the only DaVinci implemention of I2S.
50 */
51 #define DAVINCI_MCBSP_DRR_REG 0x00
52 #define DAVINCI_MCBSP_DXR_REG 0x04
53 #define DAVINCI_MCBSP_SPCR_REG 0x08
54 #define DAVINCI_MCBSP_RCR_REG 0x0c
55 #define DAVINCI_MCBSP_XCR_REG 0x10
56 #define DAVINCI_MCBSP_SRGR_REG 0x14
57 #define DAVINCI_MCBSP_PCR_REG 0x24
58
59 #define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
60 #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
61 #define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
62 #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
63 #define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
64 #define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
65 #define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
66
67 #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
68 #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
69 #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
70 #define DAVINCI_MCBSP_RCR_RFIG (1 << 18)
71 #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
72 #define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24)
73 #define DAVINCI_MCBSP_RCR_RPHASE BIT(31)
74
75 #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
76 #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
77 #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
78 #define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
79 #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
80 #define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24)
81 #define DAVINCI_MCBSP_XCR_XPHASE BIT(31)
82
83 #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
84 #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
85 #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
86 #define DAVINCI_MCBSP_SRGR_CLKSM BIT(29)
87
88 #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
89 #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
90 #define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
91 #define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
92 #define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
93 #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
94 #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
95 #define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
96 #define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
97
98 enum {
99 DAVINCI_MCBSP_WORD_8 = 0,
100 DAVINCI_MCBSP_WORD_12,
101 DAVINCI_MCBSP_WORD_16,
102 DAVINCI_MCBSP_WORD_20,
103 DAVINCI_MCBSP_WORD_24,
104 DAVINCI_MCBSP_WORD_32,
105 };
106
107 static const unsigned char data_type[SNDRV_PCM_FORMAT_S32_LE + 1] = {
108 [SNDRV_PCM_FORMAT_S8] = 1,
109 [SNDRV_PCM_FORMAT_S16_LE] = 2,
110 [SNDRV_PCM_FORMAT_S32_LE] = 4,
111 };
112
113 static const unsigned char asp_word_length[SNDRV_PCM_FORMAT_S32_LE + 1] = {
114 [SNDRV_PCM_FORMAT_S8] = DAVINCI_MCBSP_WORD_8,
115 [SNDRV_PCM_FORMAT_S16_LE] = DAVINCI_MCBSP_WORD_16,
116 [SNDRV_PCM_FORMAT_S32_LE] = DAVINCI_MCBSP_WORD_32,
117 };
118
119 static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = {
120 [SNDRV_PCM_FORMAT_S8] = SNDRV_PCM_FORMAT_S16_LE,
121 [SNDRV_PCM_FORMAT_S16_LE] = SNDRV_PCM_FORMAT_S32_LE,
122 };
123
124 struct davinci_mcbsp_dev {
125 struct device *dev;
126 struct davinci_pcm_dma_params dma_params[2];
127 void __iomem *base;
128 #define MOD_DSP_A 0
129 #define MOD_DSP_B 1
130 int mode;
131 u32 pcr;
132 struct clk *clk;
133 /*
134 * Combining both channels into 1 element will at least double the
135 * amount of time between servicing the dma channel, increase
136 * effiency, and reduce the chance of overrun/underrun. But,
137 * it will result in the left & right channels being swapped.
138 *
139 * If relabeling the left and right channels is not possible,
140 * you may want to let the codec know to swap them back.
141 *
142 * It may allow x10 the amount of time to service dma requests,
143 * if the codec is master and is using an unnecessarily fast bit clock
144 * (ie. tlvaic23b), independent of the sample rate. So, having an
145 * entire frame at once means it can be serviced at the sample rate
146 * instead of the bit clock rate.
147 *
148 * In the now unlikely case that an underrun still
149 * occurs, both the left and right samples will be repeated
150 * so that no pops are heard, and the left and right channels
151 * won't end up being swapped because of the underrun.
152 */
153 unsigned enable_channel_combine:1;
154
155 unsigned int fmt;
156 int clk_div;
157 int clk_input_pin;
158 bool i2s_accurate_sck;
159 };
160
161 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
162 int reg, u32 val)
163 {
164 __raw_writel(val, dev->base + reg);
165 }
166
167 static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
168 {
169 return __raw_readl(dev->base + reg);
170 }
171
172 static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
173 {
174 u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
175 /* The clock needs to toggle to complete reset.
176 * So, fake it by toggling the clk polarity.
177 */
178 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
179 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
180 }
181
182 static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
183 struct snd_pcm_substream *substream)
184 {
185 struct snd_soc_pcm_runtime *rtd = substream->private_data;
186 struct snd_soc_platform *platform = rtd->platform;
187 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
188 u32 spcr;
189 u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
190 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
191 if (spcr & mask) {
192 /* start off disabled */
193 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
194 spcr & ~mask);
195 toggle_clock(dev, playback);
196 }
197 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
198 DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
199 /* Start the sample generator */
200 spcr |= DAVINCI_MCBSP_SPCR_GRST;
201 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
202 }
203
204 if (playback) {
205 /* Stop the DMA to avoid data loss */
206 /* while the transmitter is out of reset to handle XSYNCERR */
207 if (platform->driver->ops->trigger) {
208 int ret = platform->driver->ops->trigger(substream,
209 SNDRV_PCM_TRIGGER_STOP);
210 if (ret < 0)
211 printk(KERN_DEBUG "Playback DMA stop failed\n");
212 }
213
214 /* Enable the transmitter */
215 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
216 spcr |= DAVINCI_MCBSP_SPCR_XRST;
217 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
218
219 /* wait for any unexpected frame sync error to occur */
220 udelay(100);
221
222 /* Disable the transmitter to clear any outstanding XSYNCERR */
223 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
224 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
225 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
226 toggle_clock(dev, playback);
227
228 /* Restart the DMA */
229 if (platform->driver->ops->trigger) {
230 int ret = platform->driver->ops->trigger(substream,
231 SNDRV_PCM_TRIGGER_START);
232 if (ret < 0)
233 printk(KERN_DEBUG "Playback DMA start failed\n");
234 }
235 }
236
237 /* Enable transmitter or receiver */
238 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
239 spcr |= mask;
240
241 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
242 /* Start frame sync */
243 spcr |= DAVINCI_MCBSP_SPCR_FRST;
244 }
245 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
246 }
247
248 static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
249 {
250 u32 spcr;
251
252 /* Reset transmitter/receiver and sample rate/frame sync generators */
253 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
254 spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
255 spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
256 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
257 toggle_clock(dev, playback);
258 }
259
260 #define DEFAULT_BITPERSAMPLE 16
261
262 static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
263 unsigned int fmt)
264 {
265 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
266 unsigned int pcr;
267 unsigned int srgr;
268 /* Attention srgr is updated by hw_params! */
269 srgr = DAVINCI_MCBSP_SRGR_FSGM |
270 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
271 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
272
273 dev->fmt = fmt;
274 /* set master/slave audio interface */
275 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
276 case SND_SOC_DAIFMT_CBS_CFS:
277 /* cpu is master */
278 pcr = DAVINCI_MCBSP_PCR_FSXM |
279 DAVINCI_MCBSP_PCR_FSRM |
280 DAVINCI_MCBSP_PCR_CLKXM |
281 DAVINCI_MCBSP_PCR_CLKRM;
282 break;
283 case SND_SOC_DAIFMT_CBM_CFS:
284 pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
285 /*
286 * Selection of the clock input pin that is the
287 * input for the Sample Rate Generator.
288 * McBSP FSR and FSX are driven by the Sample Rate
289 * Generator.
290 */
291 switch (dev->clk_input_pin) {
292 case MCBSP_CLKS:
293 pcr |= DAVINCI_MCBSP_PCR_CLKXM |
294 DAVINCI_MCBSP_PCR_CLKRM;
295 break;
296 case MCBSP_CLKR:
297 pcr |= DAVINCI_MCBSP_PCR_SCLKME;
298 break;
299 default:
300 dev_err(dev->dev, "bad clk_input_pin\n");
301 return -EINVAL;
302 }
303
304 break;
305 case SND_SOC_DAIFMT_CBM_CFM:
306 /* codec is master */
307 pcr = 0;
308 break;
309 default:
310 printk(KERN_ERR "%s:bad master\n", __func__);
311 return -EINVAL;
312 }
313
314 /* interface format */
315 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
316 case SND_SOC_DAIFMT_I2S:
317 /* Davinci doesn't support TRUE I2S, but some codecs will have
318 * the left and right channels contiguous. This allows
319 * dsp_a mode to be used with an inverted normal frame clk.
320 * If your codec is master and does not have contiguous
321 * channels, then you will have sound on only one channel.
322 * Try using a different mode, or codec as slave.
323 *
324 * The TLV320AIC33 is an example of a codec where this works.
325 * It has a variable bit clock frequency allowing it to have
326 * valid data on every bit clock.
327 *
328 * The TLV320AIC23 is an example of a codec where this does not
329 * work. It has a fixed bit clock frequency with progressively
330 * more empty bit clock slots between channels as the sample
331 * rate is lowered.
332 */
333 fmt ^= SND_SOC_DAIFMT_NB_IF;
334 case SND_SOC_DAIFMT_DSP_A:
335 dev->mode = MOD_DSP_A;
336 break;
337 case SND_SOC_DAIFMT_DSP_B:
338 dev->mode = MOD_DSP_B;
339 break;
340 default:
341 printk(KERN_ERR "%s:bad format\n", __func__);
342 return -EINVAL;
343 }
344
345 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
346 case SND_SOC_DAIFMT_NB_NF:
347 /* CLKRP Receive clock polarity,
348 * 1 - sampled on rising edge of CLKR
349 * valid on rising edge
350 * CLKXP Transmit clock polarity,
351 * 1 - clocked on falling edge of CLKX
352 * valid on rising edge
353 * FSRP Receive frame sync pol, 0 - active high
354 * FSXP Transmit frame sync pol, 0 - active high
355 */
356 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
357 break;
358 case SND_SOC_DAIFMT_IB_IF:
359 /* CLKRP Receive clock polarity,
360 * 0 - sampled on falling edge of CLKR
361 * valid on falling edge
362 * CLKXP Transmit clock polarity,
363 * 0 - clocked on rising edge of CLKX
364 * valid on falling edge
365 * FSRP Receive frame sync pol, 1 - active low
366 * FSXP Transmit frame sync pol, 1 - active low
367 */
368 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
369 break;
370 case SND_SOC_DAIFMT_NB_IF:
371 /* CLKRP Receive clock polarity,
372 * 1 - sampled on rising edge of CLKR
373 * valid on rising edge
374 * CLKXP Transmit clock polarity,
375 * 1 - clocked on falling edge of CLKX
376 * valid on rising edge
377 * FSRP Receive frame sync pol, 1 - active low
378 * FSXP Transmit frame sync pol, 1 - active low
379 */
380 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
381 DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
382 break;
383 case SND_SOC_DAIFMT_IB_NF:
384 /* CLKRP Receive clock polarity,
385 * 0 - sampled on falling edge of CLKR
386 * valid on falling edge
387 * CLKXP Transmit clock polarity,
388 * 0 - clocked on rising edge of CLKX
389 * valid on falling edge
390 * FSRP Receive frame sync pol, 0 - active high
391 * FSXP Transmit frame sync pol, 0 - active high
392 */
393 break;
394 default:
395 return -EINVAL;
396 }
397 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
398 dev->pcr = pcr;
399 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
400 return 0;
401 }
402
403 static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
404 int div_id, int div)
405 {
406 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
407
408 if (div_id != DAVINCI_MCBSP_CLKGDV)
409 return -ENODEV;
410
411 dev->clk_div = div;
412 return 0;
413 }
414
415 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
416 struct snd_pcm_hw_params *params,
417 struct snd_soc_dai *dai)
418 {
419 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
420 struct davinci_pcm_dma_params *dma_params =
421 &dev->dma_params[substream->stream];
422 struct snd_interval *i = NULL;
423 int mcbsp_word_length, master;
424 unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
425 u32 spcr;
426 snd_pcm_format_t fmt;
427 unsigned element_cnt = 1;
428
429 dai->capture_dma_data = dev->dma_params;
430 dai->playback_dma_data = dev->dma_params;
431
432 /* general line settings */
433 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
434 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
435 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
436 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
437 } else {
438 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
439 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
440 }
441
442 master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
443 fmt = params_format(params);
444 mcbsp_word_length = asp_word_length[fmt];
445
446 switch (master) {
447 case SND_SOC_DAIFMT_CBS_CFS:
448 freq = clk_get_rate(dev->clk);
449 srgr = DAVINCI_MCBSP_SRGR_FSGM |
450 DAVINCI_MCBSP_SRGR_CLKSM;
451 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
452 8 - 1);
453 if (dev->i2s_accurate_sck) {
454 clk_div = 256;
455 do {
456 framesize = (freq / (--clk_div)) /
457 params->rate_num *
458 params->rate_den;
459 } while (((framesize < 33) || (framesize > 4095)) &&
460 (clk_div));
461 clk_div--;
462 srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
463 } else {
464 /* symmetric waveforms */
465 clk_div = freq / (mcbsp_word_length * 16) /
466 params->rate_num * params->rate_den;
467 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
468 16 - 1);
469 }
470 clk_div &= 0xFF;
471 srgr |= clk_div;
472 break;
473 case SND_SOC_DAIFMT_CBM_CFS:
474 srgr = DAVINCI_MCBSP_SRGR_FSGM;
475 clk_div = dev->clk_div - 1;
476 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1);
477 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1);
478 clk_div &= 0xFF;
479 srgr |= clk_div;
480 break;
481 case SND_SOC_DAIFMT_CBM_CFM:
482 /* Clock and frame sync given from external sources */
483 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
484 srgr = DAVINCI_MCBSP_SRGR_FSGM;
485 srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
486 pr_debug("%s - %d FWID set: re-read srgr = %X\n",
487 __func__, __LINE__, snd_interval_value(i) - 1);
488
489 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
490 srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
491 break;
492 default:
493 return -EINVAL;
494 }
495 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
496
497 rcr = DAVINCI_MCBSP_RCR_RFIG;
498 xcr = DAVINCI_MCBSP_XCR_XFIG;
499 if (dev->mode == MOD_DSP_B) {
500 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0);
501 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0);
502 } else {
503 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
504 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
505 }
506 /* Determine xfer data type */
507 fmt = params_format(params);
508 if ((fmt > SNDRV_PCM_FORMAT_S32_LE) || !data_type[fmt]) {
509 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
510 return -EINVAL;
511 }
512
513 if (params_channels(params) == 2) {
514 element_cnt = 2;
515 if (double_fmt[fmt] && dev->enable_channel_combine) {
516 element_cnt = 1;
517 fmt = double_fmt[fmt];
518 }
519 switch (master) {
520 case SND_SOC_DAIFMT_CBS_CFS:
521 case SND_SOC_DAIFMT_CBS_CFM:
522 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0);
523 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0);
524 rcr |= DAVINCI_MCBSP_RCR_RPHASE;
525 xcr |= DAVINCI_MCBSP_XCR_XPHASE;
526 break;
527 case SND_SOC_DAIFMT_CBM_CFM:
528 case SND_SOC_DAIFMT_CBM_CFS:
529 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1);
530 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1);
531 break;
532 default:
533 return -EINVAL;
534 }
535 }
536 dma_params->acnt = dma_params->data_type = data_type[fmt];
537 dma_params->fifo_level = 0;
538 mcbsp_word_length = asp_word_length[fmt];
539
540 switch (master) {
541 case SND_SOC_DAIFMT_CBS_CFS:
542 case SND_SOC_DAIFMT_CBS_CFM:
543 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0);
544 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0);
545 break;
546 case SND_SOC_DAIFMT_CBM_CFM:
547 case SND_SOC_DAIFMT_CBM_CFS:
548 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
549 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
550 break;
551 default:
552 return -EINVAL;
553 }
554
555 rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
556 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
557 xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
558 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
559
560 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
561 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
562 else
563 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
564
565 pr_debug("%s - %d srgr=%X\n", __func__, __LINE__, srgr);
566 pr_debug("%s - %d xcr=%X\n", __func__, __LINE__, xcr);
567 pr_debug("%s - %d rcr=%X\n", __func__, __LINE__, rcr);
568 return 0;
569 }
570
571 static int davinci_i2s_prepare(struct snd_pcm_substream *substream,
572 struct snd_soc_dai *dai)
573 {
574 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
575 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
576 davinci_mcbsp_stop(dev, playback);
577 return 0;
578 }
579
580 static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
581 struct snd_soc_dai *dai)
582 {
583 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
584 int ret = 0;
585 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
586
587 switch (cmd) {
588 case SNDRV_PCM_TRIGGER_START:
589 case SNDRV_PCM_TRIGGER_RESUME:
590 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
591 davinci_mcbsp_start(dev, substream);
592 break;
593 case SNDRV_PCM_TRIGGER_STOP:
594 case SNDRV_PCM_TRIGGER_SUSPEND:
595 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
596 davinci_mcbsp_stop(dev, playback);
597 break;
598 default:
599 ret = -EINVAL;
600 }
601 return ret;
602 }
603
604 static void davinci_i2s_shutdown(struct snd_pcm_substream *substream,
605 struct snd_soc_dai *dai)
606 {
607 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
608 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
609 davinci_mcbsp_stop(dev, playback);
610 }
611
612 #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
613
614 static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
615 .shutdown = davinci_i2s_shutdown,
616 .prepare = davinci_i2s_prepare,
617 .trigger = davinci_i2s_trigger,
618 .hw_params = davinci_i2s_hw_params,
619 .set_fmt = davinci_i2s_set_dai_fmt,
620 .set_clkdiv = davinci_i2s_dai_set_clkdiv,
621
622 };
623
624 static struct snd_soc_dai_driver davinci_i2s_dai = {
625 .playback = {
626 .channels_min = 2,
627 .channels_max = 2,
628 .rates = DAVINCI_I2S_RATES,
629 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
630 .capture = {
631 .channels_min = 2,
632 .channels_max = 2,
633 .rates = DAVINCI_I2S_RATES,
634 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
635 .ops = &davinci_i2s_dai_ops,
636
637 };
638
639 static int davinci_i2s_probe(struct platform_device *pdev)
640 {
641 struct snd_platform_data *pdata = pdev->dev.platform_data;
642 struct davinci_mcbsp_dev *dev;
643 struct resource *mem, *ioarea, *res;
644 enum dma_event_q asp_chan_q = EVENTQ_0;
645 enum dma_event_q ram_chan_q = EVENTQ_1;
646 int ret;
647
648 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
649 if (!mem) {
650 dev_err(&pdev->dev, "no mem resource?\n");
651 return -ENODEV;
652 }
653
654 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
655 pdev->name);
656 if (!ioarea) {
657 dev_err(&pdev->dev, "McBSP region already claimed\n");
658 return -EBUSY;
659 }
660
661 dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
662 if (!dev) {
663 ret = -ENOMEM;
664 goto err_release_region;
665 }
666 if (pdata) {
667 dev->enable_channel_combine = pdata->enable_channel_combine;
668 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].sram_size =
669 pdata->sram_size_playback;
670 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size =
671 pdata->sram_size_capture;
672 dev->clk_input_pin = pdata->clk_input_pin;
673 dev->i2s_accurate_sck = pdata->i2s_accurate_sck;
674 asp_chan_q = pdata->asp_chan_q;
675 ram_chan_q = pdata->ram_chan_q;
676 }
677
678 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].asp_chan_q = asp_chan_q;
679 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].ram_chan_q = ram_chan_q;
680 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].asp_chan_q = asp_chan_q;
681 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].ram_chan_q = ram_chan_q;
682
683 dev->clk = clk_get(&pdev->dev, NULL);
684 if (IS_ERR(dev->clk)) {
685 ret = -ENODEV;
686 goto err_free_mem;
687 }
688 clk_enable(dev->clk);
689
690 dev->base = (void __iomem *)IO_ADDRESS(mem->start);
691
692 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].dma_addr =
693 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
694
695 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].dma_addr =
696 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
697
698 /* first TX, then RX */
699 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
700 if (!res) {
701 dev_err(&pdev->dev, "no DMA resource\n");
702 ret = -ENXIO;
703 goto err_free_mem;
704 }
705 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].channel = res->start;
706
707 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
708 if (!res) {
709 dev_err(&pdev->dev, "no DMA resource\n");
710 ret = -ENXIO;
711 goto err_free_mem;
712 }
713 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].channel = res->start;
714 dev->dev = &pdev->dev;
715
716 dev_set_drvdata(&pdev->dev, dev);
717
718 ret = snd_soc_register_dai(&pdev->dev, &davinci_i2s_dai);
719 if (ret != 0)
720 goto err_free_mem;
721
722 return 0;
723
724 err_free_mem:
725 kfree(dev);
726 err_release_region:
727 release_mem_region(mem->start, (mem->end - mem->start) + 1);
728
729 return ret;
730 }
731
732 static int davinci_i2s_remove(struct platform_device *pdev)
733 {
734 struct davinci_mcbsp_dev *dev = dev_get_drvdata(&pdev->dev);
735 struct resource *mem;
736
737 snd_soc_unregister_dai(&pdev->dev);
738 clk_disable(dev->clk);
739 clk_put(dev->clk);
740 dev->clk = NULL;
741 kfree(dev);
742 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
743 release_mem_region(mem->start, (mem->end - mem->start) + 1);
744
745 return 0;
746 }
747
748 static struct platform_driver davinci_mcbsp_driver = {
749 .probe = davinci_i2s_probe,
750 .remove = davinci_i2s_remove,
751 .driver = {
752 .name = "davinci-i2s",
753 .owner = THIS_MODULE,
754 },
755 };
756
757 static int __init davinci_i2s_init(void)
758 {
759 return platform_driver_register(&davinci_mcbsp_driver);
760 }
761 module_init(davinci_i2s_init);
762
763 static void __exit davinci_i2s_exit(void)
764 {
765 platform_driver_unregister(&davinci_mcbsp_driver);
766 }
767 module_exit(davinci_i2s_exit);
768
769 MODULE_AUTHOR("Vladimir Barinov");
770 MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
771 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)