2 * wm8994.c -- WM8994 ALSA SoC Audio driver
4 * Copyright 2009 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
41 #define WM1811_JACKDET_MODE_NONE 0x0000
42 #define WM1811_JACKDET_MODE_JACK 0x0100
43 #define WM1811_JACKDET_MODE_MIC 0x0080
44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
46 #define WM8994_NUM_DRC 3
47 #define WM8994_NUM_EQ 3
49 static int wm8994_drc_base
[] = {
55 static int wm8994_retune_mobile_base
[] = {
56 WM8994_AIF1_DAC1_EQ_GAINS_1
,
57 WM8994_AIF1_DAC2_EQ_GAINS_1
,
58 WM8994_AIF2_EQ_GAINS_1
,
61 static void wm8958_default_micdet(u16 status
, void *data
);
63 static const struct wm8958_micd_rate micdet_rates
[] = {
64 { 32768, true, 1, 4 },
65 { 32768, false, 1, 1 },
66 { 44100 * 256, true, 7, 10 },
67 { 44100 * 256, false, 7, 10 },
70 static const struct wm8958_micd_rate jackdet_rates
[] = {
71 { 32768, true, 0, 1 },
72 { 32768, false, 0, 1 },
73 { 44100 * 256, true, 7, 10 },
74 { 44100 * 256, false, 7, 10 },
77 static void wm8958_micd_set_rate(struct snd_soc_codec
*codec
)
79 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
80 int best
, i
, sysclk
, val
;
82 const struct wm8958_micd_rate
*rates
;
85 if (wm8994
->jack_cb
!= wm8958_default_micdet
)
88 idle
= !wm8994
->jack_mic
;
90 sysclk
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
91 if (sysclk
& WM8994_SYSCLK_SRC
)
92 sysclk
= wm8994
->aifclk
[1];
94 sysclk
= wm8994
->aifclk
[0];
96 if (wm8994
->pdata
&& wm8994
->pdata
->micd_rates
) {
97 rates
= wm8994
->pdata
->micd_rates
;
98 num_rates
= wm8994
->pdata
->num_micd_rates
;
99 } else if (wm8994
->jackdet
) {
100 rates
= jackdet_rates
;
101 num_rates
= ARRAY_SIZE(jackdet_rates
);
103 rates
= micdet_rates
;
104 num_rates
= ARRAY_SIZE(micdet_rates
);
108 for (i
= 0; i
< num_rates
; i
++) {
109 if (rates
[i
].idle
!= idle
)
111 if (abs(rates
[i
].sysclk
- sysclk
) <
112 abs(rates
[best
].sysclk
- sysclk
))
114 else if (rates
[best
].idle
!= idle
)
118 val
= rates
[best
].start
<< WM8958_MICD_BIAS_STARTTIME_SHIFT
119 | rates
[best
].rate
<< WM8958_MICD_RATE_SHIFT
;
121 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
122 WM8958_MICD_BIAS_STARTTIME_MASK
|
123 WM8958_MICD_RATE_MASK
, val
);
126 static int configure_aif_clock(struct snd_soc_codec
*codec
, int aif
)
128 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
138 switch (wm8994
->sysclk
[aif
]) {
139 case WM8994_SYSCLK_MCLK1
:
140 rate
= wm8994
->mclk
[0];
143 case WM8994_SYSCLK_MCLK2
:
145 rate
= wm8994
->mclk
[1];
148 case WM8994_SYSCLK_FLL1
:
150 rate
= wm8994
->fll
[0].out
;
153 case WM8994_SYSCLK_FLL2
:
155 rate
= wm8994
->fll
[1].out
;
162 if (rate
>= 13500000) {
164 reg1
|= WM8994_AIF1CLK_DIV
;
166 dev_dbg(codec
->dev
, "Dividing AIF%d clock to %dHz\n",
170 wm8994
->aifclk
[aif
] = rate
;
172 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
+ offset
,
173 WM8994_AIF1CLK_SRC_MASK
| WM8994_AIF1CLK_DIV
,
179 static int configure_clock(struct snd_soc_codec
*codec
)
181 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
184 /* Bring up the AIF clocks first */
185 configure_aif_clock(codec
, 0);
186 configure_aif_clock(codec
, 1);
188 /* Then switch CLK_SYS over to the higher of them; a change
189 * can only happen as a result of a clocking change which can
190 * only be made outside of DAPM so we can safely redo the
194 /* If they're equal it doesn't matter which is used */
195 if (wm8994
->aifclk
[0] == wm8994
->aifclk
[1]) {
196 wm8958_micd_set_rate(codec
);
200 if (wm8994
->aifclk
[0] < wm8994
->aifclk
[1])
201 new = WM8994_SYSCLK_SRC
;
205 change
= snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
206 WM8994_SYSCLK_SRC
, new);
208 snd_soc_dapm_sync(&codec
->dapm
);
210 wm8958_micd_set_rate(codec
);
215 static int check_clk_sys(struct snd_soc_dapm_widget
*source
,
216 struct snd_soc_dapm_widget
*sink
)
218 int reg
= snd_soc_read(source
->codec
, WM8994_CLOCKING_1
);
221 /* Check what we're currently using for CLK_SYS */
222 if (reg
& WM8994_SYSCLK_SRC
)
227 return strcmp(source
->name
, clk
) == 0;
230 static const char *sidetone_hpf_text
[] = {
231 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
234 static const struct soc_enum sidetone_hpf
=
235 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 7, 7, sidetone_hpf_text
);
237 static const char *adc_hpf_text
[] = {
238 "HiFi", "Voice 1", "Voice 2", "Voice 3"
241 static const struct soc_enum aif1adc1_hpf
=
242 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS
, 13, 4, adc_hpf_text
);
244 static const struct soc_enum aif1adc2_hpf
=
245 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS
, 13, 4, adc_hpf_text
);
247 static const struct soc_enum aif2adc_hpf
=
248 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS
, 13, 4, adc_hpf_text
);
250 static const DECLARE_TLV_DB_SCALE(aif_tlv
, 0, 600, 0);
251 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
252 static const DECLARE_TLV_DB_SCALE(st_tlv
, -3600, 300, 0);
253 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv
, -1600, 183, 0);
254 static const DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
255 static const DECLARE_TLV_DB_SCALE(ng_tlv
, -10200, 600, 0);
256 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv
, 0, 900, 0);
258 #define WM8994_DRC_SWITCH(xname, reg, shift) \
259 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
260 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
261 .put = wm8994_put_drc_sw, \
262 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
264 static int wm8994_put_drc_sw(struct snd_kcontrol
*kcontrol
,
265 struct snd_ctl_elem_value
*ucontrol
)
267 struct soc_mixer_control
*mc
=
268 (struct soc_mixer_control
*)kcontrol
->private_value
;
269 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
272 /* Can't enable both ADC and DAC paths simultaneously */
273 if (mc
->shift
== WM8994_AIF1DAC1_DRC_ENA_SHIFT
)
274 mask
= WM8994_AIF1ADC1L_DRC_ENA_MASK
|
275 WM8994_AIF1ADC1R_DRC_ENA_MASK
;
277 mask
= WM8994_AIF1DAC1_DRC_ENA_MASK
;
279 ret
= snd_soc_read(codec
, mc
->reg
);
285 return snd_soc_put_volsw(kcontrol
, ucontrol
);
288 static void wm8994_set_drc(struct snd_soc_codec
*codec
, int drc
)
290 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
291 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
292 int base
= wm8994_drc_base
[drc
];
293 int cfg
= wm8994
->drc_cfg
[drc
];
296 /* Save any enables; the configuration should clear them. */
297 save
= snd_soc_read(codec
, base
);
298 save
&= WM8994_AIF1DAC1_DRC_ENA
| WM8994_AIF1ADC1L_DRC_ENA
|
299 WM8994_AIF1ADC1R_DRC_ENA
;
301 for (i
= 0; i
< WM8994_DRC_REGS
; i
++)
302 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
303 pdata
->drc_cfgs
[cfg
].regs
[i
]);
305 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_DRC_ENA
|
306 WM8994_AIF1ADC1L_DRC_ENA
|
307 WM8994_AIF1ADC1R_DRC_ENA
, save
);
310 /* Icky as hell but saves code duplication */
311 static int wm8994_get_drc(const char *name
)
313 if (strcmp(name
, "AIF1DRC1 Mode") == 0)
315 if (strcmp(name
, "AIF1DRC2 Mode") == 0)
317 if (strcmp(name
, "AIF2DRC Mode") == 0)
322 static int wm8994_put_drc_enum(struct snd_kcontrol
*kcontrol
,
323 struct snd_ctl_elem_value
*ucontrol
)
325 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
326 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
327 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
328 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
329 int value
= ucontrol
->value
.integer
.value
[0];
334 if (value
>= pdata
->num_drc_cfgs
)
337 wm8994
->drc_cfg
[drc
] = value
;
339 wm8994_set_drc(codec
, drc
);
344 static int wm8994_get_drc_enum(struct snd_kcontrol
*kcontrol
,
345 struct snd_ctl_elem_value
*ucontrol
)
347 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
348 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
349 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
351 ucontrol
->value
.enumerated
.item
[0] = wm8994
->drc_cfg
[drc
];
356 static void wm8994_set_retune_mobile(struct snd_soc_codec
*codec
, int block
)
358 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
359 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
360 int base
= wm8994_retune_mobile_base
[block
];
361 int iface
, best
, best_val
, save
, i
, cfg
;
363 if (!pdata
|| !wm8994
->num_retune_mobile_texts
)
378 /* Find the version of the currently selected configuration
379 * with the nearest sample rate. */
380 cfg
= wm8994
->retune_mobile_cfg
[block
];
383 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
384 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
385 wm8994
->retune_mobile_texts
[cfg
]) == 0 &&
386 abs(pdata
->retune_mobile_cfgs
[i
].rate
387 - wm8994
->dac_rates
[iface
]) < best_val
) {
389 best_val
= abs(pdata
->retune_mobile_cfgs
[i
].rate
390 - wm8994
->dac_rates
[iface
]);
394 dev_dbg(codec
->dev
, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
396 pdata
->retune_mobile_cfgs
[best
].name
,
397 pdata
->retune_mobile_cfgs
[best
].rate
,
398 wm8994
->dac_rates
[iface
]);
400 /* The EQ will be disabled while reconfiguring it, remember the
401 * current configuration.
403 save
= snd_soc_read(codec
, base
);
404 save
&= WM8994_AIF1DAC1_EQ_ENA
;
406 for (i
= 0; i
< WM8994_EQ_REGS
; i
++)
407 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
408 pdata
->retune_mobile_cfgs
[best
].regs
[i
]);
410 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_EQ_ENA
, save
);
413 /* Icky as hell but saves code duplication */
414 static int wm8994_get_retune_mobile_block(const char *name
)
416 if (strcmp(name
, "AIF1.1 EQ Mode") == 0)
418 if (strcmp(name
, "AIF1.2 EQ Mode") == 0)
420 if (strcmp(name
, "AIF2 EQ Mode") == 0)
425 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
426 struct snd_ctl_elem_value
*ucontrol
)
428 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
429 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
430 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
431 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
432 int value
= ucontrol
->value
.integer
.value
[0];
437 if (value
>= pdata
->num_retune_mobile_cfgs
)
440 wm8994
->retune_mobile_cfg
[block
] = value
;
442 wm8994_set_retune_mobile(codec
, block
);
447 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
448 struct snd_ctl_elem_value
*ucontrol
)
450 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
451 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
452 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
454 ucontrol
->value
.enumerated
.item
[0] = wm8994
->retune_mobile_cfg
[block
];
459 static const char *aif_chan_src_text
[] = {
463 static const struct soc_enum aif1adcl_src
=
464 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 15, 2, aif_chan_src_text
);
466 static const struct soc_enum aif1adcr_src
=
467 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 14, 2, aif_chan_src_text
);
469 static const struct soc_enum aif2adcl_src
=
470 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 15, 2, aif_chan_src_text
);
472 static const struct soc_enum aif2adcr_src
=
473 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 14, 2, aif_chan_src_text
);
475 static const struct soc_enum aif1dacl_src
=
476 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 15, 2, aif_chan_src_text
);
478 static const struct soc_enum aif1dacr_src
=
479 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 14, 2, aif_chan_src_text
);
481 static const struct soc_enum aif2dacl_src
=
482 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 15, 2, aif_chan_src_text
);
484 static const struct soc_enum aif2dacr_src
=
485 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 14, 2, aif_chan_src_text
);
487 static const char *osr_text
[] = {
488 "Low Power", "High Performance",
491 static const struct soc_enum dac_osr
=
492 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING
, 0, 2, osr_text
);
494 static const struct soc_enum adc_osr
=
495 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING
, 1, 2, osr_text
);
497 static const struct snd_kcontrol_new wm8994_snd_controls
[] = {
498 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME
,
499 WM8994_AIF1_ADC1_RIGHT_VOLUME
,
500 1, 119, 0, digital_tlv
),
501 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME
,
502 WM8994_AIF1_ADC2_RIGHT_VOLUME
,
503 1, 119, 0, digital_tlv
),
504 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME
,
505 WM8994_AIF2_ADC_RIGHT_VOLUME
,
506 1, 119, 0, digital_tlv
),
508 SOC_ENUM("AIF1ADCL Source", aif1adcl_src
),
509 SOC_ENUM("AIF1ADCR Source", aif1adcr_src
),
510 SOC_ENUM("AIF2ADCL Source", aif2adcl_src
),
511 SOC_ENUM("AIF2ADCR Source", aif2adcr_src
),
513 SOC_ENUM("AIF1DACL Source", aif1dacl_src
),
514 SOC_ENUM("AIF1DACR Source", aif1dacr_src
),
515 SOC_ENUM("AIF2DACL Source", aif2dacl_src
),
516 SOC_ENUM("AIF2DACR Source", aif2dacr_src
),
518 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME
,
519 WM8994_AIF1_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
520 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME
,
521 WM8994_AIF1_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
522 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME
,
523 WM8994_AIF2_DAC_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
525 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2
, 10, 3, 0, aif_tlv
),
526 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2
, 10, 3, 0, aif_tlv
),
528 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1
, 0, 1, 0),
529 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1
, 0, 1, 0),
530 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1
, 0, 1, 0),
532 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1
, 2),
533 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1
, 1),
534 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1
, 0),
536 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1
, 2),
537 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1
, 1),
538 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1
, 0),
540 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1
, 2),
541 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1
, 1),
542 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1
, 0),
544 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
546 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
548 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
550 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
552 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf
),
553 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE
, 6, 1, 0),
555 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf
),
556 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS
, 12, 11, 1, 0),
558 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf
),
559 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS
, 12, 11, 1, 0),
561 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf
),
562 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS
, 12, 11, 1, 0),
564 SOC_ENUM("ADC OSR", adc_osr
),
565 SOC_ENUM("DAC OSR", dac_osr
),
567 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME
,
568 WM8994_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
569 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME
,
570 WM8994_DAC1_RIGHT_VOLUME
, 9, 1, 1),
572 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME
,
573 WM8994_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
574 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME
,
575 WM8994_DAC2_RIGHT_VOLUME
, 9, 1, 1),
577 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION
,
578 6, 1, 1, wm_hubs_spkmix_tlv
),
579 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION
,
580 2, 1, 1, wm_hubs_spkmix_tlv
),
582 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION
,
583 6, 1, 1, wm_hubs_spkmix_tlv
),
584 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION
,
585 2, 1, 1, wm_hubs_spkmix_tlv
),
587 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2
,
588 10, 15, 0, wm8994_3d_tlv
),
589 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2
,
591 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2
,
592 10, 15, 0, wm8994_3d_tlv
),
593 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2
,
595 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2
,
596 10, 15, 0, wm8994_3d_tlv
),
597 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2
,
601 static const struct snd_kcontrol_new wm8994_eq_controls
[] = {
602 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 11, 31, 0,
604 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 6, 31, 0,
606 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 1, 31, 0,
608 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 11, 31, 0,
610 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 6, 31, 0,
613 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 11, 31, 0,
615 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 6, 31, 0,
617 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 1, 31, 0,
619 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 11, 31, 0,
621 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 6, 31, 0,
624 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1
, 11, 31, 0,
626 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1
, 6, 31, 0,
628 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1
, 1, 31, 0,
630 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2
, 11, 31, 0,
632 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2
, 6, 31, 0,
636 static const char *wm8958_ng_text
[] = {
637 "30ms", "125ms", "250ms", "500ms",
640 static const struct soc_enum wm8958_aif1dac1_ng_hold
=
641 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE
,
642 WM8958_AIF1DAC1_NG_THR_SHIFT
, 4, wm8958_ng_text
);
644 static const struct soc_enum wm8958_aif1dac2_ng_hold
=
645 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE
,
646 WM8958_AIF1DAC2_NG_THR_SHIFT
, 4, wm8958_ng_text
);
648 static const struct soc_enum wm8958_aif2dac_ng_hold
=
649 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE
,
650 WM8958_AIF2DAC_NG_THR_SHIFT
, 4, wm8958_ng_text
);
652 static const struct snd_kcontrol_new wm8958_snd_controls
[] = {
653 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2
, 10, 3, 0, aif_tlv
),
655 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE
,
656 WM8958_AIF1DAC1_NG_ENA_SHIFT
, 1, 0),
657 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold
),
658 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
659 WM8958_AIF1_DAC1_NOISE_GATE
, WM8958_AIF1DAC1_NG_THR_SHIFT
,
662 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE
,
663 WM8958_AIF1DAC2_NG_ENA_SHIFT
, 1, 0),
664 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold
),
665 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
666 WM8958_AIF1_DAC2_NOISE_GATE
, WM8958_AIF1DAC2_NG_THR_SHIFT
,
669 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE
,
670 WM8958_AIF2DAC_NG_ENA_SHIFT
, 1, 0),
671 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold
),
672 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
673 WM8958_AIF2_DAC_NOISE_GATE
, WM8958_AIF2DAC_NG_THR_SHIFT
,
677 static const struct snd_kcontrol_new wm1811_snd_controls
[] = {
678 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1
, 7, 1, 0,
680 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1
, 8, 1, 0,
684 /* We run all mode setting through a function to enforce audio mode */
685 static void wm1811_jackdet_set_mode(struct snd_soc_codec
*codec
, u16 mode
)
687 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
689 if (!wm8994
->jackdet
|| !wm8994
->jack_cb
)
692 if (wm8994
->active_refcount
)
693 mode
= WM1811_JACKDET_MODE_AUDIO
;
695 if (mode
== wm8994
->jackdet_mode
)
698 wm8994
->jackdet_mode
= mode
;
700 /* Always use audio mode to detect while the system is active */
701 if (mode
!= WM1811_JACKDET_MODE_NONE
)
702 mode
= WM1811_JACKDET_MODE_AUDIO
;
704 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
705 WM1811_JACKDET_MODE_MASK
, mode
);
708 static void active_reference(struct snd_soc_codec
*codec
)
710 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
712 mutex_lock(&wm8994
->accdet_lock
);
714 wm8994
->active_refcount
++;
716 dev_dbg(codec
->dev
, "Active refcount incremented, now %d\n",
717 wm8994
->active_refcount
);
719 /* If we're using jack detection go into audio mode */
720 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_AUDIO
);
722 mutex_unlock(&wm8994
->accdet_lock
);
725 static void active_dereference(struct snd_soc_codec
*codec
)
727 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
730 mutex_lock(&wm8994
->accdet_lock
);
732 wm8994
->active_refcount
--;
734 dev_dbg(codec
->dev
, "Active refcount decremented, now %d\n",
735 wm8994
->active_refcount
);
737 if (wm8994
->active_refcount
== 0) {
738 /* Go into appropriate detection only mode */
739 if (wm8994
->jack_mic
|| wm8994
->mic_detecting
)
740 mode
= WM1811_JACKDET_MODE_MIC
;
742 mode
= WM1811_JACKDET_MODE_JACK
;
744 wm1811_jackdet_set_mode(codec
, mode
);
747 mutex_unlock(&wm8994
->accdet_lock
);
750 static int clk_sys_event(struct snd_soc_dapm_widget
*w
,
751 struct snd_kcontrol
*kcontrol
, int event
)
753 struct snd_soc_codec
*codec
= w
->codec
;
756 case SND_SOC_DAPM_PRE_PMU
:
757 return configure_clock(codec
);
759 case SND_SOC_DAPM_POST_PMD
:
760 configure_clock(codec
);
767 static void vmid_reference(struct snd_soc_codec
*codec
)
769 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
771 pm_runtime_get_sync(codec
->dev
);
773 wm8994
->vmid_refcount
++;
775 dev_dbg(codec
->dev
, "Referencing VMID, refcount is now %d\n",
776 wm8994
->vmid_refcount
);
778 if (wm8994
->vmid_refcount
== 1) {
779 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
780 WM8994_LINEOUT1_DISCH
|
781 WM8994_LINEOUT2_DISCH
, 0);
783 wm_hubs_vmid_ena(codec
);
785 switch (wm8994
->vmid_mode
) {
787 WARN_ON(0 == "Invalid VMID mode");
788 case WM8994_VMID_NORMAL
:
789 /* Startup bias, VMID ramp & buffer */
790 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
793 WM8994_STARTUP_BIAS_ENA
|
794 WM8994_VMID_BUF_ENA
|
795 WM8994_VMID_RAMP_MASK
,
797 WM8994_STARTUP_BIAS_ENA
|
798 WM8994_VMID_BUF_ENA
|
799 (0x3 << WM8994_VMID_RAMP_SHIFT
));
801 /* Main bias enable, VMID=2x40k */
802 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
804 WM8994_VMID_SEL_MASK
,
805 WM8994_BIAS_ENA
| 0x2);
809 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
810 WM8994_VMID_RAMP_MASK
|
815 case WM8994_VMID_FORCE
:
816 /* Startup bias, slow VMID ramp & buffer */
817 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
820 WM8994_STARTUP_BIAS_ENA
|
821 WM8994_VMID_BUF_ENA
|
822 WM8994_VMID_RAMP_MASK
,
824 WM8994_STARTUP_BIAS_ENA
|
825 WM8994_VMID_BUF_ENA
|
826 (0x2 << WM8994_VMID_RAMP_SHIFT
));
828 /* Main bias enable, VMID=2x40k */
829 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
831 WM8994_VMID_SEL_MASK
,
832 WM8994_BIAS_ENA
| 0x2);
836 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
837 WM8994_VMID_RAMP_MASK
|
845 static void vmid_dereference(struct snd_soc_codec
*codec
)
847 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
849 wm8994
->vmid_refcount
--;
851 dev_dbg(codec
->dev
, "Dereferencing VMID, refcount is now %d\n",
852 wm8994
->vmid_refcount
);
854 if (wm8994
->vmid_refcount
== 0) {
855 if (wm8994
->hubs
.lineout1_se
)
856 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_3
,
857 WM8994_LINEOUT1N_ENA
|
858 WM8994_LINEOUT1P_ENA
,
859 WM8994_LINEOUT1N_ENA
|
860 WM8994_LINEOUT1P_ENA
);
862 if (wm8994
->hubs
.lineout2_se
)
863 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_3
,
864 WM8994_LINEOUT2N_ENA
|
865 WM8994_LINEOUT2P_ENA
,
866 WM8994_LINEOUT2N_ENA
|
867 WM8994_LINEOUT2P_ENA
);
869 /* Start discharging VMID */
870 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
876 switch (wm8994
->vmid_mode
) {
877 case WM8994_VMID_FORCE
:
884 snd_soc_update_bits(codec
, WM8994_ADDITIONAL_CONTROL
,
885 WM8994_VROI
, WM8994_VROI
);
887 /* Active discharge */
888 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
889 WM8994_LINEOUT1_DISCH
|
890 WM8994_LINEOUT2_DISCH
,
891 WM8994_LINEOUT1_DISCH
|
892 WM8994_LINEOUT2_DISCH
);
896 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_3
,
897 WM8994_LINEOUT1N_ENA
|
898 WM8994_LINEOUT1P_ENA
|
899 WM8994_LINEOUT2N_ENA
|
900 WM8994_LINEOUT2P_ENA
, 0);
902 snd_soc_update_bits(codec
, WM8994_ADDITIONAL_CONTROL
,
905 /* Switch off startup biases */
906 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
908 WM8994_STARTUP_BIAS_ENA
|
909 WM8994_VMID_BUF_ENA
|
910 WM8994_VMID_RAMP_MASK
, 0);
912 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
913 WM8994_BIAS_ENA
| WM8994_VMID_SEL_MASK
, 0);
915 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
916 WM8994_VMID_RAMP_MASK
, 0);
919 pm_runtime_put(codec
->dev
);
922 static int vmid_event(struct snd_soc_dapm_widget
*w
,
923 struct snd_kcontrol
*kcontrol
, int event
)
925 struct snd_soc_codec
*codec
= w
->codec
;
928 case SND_SOC_DAPM_PRE_PMU
:
929 vmid_reference(codec
);
932 case SND_SOC_DAPM_POST_PMD
:
933 vmid_dereference(codec
);
940 static void wm8994_update_class_w(struct snd_soc_codec
*codec
)
942 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
944 int source
= 0; /* GCC flow analysis can't track enable */
947 /* Only support direct DAC->headphone paths */
948 reg
= snd_soc_read(codec
, WM8994_OUTPUT_MIXER_1
);
949 if (!(reg
& WM8994_DAC1L_TO_HPOUT1L
)) {
950 dev_vdbg(codec
->dev
, "HPL connected to output mixer\n");
954 reg
= snd_soc_read(codec
, WM8994_OUTPUT_MIXER_2
);
955 if (!(reg
& WM8994_DAC1R_TO_HPOUT1R
)) {
956 dev_vdbg(codec
->dev
, "HPR connected to output mixer\n");
960 /* We also need the same setting for L/R and only one path */
961 reg
= snd_soc_read(codec
, WM8994_DAC1_LEFT_MIXER_ROUTING
);
963 case WM8994_AIF2DACL_TO_DAC1L
:
964 dev_vdbg(codec
->dev
, "Class W source AIF2DAC\n");
965 source
= 2 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
967 case WM8994_AIF1DAC2L_TO_DAC1L
:
968 dev_vdbg(codec
->dev
, "Class W source AIF1DAC2\n");
969 source
= 1 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
971 case WM8994_AIF1DAC1L_TO_DAC1L
:
972 dev_vdbg(codec
->dev
, "Class W source AIF1DAC1\n");
973 source
= 0 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
976 dev_vdbg(codec
->dev
, "DAC mixer setting: %x\n", reg
);
981 reg_r
= snd_soc_read(codec
, WM8994_DAC1_RIGHT_MIXER_ROUTING
);
983 dev_vdbg(codec
->dev
, "Left and right DAC mixers different\n");
988 dev_dbg(codec
->dev
, "Class W enabled\n");
989 snd_soc_update_bits(codec
, WM8994_CLASS_W_1
,
991 WM8994_CP_DYN_SRC_SEL_MASK
,
992 source
| WM8994_CP_DYN_PWR
);
993 wm8994
->hubs
.class_w
= true;
996 dev_dbg(codec
->dev
, "Class W disabled\n");
997 snd_soc_update_bits(codec
, WM8994_CLASS_W_1
,
998 WM8994_CP_DYN_PWR
, 0);
999 wm8994
->hubs
.class_w
= false;
1003 static int aif1clk_ev(struct snd_soc_dapm_widget
*w
,
1004 struct snd_kcontrol
*kcontrol
, int event
)
1006 struct snd_soc_codec
*codec
= w
->codec
;
1007 struct wm8994
*control
= codec
->control_data
;
1008 int mask
= WM8994_AIF1DAC1L_ENA
| WM8994_AIF1DAC1R_ENA
;
1013 switch (control
->type
) {
1016 mask
|= WM8994_AIF1DAC2L_ENA
| WM8994_AIF1DAC2R_ENA
;
1023 case SND_SOC_DAPM_PRE_PMU
:
1024 val
= snd_soc_read(codec
, WM8994_AIF1_CONTROL_1
);
1025 if ((val
& WM8994_AIF1ADCL_SRC
) &&
1026 (val
& WM8994_AIF1ADCR_SRC
))
1027 adc
= WM8994_AIF1ADC1R_ENA
| WM8994_AIF1ADC2R_ENA
;
1028 else if (!(val
& WM8994_AIF1ADCL_SRC
) &&
1029 !(val
& WM8994_AIF1ADCR_SRC
))
1030 adc
= WM8994_AIF1ADC1L_ENA
| WM8994_AIF1ADC2L_ENA
;
1032 adc
= WM8994_AIF1ADC1R_ENA
| WM8994_AIF1ADC2R_ENA
|
1033 WM8994_AIF1ADC1L_ENA
| WM8994_AIF1ADC2L_ENA
;
1035 val
= snd_soc_read(codec
, WM8994_AIF1_CONTROL_2
);
1036 if ((val
& WM8994_AIF1DACL_SRC
) &&
1037 (val
& WM8994_AIF1DACR_SRC
))
1038 dac
= WM8994_AIF1DAC1R_ENA
| WM8994_AIF1DAC2R_ENA
;
1039 else if (!(val
& WM8994_AIF1DACL_SRC
) &&
1040 !(val
& WM8994_AIF1DACR_SRC
))
1041 dac
= WM8994_AIF1DAC1L_ENA
| WM8994_AIF1DAC2L_ENA
;
1043 dac
= WM8994_AIF1DAC1R_ENA
| WM8994_AIF1DAC2R_ENA
|
1044 WM8994_AIF1DAC1L_ENA
| WM8994_AIF1DAC2L_ENA
;
1046 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1048 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1050 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1051 WM8994_AIF1DSPCLK_ENA
|
1052 WM8994_SYSDSPCLK_ENA
,
1053 WM8994_AIF1DSPCLK_ENA
|
1054 WM8994_SYSDSPCLK_ENA
);
1055 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
, mask
,
1056 WM8994_AIF1ADC1R_ENA
|
1057 WM8994_AIF1ADC1L_ENA
|
1058 WM8994_AIF1ADC2R_ENA
|
1059 WM8994_AIF1ADC2L_ENA
);
1060 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
, mask
,
1061 WM8994_AIF1DAC1R_ENA
|
1062 WM8994_AIF1DAC1L_ENA
|
1063 WM8994_AIF1DAC2R_ENA
|
1064 WM8994_AIF1DAC2L_ENA
);
1067 case SND_SOC_DAPM_PRE_PMD
:
1068 case SND_SOC_DAPM_POST_PMD
:
1069 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1071 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1074 val
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
1075 if (val
& WM8994_AIF2DSPCLK_ENA
)
1076 val
= WM8994_SYSDSPCLK_ENA
;
1079 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1080 WM8994_SYSDSPCLK_ENA
|
1081 WM8994_AIF1DSPCLK_ENA
, val
);
1088 static int aif2clk_ev(struct snd_soc_dapm_widget
*w
,
1089 struct snd_kcontrol
*kcontrol
, int event
)
1091 struct snd_soc_codec
*codec
= w
->codec
;
1097 case SND_SOC_DAPM_PRE_PMU
:
1098 val
= snd_soc_read(codec
, WM8994_AIF2_CONTROL_1
);
1099 if ((val
& WM8994_AIF2ADCL_SRC
) &&
1100 (val
& WM8994_AIF2ADCR_SRC
))
1101 adc
= WM8994_AIF2ADCR_ENA
;
1102 else if (!(val
& WM8994_AIF2ADCL_SRC
) &&
1103 !(val
& WM8994_AIF2ADCR_SRC
))
1104 adc
= WM8994_AIF2ADCL_ENA
;
1106 adc
= WM8994_AIF2ADCL_ENA
| WM8994_AIF2ADCR_ENA
;
1109 val
= snd_soc_read(codec
, WM8994_AIF2_CONTROL_2
);
1110 if ((val
& WM8994_AIF2DACL_SRC
) &&
1111 (val
& WM8994_AIF2DACR_SRC
))
1112 dac
= WM8994_AIF2DACR_ENA
;
1113 else if (!(val
& WM8994_AIF2DACL_SRC
) &&
1114 !(val
& WM8994_AIF2DACR_SRC
))
1115 dac
= WM8994_AIF2DACL_ENA
;
1117 dac
= WM8994_AIF2DACL_ENA
| WM8994_AIF2DACR_ENA
;
1119 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1120 WM8994_AIF2ADCL_ENA
|
1121 WM8994_AIF2ADCR_ENA
, adc
);
1122 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1123 WM8994_AIF2DACL_ENA
|
1124 WM8994_AIF2DACR_ENA
, dac
);
1125 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1126 WM8994_AIF2DSPCLK_ENA
|
1127 WM8994_SYSDSPCLK_ENA
,
1128 WM8994_AIF2DSPCLK_ENA
|
1129 WM8994_SYSDSPCLK_ENA
);
1130 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_4
,
1131 WM8994_AIF2ADCL_ENA
|
1132 WM8994_AIF2ADCR_ENA
,
1133 WM8994_AIF2ADCL_ENA
|
1134 WM8994_AIF2ADCR_ENA
);
1135 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1136 WM8994_AIF2DACL_ENA
|
1137 WM8994_AIF2DACR_ENA
,
1138 WM8994_AIF2DACL_ENA
|
1139 WM8994_AIF2DACR_ENA
);
1142 case SND_SOC_DAPM_PRE_PMD
:
1143 case SND_SOC_DAPM_POST_PMD
:
1144 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1145 WM8994_AIF2DACL_ENA
|
1146 WM8994_AIF2DACR_ENA
, 0);
1147 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1148 WM8994_AIF2ADCL_ENA
|
1149 WM8994_AIF2ADCR_ENA
, 0);
1151 val
= snd_soc_read(codec
, WM8994_CLOCKING_1
);
1152 if (val
& WM8994_AIF1DSPCLK_ENA
)
1153 val
= WM8994_SYSDSPCLK_ENA
;
1156 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
,
1157 WM8994_SYSDSPCLK_ENA
|
1158 WM8994_AIF2DSPCLK_ENA
, val
);
1165 static int aif1clk_late_ev(struct snd_soc_dapm_widget
*w
,
1166 struct snd_kcontrol
*kcontrol
, int event
)
1168 struct snd_soc_codec
*codec
= w
->codec
;
1169 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1172 case SND_SOC_DAPM_PRE_PMU
:
1173 wm8994
->aif1clk_enable
= 1;
1175 case SND_SOC_DAPM_POST_PMD
:
1176 wm8994
->aif1clk_disable
= 1;
1183 static int aif2clk_late_ev(struct snd_soc_dapm_widget
*w
,
1184 struct snd_kcontrol
*kcontrol
, int event
)
1186 struct snd_soc_codec
*codec
= w
->codec
;
1187 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1190 case SND_SOC_DAPM_PRE_PMU
:
1191 wm8994
->aif2clk_enable
= 1;
1193 case SND_SOC_DAPM_POST_PMD
:
1194 wm8994
->aif2clk_disable
= 1;
1201 static int late_enable_ev(struct snd_soc_dapm_widget
*w
,
1202 struct snd_kcontrol
*kcontrol
, int event
)
1204 struct snd_soc_codec
*codec
= w
->codec
;
1205 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1208 case SND_SOC_DAPM_PRE_PMU
:
1209 if (wm8994
->aif1clk_enable
) {
1210 aif1clk_ev(w
, kcontrol
, event
);
1211 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1212 WM8994_AIF1CLK_ENA_MASK
,
1213 WM8994_AIF1CLK_ENA
);
1214 wm8994
->aif1clk_enable
= 0;
1216 if (wm8994
->aif2clk_enable
) {
1217 aif2clk_ev(w
, kcontrol
, event
);
1218 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1219 WM8994_AIF2CLK_ENA_MASK
,
1220 WM8994_AIF2CLK_ENA
);
1221 wm8994
->aif2clk_enable
= 0;
1226 /* We may also have postponed startup of DSP, handle that. */
1227 wm8958_aif_ev(w
, kcontrol
, event
);
1232 static int late_disable_ev(struct snd_soc_dapm_widget
*w
,
1233 struct snd_kcontrol
*kcontrol
, int event
)
1235 struct snd_soc_codec
*codec
= w
->codec
;
1236 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1239 case SND_SOC_DAPM_POST_PMD
:
1240 if (wm8994
->aif1clk_disable
) {
1241 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1242 WM8994_AIF1CLK_ENA_MASK
, 0);
1243 aif1clk_ev(w
, kcontrol
, event
);
1244 wm8994
->aif1clk_disable
= 0;
1246 if (wm8994
->aif2clk_disable
) {
1247 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1248 WM8994_AIF2CLK_ENA_MASK
, 0);
1249 aif2clk_ev(w
, kcontrol
, event
);
1250 wm8994
->aif2clk_disable
= 0;
1258 static int adc_mux_ev(struct snd_soc_dapm_widget
*w
,
1259 struct snd_kcontrol
*kcontrol
, int event
)
1261 late_enable_ev(w
, kcontrol
, event
);
1265 static int micbias_ev(struct snd_soc_dapm_widget
*w
,
1266 struct snd_kcontrol
*kcontrol
, int event
)
1268 late_enable_ev(w
, kcontrol
, event
);
1272 static int dac_ev(struct snd_soc_dapm_widget
*w
,
1273 struct snd_kcontrol
*kcontrol
, int event
)
1275 struct snd_soc_codec
*codec
= w
->codec
;
1276 unsigned int mask
= 1 << w
->shift
;
1278 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
1283 static const char *hp_mux_text
[] = {
1288 #define WM8994_HP_ENUM(xname, xenum) \
1289 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1290 .info = snd_soc_info_enum_double, \
1291 .get = snd_soc_dapm_get_enum_double, \
1292 .put = wm8994_put_hp_enum, \
1293 .private_value = (unsigned long)&xenum }
1295 static int wm8994_put_hp_enum(struct snd_kcontrol
*kcontrol
,
1296 struct snd_ctl_elem_value
*ucontrol
)
1298 struct snd_soc_dapm_widget_list
*wlist
= snd_kcontrol_chip(kcontrol
);
1299 struct snd_soc_dapm_widget
*w
= wlist
->widgets
[0];
1300 struct snd_soc_codec
*codec
= w
->codec
;
1303 ret
= snd_soc_dapm_put_enum_double(kcontrol
, ucontrol
);
1305 wm8994_update_class_w(codec
);
1310 static const struct soc_enum hpl_enum
=
1311 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1
, 8, 2, hp_mux_text
);
1313 static const struct snd_kcontrol_new hpl_mux
=
1314 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum
);
1316 static const struct soc_enum hpr_enum
=
1317 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2
, 8, 2, hp_mux_text
);
1319 static const struct snd_kcontrol_new hpr_mux
=
1320 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum
);
1322 static const char *adc_mux_text
[] = {
1327 static const struct soc_enum adc_enum
=
1328 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text
);
1330 static const struct snd_kcontrol_new adcl_mux
=
1331 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum
);
1333 static const struct snd_kcontrol_new adcr_mux
=
1334 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum
);
1336 static const struct snd_kcontrol_new left_speaker_mixer
[] = {
1337 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 9, 1, 0),
1338 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 7, 1, 0),
1339 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER
, 5, 1, 0),
1340 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 3, 1, 0),
1341 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 1, 1, 0),
1344 static const struct snd_kcontrol_new right_speaker_mixer
[] = {
1345 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 8, 1, 0),
1346 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 6, 1, 0),
1347 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER
, 4, 1, 0),
1348 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 2, 1, 0),
1349 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 0, 1, 0),
1352 /* Debugging; dump chip status after DAPM transitions */
1353 static int post_ev(struct snd_soc_dapm_widget
*w
,
1354 struct snd_kcontrol
*kcontrol
, int event
)
1356 struct snd_soc_codec
*codec
= w
->codec
;
1357 dev_dbg(codec
->dev
, "SRC status: %x\n",
1359 WM8994_RATE_STATUS
));
1363 static const struct snd_kcontrol_new aif1adc1l_mix
[] = {
1364 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
1366 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
1370 static const struct snd_kcontrol_new aif1adc1r_mix
[] = {
1371 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
1373 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
1377 static const struct snd_kcontrol_new aif1adc2l_mix
[] = {
1378 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
1380 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
1384 static const struct snd_kcontrol_new aif1adc2r_mix
[] = {
1385 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
1387 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
1391 static const struct snd_kcontrol_new aif2dac2l_mix
[] = {
1392 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1394 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1396 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1398 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1400 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
1404 static const struct snd_kcontrol_new aif2dac2r_mix
[] = {
1405 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1407 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1409 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1411 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1413 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
1417 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1418 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1419 .info = snd_soc_info_volsw, \
1420 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1421 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1423 static int wm8994_put_class_w(struct snd_kcontrol
*kcontrol
,
1424 struct snd_ctl_elem_value
*ucontrol
)
1426 struct snd_soc_dapm_widget_list
*wlist
= snd_kcontrol_chip(kcontrol
);
1427 struct snd_soc_dapm_widget
*w
= wlist
->widgets
[0];
1428 struct snd_soc_codec
*codec
= w
->codec
;
1431 ret
= snd_soc_dapm_put_volsw(kcontrol
, ucontrol
);
1433 wm8994_update_class_w(codec
);
1438 static const struct snd_kcontrol_new dac1l_mix
[] = {
1439 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1441 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1443 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1445 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1447 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1451 static const struct snd_kcontrol_new dac1r_mix
[] = {
1452 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1454 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1456 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1458 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1460 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1464 static const char *sidetone_text
[] = {
1465 "ADC/DMIC1", "DMIC2",
1468 static const struct soc_enum sidetone1_enum
=
1469 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 0, 2, sidetone_text
);
1471 static const struct snd_kcontrol_new sidetone1_mux
=
1472 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum
);
1474 static const struct soc_enum sidetone2_enum
=
1475 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 1, 2, sidetone_text
);
1477 static const struct snd_kcontrol_new sidetone2_mux
=
1478 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum
);
1480 static const char *aif1dac_text
[] = {
1481 "AIF1DACDAT", "AIF3DACDAT",
1484 static const struct soc_enum aif1dac_enum
=
1485 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 0, 2, aif1dac_text
);
1487 static const struct snd_kcontrol_new aif1dac_mux
=
1488 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum
);
1490 static const char *aif2dac_text
[] = {
1491 "AIF2DACDAT", "AIF3DACDAT",
1494 static const struct soc_enum aif2dac_enum
=
1495 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 1, 2, aif2dac_text
);
1497 static const struct snd_kcontrol_new aif2dac_mux
=
1498 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum
);
1500 static const char *aif2adc_text
[] = {
1501 "AIF2ADCDAT", "AIF3DACDAT",
1504 static const struct soc_enum aif2adc_enum
=
1505 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 2, 2, aif2adc_text
);
1507 static const struct snd_kcontrol_new aif2adc_mux
=
1508 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum
);
1510 static const char *aif3adc_text
[] = {
1511 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1514 static const struct soc_enum wm8994_aif3adc_enum
=
1515 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 3, aif3adc_text
);
1517 static const struct snd_kcontrol_new wm8994_aif3adc_mux
=
1518 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum
);
1520 static const struct soc_enum wm8958_aif3adc_enum
=
1521 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 4, aif3adc_text
);
1523 static const struct snd_kcontrol_new wm8958_aif3adc_mux
=
1524 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum
);
1526 static const char *mono_pcm_out_text
[] = {
1527 "None", "AIF2ADCL", "AIF2ADCR",
1530 static const struct soc_enum mono_pcm_out_enum
=
1531 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 9, 3, mono_pcm_out_text
);
1533 static const struct snd_kcontrol_new mono_pcm_out_mux
=
1534 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum
);
1536 static const char *aif2dac_src_text
[] = {
1540 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1541 static const struct soc_enum aif2dacl_src_enum
=
1542 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 7, 2, aif2dac_src_text
);
1544 static const struct snd_kcontrol_new aif2dacl_src_mux
=
1545 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum
);
1547 static const struct soc_enum aif2dacr_src_enum
=
1548 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 8, 2, aif2dac_src_text
);
1550 static const struct snd_kcontrol_new aif2dacr_src_mux
=
1551 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum
);
1553 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets
[] = {
1554 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM
, 0, 0, aif1clk_late_ev
,
1555 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1556 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM
, 0, 0, aif2clk_late_ev
,
1557 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1559 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1560 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1561 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1562 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1563 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1564 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1565 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1566 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1567 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1568 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1570 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3
, 8, 0,
1571 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
),
1572 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1573 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3
, 9, 0,
1574 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
),
1575 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1576 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpl_mux
,
1577 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1578 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpr_mux
,
1579 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1581 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev
)
1584 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets
[] = {
1585 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1
, 0, 0, aif1clk_ev
,
1586 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_PRE_PMD
),
1587 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1
, 0, 0, aif2clk_ev
,
1588 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_PRE_PMD
),
1589 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM
, 0, 0, NULL
, 0),
1590 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3
, 8, 0,
1591 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
)),
1592 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3
, 9, 0,
1593 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
)),
1594 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpl_mux
),
1595 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpr_mux
),
1598 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets
[] = {
1599 SND_SOC_DAPM_DAC_E("DAC2L", NULL
, SND_SOC_NOPM
, 3, 0,
1600 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1601 SND_SOC_DAPM_DAC_E("DAC2R", NULL
, SND_SOC_NOPM
, 2, 0,
1602 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1603 SND_SOC_DAPM_DAC_E("DAC1L", NULL
, SND_SOC_NOPM
, 1, 0,
1604 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1605 SND_SOC_DAPM_DAC_E("DAC1R", NULL
, SND_SOC_NOPM
, 0, 0,
1606 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1609 static const struct snd_soc_dapm_widget wm8994_dac_widgets
[] = {
1610 SND_SOC_DAPM_DAC("DAC2L", NULL
, WM8994_POWER_MANAGEMENT_5
, 3, 0),
1611 SND_SOC_DAPM_DAC("DAC2R", NULL
, WM8994_POWER_MANAGEMENT_5
, 2, 0),
1612 SND_SOC_DAPM_DAC("DAC1L", NULL
, WM8994_POWER_MANAGEMENT_5
, 1, 0),
1613 SND_SOC_DAPM_DAC("DAC1R", NULL
, WM8994_POWER_MANAGEMENT_5
, 0, 0),
1616 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets
[] = {
1617 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
,
1618 adc_mux_ev
, SND_SOC_DAPM_PRE_PMU
),
1619 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
,
1620 adc_mux_ev
, SND_SOC_DAPM_PRE_PMU
),
1623 static const struct snd_soc_dapm_widget wm8994_adc_widgets
[] = {
1624 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
),
1625 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
),
1628 static const struct snd_soc_dapm_widget wm8994_dapm_widgets
[] = {
1629 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1630 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1631 SND_SOC_DAPM_INPUT("Clock"),
1633 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM
, 0, 0, micbias_ev
,
1634 SND_SOC_DAPM_PRE_PMU
),
1635 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM
, 0, 0, vmid_event
,
1636 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1638 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM
, 0, 0, clk_sys_event
,
1639 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1641 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM
, 3, 0, NULL
, 0),
1642 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM
, 2, 0, NULL
, 0),
1643 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM
, 1, 0, NULL
, 0),
1645 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL
,
1646 0, SND_SOC_NOPM
, 9, 0),
1647 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL
,
1648 0, SND_SOC_NOPM
, 8, 0),
1649 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL
, 0,
1650 SND_SOC_NOPM
, 9, 0, wm8958_aif_ev
,
1651 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1652 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL
, 0,
1653 SND_SOC_NOPM
, 8, 0, wm8958_aif_ev
,
1654 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1656 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL
,
1657 0, SND_SOC_NOPM
, 11, 0),
1658 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL
,
1659 0, SND_SOC_NOPM
, 10, 0),
1660 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL
, 0,
1661 SND_SOC_NOPM
, 11, 0, wm8958_aif_ev
,
1662 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1663 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL
, 0,
1664 SND_SOC_NOPM
, 10, 0, wm8958_aif_ev
,
1665 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1667 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM
, 0, 0,
1668 aif1adc1l_mix
, ARRAY_SIZE(aif1adc1l_mix
)),
1669 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM
, 0, 0,
1670 aif1adc1r_mix
, ARRAY_SIZE(aif1adc1r_mix
)),
1672 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM
, 0, 0,
1673 aif1adc2l_mix
, ARRAY_SIZE(aif1adc2l_mix
)),
1674 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM
, 0, 0,
1675 aif1adc2r_mix
, ARRAY_SIZE(aif1adc2r_mix
)),
1677 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM
, 0, 0,
1678 aif2dac2l_mix
, ARRAY_SIZE(aif2dac2l_mix
)),
1679 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM
, 0, 0,
1680 aif2dac2r_mix
, ARRAY_SIZE(aif2dac2r_mix
)),
1682 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone1_mux
),
1683 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone2_mux
),
1685 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM
, 0, 0,
1686 dac1l_mix
, ARRAY_SIZE(dac1l_mix
)),
1687 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM
, 0, 0,
1688 dac1r_mix
, ARRAY_SIZE(dac1r_mix
)),
1690 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL
, 0,
1691 SND_SOC_NOPM
, 13, 0),
1692 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL
, 0,
1693 SND_SOC_NOPM
, 12, 0),
1694 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL
, 0,
1695 SND_SOC_NOPM
, 13, 0, wm8958_aif_ev
,
1696 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1697 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL
, 0,
1698 SND_SOC_NOPM
, 12, 0, wm8958_aif_ev
,
1699 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1701 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1702 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1703 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1704 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1706 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM
, 0, 0, &aif1dac_mux
),
1707 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM
, 0, 0, &aif2dac_mux
),
1708 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM
, 0, 0, &aif2adc_mux
),
1710 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1711 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL
, 0, SND_SOC_NOPM
, 0, 0),
1713 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1
, 4, 0, NULL
, 0),
1715 SND_SOC_DAPM_ADC("DMIC2L", NULL
, WM8994_POWER_MANAGEMENT_4
, 5, 0),
1716 SND_SOC_DAPM_ADC("DMIC2R", NULL
, WM8994_POWER_MANAGEMENT_4
, 4, 0),
1717 SND_SOC_DAPM_ADC("DMIC1L", NULL
, WM8994_POWER_MANAGEMENT_4
, 3, 0),
1718 SND_SOC_DAPM_ADC("DMIC1R", NULL
, WM8994_POWER_MANAGEMENT_4
, 2, 0),
1720 /* Power is done with the muxes since the ADC power also controls the
1721 * downsampling chain, the chip will automatically manage the analogue
1722 * specific portions.
1724 SND_SOC_DAPM_ADC("ADCL", NULL
, SND_SOC_NOPM
, 1, 0),
1725 SND_SOC_DAPM_ADC("ADCR", NULL
, SND_SOC_NOPM
, 0, 0),
1727 SND_SOC_DAPM_POST("Debug log", post_ev
),
1730 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets
[] = {
1731 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8994_aif3adc_mux
),
1734 static const struct snd_soc_dapm_widget wm8958_dapm_widgets
[] = {
1735 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM
, 0, 0, &mono_pcm_out_mux
),
1736 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM
, 0, 0, &aif2dacl_src_mux
),
1737 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM
, 0, 0, &aif2dacr_src_mux
),
1738 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8958_aif3adc_mux
),
1741 static const struct snd_soc_dapm_route intercon
[] = {
1742 { "CLK_SYS", NULL
, "AIF1CLK", check_clk_sys
},
1743 { "CLK_SYS", NULL
, "AIF2CLK", check_clk_sys
},
1745 { "DSP1CLK", NULL
, "CLK_SYS" },
1746 { "DSP2CLK", NULL
, "CLK_SYS" },
1747 { "DSPINTCLK", NULL
, "CLK_SYS" },
1749 { "AIF1ADC1L", NULL
, "AIF1CLK" },
1750 { "AIF1ADC1L", NULL
, "DSP1CLK" },
1751 { "AIF1ADC1R", NULL
, "AIF1CLK" },
1752 { "AIF1ADC1R", NULL
, "DSP1CLK" },
1753 { "AIF1ADC1R", NULL
, "DSPINTCLK" },
1755 { "AIF1DAC1L", NULL
, "AIF1CLK" },
1756 { "AIF1DAC1L", NULL
, "DSP1CLK" },
1757 { "AIF1DAC1R", NULL
, "AIF1CLK" },
1758 { "AIF1DAC1R", NULL
, "DSP1CLK" },
1759 { "AIF1DAC1R", NULL
, "DSPINTCLK" },
1761 { "AIF1ADC2L", NULL
, "AIF1CLK" },
1762 { "AIF1ADC2L", NULL
, "DSP1CLK" },
1763 { "AIF1ADC2R", NULL
, "AIF1CLK" },
1764 { "AIF1ADC2R", NULL
, "DSP1CLK" },
1765 { "AIF1ADC2R", NULL
, "DSPINTCLK" },
1767 { "AIF1DAC2L", NULL
, "AIF1CLK" },
1768 { "AIF1DAC2L", NULL
, "DSP1CLK" },
1769 { "AIF1DAC2R", NULL
, "AIF1CLK" },
1770 { "AIF1DAC2R", NULL
, "DSP1CLK" },
1771 { "AIF1DAC2R", NULL
, "DSPINTCLK" },
1773 { "AIF2ADCL", NULL
, "AIF2CLK" },
1774 { "AIF2ADCL", NULL
, "DSP2CLK" },
1775 { "AIF2ADCR", NULL
, "AIF2CLK" },
1776 { "AIF2ADCR", NULL
, "DSP2CLK" },
1777 { "AIF2ADCR", NULL
, "DSPINTCLK" },
1779 { "AIF2DACL", NULL
, "AIF2CLK" },
1780 { "AIF2DACL", NULL
, "DSP2CLK" },
1781 { "AIF2DACR", NULL
, "AIF2CLK" },
1782 { "AIF2DACR", NULL
, "DSP2CLK" },
1783 { "AIF2DACR", NULL
, "DSPINTCLK" },
1785 { "DMIC1L", NULL
, "DMIC1DAT" },
1786 { "DMIC1L", NULL
, "CLK_SYS" },
1787 { "DMIC1R", NULL
, "DMIC1DAT" },
1788 { "DMIC1R", NULL
, "CLK_SYS" },
1789 { "DMIC2L", NULL
, "DMIC2DAT" },
1790 { "DMIC2L", NULL
, "CLK_SYS" },
1791 { "DMIC2R", NULL
, "DMIC2DAT" },
1792 { "DMIC2R", NULL
, "CLK_SYS" },
1794 { "ADCL", NULL
, "AIF1CLK" },
1795 { "ADCL", NULL
, "DSP1CLK" },
1796 { "ADCL", NULL
, "DSPINTCLK" },
1798 { "ADCR", NULL
, "AIF1CLK" },
1799 { "ADCR", NULL
, "DSP1CLK" },
1800 { "ADCR", NULL
, "DSPINTCLK" },
1802 { "ADCL Mux", "ADC", "ADCL" },
1803 { "ADCL Mux", "DMIC", "DMIC1L" },
1804 { "ADCR Mux", "ADC", "ADCR" },
1805 { "ADCR Mux", "DMIC", "DMIC1R" },
1807 { "DAC1L", NULL
, "AIF1CLK" },
1808 { "DAC1L", NULL
, "DSP1CLK" },
1809 { "DAC1L", NULL
, "DSPINTCLK" },
1811 { "DAC1R", NULL
, "AIF1CLK" },
1812 { "DAC1R", NULL
, "DSP1CLK" },
1813 { "DAC1R", NULL
, "DSPINTCLK" },
1815 { "DAC2L", NULL
, "AIF2CLK" },
1816 { "DAC2L", NULL
, "DSP2CLK" },
1817 { "DAC2L", NULL
, "DSPINTCLK" },
1819 { "DAC2R", NULL
, "AIF2DACR" },
1820 { "DAC2R", NULL
, "AIF2CLK" },
1821 { "DAC2R", NULL
, "DSP2CLK" },
1822 { "DAC2R", NULL
, "DSPINTCLK" },
1824 { "TOCLK", NULL
, "CLK_SYS" },
1826 { "AIF1DACDAT", NULL
, "AIF1 Playback" },
1827 { "AIF2DACDAT", NULL
, "AIF2 Playback" },
1828 { "AIF3DACDAT", NULL
, "AIF3 Playback" },
1830 { "AIF1 Capture", NULL
, "AIF1ADCDAT" },
1831 { "AIF2 Capture", NULL
, "AIF2ADCDAT" },
1832 { "AIF3 Capture", NULL
, "AIF3ADCDAT" },
1835 { "AIF1ADC1L", NULL
, "AIF1ADC1L Mixer" },
1836 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1837 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1839 { "AIF1ADC1R", NULL
, "AIF1ADC1R Mixer" },
1840 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1841 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1843 { "AIF1ADC2L", NULL
, "AIF1ADC2L Mixer" },
1844 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1845 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1847 { "AIF1ADC2R", NULL
, "AIF1ADC2R Mixer" },
1848 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1849 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1851 /* Pin level routing for AIF3 */
1852 { "AIF1DAC1L", NULL
, "AIF1DAC Mux" },
1853 { "AIF1DAC1R", NULL
, "AIF1DAC Mux" },
1854 { "AIF1DAC2L", NULL
, "AIF1DAC Mux" },
1855 { "AIF1DAC2R", NULL
, "AIF1DAC Mux" },
1857 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1858 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1859 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1860 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1861 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1862 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1863 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1866 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1867 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1868 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1869 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1870 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1872 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1873 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1874 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1875 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1876 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1878 /* DAC2/AIF2 outputs */
1879 { "AIF2ADCL", NULL
, "AIF2DAC2L Mixer" },
1880 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1881 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1882 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1883 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1884 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1886 { "AIF2ADCR", NULL
, "AIF2DAC2R Mixer" },
1887 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1888 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1889 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1890 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1891 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1893 { "AIF1ADCDAT", NULL
, "AIF1ADC1L" },
1894 { "AIF1ADCDAT", NULL
, "AIF1ADC1R" },
1895 { "AIF1ADCDAT", NULL
, "AIF1ADC2L" },
1896 { "AIF1ADCDAT", NULL
, "AIF1ADC2R" },
1898 { "AIF2ADCDAT", NULL
, "AIF2ADC Mux" },
1901 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1902 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1903 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1904 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1905 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1906 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1907 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1908 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1911 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1912 { "Left Sidetone", "DMIC2", "DMIC2L" },
1913 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1914 { "Right Sidetone", "DMIC2", "DMIC2R" },
1917 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1918 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1920 { "SPKL", "DAC1 Switch", "DAC1L" },
1921 { "SPKL", "DAC2 Switch", "DAC2L" },
1923 { "SPKR", "DAC1 Switch", "DAC1R" },
1924 { "SPKR", "DAC2 Switch", "DAC2R" },
1926 { "Left Headphone Mux", "DAC", "DAC1L" },
1927 { "Right Headphone Mux", "DAC", "DAC1R" },
1930 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon
[] = {
1931 { "DAC1L", NULL
, "Late DAC1L Enable PGA" },
1932 { "Late DAC1L Enable PGA", NULL
, "DAC1L Mixer" },
1933 { "DAC1R", NULL
, "Late DAC1R Enable PGA" },
1934 { "Late DAC1R Enable PGA", NULL
, "DAC1R Mixer" },
1935 { "DAC2L", NULL
, "Late DAC2L Enable PGA" },
1936 { "Late DAC2L Enable PGA", NULL
, "AIF2DAC2L Mixer" },
1937 { "DAC2R", NULL
, "Late DAC2R Enable PGA" },
1938 { "Late DAC2R Enable PGA", NULL
, "AIF2DAC2R Mixer" }
1941 static const struct snd_soc_dapm_route wm8994_lateclk_intercon
[] = {
1942 { "DAC1L", NULL
, "DAC1L Mixer" },
1943 { "DAC1R", NULL
, "DAC1R Mixer" },
1944 { "DAC2L", NULL
, "AIF2DAC2L Mixer" },
1945 { "DAC2R", NULL
, "AIF2DAC2R Mixer" },
1948 static const struct snd_soc_dapm_route wm8994_revd_intercon
[] = {
1949 { "AIF1DACDAT", NULL
, "AIF2DACDAT" },
1950 { "AIF2DACDAT", NULL
, "AIF1DACDAT" },
1951 { "AIF1ADCDAT", NULL
, "AIF2ADCDAT" },
1952 { "AIF2ADCDAT", NULL
, "AIF1ADCDAT" },
1953 { "MICBIAS1", NULL
, "CLK_SYS" },
1954 { "MICBIAS1", NULL
, "MICBIAS Supply" },
1955 { "MICBIAS2", NULL
, "CLK_SYS" },
1956 { "MICBIAS2", NULL
, "MICBIAS Supply" },
1959 static const struct snd_soc_dapm_route wm8994_intercon
[] = {
1960 { "AIF2DACL", NULL
, "AIF2DAC Mux" },
1961 { "AIF2DACR", NULL
, "AIF2DAC Mux" },
1962 { "MICBIAS1", NULL
, "VMID" },
1963 { "MICBIAS2", NULL
, "VMID" },
1966 static const struct snd_soc_dapm_route wm8958_intercon
[] = {
1967 { "AIF2DACL", NULL
, "AIF2DACL Mux" },
1968 { "AIF2DACR", NULL
, "AIF2DACR Mux" },
1970 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1971 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1972 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1973 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1975 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1976 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1978 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1981 /* The size in bits of the FLL divide multiplied by 10
1982 * to allow rounding later */
1983 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1993 static int wm8994_get_fll_config(struct fll_div
*fll
,
1994 int freq_in
, int freq_out
)
1997 unsigned int K
, Ndiv
, Nmod
;
1999 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in
, freq_out
);
2001 /* Scale the input frequency down to <= 13.5MHz */
2002 fll
->clk_ref_div
= 0;
2003 while (freq_in
> 13500000) {
2007 if (fll
->clk_ref_div
> 3)
2010 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll
->clk_ref_div
, freq_in
);
2012 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2014 while (freq_out
* (fll
->outdiv
+ 1) < 90000000) {
2016 if (fll
->outdiv
> 63)
2019 freq_out
*= fll
->outdiv
+ 1;
2020 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll
->outdiv
, freq_out
);
2022 if (freq_in
> 1000000) {
2023 fll
->fll_fratio
= 0;
2024 } else if (freq_in
> 256000) {
2025 fll
->fll_fratio
= 1;
2027 } else if (freq_in
> 128000) {
2028 fll
->fll_fratio
= 2;
2030 } else if (freq_in
> 64000) {
2031 fll
->fll_fratio
= 3;
2034 fll
->fll_fratio
= 4;
2037 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll
->fll_fratio
, freq_in
);
2039 /* Now, calculate N.K */
2040 Ndiv
= freq_out
/ freq_in
;
2043 Nmod
= freq_out
% freq_in
;
2044 pr_debug("Nmod=%d\n", Nmod
);
2046 /* Calculate fractional part - scale up so we can round. */
2047 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
2049 do_div(Kpart
, freq_in
);
2051 K
= Kpart
& 0xFFFFFFFF;
2056 /* Move down to proper range now rounding is done */
2059 pr_debug("N=%x K=%x\n", fll
->n
, fll
->k
);
2064 static int _wm8994_set_fll(struct snd_soc_codec
*codec
, int id
, int src
,
2065 unsigned int freq_in
, unsigned int freq_out
)
2067 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2068 struct wm8994
*control
= wm8994
->wm8994
;
2069 int reg_offset
, ret
;
2071 u16 reg
, aif1
, aif2
;
2072 unsigned long timeout
;
2075 aif1
= snd_soc_read(codec
, WM8994_AIF1_CLOCKING_1
)
2076 & WM8994_AIF1CLK_ENA
;
2078 aif2
= snd_soc_read(codec
, WM8994_AIF2_CLOCKING_1
)
2079 & WM8994_AIF2CLK_ENA
;
2094 reg
= snd_soc_read(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
);
2095 was_enabled
= reg
& WM8994_FLL1_ENA
;
2099 /* Allow no source specification when stopping */
2102 src
= wm8994
->fll
[id
].src
;
2104 case WM8994_FLL_SRC_MCLK1
:
2105 case WM8994_FLL_SRC_MCLK2
:
2106 case WM8994_FLL_SRC_LRCLK
:
2107 case WM8994_FLL_SRC_BCLK
:
2113 /* Are we changing anything? */
2114 if (wm8994
->fll
[id
].src
== src
&&
2115 wm8994
->fll
[id
].in
== freq_in
&& wm8994
->fll
[id
].out
== freq_out
)
2118 /* If we're stopping the FLL redo the old config - no
2119 * registers will actually be written but we avoid GCC flow
2120 * analysis bugs spewing warnings.
2123 ret
= wm8994_get_fll_config(&fll
, freq_in
, freq_out
);
2125 ret
= wm8994_get_fll_config(&fll
, wm8994
->fll
[id
].in
,
2126 wm8994
->fll
[id
].out
);
2130 /* Gate the AIF clocks while we reclock */
2131 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
2132 WM8994_AIF1CLK_ENA
, 0);
2133 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
2134 WM8994_AIF2CLK_ENA
, 0);
2136 /* We always need to disable the FLL while reconfiguring */
2137 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
2138 WM8994_FLL1_ENA
, 0);
2140 reg
= (fll
.outdiv
<< WM8994_FLL1_OUTDIV_SHIFT
) |
2141 (fll
.fll_fratio
<< WM8994_FLL1_FRATIO_SHIFT
);
2142 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_2
+ reg_offset
,
2143 WM8994_FLL1_OUTDIV_MASK
|
2144 WM8994_FLL1_FRATIO_MASK
, reg
);
2146 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_3
+ reg_offset
,
2147 WM8994_FLL1_K_MASK
, fll
.k
);
2149 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_4
+ reg_offset
,
2151 fll
.n
<< WM8994_FLL1_N_SHIFT
);
2153 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_5
+ reg_offset
,
2154 WM8994_FLL1_REFCLK_DIV_MASK
|
2155 WM8994_FLL1_REFCLK_SRC_MASK
,
2156 (fll
.clk_ref_div
<< WM8994_FLL1_REFCLK_DIV_SHIFT
) |
2159 /* Clear any pending completion from a previous failure */
2160 try_wait_for_completion(&wm8994
->fll_locked
[id
]);
2162 /* Enable (with fractional mode if required) */
2164 /* Enable VMID if we need it */
2166 active_reference(codec
);
2168 switch (control
->type
) {
2170 vmid_reference(codec
);
2173 if (wm8994
->revision
< 1)
2174 vmid_reference(codec
);
2182 reg
= WM8994_FLL1_ENA
| WM8994_FLL1_FRAC
;
2184 reg
= WM8994_FLL1_ENA
;
2185 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
2186 WM8994_FLL1_ENA
| WM8994_FLL1_FRAC
,
2189 if (wm8994
->fll_locked_irq
) {
2190 timeout
= wait_for_completion_timeout(&wm8994
->fll_locked
[id
],
2191 msecs_to_jiffies(10));
2193 dev_warn(codec
->dev
,
2194 "Timed out waiting for FLL lock\n");
2200 switch (control
->type
) {
2202 vmid_dereference(codec
);
2205 if (wm8994
->revision
< 1)
2206 vmid_dereference(codec
);
2212 active_dereference(codec
);
2216 wm8994
->fll
[id
].in
= freq_in
;
2217 wm8994
->fll
[id
].out
= freq_out
;
2218 wm8994
->fll
[id
].src
= src
;
2220 /* Enable any gated AIF clocks */
2221 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
2222 WM8994_AIF1CLK_ENA
, aif1
);
2223 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
2224 WM8994_AIF2CLK_ENA
, aif2
);
2226 configure_clock(codec
);
2231 static irqreturn_t
wm8994_fll_locked_irq(int irq
, void *data
)
2233 struct completion
*completion
= data
;
2235 complete(completion
);
2240 static int opclk_divs
[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2242 static int wm8994_set_fll(struct snd_soc_dai
*dai
, int id
, int src
,
2243 unsigned int freq_in
, unsigned int freq_out
)
2245 return _wm8994_set_fll(dai
->codec
, id
, src
, freq_in
, freq_out
);
2248 static int wm8994_set_dai_sysclk(struct snd_soc_dai
*dai
,
2249 int clk_id
, unsigned int freq
, int dir
)
2251 struct snd_soc_codec
*codec
= dai
->codec
;
2252 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2261 /* AIF3 shares clocking with AIF1/2 */
2266 case WM8994_SYSCLK_MCLK1
:
2267 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK1
;
2268 wm8994
->mclk
[0] = freq
;
2269 dev_dbg(dai
->dev
, "AIF%d using MCLK1 at %uHz\n",
2273 case WM8994_SYSCLK_MCLK2
:
2274 /* TODO: Set GPIO AF */
2275 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK2
;
2276 wm8994
->mclk
[1] = freq
;
2277 dev_dbg(dai
->dev
, "AIF%d using MCLK2 at %uHz\n",
2281 case WM8994_SYSCLK_FLL1
:
2282 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL1
;
2283 dev_dbg(dai
->dev
, "AIF%d using FLL1\n", dai
->id
);
2286 case WM8994_SYSCLK_FLL2
:
2287 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL2
;
2288 dev_dbg(dai
->dev
, "AIF%d using FLL2\n", dai
->id
);
2291 case WM8994_SYSCLK_OPCLK
:
2292 /* Special case - a division (times 10) is given and
2293 * no effect on main clocking.
2296 for (i
= 0; i
< ARRAY_SIZE(opclk_divs
); i
++)
2297 if (opclk_divs
[i
] == freq
)
2299 if (i
== ARRAY_SIZE(opclk_divs
))
2301 snd_soc_update_bits(codec
, WM8994_CLOCKING_2
,
2302 WM8994_OPCLK_DIV_MASK
, i
);
2303 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
2304 WM8994_OPCLK_ENA
, WM8994_OPCLK_ENA
);
2306 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
2307 WM8994_OPCLK_ENA
, 0);
2314 configure_clock(codec
);
2319 static int wm8994_set_bias_level(struct snd_soc_codec
*codec
,
2320 enum snd_soc_bias_level level
)
2322 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2323 struct wm8994
*control
= wm8994
->wm8994
;
2325 wm_hubs_set_bias_level(codec
, level
);
2328 case SND_SOC_BIAS_ON
:
2331 case SND_SOC_BIAS_PREPARE
:
2332 /* MICBIAS into regulating mode */
2333 switch (control
->type
) {
2336 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
2337 WM8958_MICB1_MODE
, 0);
2338 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
2339 WM8958_MICB2_MODE
, 0);
2345 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_STANDBY
)
2346 active_reference(codec
);
2349 case SND_SOC_BIAS_STANDBY
:
2350 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
2351 switch (control
->type
) {
2353 if (wm8994
->revision
== 0) {
2354 /* Optimise performance for rev A */
2355 snd_soc_update_bits(codec
,
2356 WM8958_CHARGE_PUMP_2
,
2366 /* Discharge LINEOUT1 & 2 */
2367 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
2368 WM8994_LINEOUT1_DISCH
|
2369 WM8994_LINEOUT2_DISCH
,
2370 WM8994_LINEOUT1_DISCH
|
2371 WM8994_LINEOUT2_DISCH
);
2374 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_PREPARE
)
2375 active_dereference(codec
);
2377 /* MICBIAS into bypass mode on newer devices */
2378 switch (control
->type
) {
2381 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
2384 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
2393 case SND_SOC_BIAS_OFF
:
2394 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_STANDBY
)
2395 wm8994
->cur_fw
= NULL
;
2399 codec
->dapm
.bias_level
= level
;
2404 int wm8994_vmid_mode(struct snd_soc_codec
*codec
, enum wm8994_vmid_mode mode
)
2406 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2409 case WM8994_VMID_NORMAL
:
2410 if (wm8994
->hubs
.lineout1_se
) {
2411 snd_soc_dapm_disable_pin(&codec
->dapm
,
2412 "LINEOUT1N Driver");
2413 snd_soc_dapm_disable_pin(&codec
->dapm
,
2414 "LINEOUT1P Driver");
2416 if (wm8994
->hubs
.lineout2_se
) {
2417 snd_soc_dapm_disable_pin(&codec
->dapm
,
2418 "LINEOUT2N Driver");
2419 snd_soc_dapm_disable_pin(&codec
->dapm
,
2420 "LINEOUT2P Driver");
2423 /* Do the sync with the old mode to allow it to clean up */
2424 snd_soc_dapm_sync(&codec
->dapm
);
2425 wm8994
->vmid_mode
= mode
;
2428 case WM8994_VMID_FORCE
:
2429 if (wm8994
->hubs
.lineout1_se
) {
2430 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
2431 "LINEOUT1N Driver");
2432 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
2433 "LINEOUT1P Driver");
2435 if (wm8994
->hubs
.lineout2_se
) {
2436 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
2437 "LINEOUT2N Driver");
2438 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
2439 "LINEOUT2P Driver");
2442 wm8994
->vmid_mode
= mode
;
2443 snd_soc_dapm_sync(&codec
->dapm
);
2453 static int wm8994_set_dai_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
2455 struct snd_soc_codec
*codec
= dai
->codec
;
2456 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2457 struct wm8994
*control
= wm8994
->wm8994
;
2465 ms_reg
= WM8994_AIF1_MASTER_SLAVE
;
2466 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2469 ms_reg
= WM8994_AIF2_MASTER_SLAVE
;
2470 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2476 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
2477 case SND_SOC_DAIFMT_CBS_CFS
:
2479 case SND_SOC_DAIFMT_CBM_CFM
:
2480 ms
= WM8994_AIF1_MSTR
;
2486 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2487 case SND_SOC_DAIFMT_DSP_B
:
2488 aif1
|= WM8994_AIF1_LRCLK_INV
;
2489 case SND_SOC_DAIFMT_DSP_A
:
2492 case SND_SOC_DAIFMT_I2S
:
2495 case SND_SOC_DAIFMT_RIGHT_J
:
2497 case SND_SOC_DAIFMT_LEFT_J
:
2504 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
2505 case SND_SOC_DAIFMT_DSP_A
:
2506 case SND_SOC_DAIFMT_DSP_B
:
2507 /* frame inversion not valid for DSP modes */
2508 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2509 case SND_SOC_DAIFMT_NB_NF
:
2511 case SND_SOC_DAIFMT_IB_NF
:
2512 aif1
|= WM8994_AIF1_BCLK_INV
;
2519 case SND_SOC_DAIFMT_I2S
:
2520 case SND_SOC_DAIFMT_RIGHT_J
:
2521 case SND_SOC_DAIFMT_LEFT_J
:
2522 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2523 case SND_SOC_DAIFMT_NB_NF
:
2525 case SND_SOC_DAIFMT_IB_IF
:
2526 aif1
|= WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
;
2528 case SND_SOC_DAIFMT_IB_NF
:
2529 aif1
|= WM8994_AIF1_BCLK_INV
;
2531 case SND_SOC_DAIFMT_NB_IF
:
2532 aif1
|= WM8994_AIF1_LRCLK_INV
;
2542 /* The AIF2 format configuration needs to be mirrored to AIF3
2543 * on WM8958 if it's in use so just do it all the time. */
2544 switch (control
->type
) {
2548 snd_soc_update_bits(codec
, WM8958_AIF3_CONTROL_1
,
2549 WM8994_AIF1_LRCLK_INV
|
2550 WM8958_AIF3_FMT_MASK
, aif1
);
2557 snd_soc_update_bits(codec
, aif1_reg
,
2558 WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
|
2559 WM8994_AIF1_FMT_MASK
,
2561 snd_soc_update_bits(codec
, ms_reg
, WM8994_AIF1_MSTR
,
2583 static int fs_ratios
[] = {
2584 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2587 static int bclk_divs
[] = {
2588 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2589 640, 880, 960, 1280, 1760, 1920
2592 static int wm8994_hw_params(struct snd_pcm_substream
*substream
,
2593 struct snd_pcm_hw_params
*params
,
2594 struct snd_soc_dai
*dai
)
2596 struct snd_soc_codec
*codec
= dai
->codec
;
2597 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2608 int id
= dai
->id
- 1;
2610 int i
, cur_val
, best_val
, bclk_rate
, best
;
2614 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2615 aif2_reg
= WM8994_AIF1_CONTROL_2
;
2616 bclk_reg
= WM8994_AIF1_BCLK
;
2617 rate_reg
= WM8994_AIF1_RATE
;
2618 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2619 wm8994
->lrclk_shared
[0]) {
2620 lrclk_reg
= WM8994_AIF1DAC_LRCLK
;
2622 lrclk_reg
= WM8994_AIF1ADC_LRCLK
;
2623 dev_dbg(codec
->dev
, "AIF1 using split LRCLK\n");
2627 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2628 aif2_reg
= WM8994_AIF2_CONTROL_2
;
2629 bclk_reg
= WM8994_AIF2_BCLK
;
2630 rate_reg
= WM8994_AIF2_RATE
;
2631 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2632 wm8994
->lrclk_shared
[1]) {
2633 lrclk_reg
= WM8994_AIF2DAC_LRCLK
;
2635 lrclk_reg
= WM8994_AIF2ADC_LRCLK
;
2636 dev_dbg(codec
->dev
, "AIF2 using split LRCLK\n");
2643 bclk_rate
= params_rate(params
) * 2;
2644 switch (params_format(params
)) {
2645 case SNDRV_PCM_FORMAT_S16_LE
:
2648 case SNDRV_PCM_FORMAT_S20_3LE
:
2652 case SNDRV_PCM_FORMAT_S24_LE
:
2656 case SNDRV_PCM_FORMAT_S32_LE
:
2664 /* Try to find an appropriate sample rate; look for an exact match. */
2665 for (i
= 0; i
< ARRAY_SIZE(srs
); i
++)
2666 if (srs
[i
].rate
== params_rate(params
))
2668 if (i
== ARRAY_SIZE(srs
))
2670 rate_val
|= srs
[i
].val
<< WM8994_AIF1_SR_SHIFT
;
2672 dev_dbg(dai
->dev
, "Sample rate is %dHz\n", srs
[i
].rate
);
2673 dev_dbg(dai
->dev
, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2674 dai
->id
, wm8994
->aifclk
[id
], bclk_rate
);
2676 if (params_channels(params
) == 1 &&
2677 (snd_soc_read(codec
, aif1_reg
) & 0x18) == 0x18)
2678 aif2
|= WM8994_AIF1_MONO
;
2680 if (wm8994
->aifclk
[id
] == 0) {
2681 dev_err(dai
->dev
, "AIF%dCLK not configured\n", dai
->id
);
2685 /* AIFCLK/fs ratio; look for a close match in either direction */
2687 best_val
= abs((fs_ratios
[0] * params_rate(params
))
2688 - wm8994
->aifclk
[id
]);
2689 for (i
= 1; i
< ARRAY_SIZE(fs_ratios
); i
++) {
2690 cur_val
= abs((fs_ratios
[i
] * params_rate(params
))
2691 - wm8994
->aifclk
[id
]);
2692 if (cur_val
>= best_val
)
2697 dev_dbg(dai
->dev
, "Selected AIF%dCLK/fs = %d\n",
2698 dai
->id
, fs_ratios
[best
]);
2701 /* We may not get quite the right frequency if using
2702 * approximate clocks so look for the closest match that is
2703 * higher than the target (we need to ensure that there enough
2704 * BCLKs to clock out the samples).
2707 for (i
= 0; i
< ARRAY_SIZE(bclk_divs
); i
++) {
2708 cur_val
= (wm8994
->aifclk
[id
] * 10 / bclk_divs
[i
]) - bclk_rate
;
2709 if (cur_val
< 0) /* BCLK table is sorted */
2713 bclk_rate
= wm8994
->aifclk
[id
] * 10 / bclk_divs
[best
];
2714 dev_dbg(dai
->dev
, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2715 bclk_divs
[best
], bclk_rate
);
2716 bclk
|= best
<< WM8994_AIF1_BCLK_DIV_SHIFT
;
2718 lrclk
= bclk_rate
/ params_rate(params
);
2720 dev_err(dai
->dev
, "Unable to generate LRCLK from %dHz BCLK\n",
2724 dev_dbg(dai
->dev
, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2725 lrclk
, bclk_rate
/ lrclk
);
2727 snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2728 snd_soc_update_bits(codec
, aif2_reg
, WM8994_AIF1_MONO
, aif2
);
2729 snd_soc_update_bits(codec
, bclk_reg
, WM8994_AIF1_BCLK_DIV_MASK
, bclk
);
2730 snd_soc_update_bits(codec
, lrclk_reg
, WM8994_AIF1DAC_RATE_MASK
,
2732 snd_soc_update_bits(codec
, rate_reg
, WM8994_AIF1_SR_MASK
|
2733 WM8994_AIF1CLK_RATE_MASK
, rate_val
);
2735 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
2738 wm8994
->dac_rates
[0] = params_rate(params
);
2739 wm8994_set_retune_mobile(codec
, 0);
2740 wm8994_set_retune_mobile(codec
, 1);
2743 wm8994
->dac_rates
[1] = params_rate(params
);
2744 wm8994_set_retune_mobile(codec
, 2);
2752 static int wm8994_aif3_hw_params(struct snd_pcm_substream
*substream
,
2753 struct snd_pcm_hw_params
*params
,
2754 struct snd_soc_dai
*dai
)
2756 struct snd_soc_codec
*codec
= dai
->codec
;
2757 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2758 struct wm8994
*control
= wm8994
->wm8994
;
2764 switch (control
->type
) {
2767 aif1_reg
= WM8958_AIF3_CONTROL_1
;
2776 switch (params_format(params
)) {
2777 case SNDRV_PCM_FORMAT_S16_LE
:
2779 case SNDRV_PCM_FORMAT_S20_3LE
:
2782 case SNDRV_PCM_FORMAT_S24_LE
:
2785 case SNDRV_PCM_FORMAT_S32_LE
:
2792 return snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2795 static void wm8994_aif_shutdown(struct snd_pcm_substream
*substream
,
2796 struct snd_soc_dai
*dai
)
2798 struct snd_soc_codec
*codec
= dai
->codec
;
2803 rate_reg
= WM8994_AIF1_RATE
;
2806 rate_reg
= WM8994_AIF2_RATE
;
2812 /* If the DAI is idle then configure the divider tree for the
2813 * lowest output rate to save a little power if the clock is
2814 * still active (eg, because it is system clock).
2816 if (rate_reg
&& !dai
->playback_active
&& !dai
->capture_active
)
2817 snd_soc_update_bits(codec
, rate_reg
,
2818 WM8994_AIF1_SR_MASK
|
2819 WM8994_AIF1CLK_RATE_MASK
, 0x9);
2822 static int wm8994_aif_mute(struct snd_soc_dai
*codec_dai
, int mute
)
2824 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2828 switch (codec_dai
->id
) {
2830 mute_reg
= WM8994_AIF1_DAC1_FILTERS_1
;
2833 mute_reg
= WM8994_AIF2_DAC_FILTERS_1
;
2840 reg
= WM8994_AIF1DAC1_MUTE
;
2844 snd_soc_update_bits(codec
, mute_reg
, WM8994_AIF1DAC1_MUTE
, reg
);
2849 static int wm8994_set_tristate(struct snd_soc_dai
*codec_dai
, int tristate
)
2851 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2854 switch (codec_dai
->id
) {
2856 reg
= WM8994_AIF1_MASTER_SLAVE
;
2857 mask
= WM8994_AIF1_TRI
;
2860 reg
= WM8994_AIF2_MASTER_SLAVE
;
2861 mask
= WM8994_AIF2_TRI
;
2864 reg
= WM8994_POWER_MANAGEMENT_6
;
2865 mask
= WM8994_AIF3_TRI
;
2876 return snd_soc_update_bits(codec
, reg
, mask
, val
);
2879 static int wm8994_aif2_probe(struct snd_soc_dai
*dai
)
2881 struct snd_soc_codec
*codec
= dai
->codec
;
2883 /* Disable the pulls on the AIF if we're using it to save power. */
2884 snd_soc_update_bits(codec
, WM8994_GPIO_3
,
2885 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
2886 snd_soc_update_bits(codec
, WM8994_GPIO_4
,
2887 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
2888 snd_soc_update_bits(codec
, WM8994_GPIO_5
,
2889 WM8994_GPN_PU
| WM8994_GPN_PD
, 0);
2894 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2896 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2897 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2899 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops
= {
2900 .set_sysclk
= wm8994_set_dai_sysclk
,
2901 .set_fmt
= wm8994_set_dai_fmt
,
2902 .hw_params
= wm8994_hw_params
,
2903 .shutdown
= wm8994_aif_shutdown
,
2904 .digital_mute
= wm8994_aif_mute
,
2905 .set_pll
= wm8994_set_fll
,
2906 .set_tristate
= wm8994_set_tristate
,
2909 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops
= {
2910 .set_sysclk
= wm8994_set_dai_sysclk
,
2911 .set_fmt
= wm8994_set_dai_fmt
,
2912 .hw_params
= wm8994_hw_params
,
2913 .shutdown
= wm8994_aif_shutdown
,
2914 .digital_mute
= wm8994_aif_mute
,
2915 .set_pll
= wm8994_set_fll
,
2916 .set_tristate
= wm8994_set_tristate
,
2919 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops
= {
2920 .hw_params
= wm8994_aif3_hw_params
,
2921 .set_tristate
= wm8994_set_tristate
,
2924 static struct snd_soc_dai_driver wm8994_dai
[] = {
2926 .name
= "wm8994-aif1",
2929 .stream_name
= "AIF1 Playback",
2932 .rates
= WM8994_RATES
,
2933 .formats
= WM8994_FORMATS
,
2937 .stream_name
= "AIF1 Capture",
2940 .rates
= WM8994_RATES
,
2941 .formats
= WM8994_FORMATS
,
2944 .ops
= &wm8994_aif1_dai_ops
,
2947 .name
= "wm8994-aif2",
2950 .stream_name
= "AIF2 Playback",
2953 .rates
= WM8994_RATES
,
2954 .formats
= WM8994_FORMATS
,
2958 .stream_name
= "AIF2 Capture",
2961 .rates
= WM8994_RATES
,
2962 .formats
= WM8994_FORMATS
,
2965 .probe
= wm8994_aif2_probe
,
2966 .ops
= &wm8994_aif2_dai_ops
,
2969 .name
= "wm8994-aif3",
2972 .stream_name
= "AIF3 Playback",
2975 .rates
= WM8994_RATES
,
2976 .formats
= WM8994_FORMATS
,
2980 .stream_name
= "AIF3 Capture",
2983 .rates
= WM8994_RATES
,
2984 .formats
= WM8994_FORMATS
,
2987 .ops
= &wm8994_aif3_dai_ops
,
2992 static int wm8994_codec_suspend(struct snd_soc_codec
*codec
)
2994 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2995 struct wm8994
*control
= wm8994
->wm8994
;
2998 switch (control
->type
) {
3000 snd_soc_update_bits(codec
, WM8994_MICBIAS
, WM8994_MICD_ENA
, 0);
3003 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
3004 WM1811_JACKDET_MODE_MASK
, 0);
3007 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3008 WM8958_MICD_ENA
, 0);
3012 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
3013 memcpy(&wm8994
->fll_suspend
[i
], &wm8994
->fll
[i
],
3014 sizeof(struct wm8994_fll_config
));
3015 ret
= _wm8994_set_fll(codec
, i
+ 1, 0, 0, 0);
3017 dev_warn(codec
->dev
, "Failed to stop FLL%d: %d\n",
3021 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
3026 static int wm8994_codec_resume(struct snd_soc_codec
*codec
)
3028 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3029 struct wm8994
*control
= wm8994
->wm8994
;
3031 unsigned int val
, mask
;
3033 if (wm8994
->revision
< 4) {
3034 /* force a HW read */
3035 ret
= regmap_read(control
->regmap
,
3036 WM8994_POWER_MANAGEMENT_5
, &val
);
3038 /* modify the cache only */
3039 codec
->cache_only
= 1;
3040 mask
= WM8994_DAC1R_ENA
| WM8994_DAC1L_ENA
|
3041 WM8994_DAC2R_ENA
| WM8994_DAC2L_ENA
;
3043 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
3045 codec
->cache_only
= 0;
3048 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
3049 if (!wm8994
->fll_suspend
[i
].out
)
3052 ret
= _wm8994_set_fll(codec
, i
+ 1,
3053 wm8994
->fll_suspend
[i
].src
,
3054 wm8994
->fll_suspend
[i
].in
,
3055 wm8994
->fll_suspend
[i
].out
);
3057 dev_warn(codec
->dev
, "Failed to restore FLL%d: %d\n",
3061 switch (control
->type
) {
3063 if (wm8994
->micdet
[0].jack
|| wm8994
->micdet
[1].jack
)
3064 snd_soc_update_bits(codec
, WM8994_MICBIAS
,
3065 WM8994_MICD_ENA
, WM8994_MICD_ENA
);
3068 if (wm8994
->jackdet
&& wm8994
->jack_cb
) {
3069 /* Restart from idle */
3070 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
3071 WM1811_JACKDET_MODE_MASK
,
3072 WM1811_JACKDET_MODE_JACK
);
3077 if (wm8994
->jack_cb
)
3078 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3079 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
3086 #define wm8994_codec_suspend NULL
3087 #define wm8994_codec_resume NULL
3090 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv
*wm8994
)
3092 struct snd_soc_codec
*codec
= wm8994
->codec
;
3093 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
3094 struct snd_kcontrol_new controls
[] = {
3095 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3096 wm8994
->retune_mobile_enum
,
3097 wm8994_get_retune_mobile_enum
,
3098 wm8994_put_retune_mobile_enum
),
3099 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3100 wm8994
->retune_mobile_enum
,
3101 wm8994_get_retune_mobile_enum
,
3102 wm8994_put_retune_mobile_enum
),
3103 SOC_ENUM_EXT("AIF2 EQ Mode",
3104 wm8994
->retune_mobile_enum
,
3105 wm8994_get_retune_mobile_enum
,
3106 wm8994_put_retune_mobile_enum
),
3111 /* We need an array of texts for the enum API but the number
3112 * of texts is likely to be less than the number of
3113 * configurations due to the sample rate dependency of the
3114 * configurations. */
3115 wm8994
->num_retune_mobile_texts
= 0;
3116 wm8994
->retune_mobile_texts
= NULL
;
3117 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
3118 for (j
= 0; j
< wm8994
->num_retune_mobile_texts
; j
++) {
3119 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
3120 wm8994
->retune_mobile_texts
[j
]) == 0)
3124 if (j
!= wm8994
->num_retune_mobile_texts
)
3127 /* Expand the array... */
3128 t
= krealloc(wm8994
->retune_mobile_texts
,
3130 (wm8994
->num_retune_mobile_texts
+ 1),
3135 /* ...store the new entry... */
3136 t
[wm8994
->num_retune_mobile_texts
] =
3137 pdata
->retune_mobile_cfgs
[i
].name
;
3139 /* ...and remember the new version. */
3140 wm8994
->num_retune_mobile_texts
++;
3141 wm8994
->retune_mobile_texts
= t
;
3144 dev_dbg(codec
->dev
, "Allocated %d unique ReTune Mobile names\n",
3145 wm8994
->num_retune_mobile_texts
);
3147 wm8994
->retune_mobile_enum
.max
= wm8994
->num_retune_mobile_texts
;
3148 wm8994
->retune_mobile_enum
.texts
= wm8994
->retune_mobile_texts
;
3150 ret
= snd_soc_add_codec_controls(wm8994
->codec
, controls
,
3151 ARRAY_SIZE(controls
));
3153 dev_err(wm8994
->codec
->dev
,
3154 "Failed to add ReTune Mobile controls: %d\n", ret
);
3157 static void wm8994_handle_pdata(struct wm8994_priv
*wm8994
)
3159 struct snd_soc_codec
*codec
= wm8994
->codec
;
3160 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
3166 wm_hubs_handle_analogue_pdata(codec
, pdata
->lineout1_diff
,
3167 pdata
->lineout2_diff
,
3172 pdata
->micbias1_lvl
,
3173 pdata
->micbias2_lvl
);
3175 dev_dbg(codec
->dev
, "%d DRC configurations\n", pdata
->num_drc_cfgs
);
3177 if (pdata
->num_drc_cfgs
) {
3178 struct snd_kcontrol_new controls
[] = {
3179 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994
->drc_enum
,
3180 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
3181 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994
->drc_enum
,
3182 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
3183 SOC_ENUM_EXT("AIF2DRC Mode", wm8994
->drc_enum
,
3184 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
3187 /* We need an array of texts for the enum API */
3188 wm8994
->drc_texts
= devm_kzalloc(wm8994
->codec
->dev
,
3189 sizeof(char *) * pdata
->num_drc_cfgs
, GFP_KERNEL
);
3190 if (!wm8994
->drc_texts
) {
3191 dev_err(wm8994
->codec
->dev
,
3192 "Failed to allocate %d DRC config texts\n",
3193 pdata
->num_drc_cfgs
);
3197 for (i
= 0; i
< pdata
->num_drc_cfgs
; i
++)
3198 wm8994
->drc_texts
[i
] = pdata
->drc_cfgs
[i
].name
;
3200 wm8994
->drc_enum
.max
= pdata
->num_drc_cfgs
;
3201 wm8994
->drc_enum
.texts
= wm8994
->drc_texts
;
3203 ret
= snd_soc_add_codec_controls(wm8994
->codec
, controls
,
3204 ARRAY_SIZE(controls
));
3206 dev_err(wm8994
->codec
->dev
,
3207 "Failed to add DRC mode controls: %d\n", ret
);
3209 for (i
= 0; i
< WM8994_NUM_DRC
; i
++)
3210 wm8994_set_drc(codec
, i
);
3213 dev_dbg(codec
->dev
, "%d ReTune Mobile configurations\n",
3214 pdata
->num_retune_mobile_cfgs
);
3216 if (pdata
->num_retune_mobile_cfgs
)
3217 wm8994_handle_retune_mobile_pdata(wm8994
);
3219 snd_soc_add_codec_controls(wm8994
->codec
, wm8994_eq_controls
,
3220 ARRAY_SIZE(wm8994_eq_controls
));
3222 for (i
= 0; i
< ARRAY_SIZE(pdata
->micbias
); i
++) {
3223 if (pdata
->micbias
[i
]) {
3224 snd_soc_write(codec
, WM8958_MICBIAS1
+ i
,
3225 pdata
->micbias
[i
] & 0xffff);
3231 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3233 * @codec: WM8994 codec
3234 * @jack: jack to report detection events on
3235 * @micbias: microphone bias to detect on
3237 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3238 * being used to bring out signals to the processor then only platform
3239 * data configuration is needed for WM8994 and processor GPIOs should
3240 * be configured using snd_soc_jack_add_gpios() instead.
3242 * Configuration of detection levels is available via the micbias1_lvl
3243 * and micbias2_lvl platform data members.
3245 int wm8994_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
3248 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3249 struct wm8994_micdet
*micdet
;
3250 struct wm8994
*control
= wm8994
->wm8994
;
3253 if (control
->type
!= WM8994
) {
3254 dev_warn(codec
->dev
, "Not a WM8994\n");
3260 micdet
= &wm8994
->micdet
[0];
3262 ret
= snd_soc_dapm_force_enable_pin(&codec
->dapm
,
3265 ret
= snd_soc_dapm_disable_pin(&codec
->dapm
,
3269 micdet
= &wm8994
->micdet
[1];
3271 ret
= snd_soc_dapm_force_enable_pin(&codec
->dapm
,
3274 ret
= snd_soc_dapm_disable_pin(&codec
->dapm
,
3278 dev_warn(codec
->dev
, "Invalid MICBIAS %d\n", micbias
);
3283 dev_warn(codec
->dev
, "Failed to configure MICBIAS%d: %d\n",
3286 dev_dbg(codec
->dev
, "Configuring microphone detection on %d %p\n",
3289 /* Store the configuration */
3290 micdet
->jack
= jack
;
3291 micdet
->detecting
= true;
3293 /* If either of the jacks is set up then enable detection */
3294 if (wm8994
->micdet
[0].jack
|| wm8994
->micdet
[1].jack
)
3295 reg
= WM8994_MICD_ENA
;
3299 snd_soc_update_bits(codec
, WM8994_MICBIAS
, WM8994_MICD_ENA
, reg
);
3301 snd_soc_dapm_sync(&codec
->dapm
);
3305 EXPORT_SYMBOL_GPL(wm8994_mic_detect
);
3307 static irqreturn_t
wm8994_mic_irq(int irq
, void *data
)
3309 struct wm8994_priv
*priv
= data
;
3310 struct snd_soc_codec
*codec
= priv
->codec
;
3314 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3315 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
3318 reg
= snd_soc_read(codec
, WM8994_INTERRUPT_RAW_STATUS_2
);
3320 dev_err(codec
->dev
, "Failed to read microphone status: %d\n",
3325 dev_dbg(codec
->dev
, "Microphone status: %x\n", reg
);
3328 if (reg
& WM8994_MIC1_DET_STS
) {
3329 if (priv
->micdet
[0].detecting
)
3330 report
= SND_JACK_HEADSET
;
3332 if (reg
& WM8994_MIC1_SHRT_STS
) {
3333 if (priv
->micdet
[0].detecting
)
3334 report
= SND_JACK_HEADPHONE
;
3336 report
|= SND_JACK_BTN_0
;
3339 priv
->micdet
[0].detecting
= false;
3341 priv
->micdet
[0].detecting
= true;
3343 snd_soc_jack_report(priv
->micdet
[0].jack
, report
,
3344 SND_JACK_HEADSET
| SND_JACK_BTN_0
);
3347 if (reg
& WM8994_MIC2_DET_STS
) {
3348 if (priv
->micdet
[1].detecting
)
3349 report
= SND_JACK_HEADSET
;
3351 if (reg
& WM8994_MIC2_SHRT_STS
) {
3352 if (priv
->micdet
[1].detecting
)
3353 report
= SND_JACK_HEADPHONE
;
3355 report
|= SND_JACK_BTN_0
;
3358 priv
->micdet
[1].detecting
= false;
3360 priv
->micdet
[1].detecting
= true;
3362 snd_soc_jack_report(priv
->micdet
[1].jack
, report
,
3363 SND_JACK_HEADSET
| SND_JACK_BTN_0
);
3368 /* Default microphone detection handler for WM8958 - the user can
3369 * override this if they wish.
3371 static void wm8958_default_micdet(u16 status
, void *data
)
3373 struct snd_soc_codec
*codec
= data
;
3374 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3377 dev_dbg(codec
->dev
, "MICDET %x\n", status
);
3379 /* Either nothing present or just starting detection */
3380 if (!(status
& WM8958_MICD_STS
)) {
3381 if (!wm8994
->jackdet
) {
3382 /* If nothing present then clear our statuses */
3383 dev_dbg(codec
->dev
, "Detected open circuit\n");
3384 wm8994
->jack_mic
= false;
3385 wm8994
->mic_detecting
= true;
3387 wm8958_micd_set_rate(codec
);
3389 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0,
3396 /* If the measurement is showing a high impedence we've got a
3399 if (wm8994
->mic_detecting
&& (status
& 0x600)) {
3400 dev_dbg(codec
->dev
, "Detected microphone\n");
3402 wm8994
->mic_detecting
= false;
3403 wm8994
->jack_mic
= true;
3405 wm8958_micd_set_rate(codec
);
3407 snd_soc_jack_report(wm8994
->micdet
[0].jack
, SND_JACK_HEADSET
,
3412 if (wm8994
->mic_detecting
&& status
& 0xfc) {
3413 dev_dbg(codec
->dev
, "Detected headphone\n");
3414 wm8994
->mic_detecting
= false;
3416 wm8958_micd_set_rate(codec
);
3418 snd_soc_jack_report(wm8994
->micdet
[0].jack
, SND_JACK_HEADPHONE
,
3421 /* If we have jackdet that will detect removal */
3422 if (wm8994
->jackdet
) {
3423 mutex_lock(&wm8994
->accdet_lock
);
3425 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3426 WM8958_MICD_ENA
, 0);
3428 wm1811_jackdet_set_mode(codec
,
3429 WM1811_JACKDET_MODE_JACK
);
3431 mutex_unlock(&wm8994
->accdet_lock
);
3433 if (wm8994
->pdata
->jd_ext_cap
) {
3434 mutex_lock(&codec
->mutex
);
3435 snd_soc_dapm_disable_pin(&codec
->dapm
,
3437 snd_soc_dapm_sync(&codec
->dapm
);
3438 mutex_unlock(&codec
->mutex
);
3443 /* Report short circuit as a button */
3444 if (wm8994
->jack_mic
) {
3447 report
|= SND_JACK_BTN_0
;
3450 report
|= SND_JACK_BTN_1
;
3453 report
|= SND_JACK_BTN_2
;
3456 report
|= SND_JACK_BTN_3
;
3459 report
|= SND_JACK_BTN_4
;
3462 report
|= SND_JACK_BTN_5
;
3464 snd_soc_jack_report(wm8994
->micdet
[0].jack
, report
,
3469 static irqreturn_t
wm1811_jackdet_irq(int irq
, void *data
)
3471 struct wm8994_priv
*wm8994
= data
;
3472 struct snd_soc_codec
*codec
= wm8994
->codec
;
3476 mutex_lock(&wm8994
->accdet_lock
);
3478 reg
= snd_soc_read(codec
, WM1811_JACKDET_CTRL
);
3480 dev_err(codec
->dev
, "Failed to read jack status: %d\n", reg
);
3481 mutex_unlock(&wm8994
->accdet_lock
);
3485 dev_dbg(codec
->dev
, "JACKDET %x\n", reg
);
3487 present
= reg
& WM1811_JACKDET_LVL
;
3490 dev_dbg(codec
->dev
, "Jack detected\n");
3492 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
3493 WM8958_MICB2_DISCH
, 0);
3495 /* Disable debounce while inserted */
3496 snd_soc_update_bits(codec
, WM1811_JACKDET_CTRL
,
3497 WM1811_JACKDET_DB
, 0);
3500 * Start off measument of microphone impedence to find
3501 * out what's actually there.
3503 wm8994
->mic_detecting
= true;
3504 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_MIC
);
3506 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3507 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
3509 dev_dbg(codec
->dev
, "Jack not detected\n");
3511 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
3512 WM8958_MICB2_DISCH
, WM8958_MICB2_DISCH
);
3514 /* Enable debounce while removed */
3515 snd_soc_update_bits(codec
, WM1811_JACKDET_CTRL
,
3516 WM1811_JACKDET_DB
, WM1811_JACKDET_DB
);
3518 wm8994
->mic_detecting
= false;
3519 wm8994
->jack_mic
= false;
3520 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3521 WM8958_MICD_ENA
, 0);
3522 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_JACK
);
3525 mutex_unlock(&wm8994
->accdet_lock
);
3527 /* If required for an external cap force MICBIAS on */
3528 if (wm8994
->pdata
->jd_ext_cap
) {
3529 mutex_lock(&codec
->mutex
);
3532 snd_soc_dapm_force_enable_pin(&codec
->dapm
,
3535 snd_soc_dapm_disable_pin(&codec
->dapm
, "MICBIAS2");
3537 snd_soc_dapm_sync(&codec
->dapm
);
3538 mutex_unlock(&codec
->mutex
);
3542 snd_soc_jack_report(wm8994
->micdet
[0].jack
,
3543 SND_JACK_MECHANICAL
, SND_JACK_MECHANICAL
);
3545 snd_soc_jack_report(wm8994
->micdet
[0].jack
, 0,
3546 SND_JACK_MECHANICAL
| SND_JACK_HEADSET
|
3553 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3555 * @codec: WM8958 codec
3556 * @jack: jack to report detection events on
3558 * Enable microphone detection functionality for the WM8958. By
3559 * default simple detection which supports the detection of up to 6
3560 * buttons plus video and microphone functionality is supported.
3562 * The WM8958 has an advanced jack detection facility which is able to
3563 * support complex accessory detection, especially when used in
3564 * conjunction with external circuitry. In order to provide maximum
3565 * flexiblity a callback is provided which allows a completely custom
3566 * detection algorithm.
3568 int wm8958_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
3569 wm8958_micdet_cb cb
, void *cb_data
)
3571 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3572 struct wm8994
*control
= wm8994
->wm8994
;
3575 switch (control
->type
) {
3585 dev_dbg(codec
->dev
, "Using default micdet callback\n");
3586 cb
= wm8958_default_micdet
;
3590 snd_soc_dapm_force_enable_pin(&codec
->dapm
, "CLK_SYS");
3591 snd_soc_dapm_sync(&codec
->dapm
);
3593 wm8994
->micdet
[0].jack
= jack
;
3594 wm8994
->jack_cb
= cb
;
3595 wm8994
->jack_cb_data
= cb_data
;
3597 wm8994
->mic_detecting
= true;
3598 wm8994
->jack_mic
= false;
3600 wm8958_micd_set_rate(codec
);
3602 /* Detect microphones and short circuits by default */
3603 if (wm8994
->pdata
->micd_lvl_sel
)
3604 micd_lvl_sel
= wm8994
->pdata
->micd_lvl_sel
;
3606 micd_lvl_sel
= 0x41;
3608 wm8994
->btn_mask
= SND_JACK_BTN_0
| SND_JACK_BTN_1
|
3609 SND_JACK_BTN_2
| SND_JACK_BTN_3
|
3610 SND_JACK_BTN_4
| SND_JACK_BTN_5
;
3612 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_2
,
3613 WM8958_MICD_LVL_SEL_MASK
, micd_lvl_sel
);
3615 WARN_ON(codec
->dapm
.bias_level
> SND_SOC_BIAS_STANDBY
);
3618 * If we can use jack detection start off with that,
3619 * otherwise jump straight to microphone detection.
3621 if (wm8994
->jackdet
) {
3622 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
3624 WM8958_MICB2_DISCH
);
3625 snd_soc_update_bits(codec
, WM8994_LDO_1
,
3626 WM8994_LDO1_DISCH
, 0);
3627 wm1811_jackdet_set_mode(codec
,
3628 WM1811_JACKDET_MODE_JACK
);
3630 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3631 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
3635 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
3636 WM8958_MICD_ENA
, 0);
3637 wm1811_jackdet_set_mode(codec
, WM1811_JACKDET_MODE_NONE
);
3638 snd_soc_dapm_disable_pin(&codec
->dapm
, "CLK_SYS");
3639 snd_soc_dapm_sync(&codec
->dapm
);
3644 EXPORT_SYMBOL_GPL(wm8958_mic_detect
);
3646 static irqreturn_t
wm8958_mic_irq(int irq
, void *data
)
3648 struct wm8994_priv
*wm8994
= data
;
3649 struct snd_soc_codec
*codec
= wm8994
->codec
;
3653 * Jack detection may have detected a removal simulataneously
3654 * with an update of the MICDET status; if so it will have
3655 * stopped detection and we can ignore this interrupt.
3657 if (!(snd_soc_read(codec
, WM8958_MIC_DETECT_1
) & WM8958_MICD_ENA
))
3660 /* We may occasionally read a detection without an impedence
3661 * range being provided - if that happens loop again.
3665 reg
= snd_soc_read(codec
, WM8958_MIC_DETECT_3
);
3668 "Failed to read mic detect status: %d\n",
3673 if (!(reg
& WM8958_MICD_VALID
)) {
3674 dev_dbg(codec
->dev
, "Mic detect data not valid\n");
3678 if (!(reg
& WM8958_MICD_STS
) || (reg
& WM8958_MICD_LVL_MASK
))
3685 dev_warn(codec
->dev
, "No impedence range reported for jack\n");
3687 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3688 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
3691 if (wm8994
->jack_cb
)
3692 wm8994
->jack_cb(reg
, wm8994
->jack_cb_data
);
3694 dev_warn(codec
->dev
, "Accessory detection with no callback\n");
3700 static irqreturn_t
wm8994_fifo_error(int irq
, void *data
)
3702 struct snd_soc_codec
*codec
= data
;
3704 dev_err(codec
->dev
, "FIFO error\n");
3709 static irqreturn_t
wm8994_temp_warn(int irq
, void *data
)
3711 struct snd_soc_codec
*codec
= data
;
3713 dev_err(codec
->dev
, "Thermal warning\n");
3718 static irqreturn_t
wm8994_temp_shut(int irq
, void *data
)
3720 struct snd_soc_codec
*codec
= data
;
3722 dev_crit(codec
->dev
, "Thermal shutdown\n");
3727 static int wm8994_codec_probe(struct snd_soc_codec
*codec
)
3729 struct wm8994
*control
= dev_get_drvdata(codec
->dev
->parent
);
3730 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3731 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
3735 wm8994
->codec
= codec
;
3736 codec
->control_data
= control
->regmap
;
3738 snd_soc_codec_set_cache_io(codec
, 16, 16, SND_SOC_REGMAP
);
3740 wm8994
->codec
= codec
;
3742 mutex_init(&wm8994
->accdet_lock
);
3744 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
3745 init_completion(&wm8994
->fll_locked
[i
]);
3747 if (wm8994
->pdata
&& wm8994
->pdata
->micdet_irq
)
3748 wm8994
->micdet_irq
= wm8994
->pdata
->micdet_irq
;
3749 else if (wm8994
->pdata
&& wm8994
->pdata
->irq_base
)
3750 wm8994
->micdet_irq
= wm8994
->pdata
->irq_base
+
3751 WM8994_IRQ_MIC1_DET
;
3753 pm_runtime_enable(codec
->dev
);
3754 pm_runtime_idle(codec
->dev
);
3756 /* By default use idle_bias_off, will override for WM8994 */
3757 codec
->dapm
.idle_bias_off
= 1;
3759 /* Set revision-specific configuration */
3760 wm8994
->revision
= snd_soc_read(codec
, WM8994_CHIP_REVISION
);
3761 switch (control
->type
) {
3763 /* Single ended line outputs should have VMID on. */
3764 if (!wm8994
->pdata
->lineout1_diff
||
3765 !wm8994
->pdata
->lineout2_diff
)
3766 codec
->dapm
.idle_bias_off
= 0;
3768 switch (wm8994
->revision
) {
3771 wm8994
->hubs
.dcs_codes_l
= -5;
3772 wm8994
->hubs
.dcs_codes_r
= -5;
3773 wm8994
->hubs
.hp_startup_mode
= 1;
3774 wm8994
->hubs
.dcs_readback_mode
= 1;
3775 wm8994
->hubs
.series_startup
= 1;
3778 wm8994
->hubs
.dcs_readback_mode
= 2;
3784 wm8994
->hubs
.dcs_readback_mode
= 1;
3785 wm8994
->hubs
.hp_startup_mode
= 1;
3789 wm8994
->hubs
.dcs_readback_mode
= 2;
3790 wm8994
->hubs
.no_series_update
= 1;
3791 wm8994
->hubs
.hp_startup_mode
= 1;
3792 wm8994
->hubs
.no_cache_class_w
= true;
3794 switch (wm8994
->revision
) {
3799 wm8994
->hubs
.dcs_codes_l
= -9;
3800 wm8994
->hubs
.dcs_codes_r
= -7;
3806 snd_soc_update_bits(codec
, WM8994_ANALOGUE_HP_1
,
3807 WM1811_HPOUT1_ATTN
, WM1811_HPOUT1_ATTN
);
3814 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
,
3815 wm8994_fifo_error
, "FIFO error", codec
);
3816 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
,
3817 wm8994_temp_warn
, "Thermal warning", codec
);
3818 wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
,
3819 wm8994_temp_shut
, "Thermal shutdown", codec
);
3821 ret
= wm8994_request_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
3822 wm_hubs_dcs_done
, "DC servo done",
3825 wm8994
->hubs
.dcs_done_irq
= true;
3827 switch (control
->type
) {
3829 if (wm8994
->micdet_irq
) {
3830 ret
= request_threaded_irq(wm8994
->micdet_irq
, NULL
,
3832 IRQF_TRIGGER_RISING
,
3836 dev_warn(codec
->dev
,
3837 "Failed to request Mic1 detect IRQ: %d\n",
3841 ret
= wm8994_request_irq(wm8994
->wm8994
,
3842 WM8994_IRQ_MIC1_SHRT
,
3843 wm8994_mic_irq
, "Mic 1 short",
3846 dev_warn(codec
->dev
,
3847 "Failed to request Mic1 short IRQ: %d\n",
3850 ret
= wm8994_request_irq(wm8994
->wm8994
,
3851 WM8994_IRQ_MIC2_DET
,
3852 wm8994_mic_irq
, "Mic 2 detect",
3855 dev_warn(codec
->dev
,
3856 "Failed to request Mic2 detect IRQ: %d\n",
3859 ret
= wm8994_request_irq(wm8994
->wm8994
,
3860 WM8994_IRQ_MIC2_SHRT
,
3861 wm8994_mic_irq
, "Mic 2 short",
3864 dev_warn(codec
->dev
,
3865 "Failed to request Mic2 short IRQ: %d\n",
3871 if (wm8994
->micdet_irq
) {
3872 ret
= request_threaded_irq(wm8994
->micdet_irq
, NULL
,
3874 IRQF_TRIGGER_RISING
,
3878 dev_warn(codec
->dev
,
3879 "Failed to request Mic detect IRQ: %d\n",
3884 switch (control
->type
) {
3886 if (wm8994
->revision
> 1) {
3887 ret
= wm8994_request_irq(wm8994
->wm8994
,
3889 wm1811_jackdet_irq
, "JACKDET",
3892 wm8994
->jackdet
= true;
3899 wm8994
->fll_locked_irq
= true;
3900 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++) {
3901 ret
= wm8994_request_irq(wm8994
->wm8994
,
3902 WM8994_IRQ_FLL1_LOCK
+ i
,
3903 wm8994_fll_locked_irq
, "FLL lock",
3904 &wm8994
->fll_locked
[i
]);
3906 wm8994
->fll_locked_irq
= false;
3909 /* Make sure we can read from the GPIOs if they're inputs */
3910 pm_runtime_get_sync(codec
->dev
);
3912 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3913 * configured on init - if a system wants to do this dynamically
3914 * at runtime we can deal with that then.
3916 ret
= regmap_read(control
->regmap
, WM8994_GPIO_1
, ®
);
3918 dev_err(codec
->dev
, "Failed to read GPIO1 state: %d\n", ret
);
3921 if ((reg
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
3922 wm8994
->lrclk_shared
[0] = 1;
3923 wm8994_dai
[0].symmetric_rates
= 1;
3925 wm8994
->lrclk_shared
[0] = 0;
3928 ret
= regmap_read(control
->regmap
, WM8994_GPIO_6
, ®
);
3930 dev_err(codec
->dev
, "Failed to read GPIO6 state: %d\n", ret
);
3933 if ((reg
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
3934 wm8994
->lrclk_shared
[1] = 1;
3935 wm8994_dai
[1].symmetric_rates
= 1;
3937 wm8994
->lrclk_shared
[1] = 0;
3940 pm_runtime_put(codec
->dev
);
3942 /* Latch volume updates (right only; we always do left then right). */
3943 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_LEFT_VOLUME
,
3944 WM8994_AIF1DAC1_VU
, WM8994_AIF1DAC1_VU
);
3945 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_RIGHT_VOLUME
,
3946 WM8994_AIF1DAC1_VU
, WM8994_AIF1DAC1_VU
);
3947 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_LEFT_VOLUME
,
3948 WM8994_AIF1DAC2_VU
, WM8994_AIF1DAC2_VU
);
3949 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_RIGHT_VOLUME
,
3950 WM8994_AIF1DAC2_VU
, WM8994_AIF1DAC2_VU
);
3951 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_LEFT_VOLUME
,
3952 WM8994_AIF2DAC_VU
, WM8994_AIF2DAC_VU
);
3953 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_RIGHT_VOLUME
,
3954 WM8994_AIF2DAC_VU
, WM8994_AIF2DAC_VU
);
3955 snd_soc_update_bits(codec
, WM8994_AIF1_ADC1_LEFT_VOLUME
,
3956 WM8994_AIF1ADC1_VU
, WM8994_AIF1ADC1_VU
);
3957 snd_soc_update_bits(codec
, WM8994_AIF1_ADC1_RIGHT_VOLUME
,
3958 WM8994_AIF1ADC1_VU
, WM8994_AIF1ADC1_VU
);
3959 snd_soc_update_bits(codec
, WM8994_AIF1_ADC2_LEFT_VOLUME
,
3960 WM8994_AIF1ADC2_VU
, WM8994_AIF1ADC2_VU
);
3961 snd_soc_update_bits(codec
, WM8994_AIF1_ADC2_RIGHT_VOLUME
,
3962 WM8994_AIF1ADC2_VU
, WM8994_AIF1ADC2_VU
);
3963 snd_soc_update_bits(codec
, WM8994_AIF2_ADC_LEFT_VOLUME
,
3964 WM8994_AIF2ADC_VU
, WM8994_AIF1ADC2_VU
);
3965 snd_soc_update_bits(codec
, WM8994_AIF2_ADC_RIGHT_VOLUME
,
3966 WM8994_AIF2ADC_VU
, WM8994_AIF1ADC2_VU
);
3967 snd_soc_update_bits(codec
, WM8994_DAC1_LEFT_VOLUME
,
3968 WM8994_DAC1_VU
, WM8994_DAC1_VU
);
3969 snd_soc_update_bits(codec
, WM8994_DAC1_RIGHT_VOLUME
,
3970 WM8994_DAC1_VU
, WM8994_DAC1_VU
);
3971 snd_soc_update_bits(codec
, WM8994_DAC2_LEFT_VOLUME
,
3972 WM8994_DAC2_VU
, WM8994_DAC2_VU
);
3973 snd_soc_update_bits(codec
, WM8994_DAC2_RIGHT_VOLUME
,
3974 WM8994_DAC2_VU
, WM8994_DAC2_VU
);
3976 /* Set the low bit of the 3D stereo depth so TLV matches */
3977 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_FILTERS_2
,
3978 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
,
3979 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
);
3980 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_FILTERS_2
,
3981 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
,
3982 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
);
3983 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_FILTERS_2
,
3984 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
,
3985 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
);
3987 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3988 * use this; it only affects behaviour on idle TDM clock
3990 switch (control
->type
) {
3993 snd_soc_update_bits(codec
, WM8994_AIF1_CONTROL_1
,
3994 WM8994_AIF1ADC_TDM
, WM8994_AIF1ADC_TDM
);
4000 /* Put MICBIAS into bypass mode by default on newer devices */
4001 switch (control
->type
) {
4004 snd_soc_update_bits(codec
, WM8958_MICBIAS1
,
4005 WM8958_MICB1_MODE
, WM8958_MICB1_MODE
);
4006 snd_soc_update_bits(codec
, WM8958_MICBIAS2
,
4007 WM8958_MICB2_MODE
, WM8958_MICB2_MODE
);
4013 wm8994_update_class_w(codec
);
4015 wm8994_handle_pdata(wm8994
);
4017 wm_hubs_add_analogue_controls(codec
);
4018 snd_soc_add_codec_controls(codec
, wm8994_snd_controls
,
4019 ARRAY_SIZE(wm8994_snd_controls
));
4020 snd_soc_dapm_new_controls(dapm
, wm8994_dapm_widgets
,
4021 ARRAY_SIZE(wm8994_dapm_widgets
));
4023 switch (control
->type
) {
4025 snd_soc_dapm_new_controls(dapm
, wm8994_specific_dapm_widgets
,
4026 ARRAY_SIZE(wm8994_specific_dapm_widgets
));
4027 if (wm8994
->revision
< 4) {
4028 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_revd_widgets
,
4029 ARRAY_SIZE(wm8994_lateclk_revd_widgets
));
4030 snd_soc_dapm_new_controls(dapm
, wm8994_adc_revd_widgets
,
4031 ARRAY_SIZE(wm8994_adc_revd_widgets
));
4032 snd_soc_dapm_new_controls(dapm
, wm8994_dac_revd_widgets
,
4033 ARRAY_SIZE(wm8994_dac_revd_widgets
));
4035 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
4036 ARRAY_SIZE(wm8994_lateclk_widgets
));
4037 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
4038 ARRAY_SIZE(wm8994_adc_widgets
));
4039 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
4040 ARRAY_SIZE(wm8994_dac_widgets
));
4044 snd_soc_add_codec_controls(codec
, wm8958_snd_controls
,
4045 ARRAY_SIZE(wm8958_snd_controls
));
4046 snd_soc_dapm_new_controls(dapm
, wm8958_dapm_widgets
,
4047 ARRAY_SIZE(wm8958_dapm_widgets
));
4048 if (wm8994
->revision
< 1) {
4049 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_revd_widgets
,
4050 ARRAY_SIZE(wm8994_lateclk_revd_widgets
));
4051 snd_soc_dapm_new_controls(dapm
, wm8994_adc_revd_widgets
,
4052 ARRAY_SIZE(wm8994_adc_revd_widgets
));
4053 snd_soc_dapm_new_controls(dapm
, wm8994_dac_revd_widgets
,
4054 ARRAY_SIZE(wm8994_dac_revd_widgets
));
4056 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
4057 ARRAY_SIZE(wm8994_lateclk_widgets
));
4058 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
4059 ARRAY_SIZE(wm8994_adc_widgets
));
4060 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
4061 ARRAY_SIZE(wm8994_dac_widgets
));
4066 snd_soc_add_codec_controls(codec
, wm8958_snd_controls
,
4067 ARRAY_SIZE(wm8958_snd_controls
));
4068 snd_soc_dapm_new_controls(dapm
, wm8958_dapm_widgets
,
4069 ARRAY_SIZE(wm8958_dapm_widgets
));
4070 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
4071 ARRAY_SIZE(wm8994_lateclk_widgets
));
4072 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
4073 ARRAY_SIZE(wm8994_adc_widgets
));
4074 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
4075 ARRAY_SIZE(wm8994_dac_widgets
));
4080 wm_hubs_add_analogue_routes(codec
, 0, 0);
4081 snd_soc_dapm_add_routes(dapm
, intercon
, ARRAY_SIZE(intercon
));
4083 switch (control
->type
) {
4085 snd_soc_dapm_add_routes(dapm
, wm8994_intercon
,
4086 ARRAY_SIZE(wm8994_intercon
));
4088 if (wm8994
->revision
< 4) {
4089 snd_soc_dapm_add_routes(dapm
, wm8994_revd_intercon
,
4090 ARRAY_SIZE(wm8994_revd_intercon
));
4091 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_revd_intercon
,
4092 ARRAY_SIZE(wm8994_lateclk_revd_intercon
));
4094 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
4095 ARRAY_SIZE(wm8994_lateclk_intercon
));
4099 if (wm8994
->revision
< 1) {
4100 snd_soc_dapm_add_routes(dapm
, wm8994_revd_intercon
,
4101 ARRAY_SIZE(wm8994_revd_intercon
));
4102 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_revd_intercon
,
4103 ARRAY_SIZE(wm8994_lateclk_revd_intercon
));
4105 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
4106 ARRAY_SIZE(wm8994_lateclk_intercon
));
4107 snd_soc_dapm_add_routes(dapm
, wm8958_intercon
,
4108 ARRAY_SIZE(wm8958_intercon
));
4111 wm8958_dsp2_init(codec
);
4114 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
4115 ARRAY_SIZE(wm8994_lateclk_intercon
));
4116 snd_soc_dapm_add_routes(dapm
, wm8958_intercon
,
4117 ARRAY_SIZE(wm8958_intercon
));
4124 if (wm8994
->jackdet
)
4125 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_GPIO(6), wm8994
);
4126 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_SHRT
, wm8994
);
4127 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_DET
, wm8994
);
4128 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_SHRT
, wm8994
);
4129 if (wm8994
->micdet_irq
)
4130 free_irq(wm8994
->micdet_irq
, wm8994
);
4131 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
4132 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FLL1_LOCK
+ i
,
4133 &wm8994
->fll_locked
[i
]);
4134 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
4136 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
, codec
);
4137 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
, codec
);
4138 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
, codec
);
4143 static int wm8994_codec_remove(struct snd_soc_codec
*codec
)
4145 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
4146 struct wm8994
*control
= wm8994
->wm8994
;
4149 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
4151 pm_runtime_disable(codec
->dev
);
4153 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll_locked
); i
++)
4154 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FLL1_LOCK
+ i
,
4155 &wm8994
->fll_locked
[i
]);
4157 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_DCS_DONE
,
4159 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_FIFOS_ERR
, codec
);
4160 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_SHUT
, codec
);
4161 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_TEMP_WARN
, codec
);
4163 if (wm8994
->jackdet
)
4164 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_GPIO(6), wm8994
);
4166 switch (control
->type
) {
4168 if (wm8994
->micdet_irq
)
4169 free_irq(wm8994
->micdet_irq
, wm8994
);
4170 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC2_DET
,
4172 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_SHRT
,
4174 wm8994_free_irq(wm8994
->wm8994
, WM8994_IRQ_MIC1_DET
,
4180 if (wm8994
->micdet_irq
)
4181 free_irq(wm8994
->micdet_irq
, wm8994
);
4185 release_firmware(wm8994
->mbc
);
4186 if (wm8994
->mbc_vss
)
4187 release_firmware(wm8994
->mbc_vss
);
4189 release_firmware(wm8994
->enh_eq
);
4190 kfree(wm8994
->retune_mobile_texts
);
4195 static struct snd_soc_codec_driver soc_codec_dev_wm8994
= {
4196 .probe
= wm8994_codec_probe
,
4197 .remove
= wm8994_codec_remove
,
4198 .suspend
= wm8994_codec_suspend
,
4199 .resume
= wm8994_codec_resume
,
4200 .set_bias_level
= wm8994_set_bias_level
,
4203 static int __devinit
wm8994_probe(struct platform_device
*pdev
)
4205 struct wm8994_priv
*wm8994
;
4207 wm8994
= devm_kzalloc(&pdev
->dev
, sizeof(struct wm8994_priv
),
4211 platform_set_drvdata(pdev
, wm8994
);
4213 wm8994
->wm8994
= dev_get_drvdata(pdev
->dev
.parent
);
4214 wm8994
->pdata
= dev_get_platdata(pdev
->dev
.parent
);
4216 return snd_soc_register_codec(&pdev
->dev
, &soc_codec_dev_wm8994
,
4217 wm8994_dai
, ARRAY_SIZE(wm8994_dai
));
4220 static int __devexit
wm8994_remove(struct platform_device
*pdev
)
4222 snd_soc_unregister_codec(&pdev
->dev
);
4226 #ifdef CONFIG_PM_SLEEP
4227 static int wm8994_suspend(struct device
*dev
)
4229 struct wm8994_priv
*wm8994
= dev_get_drvdata(dev
);
4231 /* Drop down to power saving mode when system is suspended */
4232 if (wm8994
->jackdet
&& !wm8994
->active_refcount
)
4233 regmap_update_bits(wm8994
->wm8994
->regmap
, WM8994_ANTIPOP_2
,
4234 WM1811_JACKDET_MODE_MASK
,
4235 wm8994
->jackdet_mode
);
4240 static int wm8994_resume(struct device
*dev
)
4242 struct wm8994_priv
*wm8994
= dev_get_drvdata(dev
);
4244 if (wm8994
->jackdet
&& wm8994
->jack_cb
)
4245 regmap_update_bits(wm8994
->wm8994
->regmap
, WM8994_ANTIPOP_2
,
4246 WM1811_JACKDET_MODE_MASK
,
4247 WM1811_JACKDET_MODE_AUDIO
);
4253 static const struct dev_pm_ops wm8994_pm_ops
= {
4254 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend
, wm8994_resume
)
4257 static struct platform_driver wm8994_codec_driver
= {
4259 .name
= "wm8994-codec",
4260 .owner
= THIS_MODULE
,
4261 .pm
= &wm8994_pm_ops
,
4263 .probe
= wm8994_probe
,
4264 .remove
= __devexit_p(wm8994_remove
),
4267 module_platform_driver(wm8994_codec_driver
);
4269 MODULE_DESCRIPTION("ASoC WM8994 driver");
4270 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4271 MODULE_LICENSE("GPL");
4272 MODULE_ALIAS("platform:wm8994-codec");