2 * wm8993.c -- WM8993 ALSA SoC audio driver
4 * Copyright 2009, 2010 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
18 #include <linux/i2c.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/spi/spi.h>
21 #include <linux/slab.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/tlv.h>
26 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/initval.h>
29 #include <sound/wm8993.h>
34 #define WM8993_NUM_SUPPLIES 6
35 static const char *wm8993_supply_names
[WM8993_NUM_SUPPLIES
] = {
44 static u16 wm8993_reg_defaults
[WM8993_REGISTER_COUNT
] = {
45 0x8993, /* R0 - Software Reset */
46 0x0000, /* R1 - Power Management (1) */
47 0x6000, /* R2 - Power Management (2) */
48 0x0000, /* R3 - Power Management (3) */
49 0x4050, /* R4 - Audio Interface (1) */
50 0x4000, /* R5 - Audio Interface (2) */
51 0x01C8, /* R6 - Clocking 1 */
52 0x0000, /* R7 - Clocking 2 */
53 0x0000, /* R8 - Audio Interface (3) */
54 0x0040, /* R9 - Audio Interface (4) */
55 0x0004, /* R10 - DAC CTRL */
56 0x00C0, /* R11 - Left DAC Digital Volume */
57 0x00C0, /* R12 - Right DAC Digital Volume */
58 0x0000, /* R13 - Digital Side Tone */
59 0x0300, /* R14 - ADC CTRL */
60 0x00C0, /* R15 - Left ADC Digital Volume */
61 0x00C0, /* R16 - Right ADC Digital Volume */
63 0x0000, /* R18 - GPIO CTRL 1 */
64 0x0010, /* R19 - GPIO1 */
65 0x0000, /* R20 - IRQ_DEBOUNCE */
67 0x8000, /* R22 - GPIOCTRL 2 */
68 0x0800, /* R23 - GPIO_POL */
69 0x008B, /* R24 - Left Line Input 1&2 Volume */
70 0x008B, /* R25 - Left Line Input 3&4 Volume */
71 0x008B, /* R26 - Right Line Input 1&2 Volume */
72 0x008B, /* R27 - Right Line Input 3&4 Volume */
73 0x006D, /* R28 - Left Output Volume */
74 0x006D, /* R29 - Right Output Volume */
75 0x0066, /* R30 - Line Outputs Volume */
76 0x0020, /* R31 - HPOUT2 Volume */
77 0x0079, /* R32 - Left OPGA Volume */
78 0x0079, /* R33 - Right OPGA Volume */
79 0x0003, /* R34 - SPKMIXL Attenuation */
80 0x0003, /* R35 - SPKMIXR Attenuation */
81 0x0011, /* R36 - SPKOUT Mixers */
82 0x0100, /* R37 - SPKOUT Boost */
83 0x0079, /* R38 - Speaker Volume Left */
84 0x0079, /* R39 - Speaker Volume Right */
85 0x0000, /* R40 - Input Mixer2 */
86 0x0000, /* R41 - Input Mixer3 */
87 0x0000, /* R42 - Input Mixer4 */
88 0x0000, /* R43 - Input Mixer5 */
89 0x0000, /* R44 - Input Mixer6 */
90 0x0000, /* R45 - Output Mixer1 */
91 0x0000, /* R46 - Output Mixer2 */
92 0x0000, /* R47 - Output Mixer3 */
93 0x0000, /* R48 - Output Mixer4 */
94 0x0000, /* R49 - Output Mixer5 */
95 0x0000, /* R50 - Output Mixer6 */
96 0x0000, /* R51 - HPOUT2 Mixer */
97 0x0000, /* R52 - Line Mixer1 */
98 0x0000, /* R53 - Line Mixer2 */
99 0x0000, /* R54 - Speaker Mixer */
100 0x0000, /* R55 - Additional Control */
101 0x0000, /* R56 - AntiPOP1 */
102 0x0000, /* R57 - AntiPOP2 */
103 0x0000, /* R58 - MICBIAS */
105 0x0000, /* R60 - FLL Control 1 */
106 0x0000, /* R61 - FLL Control 2 */
107 0x0000, /* R62 - FLL Control 3 */
108 0x2EE0, /* R63 - FLL Control 4 */
109 0x0002, /* R64 - FLL Control 5 */
110 0x2287, /* R65 - Clocking 3 */
111 0x025F, /* R66 - Clocking 4 */
112 0x0000, /* R67 - MW Slave Control */
114 0x0002, /* R69 - Bus Control 1 */
115 0x0000, /* R70 - Write Sequencer 0 */
116 0x0000, /* R71 - Write Sequencer 1 */
117 0x0000, /* R72 - Write Sequencer 2 */
118 0x0000, /* R73 - Write Sequencer 3 */
119 0x0000, /* R74 - Write Sequencer 4 */
120 0x0000, /* R75 - Write Sequencer 5 */
121 0x1F25, /* R76 - Charge Pump 1 */
126 0x0000, /* R81 - Class W 0 */
129 0x0000, /* R84 - DC Servo 0 */
130 0x054A, /* R85 - DC Servo 1 */
132 0x0000, /* R87 - DC Servo 3 */
133 0x0000, /* R88 - DC Servo Readback 0 */
134 0x0000, /* R89 - DC Servo Readback 1 */
135 0x0000, /* R90 - DC Servo Readback 2 */
141 0x0100, /* R96 - Analogue HP 0 */
143 0x0000, /* R98 - EQ1 */
144 0x000C, /* R99 - EQ2 */
145 0x000C, /* R100 - EQ3 */
146 0x000C, /* R101 - EQ4 */
147 0x000C, /* R102 - EQ5 */
148 0x000C, /* R103 - EQ6 */
149 0x0FCA, /* R104 - EQ7 */
150 0x0400, /* R105 - EQ8 */
151 0x00D8, /* R106 - EQ9 */
152 0x1EB5, /* R107 - EQ10 */
153 0xF145, /* R108 - EQ11 */
154 0x0B75, /* R109 - EQ12 */
155 0x01C5, /* R110 - EQ13 */
156 0x1C58, /* R111 - EQ14 */
157 0xF373, /* R112 - EQ15 */
158 0x0A54, /* R113 - EQ16 */
159 0x0558, /* R114 - EQ17 */
160 0x168E, /* R115 - EQ18 */
161 0xF829, /* R116 - EQ19 */
162 0x07AD, /* R117 - EQ20 */
163 0x1103, /* R118 - EQ21 */
164 0x0564, /* R119 - EQ22 */
165 0x0559, /* R120 - EQ23 */
166 0x4000, /* R121 - EQ24 */
167 0x0000, /* R122 - Digital Pulls */
168 0x0F08, /* R123 - DRC Control 1 */
169 0x0000, /* R124 - DRC Control 2 */
170 0x0080, /* R125 - DRC Control 3 */
171 0x0000, /* R126 - DRC Control 4 */
177 } clk_sys_rates
[] = {
206 int div
; /* *10 due to .5s */
228 struct wm_hubs_data hubs_data
;
229 u16 reg_cache
[WM8993_REGISTER_COUNT
];
230 struct regulator_bulk_data supplies
[WM8993_NUM_SUPPLIES
];
231 struct wm8993_platform_data pdata
;
232 enum snd_soc_control_type control_type
;
237 unsigned int mclk_rate
;
238 unsigned int sysclk_rate
;
242 unsigned int fll_fref
;
243 unsigned int fll_fout
;
247 static int wm8993_volatile(unsigned int reg
)
250 case WM8993_SOFTWARE_RESET
:
251 case WM8993_DC_SERVO_0
:
252 case WM8993_DC_SERVO_READBACK_0
:
253 case WM8993_DC_SERVO_READBACK_1
:
254 case WM8993_DC_SERVO_READBACK_2
:
269 /* The size in bits of the FLL divide multiplied by 10
270 * to allow rounding later */
271 #define FIXED_FLL_SIZE ((1 << 16) * 10)
280 { 64000, 128000, 3, 8 },
281 { 128000, 256000, 2, 4 },
282 { 256000, 1000000, 1, 2 },
283 { 1000000, 13500000, 0, 1 },
286 static int fll_factors(struct _fll_div
*fll_div
, unsigned int Fref
,
290 unsigned int K
, Ndiv
, Nmod
, target
;
294 /* Fref must be <=13.5MHz */
296 fll_div
->fll_clk_ref_div
= 0;
297 while ((Fref
/ div
) > 13500000) {
299 fll_div
->fll_clk_ref_div
++;
302 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
308 pr_debug("Fref=%u Fout=%u\n", Fref
, Fout
);
310 /* Apply the division for our remaining calculations */
313 /* Fvco should be 90-100MHz; don't check the upper bound */
316 while (target
< 90000000) {
320 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
325 fll_div
->fll_outdiv
= div
;
327 pr_debug("Fvco=%dHz\n", target
);
329 /* Find an appropraite FLL_FRATIO and factor it out of the target */
330 for (i
= 0; i
< ARRAY_SIZE(fll_fratios
); i
++) {
331 if (fll_fratios
[i
].min
<= Fref
&& Fref
<= fll_fratios
[i
].max
) {
332 fll_div
->fll_fratio
= fll_fratios
[i
].fll_fratio
;
333 target
/= fll_fratios
[i
].ratio
;
337 if (i
== ARRAY_SIZE(fll_fratios
)) {
338 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref
);
342 /* Now, calculate N.K */
343 Ndiv
= target
/ Fref
;
346 Nmod
= target
% Fref
;
347 pr_debug("Nmod=%d\n", Nmod
);
349 /* Calculate fractional part - scale up so we can round. */
350 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
354 K
= Kpart
& 0xFFFFFFFF;
359 /* Move down to proper range now rounding is done */
362 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
363 fll_div
->n
, fll_div
->k
,
364 fll_div
->fll_fratio
, fll_div
->fll_outdiv
,
365 fll_div
->fll_clk_ref_div
);
370 static int _wm8993_set_fll(struct snd_soc_codec
*codec
, int fll_id
, int source
,
371 unsigned int Fref
, unsigned int Fout
)
373 struct wm8993_priv
*wm8993
= snd_soc_codec_get_drvdata(codec
);
374 u16 reg1
, reg4
, reg5
;
375 struct _fll_div fll_div
;
379 if (Fref
== wm8993
->fll_fref
&& Fout
== wm8993
->fll_fout
)
382 /* Disable the FLL */
384 dev_dbg(codec
->dev
, "FLL disabled\n");
385 wm8993
->fll_fref
= 0;
386 wm8993
->fll_fout
= 0;
388 reg1
= snd_soc_read(codec
, WM8993_FLL_CONTROL_1
);
389 reg1
&= ~WM8993_FLL_ENA
;
390 snd_soc_write(codec
, WM8993_FLL_CONTROL_1
, reg1
);
395 ret
= fll_factors(&fll_div
, Fref
, Fout
);
399 reg5
= snd_soc_read(codec
, WM8993_FLL_CONTROL_5
);
400 reg5
&= ~WM8993_FLL_CLK_SRC_MASK
;
403 case WM8993_FLL_MCLK
:
406 case WM8993_FLL_LRCLK
:
410 case WM8993_FLL_BCLK
:
415 dev_err(codec
->dev
, "Unknown FLL ID %d\n", fll_id
);
419 /* Any FLL configuration change requires that the FLL be
421 reg1
= snd_soc_read(codec
, WM8993_FLL_CONTROL_1
);
422 reg1
&= ~WM8993_FLL_ENA
;
423 snd_soc_write(codec
, WM8993_FLL_CONTROL_1
, reg1
);
425 /* Apply the configuration */
427 reg1
|= WM8993_FLL_FRAC_MASK
;
429 reg1
&= ~WM8993_FLL_FRAC_MASK
;
430 snd_soc_write(codec
, WM8993_FLL_CONTROL_1
, reg1
);
432 snd_soc_write(codec
, WM8993_FLL_CONTROL_2
,
433 (fll_div
.fll_outdiv
<< WM8993_FLL_OUTDIV_SHIFT
) |
434 (fll_div
.fll_fratio
<< WM8993_FLL_FRATIO_SHIFT
));
435 snd_soc_write(codec
, WM8993_FLL_CONTROL_3
, fll_div
.k
);
437 reg4
= snd_soc_read(codec
, WM8993_FLL_CONTROL_4
);
438 reg4
&= ~WM8993_FLL_N_MASK
;
439 reg4
|= fll_div
.n
<< WM8993_FLL_N_SHIFT
;
440 snd_soc_write(codec
, WM8993_FLL_CONTROL_4
, reg4
);
442 reg5
&= ~WM8993_FLL_CLK_REF_DIV_MASK
;
443 reg5
|= fll_div
.fll_clk_ref_div
<< WM8993_FLL_CLK_REF_DIV_SHIFT
;
444 snd_soc_write(codec
, WM8993_FLL_CONTROL_5
, reg5
);
447 snd_soc_write(codec
, WM8993_FLL_CONTROL_1
, reg1
| WM8993_FLL_ENA
);
449 dev_dbg(codec
->dev
, "FLL enabled at %dHz->%dHz\n", Fref
, Fout
);
451 wm8993
->fll_fref
= Fref
;
452 wm8993
->fll_fout
= Fout
;
453 wm8993
->fll_src
= source
;
458 static int wm8993_set_fll(struct snd_soc_dai
*dai
, int fll_id
, int source
,
459 unsigned int Fref
, unsigned int Fout
)
461 return _wm8993_set_fll(dai
->codec
, fll_id
, source
, Fref
, Fout
);
464 static int configure_clock(struct snd_soc_codec
*codec
)
466 struct wm8993_priv
*wm8993
= snd_soc_codec_get_drvdata(codec
);
469 /* This should be done on init() for bypass paths */
470 switch (wm8993
->sysclk_source
) {
471 case WM8993_SYSCLK_MCLK
:
472 dev_dbg(codec
->dev
, "Using %dHz MCLK\n", wm8993
->mclk_rate
);
474 reg
= snd_soc_read(codec
, WM8993_CLOCKING_2
);
475 reg
&= ~(WM8993_MCLK_DIV
| WM8993_SYSCLK_SRC
);
476 if (wm8993
->mclk_rate
> 13500000) {
477 reg
|= WM8993_MCLK_DIV
;
478 wm8993
->sysclk_rate
= wm8993
->mclk_rate
/ 2;
480 reg
&= ~WM8993_MCLK_DIV
;
481 wm8993
->sysclk_rate
= wm8993
->mclk_rate
;
483 snd_soc_write(codec
, WM8993_CLOCKING_2
, reg
);
486 case WM8993_SYSCLK_FLL
:
487 dev_dbg(codec
->dev
, "Using %dHz FLL clock\n",
490 reg
= snd_soc_read(codec
, WM8993_CLOCKING_2
);
491 reg
|= WM8993_SYSCLK_SRC
;
492 if (wm8993
->fll_fout
> 13500000) {
493 reg
|= WM8993_MCLK_DIV
;
494 wm8993
->sysclk_rate
= wm8993
->fll_fout
/ 2;
496 reg
&= ~WM8993_MCLK_DIV
;
497 wm8993
->sysclk_rate
= wm8993
->fll_fout
;
499 snd_soc_write(codec
, WM8993_CLOCKING_2
, reg
);
503 dev_err(codec
->dev
, "System clock not configured\n");
507 dev_dbg(codec
->dev
, "CLK_SYS is %dHz\n", wm8993
->sysclk_rate
);
512 static const DECLARE_TLV_DB_SCALE(sidetone_tlv
, -3600, 300, 0);
513 static const DECLARE_TLV_DB_SCALE(drc_comp_threash
, -4500, 75, 0);
514 static const DECLARE_TLV_DB_SCALE(drc_comp_amp
, -2250, 75, 0);
515 static const DECLARE_TLV_DB_SCALE(drc_min_tlv
, -1800, 600, 0);
516 static const unsigned int drc_max_tlv
[] = {
517 TLV_DB_RANGE_HEAD(4),
518 0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0),
519 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
521 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv
, 1200, 600, 0);
522 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv
, -1800, 300, 0);
523 static const DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
524 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
525 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv
, 0, 600, 0);
527 static const char *dac_deemph_text
[] = {
534 static const struct soc_enum dac_deemph
=
535 SOC_ENUM_SINGLE(WM8993_DAC_CTRL
, 4, 4, dac_deemph_text
);
537 static const char *adc_hpf_text
[] = {
544 static const struct soc_enum adc_hpf
=
545 SOC_ENUM_SINGLE(WM8993_ADC_CTRL
, 5, 4, adc_hpf_text
);
547 static const char *drc_path_text
[] = {
552 static const struct soc_enum drc_path
=
553 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1
, 14, 2, drc_path_text
);
555 static const char *drc_r0_text
[] = {
564 static const struct soc_enum drc_r0
=
565 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3
, 8, 6, drc_r0_text
);
567 static const char *drc_r1_text
[] = {
575 static const struct soc_enum drc_r1
=
576 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_4
, 13, 5, drc_r1_text
);
578 static const char *drc_attack_text
[] = {
593 static const struct soc_enum drc_attack
=
594 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2
, 12, 12, drc_attack_text
);
596 static const char *drc_decay_text
[] = {
608 static const struct soc_enum drc_decay
=
609 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2
, 8, 9, drc_decay_text
);
611 static const char *drc_ff_text
[] = {
616 static const struct soc_enum drc_ff
=
617 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3
, 7, 2, drc_ff_text
);
619 static const char *drc_qr_rate_text
[] = {
625 static const struct soc_enum drc_qr_rate
=
626 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3
, 0, 3, drc_qr_rate_text
);
628 static const char *drc_smooth_text
[] = {
634 static const struct soc_enum drc_smooth
=
635 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1
, 4, 3, drc_smooth_text
);
637 static const struct snd_kcontrol_new wm8993_snd_controls
[] = {
638 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE
,
639 5, 9, 12, 0, sidetone_tlv
),
641 SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1
, 15, 1, 0),
642 SOC_ENUM("DRC Path", drc_path
),
643 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8993_DRC_CONTROL_2
,
644 2, 60, 1, drc_comp_threash
),
645 SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3
,
646 11, 30, 1, drc_comp_amp
),
647 SOC_ENUM("DRC R0", drc_r0
),
648 SOC_ENUM("DRC R1", drc_r1
),
649 SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1
, 2, 3, 1,
651 SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1
, 0, 3, 0,
653 SOC_ENUM("DRC Attack Rate", drc_attack
),
654 SOC_ENUM("DRC Decay Rate", drc_decay
),
655 SOC_ENUM("DRC FF Delay", drc_ff
),
656 SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1
, 9, 1, 0),
657 SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1
, 10, 1, 0),
658 SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3
, 2, 3, 0,
660 SOC_ENUM("DRC Quick Release Rate", drc_qr_rate
),
661 SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1
, 11, 1, 0),
662 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1
, 8, 1, 0),
663 SOC_ENUM("DRC Smoothing Hysteresis Threshold", drc_smooth
),
664 SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4
, 8, 18, 0,
667 SOC_SINGLE("EQ Switch", WM8993_EQ1
, 0, 1, 0),
669 SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME
,
670 WM8993_RIGHT_ADC_DIGITAL_VOLUME
, 1, 96, 0, digital_tlv
),
671 SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL
, 8, 1, 0),
672 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf
),
674 SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME
,
675 WM8993_RIGHT_DAC_DIGITAL_VOLUME
, 1, 96, 0, digital_tlv
),
676 SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2
, 10, 3, 0,
678 SOC_ENUM("DAC Deemphasis", dac_deemph
),
680 SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION
,
681 2, 1, 1, wm_hubs_spkmix_tlv
),
683 SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION
,
684 2, 1, 1, wm_hubs_spkmix_tlv
),
687 static const struct snd_kcontrol_new wm8993_eq_controls
[] = {
688 SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2
, 0, 24, 0, eq_tlv
),
689 SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3
, 0, 24, 0, eq_tlv
),
690 SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4
, 0, 24, 0, eq_tlv
),
691 SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5
, 0, 24, 0, eq_tlv
),
692 SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6
, 0, 24, 0, eq_tlv
),
695 static int clk_sys_event(struct snd_soc_dapm_widget
*w
,
696 struct snd_kcontrol
*kcontrol
, int event
)
698 struct snd_soc_codec
*codec
= w
->codec
;
701 case SND_SOC_DAPM_PRE_PMU
:
702 return configure_clock(codec
);
704 case SND_SOC_DAPM_POST_PMD
:
712 * When used with DAC outputs only the WM8993 charge pump supports
713 * operation in class W mode, providing very low power consumption
714 * when used with digital sources. Enable and disable this mode
715 * automatically depending on the mixer configuration.
717 * Currently the only supported paths are the direct DAC->headphone
718 * paths (which provide minimum power consumption anyway).
720 static int class_w_put(struct snd_kcontrol
*kcontrol
,
721 struct snd_ctl_elem_value
*ucontrol
)
723 struct snd_soc_dapm_widget
*widget
= snd_kcontrol_chip(kcontrol
);
724 struct snd_soc_codec
*codec
= widget
->codec
;
725 struct wm8993_priv
*wm8993
= snd_soc_codec_get_drvdata(codec
);
728 /* Turn it off if we're using the main output mixer */
729 if (ucontrol
->value
.integer
.value
[0] == 0) {
730 if (wm8993
->class_w_users
== 0) {
731 dev_dbg(codec
->dev
, "Disabling Class W\n");
732 snd_soc_update_bits(codec
, WM8993_CLASS_W_0
,
737 wm8993
->class_w_users
++;
740 /* Implement the change */
741 ret
= snd_soc_dapm_put_enum_double(kcontrol
, ucontrol
);
743 /* Enable it if we're using the direct DAC path */
744 if (ucontrol
->value
.integer
.value
[0] == 1) {
745 if (wm8993
->class_w_users
== 1) {
746 dev_dbg(codec
->dev
, "Enabling Class W\n");
747 snd_soc_update_bits(codec
, WM8993_CLASS_W_0
,
753 wm8993
->class_w_users
--;
756 dev_dbg(codec
->dev
, "Indirect DAC use count now %d\n",
757 wm8993
->class_w_users
);
762 #define SOC_DAPM_ENUM_W(xname, xenum) \
763 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
764 .info = snd_soc_info_enum_double, \
765 .get = snd_soc_dapm_get_enum_double, \
766 .put = class_w_put, \
767 .private_value = (unsigned long)&xenum }
769 static const char *hp_mux_text
[] = {
774 static const struct soc_enum hpl_enum
=
775 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER1
, 8, 2, hp_mux_text
);
777 static const struct snd_kcontrol_new hpl_mux
=
778 SOC_DAPM_ENUM_W("Left Headphone Mux", hpl_enum
);
780 static const struct soc_enum hpr_enum
=
781 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER2
, 8, 2, hp_mux_text
);
783 static const struct snd_kcontrol_new hpr_mux
=
784 SOC_DAPM_ENUM_W("Right Headphone Mux", hpr_enum
);
786 static const struct snd_kcontrol_new left_speaker_mixer
[] = {
787 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER
, 7, 1, 0),
788 SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER
, 5, 1, 0),
789 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER
, 3, 1, 0),
790 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER
, 6, 1, 0),
793 static const struct snd_kcontrol_new right_speaker_mixer
[] = {
794 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER
, 6, 1, 0),
795 SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER
, 4, 1, 0),
796 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER
, 2, 1, 0),
797 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER
, 0, 1, 0),
800 static const char *aif_text
[] = {
804 static const struct soc_enum aifoutl_enum
=
805 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1
, 15, 2, aif_text
);
807 static const struct snd_kcontrol_new aifoutl_mux
=
808 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum
);
810 static const struct soc_enum aifoutr_enum
=
811 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1
, 14, 2, aif_text
);
813 static const struct snd_kcontrol_new aifoutr_mux
=
814 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum
);
816 static const struct soc_enum aifinl_enum
=
817 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2
, 15, 2, aif_text
);
819 static const struct snd_kcontrol_new aifinl_mux
=
820 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum
);
822 static const struct soc_enum aifinr_enum
=
823 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2
, 14, 2, aif_text
);
825 static const struct snd_kcontrol_new aifinr_mux
=
826 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum
);
828 static const char *sidetone_text
[] = {
829 "None", "Left", "Right"
832 static const struct soc_enum sidetonel_enum
=
833 SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE
, 2, 3, sidetone_text
);
835 static const struct snd_kcontrol_new sidetonel_mux
=
836 SOC_DAPM_ENUM("Left Sidetone", sidetonel_enum
);
838 static const struct soc_enum sidetoner_enum
=
839 SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE
, 0, 3, sidetone_text
);
841 static const struct snd_kcontrol_new sidetoner_mux
=
842 SOC_DAPM_ENUM("Right Sidetone", sidetoner_enum
);
844 static const struct snd_soc_dapm_widget wm8993_dapm_widgets
[] = {
845 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1
, 1, 0, clk_sys_event
,
846 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
847 SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1
, 14, 0, NULL
, 0),
848 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3
, 0, 0, NULL
, 0),
850 SND_SOC_DAPM_ADC("ADCL", NULL
, WM8993_POWER_MANAGEMENT_2
, 1, 0),
851 SND_SOC_DAPM_ADC("ADCR", NULL
, WM8993_POWER_MANAGEMENT_2
, 0, 0),
853 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM
, 0, 0, &aifoutl_mux
),
854 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM
, 0, 0, &aifoutr_mux
),
856 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM
, 0, 0),
857 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM
, 0, 0),
859 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM
, 0, 0),
860 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM
, 0, 0),
862 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM
, 0, 0, &aifinl_mux
),
863 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM
, 0, 0, &aifinr_mux
),
865 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM
, 0, 0, &sidetonel_mux
),
866 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM
, 0, 0, &sidetoner_mux
),
868 SND_SOC_DAPM_DAC("DACL", NULL
, WM8993_POWER_MANAGEMENT_3
, 1, 0),
869 SND_SOC_DAPM_DAC("DACR", NULL
, WM8993_POWER_MANAGEMENT_3
, 0, 0),
871 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpl_mux
),
872 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpr_mux
),
874 SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3
, 8, 0,
875 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
)),
876 SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3
, 9, 0,
877 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
)),
881 static const struct snd_soc_dapm_route routes
[] = {
882 { "ADCL", NULL
, "CLK_SYS" },
883 { "ADCL", NULL
, "CLK_DSP" },
884 { "ADCR", NULL
, "CLK_SYS" },
885 { "ADCR", NULL
, "CLK_DSP" },
887 { "AIFOUTL Mux", "Left", "ADCL" },
888 { "AIFOUTL Mux", "Right", "ADCR" },
889 { "AIFOUTR Mux", "Left", "ADCL" },
890 { "AIFOUTR Mux", "Right", "ADCR" },
892 { "AIFOUTL", NULL
, "AIFOUTL Mux" },
893 { "AIFOUTR", NULL
, "AIFOUTR Mux" },
895 { "DACL Mux", "Left", "AIFINL" },
896 { "DACL Mux", "Right", "AIFINR" },
897 { "DACR Mux", "Left", "AIFINL" },
898 { "DACR Mux", "Right", "AIFINR" },
900 { "DACL Sidetone", "Left", "ADCL" },
901 { "DACL Sidetone", "Right", "ADCR" },
902 { "DACR Sidetone", "Left", "ADCL" },
903 { "DACR Sidetone", "Right", "ADCR" },
905 { "DACL", NULL
, "CLK_SYS" },
906 { "DACL", NULL
, "CLK_DSP" },
907 { "DACL", NULL
, "DACL Mux" },
908 { "DACL", NULL
, "DACL Sidetone" },
909 { "DACR", NULL
, "CLK_SYS" },
910 { "DACR", NULL
, "CLK_DSP" },
911 { "DACR", NULL
, "DACR Mux" },
912 { "DACR", NULL
, "DACR Sidetone" },
914 { "Left Output Mixer", "DAC Switch", "DACL" },
916 { "Right Output Mixer", "DAC Switch", "DACR" },
918 { "Left Output PGA", NULL
, "CLK_SYS" },
920 { "Right Output PGA", NULL
, "CLK_SYS" },
922 { "SPKL", "DAC Switch", "DACL" },
923 { "SPKL", NULL
, "CLK_SYS" },
925 { "SPKR", "DAC Switch", "DACR" },
926 { "SPKR", NULL
, "CLK_SYS" },
928 { "Left Headphone Mux", "DAC", "DACL" },
929 { "Right Headphone Mux", "DAC", "DACR" },
932 static void wm8993_cache_restore(struct snd_soc_codec
*codec
)
934 u16
*cache
= codec
->reg_cache
;
937 if (!codec
->cache_sync
)
940 /* Reenable hardware writes */
941 codec
->cache_only
= 0;
943 /* Restore the register settings */
944 for (i
= 1; i
< WM8993_MAX_REGISTER
; i
++) {
945 if (cache
[i
] == wm8993_reg_defaults
[i
])
947 snd_soc_write(codec
, i
, cache
[i
]);
950 /* We're in sync again */
951 codec
->cache_sync
= 0;
954 static int wm8993_set_bias_level(struct snd_soc_codec
*codec
,
955 enum snd_soc_bias_level level
)
957 struct wm8993_priv
*wm8993
= snd_soc_codec_get_drvdata(codec
);
961 case SND_SOC_BIAS_ON
:
962 case SND_SOC_BIAS_PREPARE
:
964 snd_soc_update_bits(codec
, WM8993_POWER_MANAGEMENT_1
,
965 WM8993_VMID_SEL_MASK
, 0x2);
966 snd_soc_update_bits(codec
, WM8993_POWER_MANAGEMENT_2
,
967 WM8993_TSHUT_ENA
, WM8993_TSHUT_ENA
);
970 case SND_SOC_BIAS_STANDBY
:
971 if (codec
->bias_level
== SND_SOC_BIAS_OFF
) {
972 ret
= regulator_bulk_enable(ARRAY_SIZE(wm8993
->supplies
),
977 wm8993_cache_restore(codec
);
979 /* Tune DC servo configuration */
980 snd_soc_write(codec
, 0x44, 3);
981 snd_soc_write(codec
, 0x56, 3);
982 snd_soc_write(codec
, 0x44, 0);
984 /* Bring up VMID with fast soft start */
985 snd_soc_update_bits(codec
, WM8993_ANTIPOP2
,
986 WM8993_STARTUP_BIAS_ENA
|
987 WM8993_VMID_BUF_ENA
|
988 WM8993_VMID_RAMP_MASK
|
990 WM8993_STARTUP_BIAS_ENA
|
991 WM8993_VMID_BUF_ENA
|
992 WM8993_VMID_RAMP_MASK
|
995 /* If either line output is single ended we
996 * need the VMID buffer */
997 if (!wm8993
->pdata
.lineout1_diff
||
998 !wm8993
->pdata
.lineout2_diff
)
999 snd_soc_update_bits(codec
, WM8993_ANTIPOP1
,
1000 WM8993_LINEOUT_VMID_BUF_ENA
,
1001 WM8993_LINEOUT_VMID_BUF_ENA
);
1004 snd_soc_update_bits(codec
, WM8993_POWER_MANAGEMENT_1
,
1005 WM8993_VMID_SEL_MASK
|
1007 WM8993_BIAS_ENA
| 0x2);
1010 /* Switch to normal bias */
1011 snd_soc_update_bits(codec
, WM8993_ANTIPOP2
,
1013 WM8993_STARTUP_BIAS_ENA
, 0);
1017 snd_soc_update_bits(codec
, WM8993_POWER_MANAGEMENT_1
,
1018 WM8993_VMID_SEL_MASK
, 0x4);
1020 snd_soc_update_bits(codec
, WM8993_POWER_MANAGEMENT_2
,
1021 WM8993_TSHUT_ENA
, 0);
1024 case SND_SOC_BIAS_OFF
:
1025 snd_soc_update_bits(codec
, WM8993_ANTIPOP1
,
1026 WM8993_LINEOUT_VMID_BUF_ENA
, 0);
1028 snd_soc_update_bits(codec
, WM8993_POWER_MANAGEMENT_1
,
1029 WM8993_VMID_SEL_MASK
| WM8993_BIAS_ENA
,
1032 #ifdef CONFIG_REGULATOR
1033 /* Post 2.6.34 we will be able to get a callback when
1034 * the regulators are disabled which we can use but
1035 * for now just assume that the power will be cut if
1036 * the regulator API is in use.
1038 codec
->cache_sync
= 1;
1041 regulator_bulk_disable(ARRAY_SIZE(wm8993
->supplies
),
1046 codec
->bias_level
= level
;
1051 static int wm8993_set_sysclk(struct snd_soc_dai
*codec_dai
,
1052 int clk_id
, unsigned int freq
, int dir
)
1054 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1055 struct wm8993_priv
*wm8993
= snd_soc_codec_get_drvdata(codec
);
1058 case WM8993_SYSCLK_MCLK
:
1059 wm8993
->mclk_rate
= freq
;
1060 case WM8993_SYSCLK_FLL
:
1061 wm8993
->sysclk_source
= clk_id
;
1071 static int wm8993_set_dai_fmt(struct snd_soc_dai
*dai
,
1074 struct snd_soc_codec
*codec
= dai
->codec
;
1075 struct wm8993_priv
*wm8993
= snd_soc_codec_get_drvdata(codec
);
1076 unsigned int aif1
= snd_soc_read(codec
, WM8993_AUDIO_INTERFACE_1
);
1077 unsigned int aif4
= snd_soc_read(codec
, WM8993_AUDIO_INTERFACE_4
);
1079 aif1
&= ~(WM8993_BCLK_DIR
| WM8993_AIF_BCLK_INV
|
1080 WM8993_AIF_LRCLK_INV
| WM8993_AIF_FMT_MASK
);
1081 aif4
&= ~WM8993_LRCLK_DIR
;
1083 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1084 case SND_SOC_DAIFMT_CBS_CFS
:
1087 case SND_SOC_DAIFMT_CBS_CFM
:
1088 aif4
|= WM8993_LRCLK_DIR
;
1091 case SND_SOC_DAIFMT_CBM_CFS
:
1092 aif1
|= WM8993_BCLK_DIR
;
1095 case SND_SOC_DAIFMT_CBM_CFM
:
1096 aif1
|= WM8993_BCLK_DIR
;
1097 aif4
|= WM8993_LRCLK_DIR
;
1104 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1105 case SND_SOC_DAIFMT_DSP_B
:
1106 aif1
|= WM8993_AIF_LRCLK_INV
;
1107 case SND_SOC_DAIFMT_DSP_A
:
1110 case SND_SOC_DAIFMT_I2S
:
1113 case SND_SOC_DAIFMT_RIGHT_J
:
1115 case SND_SOC_DAIFMT_LEFT_J
:
1122 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1123 case SND_SOC_DAIFMT_DSP_A
:
1124 case SND_SOC_DAIFMT_DSP_B
:
1125 /* frame inversion not valid for DSP modes */
1126 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1127 case SND_SOC_DAIFMT_NB_NF
:
1129 case SND_SOC_DAIFMT_IB_NF
:
1130 aif1
|= WM8993_AIF_BCLK_INV
;
1137 case SND_SOC_DAIFMT_I2S
:
1138 case SND_SOC_DAIFMT_RIGHT_J
:
1139 case SND_SOC_DAIFMT_LEFT_J
:
1140 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1141 case SND_SOC_DAIFMT_NB_NF
:
1143 case SND_SOC_DAIFMT_IB_IF
:
1144 aif1
|= WM8993_AIF_BCLK_INV
| WM8993_AIF_LRCLK_INV
;
1146 case SND_SOC_DAIFMT_IB_NF
:
1147 aif1
|= WM8993_AIF_BCLK_INV
;
1149 case SND_SOC_DAIFMT_NB_IF
:
1150 aif1
|= WM8993_AIF_LRCLK_INV
;
1160 snd_soc_write(codec
, WM8993_AUDIO_INTERFACE_1
, aif1
);
1161 snd_soc_write(codec
, WM8993_AUDIO_INTERFACE_4
, aif4
);
1166 static int wm8993_hw_params(struct snd_pcm_substream
*substream
,
1167 struct snd_pcm_hw_params
*params
,
1168 struct snd_soc_dai
*dai
)
1170 struct snd_soc_codec
*codec
= dai
->codec
;
1171 struct wm8993_priv
*wm8993
= snd_soc_codec_get_drvdata(codec
);
1172 int ret
, i
, best
, best_val
, cur_val
;
1173 unsigned int clocking1
, clocking3
, aif1
, aif4
;
1175 clocking1
= snd_soc_read(codec
, WM8993_CLOCKING_1
);
1176 clocking1
&= ~WM8993_BCLK_DIV_MASK
;
1178 clocking3
= snd_soc_read(codec
, WM8993_CLOCKING_3
);
1179 clocking3
&= ~(WM8993_CLK_SYS_RATE_MASK
| WM8993_SAMPLE_RATE_MASK
);
1181 aif1
= snd_soc_read(codec
, WM8993_AUDIO_INTERFACE_1
);
1182 aif1
&= ~WM8993_AIF_WL_MASK
;
1184 aif4
= snd_soc_read(codec
, WM8993_AUDIO_INTERFACE_4
);
1185 aif4
&= ~WM8993_LRCLK_RATE_MASK
;
1187 /* What BCLK do we need? */
1188 wm8993
->fs
= params_rate(params
);
1189 wm8993
->bclk
= 2 * wm8993
->fs
;
1190 if (wm8993
->tdm_slots
) {
1191 dev_dbg(codec
->dev
, "Configuring for %d %d bit TDM slots\n",
1192 wm8993
->tdm_slots
, wm8993
->tdm_width
);
1193 wm8993
->bclk
*= wm8993
->tdm_width
* wm8993
->tdm_slots
;
1195 switch (params_format(params
)) {
1196 case SNDRV_PCM_FORMAT_S16_LE
:
1199 case SNDRV_PCM_FORMAT_S20_3LE
:
1203 case SNDRV_PCM_FORMAT_S24_LE
:
1207 case SNDRV_PCM_FORMAT_S32_LE
:
1216 dev_dbg(codec
->dev
, "Target BCLK is %dHz\n", wm8993
->bclk
);
1218 ret
= configure_clock(codec
);
1222 /* Select nearest CLK_SYS_RATE */
1224 best_val
= abs((wm8993
->sysclk_rate
/ clk_sys_rates
[0].ratio
)
1226 for (i
= 1; i
< ARRAY_SIZE(clk_sys_rates
); i
++) {
1227 cur_val
= abs((wm8993
->sysclk_rate
/
1228 clk_sys_rates
[i
].ratio
) - wm8993
->fs
);;
1229 if (cur_val
< best_val
) {
1234 dev_dbg(codec
->dev
, "Selected CLK_SYS_RATIO of %d\n",
1235 clk_sys_rates
[best
].ratio
);
1236 clocking3
|= (clk_sys_rates
[best
].clk_sys_rate
1237 << WM8993_CLK_SYS_RATE_SHIFT
);
1241 best_val
= abs(wm8993
->fs
- sample_rates
[0].rate
);
1242 for (i
= 1; i
< ARRAY_SIZE(sample_rates
); i
++) {
1244 cur_val
= abs(wm8993
->fs
- sample_rates
[i
].rate
);
1245 if (cur_val
< best_val
) {
1250 dev_dbg(codec
->dev
, "Selected SAMPLE_RATE of %dHz\n",
1251 sample_rates
[best
].rate
);
1252 clocking3
|= (sample_rates
[best
].sample_rate
1253 << WM8993_SAMPLE_RATE_SHIFT
);
1258 for (i
= 0; i
< ARRAY_SIZE(bclk_divs
); i
++) {
1259 cur_val
= ((wm8993
->sysclk_rate
* 10) / bclk_divs
[i
].div
)
1261 if (cur_val
< 0) /* Table is sorted */
1263 if (cur_val
< best_val
) {
1268 wm8993
->bclk
= (wm8993
->sysclk_rate
* 10) / bclk_divs
[best
].div
;
1269 dev_dbg(codec
->dev
, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1270 bclk_divs
[best
].div
, wm8993
->bclk
);
1271 clocking1
|= bclk_divs
[best
].bclk_div
<< WM8993_BCLK_DIV_SHIFT
;
1273 /* LRCLK is a simple fraction of BCLK */
1274 dev_dbg(codec
->dev
, "LRCLK_RATE is %d\n", wm8993
->bclk
/ wm8993
->fs
);
1275 aif4
|= wm8993
->bclk
/ wm8993
->fs
;
1277 snd_soc_write(codec
, WM8993_CLOCKING_1
, clocking1
);
1278 snd_soc_write(codec
, WM8993_CLOCKING_3
, clocking3
);
1279 snd_soc_write(codec
, WM8993_AUDIO_INTERFACE_1
, aif1
);
1280 snd_soc_write(codec
, WM8993_AUDIO_INTERFACE_4
, aif4
);
1282 /* ReTune Mobile? */
1283 if (wm8993
->pdata
.num_retune_configs
) {
1284 u16 eq1
= snd_soc_read(codec
, WM8993_EQ1
);
1285 struct wm8993_retune_mobile_setting
*s
;
1288 best_val
= abs(wm8993
->pdata
.retune_configs
[0].rate
1290 for (i
= 0; i
< wm8993
->pdata
.num_retune_configs
; i
++) {
1291 cur_val
= abs(wm8993
->pdata
.retune_configs
[i
].rate
1293 if (cur_val
< best_val
) {
1298 s
= &wm8993
->pdata
.retune_configs
[best
];
1300 dev_dbg(codec
->dev
, "ReTune Mobile %s tuned for %dHz\n",
1303 /* Disable EQ while we reconfigure */
1304 snd_soc_update_bits(codec
, WM8993_EQ1
, WM8993_EQ_ENA
, 0);
1306 for (i
= 1; i
< ARRAY_SIZE(s
->config
); i
++)
1307 snd_soc_write(codec
, WM8993_EQ1
+ i
, s
->config
[i
]);
1309 snd_soc_update_bits(codec
, WM8993_EQ1
, WM8993_EQ_ENA
, eq1
);
1315 static int wm8993_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
1317 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1320 reg
= snd_soc_read(codec
, WM8993_DAC_CTRL
);
1323 reg
|= WM8993_DAC_MUTE
;
1325 reg
&= ~WM8993_DAC_MUTE
;
1327 snd_soc_write(codec
, WM8993_DAC_CTRL
, reg
);
1332 static int wm8993_set_tdm_slot(struct snd_soc_dai
*dai
, unsigned int tx_mask
,
1333 unsigned int rx_mask
, int slots
, int slot_width
)
1335 struct snd_soc_codec
*codec
= dai
->codec
;
1336 struct wm8993_priv
*wm8993
= snd_soc_codec_get_drvdata(codec
);
1340 /* Don't need to validate anything if we're turning off TDM */
1342 wm8993
->tdm_slots
= 0;
1346 /* Note that we allow configurations we can't handle ourselves -
1347 * for example, we can generate clocks for slots 2 and up even if
1348 * we can't use those slots ourselves.
1350 aif1
|= WM8993_AIFADC_TDM
;
1351 aif2
|= WM8993_AIFDAC_TDM
;
1357 aif1
|= WM8993_AIFADC_TDM_CHAN
;
1368 aif2
|= WM8993_AIFDAC_TDM_CHAN
;
1375 wm8993
->tdm_width
= slot_width
;
1376 wm8993
->tdm_slots
= slots
/ 2;
1378 snd_soc_update_bits(codec
, WM8993_AUDIO_INTERFACE_1
,
1379 WM8993_AIFADC_TDM
| WM8993_AIFADC_TDM_CHAN
, aif1
);
1380 snd_soc_update_bits(codec
, WM8993_AUDIO_INTERFACE_2
,
1381 WM8993_AIFDAC_TDM
| WM8993_AIFDAC_TDM_CHAN
, aif2
);
1386 static struct snd_soc_dai_ops wm8993_ops
= {
1387 .set_sysclk
= wm8993_set_sysclk
,
1388 .set_fmt
= wm8993_set_dai_fmt
,
1389 .hw_params
= wm8993_hw_params
,
1390 .digital_mute
= wm8993_digital_mute
,
1391 .set_pll
= wm8993_set_fll
,
1392 .set_tdm_slot
= wm8993_set_tdm_slot
,
1395 #define WM8993_RATES SNDRV_PCM_RATE_8000_48000
1397 #define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1398 SNDRV_PCM_FMTBIT_S20_3LE |\
1399 SNDRV_PCM_FMTBIT_S24_LE |\
1400 SNDRV_PCM_FMTBIT_S32_LE)
1402 static struct snd_soc_dai_driver wm8993_dai
= {
1403 .name
= "wm8993-hifi",
1405 .stream_name
= "Playback",
1408 .rates
= WM8993_RATES
,
1409 .formats
= WM8993_FORMATS
,
1412 .stream_name
= "Capture",
1415 .rates
= WM8993_RATES
,
1416 .formats
= WM8993_FORMATS
,
1419 .symmetric_rates
= 1,
1422 static int wm8993_probe(struct snd_soc_codec
*codec
)
1424 struct wm8993_priv
*wm8993
= snd_soc_codec_get_drvdata(codec
);
1427 wm8993
->hubs_data
.hp_startup_mode
= 1;
1428 wm8993
->hubs_data
.dcs_codes
= -2;
1430 ret
= snd_soc_codec_set_cache_io(codec
, 8, 16, SND_SOC_I2C
);
1432 dev_err(codec
->dev
, "Failed to set cache I/O: %d\n", ret
);
1436 for (i
= 0; i
< ARRAY_SIZE(wm8993
->supplies
); i
++)
1437 wm8993
->supplies
[i
].supply
= wm8993_supply_names
[i
];
1439 ret
= regulator_bulk_get(codec
->dev
, ARRAY_SIZE(wm8993
->supplies
),
1442 dev_err(codec
->dev
, "Failed to request supplies: %d\n", ret
);
1446 ret
= regulator_bulk_enable(ARRAY_SIZE(wm8993
->supplies
),
1449 dev_err(codec
->dev
, "Failed to enable supplies: %d\n", ret
);
1453 val
= snd_soc_read(codec
, WM8993_SOFTWARE_RESET
);
1454 if (val
!= wm8993_reg_defaults
[WM8993_SOFTWARE_RESET
]) {
1455 dev_err(codec
->dev
, "Invalid ID register value %x\n", val
);
1460 ret
= snd_soc_write(codec
, WM8993_SOFTWARE_RESET
, 0xffff);
1464 codec
->cache_only
= 1;
1466 /* By default we're using the output mixers */
1467 wm8993
->class_w_users
= 2;
1469 /* Latch volume update bits and default ZC on */
1470 snd_soc_update_bits(codec
, WM8993_RIGHT_DAC_DIGITAL_VOLUME
,
1471 WM8993_DAC_VU
, WM8993_DAC_VU
);
1472 snd_soc_update_bits(codec
, WM8993_RIGHT_ADC_DIGITAL_VOLUME
,
1473 WM8993_ADC_VU
, WM8993_ADC_VU
);
1475 /* Manualy manage the HPOUT sequencing for independent stereo
1477 snd_soc_update_bits(codec
, WM8993_ANALOGUE_HP_0
,
1478 WM8993_HPOUT1_AUTO_PU
, 0);
1480 /* Use automatic clock configuration */
1481 snd_soc_update_bits(codec
, WM8993_CLOCKING_4
, WM8993_SR_MODE
, 0);
1483 wm_hubs_handle_analogue_pdata(codec
, wm8993
->pdata
.lineout1_diff
,
1484 wm8993
->pdata
.lineout2_diff
,
1485 wm8993
->pdata
.lineout1fb
,
1486 wm8993
->pdata
.lineout2fb
,
1487 wm8993
->pdata
.jd_scthr
,
1488 wm8993
->pdata
.jd_thr
,
1489 wm8993
->pdata
.micbias1_lvl
,
1490 wm8993
->pdata
.micbias2_lvl
);
1492 ret
= wm8993_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1496 snd_soc_add_controls(codec
, wm8993_snd_controls
,
1497 ARRAY_SIZE(wm8993_snd_controls
));
1498 if (wm8993
->pdata
.num_retune_configs
!= 0) {
1499 dev_dbg(codec
->dev
, "Using ReTune Mobile\n");
1501 dev_dbg(codec
->dev
, "No ReTune Mobile, using normal EQ\n");
1502 snd_soc_add_controls(codec
, wm8993_eq_controls
,
1503 ARRAY_SIZE(wm8993_eq_controls
));
1506 snd_soc_dapm_new_controls(codec
, wm8993_dapm_widgets
,
1507 ARRAY_SIZE(wm8993_dapm_widgets
));
1508 wm_hubs_add_analogue_controls(codec
);
1510 snd_soc_dapm_add_routes(codec
, routes
, ARRAY_SIZE(routes
));
1511 wm_hubs_add_analogue_routes(codec
, wm8993
->pdata
.lineout1_diff
,
1512 wm8993
->pdata
.lineout2_diff
);
1517 regulator_bulk_disable(ARRAY_SIZE(wm8993
->supplies
), wm8993
->supplies
);
1519 regulator_bulk_free(ARRAY_SIZE(wm8993
->supplies
), wm8993
->supplies
);
1523 static int wm8993_remove(struct snd_soc_codec
*codec
)
1525 struct wm8993_priv
*wm8993
= snd_soc_codec_get_drvdata(codec
);
1527 wm8993_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1528 regulator_bulk_free(ARRAY_SIZE(wm8993
->supplies
), wm8993
->supplies
);
1533 static int wm8993_suspend(struct snd_soc_codec
*codec
, pm_message_t state
)
1535 struct wm8993_priv
*wm8993
= snd_soc_codec_get_drvdata(codec
);
1536 int fll_fout
= wm8993
->fll_fout
;
1537 int fll_fref
= wm8993
->fll_fref
;
1540 /* Stop the FLL in an orderly fashion */
1541 ret
= _wm8993_set_fll(codec
, 0, 0, 0, 0);
1543 dev_err(codec
->dev
, "Failed to stop FLL\n");
1547 wm8993
->fll_fout
= fll_fout
;
1548 wm8993
->fll_fref
= fll_fref
;
1550 wm8993_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1555 static int wm8993_resume(struct snd_soc_codec
*codec
)
1557 struct wm8993_priv
*wm8993
= snd_soc_codec_get_drvdata(codec
);
1560 wm8993_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1562 /* Restart the FLL? */
1563 if (wm8993
->fll_fout
) {
1564 int fll_fout
= wm8993
->fll_fout
;
1565 int fll_fref
= wm8993
->fll_fref
;
1567 wm8993
->fll_fref
= 0;
1568 wm8993
->fll_fout
= 0;
1570 ret
= _wm8993_set_fll(codec
, 0, wm8993
->fll_src
,
1571 fll_fref
, fll_fout
);
1573 dev_err(codec
->dev
, "Failed to restart FLL\n");
1579 #define wm8993_suspend NULL
1580 #define wm8993_resume NULL
1583 static struct snd_soc_codec_driver soc_codec_dev_wm8993
= {
1584 .probe
= wm8993_probe
,
1585 .remove
= wm8993_remove
,
1586 .suspend
= wm8993_suspend
,
1587 .resume
= wm8993_resume
,
1588 .set_bias_level
= wm8993_set_bias_level
,
1589 .reg_cache_size
= ARRAY_SIZE(wm8993_reg_defaults
),
1590 .reg_word_size
= sizeof(u16
),
1591 .reg_cache_default
= wm8993_reg_defaults
,
1592 .volatile_register
= wm8993_volatile
,
1595 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1596 static __devinit
int wm8993_i2c_probe(struct i2c_client
*i2c
,
1597 const struct i2c_device_id
*id
)
1599 struct wm8993_priv
*wm8993
;
1602 wm8993
= kzalloc(sizeof(struct wm8993_priv
), GFP_KERNEL
);
1606 i2c_set_clientdata(i2c
, wm8993
);
1608 ret
= snd_soc_register_codec(&i2c
->dev
,
1609 &soc_codec_dev_wm8993
, &wm8993_dai
, 1);
1615 static __devexit
int wm8993_i2c_remove(struct i2c_client
*client
)
1617 snd_soc_unregister_codec(&client
->dev
);
1618 kfree(i2c_get_clientdata(client
));
1622 static const struct i2c_device_id wm8993_i2c_id
[] = {
1626 MODULE_DEVICE_TABLE(i2c
, wm8993_i2c_id
);
1628 static struct i2c_driver wm8993_i2c_driver
= {
1630 .name
= "wm8993-codec",
1631 .owner
= THIS_MODULE
,
1633 .probe
= wm8993_i2c_probe
,
1634 .remove
= __devexit_p(wm8993_i2c_remove
),
1635 .id_table
= wm8993_i2c_id
,
1639 static int __init
wm8993_modinit(void)
1642 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1643 ret
= i2c_add_driver(&wm8993_i2c_driver
);
1645 pr_err("WM8993: Unable to register I2C driver: %d\n",
1651 module_init(wm8993_modinit
);
1653 static void __exit
wm8993_exit(void)
1655 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1656 i2c_del_driver(&wm8993_i2c_driver
);
1659 module_exit(wm8993_exit
);
1662 MODULE_DESCRIPTION("ASoC WM8993 driver");
1663 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1664 MODULE_LICENSE("GPL");