2 * wm8580.c -- WM8580 ALSA Soc Audio driver
4 * Copyright 2008 Wolfson Microelectronics PLC.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
12 * The WM8580 is a multichannel codec with S/PDIF support, featuring six
13 * DAC channels and two ADC channels.
15 * Currently only the primary audio interface is supported - S/PDIF and
16 * the secondary audio interfaces are not.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
25 #include <linux/i2c.h>
26 #include <linux/platform_device.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/soc.h>
31 #include <sound/soc-dapm.h>
32 #include <sound/tlv.h>
33 #include <sound/initval.h>
34 #include <asm/div64.h>
38 #define WM8580_VERSION "0.1"
45 /* codec private data */
51 /* WM8580 register space */
52 #define WM8580_PLLA1 0x00
53 #define WM8580_PLLA2 0x01
54 #define WM8580_PLLA3 0x02
55 #define WM8580_PLLA4 0x03
56 #define WM8580_PLLB1 0x04
57 #define WM8580_PLLB2 0x05
58 #define WM8580_PLLB3 0x06
59 #define WM8580_PLLB4 0x07
60 #define WM8580_CLKSEL 0x08
61 #define WM8580_PAIF1 0x09
62 #define WM8580_PAIF2 0x0A
63 #define WM8580_SAIF1 0x0B
64 #define WM8580_PAIF3 0x0C
65 #define WM8580_PAIF4 0x0D
66 #define WM8580_SAIF2 0x0E
67 #define WM8580_DAC_CONTROL1 0x0F
68 #define WM8580_DAC_CONTROL2 0x10
69 #define WM8580_DAC_CONTROL3 0x11
70 #define WM8580_DAC_CONTROL4 0x12
71 #define WM8580_DAC_CONTROL5 0x13
72 #define WM8580_DIGITAL_ATTENUATION_DACL1 0x14
73 #define WM8580_DIGITAL_ATTENUATION_DACR1 0x15
74 #define WM8580_DIGITAL_ATTENUATION_DACL2 0x16
75 #define WM8580_DIGITAL_ATTENUATION_DACR2 0x17
76 #define WM8580_DIGITAL_ATTENUATION_DACL3 0x18
77 #define WM8580_DIGITAL_ATTENUATION_DACR3 0x19
78 #define WM8580_MASTER_DIGITAL_ATTENUATION 0x1C
79 #define WM8580_ADC_CONTROL1 0x1D
80 #define WM8580_SPDTXCHAN0 0x1E
81 #define WM8580_SPDTXCHAN1 0x1F
82 #define WM8580_SPDTXCHAN2 0x20
83 #define WM8580_SPDTXCHAN3 0x21
84 #define WM8580_SPDTXCHAN4 0x22
85 #define WM8580_SPDTXCHAN5 0x23
86 #define WM8580_SPDMODE 0x24
87 #define WM8580_INTMASK 0x25
88 #define WM8580_GPO1 0x26
89 #define WM8580_GPO2 0x27
90 #define WM8580_GPO3 0x28
91 #define WM8580_GPO4 0x29
92 #define WM8580_GPO5 0x2A
93 #define WM8580_INTSTAT 0x2B
94 #define WM8580_SPDRXCHAN1 0x2C
95 #define WM8580_SPDRXCHAN2 0x2D
96 #define WM8580_SPDRXCHAN3 0x2E
97 #define WM8580_SPDRXCHAN4 0x2F
98 #define WM8580_SPDRXCHAN5 0x30
99 #define WM8580_SPDSTAT 0x31
100 #define WM8580_PWRDN1 0x32
101 #define WM8580_PWRDN2 0x33
102 #define WM8580_READBACK 0x34
103 #define WM8580_RESET 0x35
105 /* PLLB4 (register 7h) */
106 #define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60
107 #define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20
108 #define WM8580_PLLB4_MCLKOUTSRC_PLLB 0x40
109 #define WM8580_PLLB4_MCLKOUTSRC_OSC 0x60
111 #define WM8580_PLLB4_CLKOUTSRC_MASK 0x180
112 #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
113 #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
114 #define WM8580_PLLB4_CLKOUTSRC_OSCCLK 0x180
116 /* CLKSEL (register 8h) */
117 #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
118 #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
119 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
121 /* AIF control 1 (registers 9h-bh) */
122 #define WM8580_AIF_RATE_MASK 0x7
123 #define WM8580_AIF_RATE_128 0x0
124 #define WM8580_AIF_RATE_192 0x1
125 #define WM8580_AIF_RATE_256 0x2
126 #define WM8580_AIF_RATE_384 0x3
127 #define WM8580_AIF_RATE_512 0x4
128 #define WM8580_AIF_RATE_768 0x5
129 #define WM8580_AIF_RATE_1152 0x6
131 #define WM8580_AIF_BCLKSEL_MASK 0x18
132 #define WM8580_AIF_BCLKSEL_64 0x00
133 #define WM8580_AIF_BCLKSEL_128 0x08
134 #define WM8580_AIF_BCLKSEL_256 0x10
135 #define WM8580_AIF_BCLKSEL_SYSCLK 0x18
137 #define WM8580_AIF_MS 0x20
139 #define WM8580_AIF_CLKSRC_MASK 0xc0
140 #define WM8580_AIF_CLKSRC_PLLA 0x40
141 #define WM8580_AIF_CLKSRC_PLLB 0x40
142 #define WM8580_AIF_CLKSRC_MCLK 0xc0
144 /* AIF control 2 (registers ch-eh) */
145 #define WM8580_AIF_FMT_MASK 0x03
146 #define WM8580_AIF_FMT_RIGHTJ 0x00
147 #define WM8580_AIF_FMT_LEFTJ 0x01
148 #define WM8580_AIF_FMT_I2S 0x02
149 #define WM8580_AIF_FMT_DSP 0x03
151 #define WM8580_AIF_LENGTH_MASK 0x0c
152 #define WM8580_AIF_LENGTH_16 0x00
153 #define WM8580_AIF_LENGTH_20 0x04
154 #define WM8580_AIF_LENGTH_24 0x08
155 #define WM8580_AIF_LENGTH_32 0x0c
157 #define WM8580_AIF_LRP 0x10
158 #define WM8580_AIF_BCP 0x20
160 /* Powerdown Register 1 (register 32h) */
161 #define WM8580_PWRDN1_PWDN 0x001
162 #define WM8580_PWRDN1_ALLDACPD 0x040
164 /* Powerdown Register 2 (register 33h) */
165 #define WM8580_PWRDN2_OSSCPD 0x001
166 #define WM8580_PWRDN2_PLLAPD 0x002
167 #define WM8580_PWRDN2_PLLBPD 0x004
168 #define WM8580_PWRDN2_SPDIFPD 0x008
169 #define WM8580_PWRDN2_SPDIFTXD 0x010
170 #define WM8580_PWRDN2_SPDIFRXD 0x020
172 #define WM8580_DAC_CONTROL5_MUTEALL 0x10
175 * wm8580 register cache
176 * We can't read the WM8580 register space when we
177 * are using 2 wire for device control, so we cache them instead.
179 static const u16 wm8580_reg
[] = {
180 0x0121, 0x017e, 0x007d, 0x0014, /*R3*/
181 0x0121, 0x017e, 0x007d, 0x0194, /*R7*/
182 0x001c, 0x0002, 0x0002, 0x00c2, /*R11*/
183 0x0182, 0x0082, 0x000a, 0x0024, /*R15*/
184 0x0009, 0x0000, 0x00ff, 0x0000, /*R19*/
185 0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R23*/
186 0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R27*/
187 0x01f0, 0x0040, 0x0000, 0x0000, /*R31(0x1F)*/
188 0x0000, 0x0000, 0x0031, 0x000b, /*R35*/
189 0x0039, 0x0000, 0x0010, 0x0032, /*R39*/
190 0x0054, 0x0076, 0x0098, 0x0000, /*R43(0x2B)*/
191 0x0000, 0x0000, 0x0000, 0x0000, /*R47*/
192 0x0000, 0x0000, 0x005e, 0x003e, /*R51(0x33)*/
193 0x0000, 0x0000 /*R53*/
197 * read wm8580 register cache
199 static inline unsigned int wm8580_read_reg_cache(struct snd_soc_codec
*codec
,
202 u16
*cache
= codec
->reg_cache
;
203 BUG_ON(reg
> ARRAY_SIZE(wm8580_reg
));
208 * write wm8580 register cache
210 static inline void wm8580_write_reg_cache(struct snd_soc_codec
*codec
,
211 unsigned int reg
, unsigned int value
)
213 u16
*cache
= codec
->reg_cache
;
219 * write to the WM8580 register space
221 static int wm8580_write(struct snd_soc_codec
*codec
, unsigned int reg
,
226 BUG_ON(reg
> ARRAY_SIZE(wm8580_reg
));
228 /* Registers are 9 bits wide */
236 if (value
== wm8580_read_reg_cache(codec
, reg
))
241 * D15..D9 WM8580 register offset
242 * D8...D0 register data
244 data
[0] = (reg
<< 1) | ((value
>> 8) & 0x0001);
245 data
[1] = value
& 0x00ff;
247 wm8580_write_reg_cache(codec
, reg
, value
);
248 if (codec
->hw_write(codec
->control_data
, data
, 2) == 2)
254 static inline unsigned int wm8580_read(struct snd_soc_codec
*codec
,
259 return wm8580_read_reg_cache(codec
, reg
);
263 static const DECLARE_TLV_DB_SCALE(dac_tlv
, -12750, 50, 1);
265 static int wm8580_out_vu(struct snd_kcontrol
*kcontrol
,
266 struct snd_ctl_elem_value
*ucontrol
)
268 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
269 int reg
= kcontrol
->private_value
& 0xff;
270 int reg2
= (kcontrol
->private_value
>> 24) & 0xff;
274 /* Clear the register cache so we write without VU set */
275 wm8580_write_reg_cache(codec
, reg
, 0);
276 wm8580_write_reg_cache(codec
, reg2
, 0);
278 ret
= snd_soc_put_volsw_2r(kcontrol
, ucontrol
);
282 /* Now write again with the volume update bit set */
283 val
= wm8580_read_reg_cache(codec
, reg
);
284 wm8580_write(codec
, reg
, val
| 0x0100);
286 val
= wm8580_read_reg_cache(codec
, reg2
);
287 wm8580_write(codec
, reg2
, val
| 0x0100);
292 #define SOC_WM8580_OUT_DOUBLE_R_TLV(xname, reg_left, reg_right, shift, max, invert, tlv_array) \
293 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
294 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
295 SNDRV_CTL_ELEM_ACCESS_READWRITE, \
296 .tlv.p = (tlv_array), \
297 .info = snd_soc_info_volsw_2r, \
298 .get = snd_soc_get_volsw_2r, .put = wm8580_out_vu, \
299 .private_value = (reg_left) | ((shift) << 8) | \
300 ((max) << 12) | ((invert) << 20) | ((reg_right) << 24) }
302 static const struct snd_kcontrol_new wm8580_snd_controls
[] = {
303 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC1 Playback Volume",
304 WM8580_DIGITAL_ATTENUATION_DACL1
,
305 WM8580_DIGITAL_ATTENUATION_DACR1
,
306 0, 0xff, 0, dac_tlv
),
307 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC2 Playback Volume",
308 WM8580_DIGITAL_ATTENUATION_DACL2
,
309 WM8580_DIGITAL_ATTENUATION_DACR2
,
310 0, 0xff, 0, dac_tlv
),
311 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC3 Playback Volume",
312 WM8580_DIGITAL_ATTENUATION_DACL3
,
313 WM8580_DIGITAL_ATTENUATION_DACR3
,
314 0, 0xff, 0, dac_tlv
),
316 SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3
, 0, 1, 0),
317 SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3
, 1, 1, 0),
318 SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3
, 2, 1, 0),
320 SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4
, 0, 1, 1, 0),
321 SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4
, 2, 3, 1, 0),
322 SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4
, 4, 5, 1, 0),
324 SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5
, 5, 1, 0),
325 SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5
, 0, 1, 0),
326 SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5
, 1, 1, 0),
327 SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5
, 2, 1, 0),
329 SOC_DOUBLE("ADC Mute Switch", WM8580_ADC_CONTROL1
, 0, 1, 1, 0),
330 SOC_SINGLE("ADC High-Pass Filter Switch", WM8580_ADC_CONTROL1
, 4, 1, 0),
333 /* Add non-DAPM controls */
334 static int wm8580_add_controls(struct snd_soc_codec
*codec
)
338 for (i
= 0; i
< ARRAY_SIZE(wm8580_snd_controls
); i
++) {
339 err
= snd_ctl_add(codec
->card
,
340 snd_soc_cnew(&wm8580_snd_controls
[i
],
347 static const struct snd_soc_dapm_widget wm8580_dapm_widgets
[] = {
348 SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1
, 2, 1),
349 SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1
, 3, 1),
350 SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1
, 4, 1),
352 SND_SOC_DAPM_OUTPUT("VOUT1L"),
353 SND_SOC_DAPM_OUTPUT("VOUT1R"),
354 SND_SOC_DAPM_OUTPUT("VOUT2L"),
355 SND_SOC_DAPM_OUTPUT("VOUT2R"),
356 SND_SOC_DAPM_OUTPUT("VOUT3L"),
357 SND_SOC_DAPM_OUTPUT("VOUT3R"),
359 SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1
, 1, 1),
361 SND_SOC_DAPM_INPUT("AINL"),
362 SND_SOC_DAPM_INPUT("AINR"),
365 static const struct snd_soc_dapm_route audio_map
[] = {
366 { "VOUT1L", NULL
, "DAC1" },
367 { "VOUT1R", NULL
, "DAC1" },
369 { "VOUT2L", NULL
, "DAC2" },
370 { "VOUT2R", NULL
, "DAC2" },
372 { "VOUT3L", NULL
, "DAC3" },
373 { "VOUT3R", NULL
, "DAC3" },
375 { "ADC", NULL
, "AINL" },
376 { "ADC", NULL
, "AINR" },
379 static int wm8580_add_widgets(struct snd_soc_codec
*codec
)
381 snd_soc_dapm_new_controls(codec
, wm8580_dapm_widgets
,
382 ARRAY_SIZE(wm8580_dapm_widgets
));
384 snd_soc_dapm_add_routes(codec
, audio_map
, ARRAY_SIZE(audio_map
));
386 snd_soc_dapm_new_widgets(codec
);
399 /* The size in bits of the pll divide */
400 #define FIXED_PLL_SIZE (1 << 22)
402 /* PLL rate to output rate divisions */
405 unsigned int freqmode
;
406 unsigned int postscale
;
418 static int pll_factors(struct _pll_div
*pll_div
, unsigned int target
,
422 unsigned int K
, Ndiv
, Nmod
;
425 pr_debug("wm8580: PLL %dHz->%dHz\n", source
, target
);
427 /* Scale the output frequency up; the PLL should run in the
428 * region of 90-100MHz.
430 for (i
= 0; i
< ARRAY_SIZE(post_table
); i
++) {
431 if (target
* post_table
[i
].div
>= 90000000 &&
432 target
* post_table
[i
].div
<= 100000000) {
433 pll_div
->freqmode
= post_table
[i
].freqmode
;
434 pll_div
->postscale
= post_table
[i
].postscale
;
435 target
*= post_table
[i
].div
;
440 if (i
== ARRAY_SIZE(post_table
)) {
441 printk(KERN_ERR
"wm8580: Unable to scale output frequency "
446 Ndiv
= target
/ source
;
450 pll_div
->prescale
= 1;
451 Ndiv
= target
/ source
;
453 pll_div
->prescale
= 0;
455 if ((Ndiv
< 5) || (Ndiv
> 13)) {
457 "WM8580 N=%d outside supported range\n", Ndiv
);
462 Nmod
= target
% source
;
463 Kpart
= FIXED_PLL_SIZE
* (long long)Nmod
;
465 do_div(Kpart
, source
);
467 K
= Kpart
& 0xFFFFFFFF;
471 pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
472 pll_div
->n
, pll_div
->k
, pll_div
->prescale
, pll_div
->freqmode
,
478 static int wm8580_set_dai_pll(struct snd_soc_dai
*codec_dai
,
479 int pll_id
, unsigned int freq_in
, unsigned int freq_out
)
482 struct snd_soc_codec
*codec
= codec_dai
->codec
;
483 struct wm8580_priv
*wm8580
= codec
->private_data
;
484 struct pll_state
*state
;
485 struct _pll_div pll_div
;
487 unsigned int pwr_mask
;
490 /* GCC isn't able to work out the ifs below for initialising/using
491 * pll_div so suppress warnings.
493 memset(&pll_div
, 0, sizeof(pll_div
));
499 pwr_mask
= WM8580_PWRDN2_PLLAPD
;
504 pwr_mask
= WM8580_PWRDN2_PLLBPD
;
510 if (freq_in
&& freq_out
) {
511 ret
= pll_factors(&pll_div
, freq_out
, freq_in
);
517 state
->out
= freq_out
;
519 /* Always disable the PLL - it is not safe to leave it running
520 * while reprogramming it.
522 reg
= wm8580_read(codec
, WM8580_PWRDN2
);
523 wm8580_write(codec
, WM8580_PWRDN2
, reg
| pwr_mask
);
525 if (!freq_in
|| !freq_out
)
528 wm8580_write(codec
, WM8580_PLLA1
+ offset
, pll_div
.k
& 0x1ff);
529 wm8580_write(codec
, WM8580_PLLA2
+ offset
, (pll_div
.k
>> 9) & 0xff);
530 wm8580_write(codec
, WM8580_PLLA3
+ offset
,
531 (pll_div
.k
>> 18 & 0xf) | (pll_div
.n
<< 4));
533 reg
= wm8580_read(codec
, WM8580_PLLA4
+ offset
);
535 reg
|= pll_div
.prescale
| pll_div
.postscale
<< 1 |
536 pll_div
.freqmode
<< 4;
538 wm8580_write(codec
, WM8580_PLLA4
+ offset
, reg
);
540 /* All done, turn it on */
541 reg
= wm8580_read(codec
, WM8580_PWRDN2
);
542 wm8580_write(codec
, WM8580_PWRDN2
, reg
& ~pwr_mask
);
548 * Set PCM DAI bit size and sample rate.
550 static int wm8580_paif_hw_params(struct snd_pcm_substream
*substream
,
551 struct snd_pcm_hw_params
*params
)
553 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
554 struct snd_soc_dai_link
*dai
= rtd
->dai
;
555 struct snd_soc_device
*socdev
= rtd
->socdev
;
556 struct snd_soc_codec
*codec
= socdev
->codec
;
557 u16 paifb
= wm8580_read(codec
, WM8580_PAIF3
+ dai
->codec_dai
->id
);
559 paifb
&= ~WM8580_AIF_LENGTH_MASK
;
561 switch (params_format(params
)) {
562 case SNDRV_PCM_FORMAT_S16_LE
:
564 case SNDRV_PCM_FORMAT_S20_3LE
:
565 paifb
|= WM8580_AIF_LENGTH_20
;
567 case SNDRV_PCM_FORMAT_S24_LE
:
568 paifb
|= WM8580_AIF_LENGTH_24
;
570 case SNDRV_PCM_FORMAT_S32_LE
:
571 paifb
|= WM8580_AIF_LENGTH_24
;
577 wm8580_write(codec
, WM8580_PAIF3
+ dai
->codec_dai
->id
, paifb
);
581 static int wm8580_set_paif_dai_fmt(struct snd_soc_dai
*codec_dai
,
584 struct snd_soc_codec
*codec
= codec_dai
->codec
;
587 int can_invert_lrclk
;
589 aifa
= wm8580_read(codec
, WM8580_PAIF1
+ codec_dai
->id
);
590 aifb
= wm8580_read(codec
, WM8580_PAIF3
+ codec_dai
->id
);
592 aifb
&= ~(WM8580_AIF_FMT_MASK
| WM8580_AIF_LRP
| WM8580_AIF_BCP
);
594 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
595 case SND_SOC_DAIFMT_CBS_CFS
:
596 aifa
&= ~WM8580_AIF_MS
;
598 case SND_SOC_DAIFMT_CBM_CFM
:
599 aifa
|= WM8580_AIF_MS
;
605 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
606 case SND_SOC_DAIFMT_I2S
:
607 can_invert_lrclk
= 1;
608 aifb
|= WM8580_AIF_FMT_I2S
;
610 case SND_SOC_DAIFMT_RIGHT_J
:
611 can_invert_lrclk
= 1;
612 aifb
|= WM8580_AIF_FMT_RIGHTJ
;
614 case SND_SOC_DAIFMT_LEFT_J
:
615 can_invert_lrclk
= 1;
616 aifb
|= WM8580_AIF_FMT_LEFTJ
;
618 case SND_SOC_DAIFMT_DSP_A
:
619 can_invert_lrclk
= 0;
620 aifb
|= WM8580_AIF_FMT_DSP
;
622 case SND_SOC_DAIFMT_DSP_B
:
623 can_invert_lrclk
= 0;
624 aifb
|= WM8580_AIF_FMT_DSP
;
625 aifb
|= WM8580_AIF_LRP
;
631 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
632 case SND_SOC_DAIFMT_NB_NF
:
635 case SND_SOC_DAIFMT_IB_IF
:
636 if (!can_invert_lrclk
)
638 aifb
|= WM8580_AIF_BCP
;
639 aifb
|= WM8580_AIF_LRP
;
642 case SND_SOC_DAIFMT_IB_NF
:
643 aifb
|= WM8580_AIF_BCP
;
646 case SND_SOC_DAIFMT_NB_IF
:
647 if (!can_invert_lrclk
)
649 aifb
|= WM8580_AIF_LRP
;
656 wm8580_write(codec
, WM8580_PAIF1
+ codec_dai
->id
, aifa
);
657 wm8580_write(codec
, WM8580_PAIF3
+ codec_dai
->id
, aifb
);
662 static int wm8580_set_dai_clkdiv(struct snd_soc_dai
*codec_dai
,
665 struct snd_soc_codec
*codec
= codec_dai
->codec
;
670 reg
= wm8580_read(codec
, WM8580_PLLB4
);
671 reg
&= ~WM8580_PLLB4_MCLKOUTSRC_MASK
;
674 case WM8580_CLKSRC_MCLK
:
678 case WM8580_CLKSRC_PLLA
:
679 reg
|= WM8580_PLLB4_MCLKOUTSRC_PLLA
;
681 case WM8580_CLKSRC_PLLB
:
682 reg
|= WM8580_PLLB4_MCLKOUTSRC_PLLB
;
685 case WM8580_CLKSRC_OSC
:
686 reg
|= WM8580_PLLB4_MCLKOUTSRC_OSC
;
692 wm8580_write(codec
, WM8580_PLLB4
, reg
);
695 case WM8580_DAC_CLKSEL
:
696 reg
= wm8580_read(codec
, WM8580_CLKSEL
);
697 reg
&= ~WM8580_CLKSEL_DAC_CLKSEL_MASK
;
700 case WM8580_CLKSRC_MCLK
:
703 case WM8580_CLKSRC_PLLA
:
704 reg
|= WM8580_CLKSEL_DAC_CLKSEL_PLLA
;
707 case WM8580_CLKSRC_PLLB
:
708 reg
|= WM8580_CLKSEL_DAC_CLKSEL_PLLB
;
714 wm8580_write(codec
, WM8580_CLKSEL
, reg
);
717 case WM8580_CLKOUTSRC
:
718 reg
= wm8580_read(codec
, WM8580_PLLB4
);
719 reg
&= ~WM8580_PLLB4_CLKOUTSRC_MASK
;
722 case WM8580_CLKSRC_NONE
:
725 case WM8580_CLKSRC_PLLA
:
726 reg
|= WM8580_PLLB4_CLKOUTSRC_PLLACLK
;
729 case WM8580_CLKSRC_PLLB
:
730 reg
|= WM8580_PLLB4_CLKOUTSRC_PLLBCLK
;
733 case WM8580_CLKSRC_OSC
:
734 reg
|= WM8580_PLLB4_CLKOUTSRC_OSCCLK
;
740 wm8580_write(codec
, WM8580_PLLB4
, reg
);
750 static int wm8580_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
752 struct snd_soc_codec
*codec
= codec_dai
->codec
;
755 reg
= wm8580_read(codec
, WM8580_DAC_CONTROL5
);
758 reg
|= WM8580_DAC_CONTROL5_MUTEALL
;
760 reg
&= ~WM8580_DAC_CONTROL5_MUTEALL
;
762 wm8580_write(codec
, WM8580_DAC_CONTROL5
, reg
);
767 static int wm8580_set_bias_level(struct snd_soc_codec
*codec
,
768 enum snd_soc_bias_level level
)
772 case SND_SOC_BIAS_ON
:
773 case SND_SOC_BIAS_PREPARE
:
774 case SND_SOC_BIAS_STANDBY
:
776 case SND_SOC_BIAS_OFF
:
777 reg
= wm8580_read(codec
, WM8580_PWRDN1
);
778 wm8580_write(codec
, WM8580_PWRDN1
, reg
| WM8580_PWRDN1_PWDN
);
781 codec
->bias_level
= level
;
785 #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
786 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
788 struct snd_soc_dai wm8580_dai
[] = {
790 .name
= "WM8580 PAIFRX",
793 .stream_name
= "Playback",
796 .rates
= SNDRV_PCM_RATE_8000_192000
,
797 .formats
= WM8580_FORMATS
,
800 .hw_params
= wm8580_paif_hw_params
,
803 .set_fmt
= wm8580_set_paif_dai_fmt
,
804 .set_clkdiv
= wm8580_set_dai_clkdiv
,
805 .set_pll
= wm8580_set_dai_pll
,
806 .digital_mute
= wm8580_digital_mute
,
810 .name
= "WM8580 PAIFTX",
813 .stream_name
= "Capture",
816 .rates
= SNDRV_PCM_RATE_8000_192000
,
817 .formats
= WM8580_FORMATS
,
820 .hw_params
= wm8580_paif_hw_params
,
823 .set_fmt
= wm8580_set_paif_dai_fmt
,
824 .set_clkdiv
= wm8580_set_dai_clkdiv
,
825 .set_pll
= wm8580_set_dai_pll
,
829 EXPORT_SYMBOL_GPL(wm8580_dai
);
832 * initialise the WM8580 driver
833 * register the mixer and dsp interfaces with the kernel
835 static int wm8580_init(struct snd_soc_device
*socdev
)
837 struct snd_soc_codec
*codec
= socdev
->codec
;
840 codec
->name
= "WM8580";
841 codec
->owner
= THIS_MODULE
;
842 codec
->read
= wm8580_read_reg_cache
;
843 codec
->write
= wm8580_write
;
844 codec
->set_bias_level
= wm8580_set_bias_level
;
845 codec
->dai
= wm8580_dai
;
846 codec
->num_dai
= ARRAY_SIZE(wm8580_dai
);
847 codec
->reg_cache_size
= ARRAY_SIZE(wm8580_reg
);
848 codec
->reg_cache
= kmemdup(wm8580_reg
, sizeof(wm8580_reg
),
851 if (codec
->reg_cache
== NULL
)
854 /* Get the codec into a known state */
855 wm8580_write(codec
, WM8580_RESET
, 0);
857 /* Power up and get individual control of the DACs */
858 wm8580_write(codec
, WM8580_PWRDN1
, wm8580_read(codec
, WM8580_PWRDN1
) &
859 ~(WM8580_PWRDN1_PWDN
| WM8580_PWRDN1_ALLDACPD
));
861 /* Make VMID high impedence */
862 wm8580_write(codec
, WM8580_ADC_CONTROL1
,
863 wm8580_read(codec
, WM8580_ADC_CONTROL1
) & ~0x100);
866 ret
= snd_soc_new_pcms(socdev
, SNDRV_DEFAULT_IDX1
,
869 printk(KERN_ERR
"wm8580: failed to create pcms\n");
873 wm8580_add_controls(codec
);
874 wm8580_add_widgets(codec
);
876 ret
= snd_soc_register_card(socdev
);
878 printk(KERN_ERR
"wm8580: failed to register card\n");
884 snd_soc_free_pcms(socdev
);
885 snd_soc_dapm_free(socdev
);
887 kfree(codec
->reg_cache
);
891 /* If the i2c layer weren't so broken, we could pass this kind of data
893 static struct snd_soc_device
*wm8580_socdev
;
895 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
898 * WM8580 2 wire address is determined by GPIO5
899 * state during powerup.
903 static unsigned short normal_i2c
[] = { 0, I2C_CLIENT_END
};
905 /* Magic definition of all other variables and things */
908 static struct i2c_driver wm8580_i2c_driver
;
909 static struct i2c_client client_template
;
911 static int wm8580_codec_probe(struct i2c_adapter
*adap
, int addr
, int kind
)
913 struct snd_soc_device
*socdev
= wm8580_socdev
;
914 struct wm8580_setup_data
*setup
= socdev
->codec_data
;
915 struct snd_soc_codec
*codec
= socdev
->codec
;
916 struct i2c_client
*i2c
;
919 if (addr
!= setup
->i2c_address
)
922 client_template
.adapter
= adap
;
923 client_template
.addr
= addr
;
925 i2c
= kmemdup(&client_template
, sizeof(client_template
), GFP_KERNEL
);
930 i2c_set_clientdata(i2c
, codec
);
931 codec
->control_data
= i2c
;
933 ret
= i2c_attach_client(i2c
);
935 dev_err(&i2c
->dev
, "failed to attach codec at addr %x\n", addr
);
939 ret
= wm8580_init(socdev
);
941 dev_err(&i2c
->dev
, "failed to initialise WM8580\n");
953 static int wm8580_i2c_detach(struct i2c_client
*client
)
955 struct snd_soc_codec
*codec
= i2c_get_clientdata(client
);
956 i2c_detach_client(client
);
957 kfree(codec
->reg_cache
);
962 static int wm8580_i2c_attach(struct i2c_adapter
*adap
)
964 return i2c_probe(adap
, &addr_data
, wm8580_codec_probe
);
967 /* corgi i2c codec control layer */
968 static struct i2c_driver wm8580_i2c_driver
= {
970 .name
= "WM8580 I2C Codec",
971 .owner
= THIS_MODULE
,
973 .attach_adapter
= wm8580_i2c_attach
,
974 .detach_client
= wm8580_i2c_detach
,
978 static struct i2c_client client_template
= {
980 .driver
= &wm8580_i2c_driver
,
984 static int wm8580_probe(struct platform_device
*pdev
)
986 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
987 struct wm8580_setup_data
*setup
;
988 struct snd_soc_codec
*codec
;
989 struct wm8580_priv
*wm8580
;
992 pr_info("WM8580 Audio Codec %s\n", WM8580_VERSION
);
994 setup
= socdev
->codec_data
;
995 codec
= kzalloc(sizeof(struct snd_soc_codec
), GFP_KERNEL
);
999 wm8580
= kzalloc(sizeof(struct wm8580_priv
), GFP_KERNEL
);
1000 if (wm8580
== NULL
) {
1005 codec
->private_data
= wm8580
;
1006 socdev
->codec
= codec
;
1007 mutex_init(&codec
->mutex
);
1008 INIT_LIST_HEAD(&codec
->dapm_widgets
);
1009 INIT_LIST_HEAD(&codec
->dapm_paths
);
1010 wm8580_socdev
= socdev
;
1012 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1013 if (setup
->i2c_address
) {
1014 normal_i2c
[0] = setup
->i2c_address
;
1015 codec
->hw_write
= (hw_write_t
)i2c_master_send
;
1016 ret
= i2c_add_driver(&wm8580_i2c_driver
);
1018 printk(KERN_ERR
"can't add i2c driver");
1021 /* Add other interfaces here */
1026 /* power down chip */
1027 static int wm8580_remove(struct platform_device
*pdev
)
1029 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1030 struct snd_soc_codec
*codec
= socdev
->codec
;
1032 if (codec
->control_data
)
1033 wm8580_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1034 snd_soc_free_pcms(socdev
);
1035 snd_soc_dapm_free(socdev
);
1036 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1037 i2c_del_driver(&wm8580_i2c_driver
);
1039 kfree(codec
->private_data
);
1045 struct snd_soc_codec_device soc_codec_dev_wm8580
= {
1046 .probe
= wm8580_probe
,
1047 .remove
= wm8580_remove
,
1049 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8580
);
1051 MODULE_DESCRIPTION("ASoC WM8580 driver");
1052 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1053 MODULE_LICENSE("GPL");