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ALSA: ASoC: Remove unused AUDIO_NAME define from codec drivers
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / wm8580.c
1 /*
2 * wm8580.c -- WM8580 ALSA Soc Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics PLC.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Notes:
12 * The WM8580 is a multichannel codec with S/PDIF support, featuring six
13 * DAC channels and two ADC channels.
14 *
15 * Currently only the primary audio interface is supported - S/PDIF and
16 * the secondary audio interfaces are not.
17 */
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/version.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/delay.h>
25 #include <linux/pm.h>
26 #include <linux/i2c.h>
27 #include <linux/platform_device.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/soc.h>
32 #include <sound/soc-dapm.h>
33 #include <sound/tlv.h>
34 #include <sound/initval.h>
35 #include <asm/div64.h>
36
37 #include "wm8580.h"
38
39 #define WM8580_VERSION "0.1"
40
41 struct pll_state {
42 unsigned int in;
43 unsigned int out;
44 };
45
46 /* codec private data */
47 struct wm8580_priv {
48 struct pll_state a;
49 struct pll_state b;
50 };
51
52 /* WM8580 register space */
53 #define WM8580_PLLA1 0x00
54 #define WM8580_PLLA2 0x01
55 #define WM8580_PLLA3 0x02
56 #define WM8580_PLLA4 0x03
57 #define WM8580_PLLB1 0x04
58 #define WM8580_PLLB2 0x05
59 #define WM8580_PLLB3 0x06
60 #define WM8580_PLLB4 0x07
61 #define WM8580_CLKSEL 0x08
62 #define WM8580_PAIF1 0x09
63 #define WM8580_PAIF2 0x0A
64 #define WM8580_SAIF1 0x0B
65 #define WM8580_PAIF3 0x0C
66 #define WM8580_PAIF4 0x0D
67 #define WM8580_SAIF2 0x0E
68 #define WM8580_DAC_CONTROL1 0x0F
69 #define WM8580_DAC_CONTROL2 0x10
70 #define WM8580_DAC_CONTROL3 0x11
71 #define WM8580_DAC_CONTROL4 0x12
72 #define WM8580_DAC_CONTROL5 0x13
73 #define WM8580_DIGITAL_ATTENUATION_DACL1 0x14
74 #define WM8580_DIGITAL_ATTENUATION_DACR1 0x15
75 #define WM8580_DIGITAL_ATTENUATION_DACL2 0x16
76 #define WM8580_DIGITAL_ATTENUATION_DACR2 0x17
77 #define WM8580_DIGITAL_ATTENUATION_DACL3 0x18
78 #define WM8580_DIGITAL_ATTENUATION_DACR3 0x19
79 #define WM8580_MASTER_DIGITAL_ATTENUATION 0x1C
80 #define WM8580_ADC_CONTROL1 0x1D
81 #define WM8580_SPDTXCHAN0 0x1E
82 #define WM8580_SPDTXCHAN1 0x1F
83 #define WM8580_SPDTXCHAN2 0x20
84 #define WM8580_SPDTXCHAN3 0x21
85 #define WM8580_SPDTXCHAN4 0x22
86 #define WM8580_SPDTXCHAN5 0x23
87 #define WM8580_SPDMODE 0x24
88 #define WM8580_INTMASK 0x25
89 #define WM8580_GPO1 0x26
90 #define WM8580_GPO2 0x27
91 #define WM8580_GPO3 0x28
92 #define WM8580_GPO4 0x29
93 #define WM8580_GPO5 0x2A
94 #define WM8580_INTSTAT 0x2B
95 #define WM8580_SPDRXCHAN1 0x2C
96 #define WM8580_SPDRXCHAN2 0x2D
97 #define WM8580_SPDRXCHAN3 0x2E
98 #define WM8580_SPDRXCHAN4 0x2F
99 #define WM8580_SPDRXCHAN5 0x30
100 #define WM8580_SPDSTAT 0x31
101 #define WM8580_PWRDN1 0x32
102 #define WM8580_PWRDN2 0x33
103 #define WM8580_READBACK 0x34
104 #define WM8580_RESET 0x35
105
106 /* PLLB4 (register 7h) */
107 #define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60
108 #define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20
109 #define WM8580_PLLB4_MCLKOUTSRC_PLLB 0x40
110 #define WM8580_PLLB4_MCLKOUTSRC_OSC 0x60
111
112 #define WM8580_PLLB4_CLKOUTSRC_MASK 0x180
113 #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
114 #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
115 #define WM8580_PLLB4_CLKOUTSRC_OSCCLK 0x180
116
117 /* CLKSEL (register 8h) */
118 #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
119 #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
120 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
121
122 /* AIF control 1 (registers 9h-bh) */
123 #define WM8580_AIF_RATE_MASK 0x7
124 #define WM8580_AIF_RATE_128 0x0
125 #define WM8580_AIF_RATE_192 0x1
126 #define WM8580_AIF_RATE_256 0x2
127 #define WM8580_AIF_RATE_384 0x3
128 #define WM8580_AIF_RATE_512 0x4
129 #define WM8580_AIF_RATE_768 0x5
130 #define WM8580_AIF_RATE_1152 0x6
131
132 #define WM8580_AIF_BCLKSEL_MASK 0x18
133 #define WM8580_AIF_BCLKSEL_64 0x00
134 #define WM8580_AIF_BCLKSEL_128 0x08
135 #define WM8580_AIF_BCLKSEL_256 0x10
136 #define WM8580_AIF_BCLKSEL_SYSCLK 0x18
137
138 #define WM8580_AIF_MS 0x20
139
140 #define WM8580_AIF_CLKSRC_MASK 0xc0
141 #define WM8580_AIF_CLKSRC_PLLA 0x40
142 #define WM8580_AIF_CLKSRC_PLLB 0x40
143 #define WM8580_AIF_CLKSRC_MCLK 0xc0
144
145 /* AIF control 2 (registers ch-eh) */
146 #define WM8580_AIF_FMT_MASK 0x03
147 #define WM8580_AIF_FMT_RIGHTJ 0x00
148 #define WM8580_AIF_FMT_LEFTJ 0x01
149 #define WM8580_AIF_FMT_I2S 0x02
150 #define WM8580_AIF_FMT_DSP 0x03
151
152 #define WM8580_AIF_LENGTH_MASK 0x0c
153 #define WM8580_AIF_LENGTH_16 0x00
154 #define WM8580_AIF_LENGTH_20 0x04
155 #define WM8580_AIF_LENGTH_24 0x08
156 #define WM8580_AIF_LENGTH_32 0x0c
157
158 #define WM8580_AIF_LRP 0x10
159 #define WM8580_AIF_BCP 0x20
160
161 /* Powerdown Register 1 (register 32h) */
162 #define WM8580_PWRDN1_PWDN 0x001
163 #define WM8580_PWRDN1_ALLDACPD 0x040
164
165 /* Powerdown Register 2 (register 33h) */
166 #define WM8580_PWRDN2_OSSCPD 0x001
167 #define WM8580_PWRDN2_PLLAPD 0x002
168 #define WM8580_PWRDN2_PLLBPD 0x004
169 #define WM8580_PWRDN2_SPDIFPD 0x008
170 #define WM8580_PWRDN2_SPDIFTXD 0x010
171 #define WM8580_PWRDN2_SPDIFRXD 0x020
172
173 #define WM8580_DAC_CONTROL5_MUTEALL 0x10
174
175 /*
176 * wm8580 register cache
177 * We can't read the WM8580 register space when we
178 * are using 2 wire for device control, so we cache them instead.
179 */
180 static const u16 wm8580_reg[] = {
181 0x0121, 0x017e, 0x007d, 0x0014, /*R3*/
182 0x0121, 0x017e, 0x007d, 0x0194, /*R7*/
183 0x001c, 0x0002, 0x0002, 0x00c2, /*R11*/
184 0x0182, 0x0082, 0x000a, 0x0024, /*R15*/
185 0x0009, 0x0000, 0x00ff, 0x0000, /*R19*/
186 0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R23*/
187 0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R27*/
188 0x01f0, 0x0040, 0x0000, 0x0000, /*R31(0x1F)*/
189 0x0000, 0x0000, 0x0031, 0x000b, /*R35*/
190 0x0039, 0x0000, 0x0010, 0x0032, /*R39*/
191 0x0054, 0x0076, 0x0098, 0x0000, /*R43(0x2B)*/
192 0x0000, 0x0000, 0x0000, 0x0000, /*R47*/
193 0x0000, 0x0000, 0x005e, 0x003e, /*R51(0x33)*/
194 0x0000, 0x0000 /*R53*/
195 };
196
197 /*
198 * read wm8580 register cache
199 */
200 static inline unsigned int wm8580_read_reg_cache(struct snd_soc_codec *codec,
201 unsigned int reg)
202 {
203 u16 *cache = codec->reg_cache;
204 BUG_ON(reg > ARRAY_SIZE(wm8580_reg));
205 return cache[reg];
206 }
207
208 /*
209 * write wm8580 register cache
210 */
211 static inline void wm8580_write_reg_cache(struct snd_soc_codec *codec,
212 unsigned int reg, unsigned int value)
213 {
214 u16 *cache = codec->reg_cache;
215
216 cache[reg] = value;
217 }
218
219 /*
220 * write to the WM8580 register space
221 */
222 static int wm8580_write(struct snd_soc_codec *codec, unsigned int reg,
223 unsigned int value)
224 {
225 u8 data[2];
226
227 BUG_ON(reg > ARRAY_SIZE(wm8580_reg));
228
229 /* Registers are 9 bits wide */
230 value &= 0x1ff;
231
232 switch (reg) {
233 case WM8580_RESET:
234 /* Uncached */
235 break;
236 default:
237 if (value == wm8580_read_reg_cache(codec, reg))
238 return 0;
239 }
240
241 /* data is
242 * D15..D9 WM8580 register offset
243 * D8...D0 register data
244 */
245 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
246 data[1] = value & 0x00ff;
247
248 wm8580_write_reg_cache(codec, reg, value);
249 if (codec->hw_write(codec->control_data, data, 2) == 2)
250 return 0;
251 else
252 return -EIO;
253 }
254
255 static inline unsigned int wm8580_read(struct snd_soc_codec *codec,
256 unsigned int reg)
257 {
258 switch (reg) {
259 default:
260 return wm8580_read_reg_cache(codec, reg);
261 }
262 }
263
264 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
265
266 static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
267 struct snd_ctl_elem_value *ucontrol)
268 {
269 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
270 int reg = kcontrol->private_value & 0xff;
271 int reg2 = (kcontrol->private_value >> 24) & 0xff;
272 int ret;
273 u16 val;
274
275 /* Clear the register cache so we write without VU set */
276 wm8580_write_reg_cache(codec, reg, 0);
277 wm8580_write_reg_cache(codec, reg2, 0);
278
279 ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
280 if (ret < 0)
281 return ret;
282
283 /* Now write again with the volume update bit set */
284 val = wm8580_read_reg_cache(codec, reg);
285 wm8580_write(codec, reg, val | 0x0100);
286
287 val = wm8580_read_reg_cache(codec, reg2);
288 wm8580_write(codec, reg2, val | 0x0100);
289
290 return 0;
291 }
292
293 #define SOC_WM8580_OUT_DOUBLE_R_TLV(xname, reg_left, reg_right, shift, max, invert, tlv_array) \
294 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
295 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
296 SNDRV_CTL_ELEM_ACCESS_READWRITE, \
297 .tlv.p = (tlv_array), \
298 .info = snd_soc_info_volsw_2r, \
299 .get = snd_soc_get_volsw_2r, .put = wm8580_out_vu, \
300 .private_value = (reg_left) | ((shift) << 8) | \
301 ((max) << 12) | ((invert) << 20) | ((reg_right) << 24) }
302
303 static const struct snd_kcontrol_new wm8580_snd_controls[] = {
304 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC1 Playback Volume",
305 WM8580_DIGITAL_ATTENUATION_DACL1,
306 WM8580_DIGITAL_ATTENUATION_DACR1,
307 0, 0xff, 0, dac_tlv),
308 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC2 Playback Volume",
309 WM8580_DIGITAL_ATTENUATION_DACL2,
310 WM8580_DIGITAL_ATTENUATION_DACR2,
311 0, 0xff, 0, dac_tlv),
312 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC3 Playback Volume",
313 WM8580_DIGITAL_ATTENUATION_DACL3,
314 WM8580_DIGITAL_ATTENUATION_DACR3,
315 0, 0xff, 0, dac_tlv),
316
317 SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
318 SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
319 SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
320
321 SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4, 0, 1, 1, 0),
322 SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4, 2, 3, 1, 0),
323 SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4, 4, 5, 1, 0),
324
325 SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
326 SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 0),
327 SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 0),
328 SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 0),
329
330 SOC_DOUBLE("ADC Mute Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 0),
331 SOC_SINGLE("ADC High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
332 };
333
334 /* Add non-DAPM controls */
335 static int wm8580_add_controls(struct snd_soc_codec *codec)
336 {
337 int err, i;
338
339 for (i = 0; i < ARRAY_SIZE(wm8580_snd_controls); i++) {
340 err = snd_ctl_add(codec->card,
341 snd_soc_cnew(&wm8580_snd_controls[i],
342 codec, NULL));
343 if (err < 0)
344 return err;
345 }
346 return 0;
347 }
348 static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
349 SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
350 SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
351 SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
352
353 SND_SOC_DAPM_OUTPUT("VOUT1L"),
354 SND_SOC_DAPM_OUTPUT("VOUT1R"),
355 SND_SOC_DAPM_OUTPUT("VOUT2L"),
356 SND_SOC_DAPM_OUTPUT("VOUT2R"),
357 SND_SOC_DAPM_OUTPUT("VOUT3L"),
358 SND_SOC_DAPM_OUTPUT("VOUT3R"),
359
360 SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
361
362 SND_SOC_DAPM_INPUT("AINL"),
363 SND_SOC_DAPM_INPUT("AINR"),
364 };
365
366 static const struct snd_soc_dapm_route audio_map[] = {
367 { "VOUT1L", NULL, "DAC1" },
368 { "VOUT1R", NULL, "DAC1" },
369
370 { "VOUT2L", NULL, "DAC2" },
371 { "VOUT2R", NULL, "DAC2" },
372
373 { "VOUT3L", NULL, "DAC3" },
374 { "VOUT3R", NULL, "DAC3" },
375
376 { "ADC", NULL, "AINL" },
377 { "ADC", NULL, "AINR" },
378 };
379
380 static int wm8580_add_widgets(struct snd_soc_codec *codec)
381 {
382 snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets,
383 ARRAY_SIZE(wm8580_dapm_widgets));
384
385 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
386
387 snd_soc_dapm_new_widgets(codec);
388 return 0;
389 }
390
391 /* PLL divisors */
392 struct _pll_div {
393 u32 prescale:1;
394 u32 postscale:1;
395 u32 freqmode:2;
396 u32 n:4;
397 u32 k:24;
398 };
399
400 /* The size in bits of the pll divide */
401 #define FIXED_PLL_SIZE (1 << 22)
402
403 /* PLL rate to output rate divisions */
404 static struct {
405 unsigned int div;
406 unsigned int freqmode;
407 unsigned int postscale;
408 } post_table[] = {
409 { 2, 0, 0 },
410 { 4, 0, 1 },
411 { 4, 1, 0 },
412 { 8, 1, 1 },
413 { 8, 2, 0 },
414 { 16, 2, 1 },
415 { 12, 3, 0 },
416 { 24, 3, 1 }
417 };
418
419 static int pll_factors(struct _pll_div *pll_div, unsigned int target,
420 unsigned int source)
421 {
422 u64 Kpart;
423 unsigned int K, Ndiv, Nmod;
424 int i;
425
426 pr_debug("wm8580: PLL %dHz->%dHz\n", source, target);
427
428 /* Scale the output frequency up; the PLL should run in the
429 * region of 90-100MHz.
430 */
431 for (i = 0; i < ARRAY_SIZE(post_table); i++) {
432 if (target * post_table[i].div >= 90000000 &&
433 target * post_table[i].div <= 100000000) {
434 pll_div->freqmode = post_table[i].freqmode;
435 pll_div->postscale = post_table[i].postscale;
436 target *= post_table[i].div;
437 break;
438 }
439 }
440
441 if (i == ARRAY_SIZE(post_table)) {
442 printk(KERN_ERR "wm8580: Unable to scale output frequency "
443 "%u\n", target);
444 return -EINVAL;
445 }
446
447 Ndiv = target / source;
448
449 if (Ndiv < 5) {
450 source /= 2;
451 pll_div->prescale = 1;
452 Ndiv = target / source;
453 } else
454 pll_div->prescale = 0;
455
456 if ((Ndiv < 5) || (Ndiv > 13)) {
457 printk(KERN_ERR
458 "WM8580 N=%d outside supported range\n", Ndiv);
459 return -EINVAL;
460 }
461
462 pll_div->n = Ndiv;
463 Nmod = target % source;
464 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
465
466 do_div(Kpart, source);
467
468 K = Kpart & 0xFFFFFFFF;
469
470 pll_div->k = K;
471
472 pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
473 pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
474 pll_div->postscale);
475
476 return 0;
477 }
478
479 static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai,
480 int pll_id, unsigned int freq_in, unsigned int freq_out)
481 {
482 int offset;
483 struct snd_soc_codec *codec = codec_dai->codec;
484 struct wm8580_priv *wm8580 = codec->private_data;
485 struct pll_state *state;
486 struct _pll_div pll_div;
487 unsigned int reg;
488 unsigned int pwr_mask;
489 int ret;
490
491 /* GCC isn't able to work out the ifs below for initialising/using
492 * pll_div so suppress warnings.
493 */
494 memset(&pll_div, 0, sizeof(pll_div));
495
496 switch (pll_id) {
497 case WM8580_PLLA:
498 state = &wm8580->a;
499 offset = 0;
500 pwr_mask = WM8580_PWRDN2_PLLAPD;
501 break;
502 case WM8580_PLLB:
503 state = &wm8580->b;
504 offset = 4;
505 pwr_mask = WM8580_PWRDN2_PLLBPD;
506 break;
507 default:
508 return -ENODEV;
509 }
510
511 if (freq_in && freq_out) {
512 ret = pll_factors(&pll_div, freq_out, freq_in);
513 if (ret != 0)
514 return ret;
515 }
516
517 state->in = freq_in;
518 state->out = freq_out;
519
520 /* Always disable the PLL - it is not safe to leave it running
521 * while reprogramming it.
522 */
523 reg = wm8580_read(codec, WM8580_PWRDN2);
524 wm8580_write(codec, WM8580_PWRDN2, reg | pwr_mask);
525
526 if (!freq_in || !freq_out)
527 return 0;
528
529 wm8580_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
530 wm8580_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0xff);
531 wm8580_write(codec, WM8580_PLLA3 + offset,
532 (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
533
534 reg = wm8580_read(codec, WM8580_PLLA4 + offset);
535 reg &= ~0x3f;
536 reg |= pll_div.prescale | pll_div.postscale << 1 |
537 pll_div.freqmode << 4;
538
539 wm8580_write(codec, WM8580_PLLA4 + offset, reg);
540
541 /* All done, turn it on */
542 reg = wm8580_read(codec, WM8580_PWRDN2);
543 wm8580_write(codec, WM8580_PWRDN2, reg & ~pwr_mask);
544
545 return 0;
546 }
547
548 /*
549 * Set PCM DAI bit size and sample rate.
550 */
551 static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
552 struct snd_pcm_hw_params *params)
553 {
554 struct snd_soc_pcm_runtime *rtd = substream->private_data;
555 struct snd_soc_dai_link *dai = rtd->dai;
556 struct snd_soc_device *socdev = rtd->socdev;
557 struct snd_soc_codec *codec = socdev->codec;
558 u16 paifb = wm8580_read(codec, WM8580_PAIF3 + dai->codec_dai->id);
559
560 paifb &= ~WM8580_AIF_LENGTH_MASK;
561 /* bit size */
562 switch (params_format(params)) {
563 case SNDRV_PCM_FORMAT_S16_LE:
564 break;
565 case SNDRV_PCM_FORMAT_S20_3LE:
566 paifb |= WM8580_AIF_LENGTH_20;
567 break;
568 case SNDRV_PCM_FORMAT_S24_LE:
569 paifb |= WM8580_AIF_LENGTH_24;
570 break;
571 case SNDRV_PCM_FORMAT_S32_LE:
572 paifb |= WM8580_AIF_LENGTH_24;
573 break;
574 default:
575 return -EINVAL;
576 }
577
578 wm8580_write(codec, WM8580_PAIF3 + dai->codec_dai->id, paifb);
579 return 0;
580 }
581
582 static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
583 unsigned int fmt)
584 {
585 struct snd_soc_codec *codec = codec_dai->codec;
586 unsigned int aifa;
587 unsigned int aifb;
588 int can_invert_lrclk;
589
590 aifa = wm8580_read(codec, WM8580_PAIF1 + codec_dai->id);
591 aifb = wm8580_read(codec, WM8580_PAIF3 + codec_dai->id);
592
593 aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
594
595 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
596 case SND_SOC_DAIFMT_CBS_CFS:
597 aifa &= ~WM8580_AIF_MS;
598 break;
599 case SND_SOC_DAIFMT_CBM_CFM:
600 aifa |= WM8580_AIF_MS;
601 break;
602 default:
603 return -EINVAL;
604 }
605
606 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
607 case SND_SOC_DAIFMT_I2S:
608 can_invert_lrclk = 1;
609 aifb |= WM8580_AIF_FMT_I2S;
610 break;
611 case SND_SOC_DAIFMT_RIGHT_J:
612 can_invert_lrclk = 1;
613 aifb |= WM8580_AIF_FMT_RIGHTJ;
614 break;
615 case SND_SOC_DAIFMT_LEFT_J:
616 can_invert_lrclk = 1;
617 aifb |= WM8580_AIF_FMT_LEFTJ;
618 break;
619 case SND_SOC_DAIFMT_DSP_A:
620 can_invert_lrclk = 0;
621 aifb |= WM8580_AIF_FMT_DSP;
622 break;
623 case SND_SOC_DAIFMT_DSP_B:
624 can_invert_lrclk = 0;
625 aifb |= WM8580_AIF_FMT_DSP;
626 aifb |= WM8580_AIF_LRP;
627 break;
628 default:
629 return -EINVAL;
630 }
631
632 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
633 case SND_SOC_DAIFMT_NB_NF:
634 break;
635
636 case SND_SOC_DAIFMT_IB_IF:
637 if (!can_invert_lrclk)
638 return -EINVAL;
639 aifb |= WM8580_AIF_BCP;
640 aifb |= WM8580_AIF_LRP;
641 break;
642
643 case SND_SOC_DAIFMT_IB_NF:
644 aifb |= WM8580_AIF_BCP;
645 break;
646
647 case SND_SOC_DAIFMT_NB_IF:
648 if (!can_invert_lrclk)
649 return -EINVAL;
650 aifb |= WM8580_AIF_LRP;
651 break;
652
653 default:
654 return -EINVAL;
655 }
656
657 wm8580_write(codec, WM8580_PAIF1 + codec_dai->id, aifa);
658 wm8580_write(codec, WM8580_PAIF3 + codec_dai->id, aifb);
659
660 return 0;
661 }
662
663 static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
664 int div_id, int div)
665 {
666 struct snd_soc_codec *codec = codec_dai->codec;
667 unsigned int reg;
668
669 switch (div_id) {
670 case WM8580_MCLK:
671 reg = wm8580_read(codec, WM8580_PLLB4);
672 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
673
674 switch (div) {
675 case WM8580_CLKSRC_MCLK:
676 /* Input */
677 break;
678
679 case WM8580_CLKSRC_PLLA:
680 reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
681 break;
682 case WM8580_CLKSRC_PLLB:
683 reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
684 break;
685
686 case WM8580_CLKSRC_OSC:
687 reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
688 break;
689
690 default:
691 return -EINVAL;
692 }
693 wm8580_write(codec, WM8580_PLLB4, reg);
694 break;
695
696 case WM8580_DAC_CLKSEL:
697 reg = wm8580_read(codec, WM8580_CLKSEL);
698 reg &= ~WM8580_CLKSEL_DAC_CLKSEL_MASK;
699
700 switch (div) {
701 case WM8580_CLKSRC_MCLK:
702 break;
703
704 case WM8580_CLKSRC_PLLA:
705 reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLA;
706 break;
707
708 case WM8580_CLKSRC_PLLB:
709 reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLB;
710 break;
711
712 default:
713 return -EINVAL;
714 }
715 wm8580_write(codec, WM8580_CLKSEL, reg);
716 break;
717
718 case WM8580_CLKOUTSRC:
719 reg = wm8580_read(codec, WM8580_PLLB4);
720 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
721
722 switch (div) {
723 case WM8580_CLKSRC_NONE:
724 break;
725
726 case WM8580_CLKSRC_PLLA:
727 reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
728 break;
729
730 case WM8580_CLKSRC_PLLB:
731 reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
732 break;
733
734 case WM8580_CLKSRC_OSC:
735 reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
736 break;
737
738 default:
739 return -EINVAL;
740 }
741 wm8580_write(codec, WM8580_PLLB4, reg);
742 break;
743
744 default:
745 return -EINVAL;
746 }
747
748 return 0;
749 }
750
751 static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute)
752 {
753 struct snd_soc_codec *codec = codec_dai->codec;
754 unsigned int reg;
755
756 reg = wm8580_read(codec, WM8580_DAC_CONTROL5);
757
758 if (mute)
759 reg |= WM8580_DAC_CONTROL5_MUTEALL;
760 else
761 reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
762
763 wm8580_write(codec, WM8580_DAC_CONTROL5, reg);
764
765 return 0;
766 }
767
768 static int wm8580_set_bias_level(struct snd_soc_codec *codec,
769 enum snd_soc_bias_level level)
770 {
771 u16 reg;
772 switch (level) {
773 case SND_SOC_BIAS_ON:
774 case SND_SOC_BIAS_PREPARE:
775 case SND_SOC_BIAS_STANDBY:
776 break;
777 case SND_SOC_BIAS_OFF:
778 reg = wm8580_read(codec, WM8580_PWRDN1);
779 wm8580_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN);
780 break;
781 }
782 codec->bias_level = level;
783 return 0;
784 }
785
786 #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
787 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
788
789 struct snd_soc_dai wm8580_dai[] = {
790 {
791 .name = "WM8580 PAIFRX",
792 .id = 0,
793 .playback = {
794 .stream_name = "Playback",
795 .channels_min = 1,
796 .channels_max = 6,
797 .rates = SNDRV_PCM_RATE_8000_192000,
798 .formats = WM8580_FORMATS,
799 },
800 .ops = {
801 .hw_params = wm8580_paif_hw_params,
802 },
803 .dai_ops = {
804 .set_fmt = wm8580_set_paif_dai_fmt,
805 .set_clkdiv = wm8580_set_dai_clkdiv,
806 .set_pll = wm8580_set_dai_pll,
807 .digital_mute = wm8580_digital_mute,
808 },
809 },
810 {
811 .name = "WM8580 PAIFTX",
812 .id = 1,
813 .capture = {
814 .stream_name = "Capture",
815 .channels_min = 2,
816 .channels_max = 2,
817 .rates = SNDRV_PCM_RATE_8000_192000,
818 .formats = WM8580_FORMATS,
819 },
820 .ops = {
821 .hw_params = wm8580_paif_hw_params,
822 },
823 .dai_ops = {
824 .set_fmt = wm8580_set_paif_dai_fmt,
825 .set_clkdiv = wm8580_set_dai_clkdiv,
826 .set_pll = wm8580_set_dai_pll,
827 },
828 },
829 };
830 EXPORT_SYMBOL_GPL(wm8580_dai);
831
832 /*
833 * initialise the WM8580 driver
834 * register the mixer and dsp interfaces with the kernel
835 */
836 static int wm8580_init(struct snd_soc_device *socdev)
837 {
838 struct snd_soc_codec *codec = socdev->codec;
839 int ret = 0;
840
841 codec->name = "WM8580";
842 codec->owner = THIS_MODULE;
843 codec->read = wm8580_read_reg_cache;
844 codec->write = wm8580_write;
845 codec->set_bias_level = wm8580_set_bias_level;
846 codec->dai = wm8580_dai;
847 codec->num_dai = ARRAY_SIZE(wm8580_dai);
848 codec->reg_cache_size = ARRAY_SIZE(wm8580_reg);
849 codec->reg_cache = kmemdup(wm8580_reg, sizeof(wm8580_reg),
850 GFP_KERNEL);
851
852 if (codec->reg_cache == NULL)
853 return -ENOMEM;
854
855 /* Get the codec into a known state */
856 wm8580_write(codec, WM8580_RESET, 0);
857
858 /* Power up and get individual control of the DACs */
859 wm8580_write(codec, WM8580_PWRDN1, wm8580_read(codec, WM8580_PWRDN1) &
860 ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD));
861
862 /* Make VMID high impedence */
863 wm8580_write(codec, WM8580_ADC_CONTROL1,
864 wm8580_read(codec, WM8580_ADC_CONTROL1) & ~0x100);
865
866 /* register pcms */
867 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1,
868 SNDRV_DEFAULT_STR1);
869 if (ret < 0) {
870 printk(KERN_ERR "wm8580: failed to create pcms\n");
871 goto pcm_err;
872 }
873
874 wm8580_add_controls(codec);
875 wm8580_add_widgets(codec);
876
877 ret = snd_soc_register_card(socdev);
878 if (ret < 0) {
879 printk(KERN_ERR "wm8580: failed to register card\n");
880 goto card_err;
881 }
882 return ret;
883
884 card_err:
885 snd_soc_free_pcms(socdev);
886 snd_soc_dapm_free(socdev);
887 pcm_err:
888 kfree(codec->reg_cache);
889 return ret;
890 }
891
892 /* If the i2c layer weren't so broken, we could pass this kind of data
893 around */
894 static struct snd_soc_device *wm8580_socdev;
895
896 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
897
898 /*
899 * WM8580 2 wire address is determined by GPIO5
900 * state during powerup.
901 * low = 0x1a
902 * high = 0x1b
903 */
904 static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END };
905
906 /* Magic definition of all other variables and things */
907 I2C_CLIENT_INSMOD;
908
909 static struct i2c_driver wm8580_i2c_driver;
910 static struct i2c_client client_template;
911
912 static int wm8580_codec_probe(struct i2c_adapter *adap, int addr, int kind)
913 {
914 struct snd_soc_device *socdev = wm8580_socdev;
915 struct wm8580_setup_data *setup = socdev->codec_data;
916 struct snd_soc_codec *codec = socdev->codec;
917 struct i2c_client *i2c;
918 int ret;
919
920 if (addr != setup->i2c_address)
921 return -ENODEV;
922
923 client_template.adapter = adap;
924 client_template.addr = addr;
925
926 i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL);
927 if (i2c == NULL) {
928 kfree(codec);
929 return -ENOMEM;
930 }
931 i2c_set_clientdata(i2c, codec);
932 codec->control_data = i2c;
933
934 ret = i2c_attach_client(i2c);
935 if (ret < 0) {
936 dev_err(&i2c->dev, "failed to attach codec at addr %x\n", addr);
937 goto err;
938 }
939
940 ret = wm8580_init(socdev);
941 if (ret < 0) {
942 dev_err(&i2c->dev, "failed to initialise WM8580\n");
943 goto err;
944 }
945
946 return ret;
947
948 err:
949 kfree(codec);
950 kfree(i2c);
951 return ret;
952 }
953
954 static int wm8580_i2c_detach(struct i2c_client *client)
955 {
956 struct snd_soc_codec *codec = i2c_get_clientdata(client);
957 i2c_detach_client(client);
958 kfree(codec->reg_cache);
959 kfree(client);
960 return 0;
961 }
962
963 static int wm8580_i2c_attach(struct i2c_adapter *adap)
964 {
965 return i2c_probe(adap, &addr_data, wm8580_codec_probe);
966 }
967
968 /* corgi i2c codec control layer */
969 static struct i2c_driver wm8580_i2c_driver = {
970 .driver = {
971 .name = "WM8580 I2C Codec",
972 .owner = THIS_MODULE,
973 },
974 .attach_adapter = wm8580_i2c_attach,
975 .detach_client = wm8580_i2c_detach,
976 .command = NULL,
977 };
978
979 static struct i2c_client client_template = {
980 .name = "WM8580",
981 .driver = &wm8580_i2c_driver,
982 };
983 #endif
984
985 static int wm8580_probe(struct platform_device *pdev)
986 {
987 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
988 struct wm8580_setup_data *setup;
989 struct snd_soc_codec *codec;
990 struct wm8580_priv *wm8580;
991 int ret = 0;
992
993 pr_info("WM8580 Audio Codec %s\n", WM8580_VERSION);
994
995 setup = socdev->codec_data;
996 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
997 if (codec == NULL)
998 return -ENOMEM;
999
1000 wm8580 = kzalloc(sizeof(struct wm8580_priv), GFP_KERNEL);
1001 if (wm8580 == NULL) {
1002 kfree(codec);
1003 return -ENOMEM;
1004 }
1005
1006 codec->private_data = wm8580;
1007 socdev->codec = codec;
1008 mutex_init(&codec->mutex);
1009 INIT_LIST_HEAD(&codec->dapm_widgets);
1010 INIT_LIST_HEAD(&codec->dapm_paths);
1011 wm8580_socdev = socdev;
1012
1013 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1014 if (setup->i2c_address) {
1015 normal_i2c[0] = setup->i2c_address;
1016 codec->hw_write = (hw_write_t)i2c_master_send;
1017 ret = i2c_add_driver(&wm8580_i2c_driver);
1018 if (ret != 0)
1019 printk(KERN_ERR "can't add i2c driver");
1020 }
1021 #else
1022 /* Add other interfaces here */
1023 #endif
1024 return ret;
1025 }
1026
1027 /* power down chip */
1028 static int wm8580_remove(struct platform_device *pdev)
1029 {
1030 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1031 struct snd_soc_codec *codec = socdev->codec;
1032
1033 if (codec->control_data)
1034 wm8580_set_bias_level(codec, SND_SOC_BIAS_OFF);
1035 snd_soc_free_pcms(socdev);
1036 snd_soc_dapm_free(socdev);
1037 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1038 i2c_del_driver(&wm8580_i2c_driver);
1039 #endif
1040 kfree(codec->private_data);
1041 kfree(codec);
1042
1043 return 0;
1044 }
1045
1046 struct snd_soc_codec_device soc_codec_dev_wm8580 = {
1047 .probe = wm8580_probe,
1048 .remove = wm8580_remove,
1049 };
1050 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8580);
1051
1052 MODULE_DESCRIPTION("ASoC WM8580 driver");
1053 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1054 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)