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ASoC: Decouple DAPM from CODECs
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / wm8580.c
1 /*
2 * wm8580.c -- WM8580 ALSA Soc Audio driver
3 *
4 * Copyright 2008, 2009 Wolfson Microelectronics PLC.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Notes:
12 * The WM8580 is a multichannel codec with S/PDIF support, featuring six
13 * DAC channels and two ADC channels.
14 *
15 * Currently only the primary audio interface is supported - S/PDIF and
16 * the secondary audio interfaces are not.
17 */
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/pm.h>
25 #include <linux/i2c.h>
26 #include <linux/platform_device.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/slab.h>
29
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 #include <sound/soc-dapm.h>
35 #include <sound/tlv.h>
36 #include <sound/initval.h>
37 #include <asm/div64.h>
38
39 #include "wm8580.h"
40
41 /* WM8580 register space */
42 #define WM8580_PLLA1 0x00
43 #define WM8580_PLLA2 0x01
44 #define WM8580_PLLA3 0x02
45 #define WM8580_PLLA4 0x03
46 #define WM8580_PLLB1 0x04
47 #define WM8580_PLLB2 0x05
48 #define WM8580_PLLB3 0x06
49 #define WM8580_PLLB4 0x07
50 #define WM8580_CLKSEL 0x08
51 #define WM8580_PAIF1 0x09
52 #define WM8580_PAIF2 0x0A
53 #define WM8580_SAIF1 0x0B
54 #define WM8580_PAIF3 0x0C
55 #define WM8580_PAIF4 0x0D
56 #define WM8580_SAIF2 0x0E
57 #define WM8580_DAC_CONTROL1 0x0F
58 #define WM8580_DAC_CONTROL2 0x10
59 #define WM8580_DAC_CONTROL3 0x11
60 #define WM8580_DAC_CONTROL4 0x12
61 #define WM8580_DAC_CONTROL5 0x13
62 #define WM8580_DIGITAL_ATTENUATION_DACL1 0x14
63 #define WM8580_DIGITAL_ATTENUATION_DACR1 0x15
64 #define WM8580_DIGITAL_ATTENUATION_DACL2 0x16
65 #define WM8580_DIGITAL_ATTENUATION_DACR2 0x17
66 #define WM8580_DIGITAL_ATTENUATION_DACL3 0x18
67 #define WM8580_DIGITAL_ATTENUATION_DACR3 0x19
68 #define WM8580_MASTER_DIGITAL_ATTENUATION 0x1C
69 #define WM8580_ADC_CONTROL1 0x1D
70 #define WM8580_SPDTXCHAN0 0x1E
71 #define WM8580_SPDTXCHAN1 0x1F
72 #define WM8580_SPDTXCHAN2 0x20
73 #define WM8580_SPDTXCHAN3 0x21
74 #define WM8580_SPDTXCHAN4 0x22
75 #define WM8580_SPDTXCHAN5 0x23
76 #define WM8580_SPDMODE 0x24
77 #define WM8580_INTMASK 0x25
78 #define WM8580_GPO1 0x26
79 #define WM8580_GPO2 0x27
80 #define WM8580_GPO3 0x28
81 #define WM8580_GPO4 0x29
82 #define WM8580_GPO5 0x2A
83 #define WM8580_INTSTAT 0x2B
84 #define WM8580_SPDRXCHAN1 0x2C
85 #define WM8580_SPDRXCHAN2 0x2D
86 #define WM8580_SPDRXCHAN3 0x2E
87 #define WM8580_SPDRXCHAN4 0x2F
88 #define WM8580_SPDRXCHAN5 0x30
89 #define WM8580_SPDSTAT 0x31
90 #define WM8580_PWRDN1 0x32
91 #define WM8580_PWRDN2 0x33
92 #define WM8580_READBACK 0x34
93 #define WM8580_RESET 0x35
94
95 #define WM8580_MAX_REGISTER 0x35
96
97 #define WM8580_DACOSR 0x40
98
99 /* PLLB4 (register 7h) */
100 #define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60
101 #define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20
102 #define WM8580_PLLB4_MCLKOUTSRC_PLLB 0x40
103 #define WM8580_PLLB4_MCLKOUTSRC_OSC 0x60
104
105 #define WM8580_PLLB4_CLKOUTSRC_MASK 0x180
106 #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
107 #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
108 #define WM8580_PLLB4_CLKOUTSRC_OSCCLK 0x180
109
110 /* CLKSEL (register 8h) */
111 #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
112 #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
113 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
114
115 /* AIF control 1 (registers 9h-bh) */
116 #define WM8580_AIF_RATE_MASK 0x7
117 #define WM8580_AIF_BCLKSEL_MASK 0x18
118
119 #define WM8580_AIF_MS 0x20
120
121 #define WM8580_AIF_CLKSRC_MASK 0xc0
122 #define WM8580_AIF_CLKSRC_PLLA 0x40
123 #define WM8580_AIF_CLKSRC_PLLB 0x40
124 #define WM8580_AIF_CLKSRC_MCLK 0xc0
125
126 /* AIF control 2 (registers ch-eh) */
127 #define WM8580_AIF_FMT_MASK 0x03
128 #define WM8580_AIF_FMT_RIGHTJ 0x00
129 #define WM8580_AIF_FMT_LEFTJ 0x01
130 #define WM8580_AIF_FMT_I2S 0x02
131 #define WM8580_AIF_FMT_DSP 0x03
132
133 #define WM8580_AIF_LENGTH_MASK 0x0c
134 #define WM8580_AIF_LENGTH_16 0x00
135 #define WM8580_AIF_LENGTH_20 0x04
136 #define WM8580_AIF_LENGTH_24 0x08
137 #define WM8580_AIF_LENGTH_32 0x0c
138
139 #define WM8580_AIF_LRP 0x10
140 #define WM8580_AIF_BCP 0x20
141
142 /* Powerdown Register 1 (register 32h) */
143 #define WM8580_PWRDN1_PWDN 0x001
144 #define WM8580_PWRDN1_ALLDACPD 0x040
145
146 /* Powerdown Register 2 (register 33h) */
147 #define WM8580_PWRDN2_OSSCPD 0x001
148 #define WM8580_PWRDN2_PLLAPD 0x002
149 #define WM8580_PWRDN2_PLLBPD 0x004
150 #define WM8580_PWRDN2_SPDIFPD 0x008
151 #define WM8580_PWRDN2_SPDIFTXD 0x010
152 #define WM8580_PWRDN2_SPDIFRXD 0x020
153
154 #define WM8580_DAC_CONTROL5_MUTEALL 0x10
155
156 /*
157 * wm8580 register cache
158 * We can't read the WM8580 register space when we
159 * are using 2 wire for device control, so we cache them instead.
160 */
161 static const u16 wm8580_reg[] = {
162 0x0121, 0x017e, 0x007d, 0x0014, /*R3*/
163 0x0121, 0x017e, 0x007d, 0x0194, /*R7*/
164 0x001c, 0x0002, 0x0002, 0x00c2, /*R11*/
165 0x0182, 0x0082, 0x000a, 0x0024, /*R15*/
166 0x0009, 0x0000, 0x00ff, 0x0000, /*R19*/
167 0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R23*/
168 0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R27*/
169 0x01f0, 0x0040, 0x0000, 0x0000, /*R31(0x1F)*/
170 0x0000, 0x0000, 0x0031, 0x000b, /*R35*/
171 0x0039, 0x0000, 0x0010, 0x0032, /*R39*/
172 0x0054, 0x0076, 0x0098, 0x0000, /*R43(0x2B)*/
173 0x0000, 0x0000, 0x0000, 0x0000, /*R47*/
174 0x0000, 0x0000, 0x005e, 0x003e, /*R51(0x33)*/
175 0x0000, 0x0000 /*R53*/
176 };
177
178 struct pll_state {
179 unsigned int in;
180 unsigned int out;
181 };
182
183 #define WM8580_NUM_SUPPLIES 3
184 static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
185 "AVDD",
186 "DVDD",
187 "PVDD",
188 };
189
190 /* codec private data */
191 struct wm8580_priv {
192 enum snd_soc_control_type control_type;
193 struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
194 u16 reg_cache[WM8580_MAX_REGISTER + 1];
195 struct pll_state a;
196 struct pll_state b;
197 int sysclk[2];
198 };
199
200 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
201
202 static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
203 struct snd_ctl_elem_value *ucontrol)
204 {
205 struct soc_mixer_control *mc =
206 (struct soc_mixer_control *)kcontrol->private_value;
207 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
208 u16 *reg_cache = codec->reg_cache;
209 unsigned int reg = mc->reg;
210 unsigned int reg2 = mc->rreg;
211 int ret;
212
213 /* Clear the register cache so we write without VU set */
214 reg_cache[reg] = 0;
215 reg_cache[reg2] = 0;
216
217 ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
218 if (ret < 0)
219 return ret;
220
221 /* Now write again with the volume update bit set */
222 snd_soc_update_bits(codec, reg, 0x100, 0x100);
223 snd_soc_update_bits(codec, reg2, 0x100, 0x100);
224
225 return 0;
226 }
227
228 #define SOC_WM8580_OUT_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, \
229 xinvert, tlv_array) \
230 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
231 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
232 SNDRV_CTL_ELEM_ACCESS_READWRITE, \
233 .tlv.p = (tlv_array), \
234 .info = snd_soc_info_volsw_2r, \
235 .get = snd_soc_get_volsw_2r, .put = wm8580_out_vu, \
236 .private_value = (unsigned long)&(struct soc_mixer_control) \
237 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
238 .max = xmax, .invert = xinvert} }
239
240 static const struct snd_kcontrol_new wm8580_snd_controls[] = {
241 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC1 Playback Volume",
242 WM8580_DIGITAL_ATTENUATION_DACL1,
243 WM8580_DIGITAL_ATTENUATION_DACR1,
244 0, 0xff, 0, dac_tlv),
245 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC2 Playback Volume",
246 WM8580_DIGITAL_ATTENUATION_DACL2,
247 WM8580_DIGITAL_ATTENUATION_DACR2,
248 0, 0xff, 0, dac_tlv),
249 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC3 Playback Volume",
250 WM8580_DIGITAL_ATTENUATION_DACL3,
251 WM8580_DIGITAL_ATTENUATION_DACR3,
252 0, 0xff, 0, dac_tlv),
253
254 SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
255 SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
256 SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
257
258 SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4, 0, 1, 1, 0),
259 SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4, 2, 3, 1, 0),
260 SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4, 4, 5, 1, 0),
261
262 SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
263 SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 1),
264 SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 1),
265 SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 1),
266
267 SOC_DOUBLE("Capture Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 1),
268 SOC_SINGLE("Capture High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
269 };
270
271 static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
272 SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
273 SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
274 SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
275
276 SND_SOC_DAPM_OUTPUT("VOUT1L"),
277 SND_SOC_DAPM_OUTPUT("VOUT1R"),
278 SND_SOC_DAPM_OUTPUT("VOUT2L"),
279 SND_SOC_DAPM_OUTPUT("VOUT2R"),
280 SND_SOC_DAPM_OUTPUT("VOUT3L"),
281 SND_SOC_DAPM_OUTPUT("VOUT3R"),
282
283 SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
284
285 SND_SOC_DAPM_INPUT("AINL"),
286 SND_SOC_DAPM_INPUT("AINR"),
287 };
288
289 static const struct snd_soc_dapm_route audio_map[] = {
290 { "VOUT1L", NULL, "DAC1" },
291 { "VOUT1R", NULL, "DAC1" },
292
293 { "VOUT2L", NULL, "DAC2" },
294 { "VOUT2R", NULL, "DAC2" },
295
296 { "VOUT3L", NULL, "DAC3" },
297 { "VOUT3R", NULL, "DAC3" },
298
299 { "ADC", NULL, "AINL" },
300 { "ADC", NULL, "AINR" },
301 };
302
303 static int wm8580_add_widgets(struct snd_soc_codec *codec)
304 {
305 struct snd_soc_dapm_context *dapm = &codec->dapm;
306
307 snd_soc_dapm_new_controls(dapm, wm8580_dapm_widgets,
308 ARRAY_SIZE(wm8580_dapm_widgets));
309 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
310
311 return 0;
312 }
313
314 /* PLL divisors */
315 struct _pll_div {
316 u32 prescale:1;
317 u32 postscale:1;
318 u32 freqmode:2;
319 u32 n:4;
320 u32 k:24;
321 };
322
323 /* The size in bits of the pll divide */
324 #define FIXED_PLL_SIZE (1 << 22)
325
326 /* PLL rate to output rate divisions */
327 static struct {
328 unsigned int div;
329 unsigned int freqmode;
330 unsigned int postscale;
331 } post_table[] = {
332 { 2, 0, 0 },
333 { 4, 0, 1 },
334 { 4, 1, 0 },
335 { 8, 1, 1 },
336 { 8, 2, 0 },
337 { 16, 2, 1 },
338 { 12, 3, 0 },
339 { 24, 3, 1 }
340 };
341
342 static int pll_factors(struct _pll_div *pll_div, unsigned int target,
343 unsigned int source)
344 {
345 u64 Kpart;
346 unsigned int K, Ndiv, Nmod;
347 int i;
348
349 pr_debug("wm8580: PLL %uHz->%uHz\n", source, target);
350
351 /* Scale the output frequency up; the PLL should run in the
352 * region of 90-100MHz.
353 */
354 for (i = 0; i < ARRAY_SIZE(post_table); i++) {
355 if (target * post_table[i].div >= 90000000 &&
356 target * post_table[i].div <= 100000000) {
357 pll_div->freqmode = post_table[i].freqmode;
358 pll_div->postscale = post_table[i].postscale;
359 target *= post_table[i].div;
360 break;
361 }
362 }
363
364 if (i == ARRAY_SIZE(post_table)) {
365 printk(KERN_ERR "wm8580: Unable to scale output frequency "
366 "%u\n", target);
367 return -EINVAL;
368 }
369
370 Ndiv = target / source;
371
372 if (Ndiv < 5) {
373 source /= 2;
374 pll_div->prescale = 1;
375 Ndiv = target / source;
376 } else
377 pll_div->prescale = 0;
378
379 if ((Ndiv < 5) || (Ndiv > 13)) {
380 printk(KERN_ERR
381 "WM8580 N=%u outside supported range\n", Ndiv);
382 return -EINVAL;
383 }
384
385 pll_div->n = Ndiv;
386 Nmod = target % source;
387 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
388
389 do_div(Kpart, source);
390
391 K = Kpart & 0xFFFFFFFF;
392
393 pll_div->k = K;
394
395 pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
396 pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
397 pll_div->postscale);
398
399 return 0;
400 }
401
402 static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
403 int source, unsigned int freq_in, unsigned int freq_out)
404 {
405 int offset;
406 struct snd_soc_codec *codec = codec_dai->codec;
407 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
408 struct pll_state *state;
409 struct _pll_div pll_div;
410 unsigned int reg;
411 unsigned int pwr_mask;
412 int ret;
413
414 /* GCC isn't able to work out the ifs below for initialising/using
415 * pll_div so suppress warnings.
416 */
417 memset(&pll_div, 0, sizeof(pll_div));
418
419 switch (pll_id) {
420 case WM8580_PLLA:
421 state = &wm8580->a;
422 offset = 0;
423 pwr_mask = WM8580_PWRDN2_PLLAPD;
424 break;
425 case WM8580_PLLB:
426 state = &wm8580->b;
427 offset = 4;
428 pwr_mask = WM8580_PWRDN2_PLLBPD;
429 break;
430 default:
431 return -ENODEV;
432 }
433
434 if (freq_in && freq_out) {
435 ret = pll_factors(&pll_div, freq_out, freq_in);
436 if (ret != 0)
437 return ret;
438 }
439
440 state->in = freq_in;
441 state->out = freq_out;
442
443 /* Always disable the PLL - it is not safe to leave it running
444 * while reprogramming it.
445 */
446 reg = snd_soc_read(codec, WM8580_PWRDN2);
447 snd_soc_write(codec, WM8580_PWRDN2, reg | pwr_mask);
448
449 if (!freq_in || !freq_out)
450 return 0;
451
452 snd_soc_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
453 snd_soc_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff);
454 snd_soc_write(codec, WM8580_PLLA3 + offset,
455 (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
456
457 reg = snd_soc_read(codec, WM8580_PLLA4 + offset);
458 reg &= ~0x1b;
459 reg |= pll_div.prescale | pll_div.postscale << 1 |
460 pll_div.freqmode << 3;
461
462 snd_soc_write(codec, WM8580_PLLA4 + offset, reg);
463
464 /* All done, turn it on */
465 reg = snd_soc_read(codec, WM8580_PWRDN2);
466 snd_soc_write(codec, WM8580_PWRDN2, reg & ~pwr_mask);
467
468 return 0;
469 }
470
471 static const int wm8580_sysclk_ratios[] = {
472 128, 192, 256, 384, 512, 768, 1152,
473 };
474
475 /*
476 * Set PCM DAI bit size and sample rate.
477 */
478 static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
479 struct snd_pcm_hw_params *params,
480 struct snd_soc_dai *dai)
481 {
482 struct snd_soc_pcm_runtime *rtd = substream->private_data;
483 struct snd_soc_codec *codec = rtd->codec;
484 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
485 u16 paifa = 0;
486 u16 paifb = 0;
487 int i, ratio, osr;
488
489 /* bit size */
490 switch (params_format(params)) {
491 case SNDRV_PCM_FORMAT_S16_LE:
492 paifa |= 0x8;
493 break;
494 case SNDRV_PCM_FORMAT_S20_3LE:
495 paifa |= 0x10;
496 paifb |= WM8580_AIF_LENGTH_20;
497 break;
498 case SNDRV_PCM_FORMAT_S24_LE:
499 paifa |= 0x10;
500 paifb |= WM8580_AIF_LENGTH_24;
501 break;
502 case SNDRV_PCM_FORMAT_S32_LE:
503 paifa |= 0x10;
504 paifb |= WM8580_AIF_LENGTH_24;
505 break;
506 default:
507 return -EINVAL;
508 }
509
510 /* Look up the SYSCLK ratio; accept only exact matches */
511 ratio = wm8580->sysclk[dai->id] / params_rate(params);
512 for (i = 0; i < ARRAY_SIZE(wm8580_sysclk_ratios); i++)
513 if (ratio == wm8580_sysclk_ratios[i])
514 break;
515 if (i == ARRAY_SIZE(wm8580_sysclk_ratios)) {
516 dev_err(codec->dev, "Invalid clock ratio %d/%d\n",
517 wm8580->sysclk[dai->id], params_rate(params));
518 return -EINVAL;
519 }
520 paifa |= i;
521 dev_dbg(codec->dev, "Running at %dfs with %dHz clock\n",
522 wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]);
523
524 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
525 switch (ratio) {
526 case 128:
527 case 192:
528 osr = WM8580_DACOSR;
529 dev_dbg(codec->dev, "Selecting 64x OSR\n");
530 break;
531 default:
532 osr = 0;
533 dev_dbg(codec->dev, "Selecting 128x OSR\n");
534 break;
535 }
536
537 snd_soc_update_bits(codec, WM8580_PAIF3, WM8580_DACOSR, osr);
538 }
539
540 snd_soc_update_bits(codec, WM8580_PAIF1 + dai->driver->id,
541 WM8580_AIF_RATE_MASK | WM8580_AIF_BCLKSEL_MASK,
542 paifa);
543 snd_soc_update_bits(codec, WM8580_PAIF3 + dai->driver->id,
544 WM8580_AIF_LENGTH_MASK, paifb);
545 return 0;
546 }
547
548 static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
549 unsigned int fmt)
550 {
551 struct snd_soc_codec *codec = codec_dai->codec;
552 unsigned int aifa;
553 unsigned int aifb;
554 int can_invert_lrclk;
555
556 aifa = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->driver->id);
557 aifb = snd_soc_read(codec, WM8580_PAIF3 + codec_dai->driver->id);
558
559 aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
560
561 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
562 case SND_SOC_DAIFMT_CBS_CFS:
563 aifa &= ~WM8580_AIF_MS;
564 break;
565 case SND_SOC_DAIFMT_CBM_CFM:
566 aifa |= WM8580_AIF_MS;
567 break;
568 default:
569 return -EINVAL;
570 }
571
572 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
573 case SND_SOC_DAIFMT_I2S:
574 can_invert_lrclk = 1;
575 aifb |= WM8580_AIF_FMT_I2S;
576 break;
577 case SND_SOC_DAIFMT_RIGHT_J:
578 can_invert_lrclk = 1;
579 aifb |= WM8580_AIF_FMT_RIGHTJ;
580 break;
581 case SND_SOC_DAIFMT_LEFT_J:
582 can_invert_lrclk = 1;
583 aifb |= WM8580_AIF_FMT_LEFTJ;
584 break;
585 case SND_SOC_DAIFMT_DSP_A:
586 can_invert_lrclk = 0;
587 aifb |= WM8580_AIF_FMT_DSP;
588 break;
589 case SND_SOC_DAIFMT_DSP_B:
590 can_invert_lrclk = 0;
591 aifb |= WM8580_AIF_FMT_DSP;
592 aifb |= WM8580_AIF_LRP;
593 break;
594 default:
595 return -EINVAL;
596 }
597
598 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
599 case SND_SOC_DAIFMT_NB_NF:
600 break;
601
602 case SND_SOC_DAIFMT_IB_IF:
603 if (!can_invert_lrclk)
604 return -EINVAL;
605 aifb |= WM8580_AIF_BCP;
606 aifb |= WM8580_AIF_LRP;
607 break;
608
609 case SND_SOC_DAIFMT_IB_NF:
610 aifb |= WM8580_AIF_BCP;
611 break;
612
613 case SND_SOC_DAIFMT_NB_IF:
614 if (!can_invert_lrclk)
615 return -EINVAL;
616 aifb |= WM8580_AIF_LRP;
617 break;
618
619 default:
620 return -EINVAL;
621 }
622
623 snd_soc_write(codec, WM8580_PAIF1 + codec_dai->driver->id, aifa);
624 snd_soc_write(codec, WM8580_PAIF3 + codec_dai->driver->id, aifb);
625
626 return 0;
627 }
628
629 static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
630 int div_id, int div)
631 {
632 struct snd_soc_codec *codec = codec_dai->codec;
633 unsigned int reg;
634
635 switch (div_id) {
636 case WM8580_MCLK:
637 reg = snd_soc_read(codec, WM8580_PLLB4);
638 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
639
640 switch (div) {
641 case WM8580_CLKSRC_MCLK:
642 /* Input */
643 break;
644
645 case WM8580_CLKSRC_PLLA:
646 reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
647 break;
648 case WM8580_CLKSRC_PLLB:
649 reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
650 break;
651
652 case WM8580_CLKSRC_OSC:
653 reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
654 break;
655
656 default:
657 return -EINVAL;
658 }
659 snd_soc_write(codec, WM8580_PLLB4, reg);
660 break;
661
662 case WM8580_CLKOUTSRC:
663 reg = snd_soc_read(codec, WM8580_PLLB4);
664 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
665
666 switch (div) {
667 case WM8580_CLKSRC_NONE:
668 break;
669
670 case WM8580_CLKSRC_PLLA:
671 reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
672 break;
673
674 case WM8580_CLKSRC_PLLB:
675 reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
676 break;
677
678 case WM8580_CLKSRC_OSC:
679 reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
680 break;
681
682 default:
683 return -EINVAL;
684 }
685 snd_soc_write(codec, WM8580_PLLB4, reg);
686 break;
687
688 default:
689 return -EINVAL;
690 }
691
692 return 0;
693 }
694
695 static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id,
696 unsigned int freq, int dir)
697 {
698 struct snd_soc_codec *codec = dai->codec;
699 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
700 int sel, sel_mask, sel_shift;
701
702 switch (dai->driver->id) {
703 case WM8580_DAI_PAIFRX:
704 sel_mask = 0x3;
705 sel_shift = 0;
706 break;
707
708 case WM8580_DAI_PAIFTX:
709 sel_mask = 0xc;
710 sel_shift = 2;
711 break;
712
713 default:
714 BUG_ON("Unknown DAI driver ID\n");
715 return -EINVAL;
716 }
717
718 switch (clk_id) {
719 case WM8580_CLKSRC_ADCMCLK:
720 if (dai->id != WM8580_DAI_PAIFTX)
721 return -EINVAL;
722 sel = 0 << sel_shift;
723 break;
724 case WM8580_CLKSRC_PLLA:
725 sel = 1 << sel_shift;
726 break;
727 case WM8580_CLKSRC_PLLB:
728 sel = 2 << sel_shift;
729 break;
730 case WM8580_CLKSRC_MCLK:
731 sel = 3 << sel_shift;
732 break;
733 default:
734 dev_err(codec->dev, "Unknown clock %d\n", clk_id);
735 return -EINVAL;
736 }
737
738 /* We really should validate PLL settings but not yet */
739 wm8580->sysclk[dai->id] = freq;
740
741 return snd_soc_update_bits(codec, WM8580_CLKSEL, sel_mask, sel);
742 }
743
744 static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute)
745 {
746 struct snd_soc_codec *codec = codec_dai->codec;
747 unsigned int reg;
748
749 reg = snd_soc_read(codec, WM8580_DAC_CONTROL5);
750
751 if (mute)
752 reg |= WM8580_DAC_CONTROL5_MUTEALL;
753 else
754 reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
755
756 snd_soc_write(codec, WM8580_DAC_CONTROL5, reg);
757
758 return 0;
759 }
760
761 static int wm8580_set_bias_level(struct snd_soc_codec *codec,
762 enum snd_soc_bias_level level)
763 {
764 u16 reg;
765 switch (level) {
766 case SND_SOC_BIAS_ON:
767 case SND_SOC_BIAS_PREPARE:
768 break;
769
770 case SND_SOC_BIAS_STANDBY:
771 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
772 /* Power up and get individual control of the DACs */
773 reg = snd_soc_read(codec, WM8580_PWRDN1);
774 reg &= ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD);
775 snd_soc_write(codec, WM8580_PWRDN1, reg);
776
777 /* Make VMID high impedence */
778 reg = snd_soc_read(codec, WM8580_ADC_CONTROL1);
779 reg &= ~0x100;
780 snd_soc_write(codec, WM8580_ADC_CONTROL1, reg);
781 }
782 break;
783
784 case SND_SOC_BIAS_OFF:
785 reg = snd_soc_read(codec, WM8580_PWRDN1);
786 snd_soc_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN);
787 break;
788 }
789 codec->dapm.bias_level = level;
790 return 0;
791 }
792
793 #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
794 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
795
796 static struct snd_soc_dai_ops wm8580_dai_ops_playback = {
797 .set_sysclk = wm8580_set_sysclk,
798 .hw_params = wm8580_paif_hw_params,
799 .set_fmt = wm8580_set_paif_dai_fmt,
800 .set_clkdiv = wm8580_set_dai_clkdiv,
801 .set_pll = wm8580_set_dai_pll,
802 .digital_mute = wm8580_digital_mute,
803 };
804
805 static struct snd_soc_dai_ops wm8580_dai_ops_capture = {
806 .set_sysclk = wm8580_set_sysclk,
807 .hw_params = wm8580_paif_hw_params,
808 .set_fmt = wm8580_set_paif_dai_fmt,
809 .set_clkdiv = wm8580_set_dai_clkdiv,
810 .set_pll = wm8580_set_dai_pll,
811 };
812
813 static struct snd_soc_dai_driver wm8580_dai[] = {
814 {
815 .name = "wm8580-hifi-playback",
816 .id = WM8580_DAI_PAIFRX,
817 .playback = {
818 .stream_name = "Playback",
819 .channels_min = 1,
820 .channels_max = 6,
821 .rates = SNDRV_PCM_RATE_8000_192000,
822 .formats = WM8580_FORMATS,
823 },
824 .ops = &wm8580_dai_ops_playback,
825 },
826 {
827 .name = "wm8580-hifi-capture",
828 .id = WM8580_DAI_PAIFTX,
829 .capture = {
830 .stream_name = "Capture",
831 .channels_min = 2,
832 .channels_max = 2,
833 .rates = SNDRV_PCM_RATE_8000_192000,
834 .formats = WM8580_FORMATS,
835 },
836 .ops = &wm8580_dai_ops_capture,
837 },
838 };
839
840 static int wm8580_probe(struct snd_soc_codec *codec)
841 {
842 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
843 int ret = 0,i;
844
845 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8580->control_type);
846 if (ret < 0) {
847 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
848 return ret;
849 }
850
851 for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++)
852 wm8580->supplies[i].supply = wm8580_supply_names[i];
853
854 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8580->supplies),
855 wm8580->supplies);
856 if (ret != 0) {
857 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
858 return ret;
859 }
860
861 ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies),
862 wm8580->supplies);
863 if (ret != 0) {
864 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
865 goto err_regulator_get;
866 }
867
868 /* Get the codec into a known state */
869 ret = snd_soc_write(codec, WM8580_RESET, 0);
870 if (ret != 0) {
871 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
872 goto err_regulator_enable;
873 }
874
875 wm8580_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
876
877 snd_soc_add_controls(codec, wm8580_snd_controls,
878 ARRAY_SIZE(wm8580_snd_controls));
879 wm8580_add_widgets(codec);
880
881 return 0;
882
883 err_regulator_enable:
884 regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
885 err_regulator_get:
886 regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
887 return ret;
888 }
889
890 /* power down chip */
891 static int wm8580_remove(struct snd_soc_codec *codec)
892 {
893 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
894
895 wm8580_set_bias_level(codec, SND_SOC_BIAS_OFF);
896
897 regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
898 regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
899
900 return 0;
901 }
902
903 static struct snd_soc_codec_driver soc_codec_dev_wm8580 = {
904 .probe = wm8580_probe,
905 .remove = wm8580_remove,
906 .set_bias_level = wm8580_set_bias_level,
907 .reg_cache_size = ARRAY_SIZE(wm8580_reg),
908 .reg_word_size = sizeof(u16),
909 .reg_cache_default = &wm8580_reg,
910 };
911
912 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
913 static int wm8580_i2c_probe(struct i2c_client *i2c,
914 const struct i2c_device_id *id)
915 {
916 struct wm8580_priv *wm8580;
917 int ret;
918
919 wm8580 = kzalloc(sizeof(struct wm8580_priv), GFP_KERNEL);
920 if (wm8580 == NULL)
921 return -ENOMEM;
922
923 i2c_set_clientdata(i2c, wm8580);
924 wm8580->control_type = SND_SOC_I2C;
925
926 ret = snd_soc_register_codec(&i2c->dev,
927 &soc_codec_dev_wm8580, wm8580_dai, ARRAY_SIZE(wm8580_dai));
928 if (ret < 0)
929 kfree(wm8580);
930 return ret;
931 }
932
933 static int wm8580_i2c_remove(struct i2c_client *client)
934 {
935 snd_soc_unregister_codec(&client->dev);
936 kfree(i2c_get_clientdata(client));
937 return 0;
938 }
939
940 static const struct i2c_device_id wm8580_i2c_id[] = {
941 { "wm8580", 0 },
942 { }
943 };
944 MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
945
946 static struct i2c_driver wm8580_i2c_driver = {
947 .driver = {
948 .name = "wm8580-codec",
949 .owner = THIS_MODULE,
950 },
951 .probe = wm8580_i2c_probe,
952 .remove = wm8580_i2c_remove,
953 .id_table = wm8580_i2c_id,
954 };
955 #endif
956
957 static int __init wm8580_modinit(void)
958 {
959 int ret = 0;
960
961 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
962 ret = i2c_add_driver(&wm8580_i2c_driver);
963 if (ret != 0) {
964 pr_err("Failed to register WM8580 I2C driver: %d\n", ret);
965 }
966 #endif
967
968 return ret;
969 }
970 module_init(wm8580_modinit);
971
972 static void __exit wm8580_exit(void)
973 {
974 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
975 i2c_del_driver(&wm8580_i2c_driver);
976 #endif
977 }
978 module_exit(wm8580_exit);
979
980 MODULE_DESCRIPTION("ASoC WM8580 driver");
981 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
982 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)