sound/soc/codecs/uda1380.c

   1 /*
   2  * uda1380.c - Philips UDA1380 ALSA SoC audio driver
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * Copyright (c) 2007-2009 Philipp Zabel <philipp.zabel@gmail.com>
   9  *
  10  * Modified by Richard Purdie <richard@openedhand.com> to fit into SoC
  11  * codec model.
  12  *
  13  * Copyright (c) 2005 Giorgio Padrin <giorgio@mandarinlogiq.org>
  14  * Copyright 2005 Openedhand Ltd.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/types.h>
  20 #include <linux/slab.h>
  21 #include <linux/errno.h>
  22 #include <linux/gpio.h>
  23 #include <linux/delay.h>
  24 #include <linux/i2c.h>
  25 #include <linux/workqueue.h>
  26 #include <sound/core.h>
  27 #include <sound/control.h>
  28 #include <sound/initval.h>
  29 #include <sound/soc.h>
  30 #include <sound/soc-dapm.h>
  31 #include <sound/tlv.h>
  32 #include <sound/uda1380.h>
  33
  34 #include "uda1380.h"
  35
  36 /* codec private data */
  37 struct uda1380_priv {
  38         struct snd_soc_codec *codec;
  39         u16 reg_cache[UDA1380_CACHEREGNUM];
  40         unsigned int dac_clk;
  41         struct work_struct work;
  42         void *control_data;
  43 };
  44
  45 /*
  46  * uda1380 register cache
  47  */
  48 static const u16 uda1380_reg[UDA1380_CACHEREGNUM] = {
  49         0x0502, 0x0000, 0x0000, 0x3f3f,
  50         0x0202, 0x0000, 0x0000, 0x0000,
  51         0x0000, 0x0000, 0x0000, 0x0000,
  52         0x0000, 0x0000, 0x0000, 0x0000,
  53         0x0000, 0xff00, 0x0000, 0x4800,
  54         0x0000, 0x0000, 0x0000, 0x0000,
  55         0x0000, 0x0000, 0x0000, 0x0000,
  56         0x0000, 0x0000, 0x0000, 0x0000,
  57         0x0000, 0x8000, 0x0002, 0x0000,
  58 };
  59
  60 static unsigned long uda1380_cache_dirty;
  61
  62 /*
  63  * read uda1380 register cache
  64  */
  65 static inline unsigned int uda1380_read_reg_cache(struct snd_soc_codec *codec,
  66         unsigned int reg)
  67 {
  68         u16 *cache = codec->reg_cache;
  69         if (reg == UDA1380_RESET)
  70                 return 0;
  71         if (reg >= UDA1380_CACHEREGNUM)
  72                 return -1;
  73         return cache[reg];
  74 }
  75
  76 /*
  77  * write uda1380 register cache
  78  */
  79 static inline void uda1380_write_reg_cache(struct snd_soc_codec *codec,
  80         u16 reg, unsigned int value)
  81 {
  82         u16 *cache = codec->reg_cache;
  83
  84         if (reg >= UDA1380_CACHEREGNUM)
  85                 return;
  86         if ((reg >= 0x10) && (cache[reg] != value))
  87                 set_bit(reg - 0x10, &uda1380_cache_dirty);
  88         cache[reg] = value;
  89 }
  90
  91 /*
  92  * write to the UDA1380 register space
  93  */
  94 static int uda1380_write(struct snd_soc_codec *codec, unsigned int reg,
  95         unsigned int value)
  96 {
  97         u8 data[3];
  98
  99         /* data is
 100          *   data[0] is register offset
 101          *   data[1] is MS byte
 102          *   data[2] is LS byte
 103          */
 104         data[0] = reg;
 105         data[1] = (value & 0xff00) >> 8;
 106         data[2] = value & 0x00ff;
 107
 108         uda1380_write_reg_cache(codec, reg, value);
 109
 110         /* the interpolator & decimator regs must only be written when the
 111          * codec DAI is active.
 112          */
 113         if (!codec->active && (reg >= UDA1380_MVOL))
 114                 return 0;
 115         pr_debug("uda1380: hw write %x val %x\n", reg, value);
 116         if (codec->hw_write(codec->control_data, data, 3) == 3) {
 117                 unsigned int val;
 118                 i2c_master_send(codec->control_data, data, 1);
 119                 i2c_master_recv(codec->control_data, data, 2);
 120                 val = (data[0]<<8) | data[1];
 121                 if (val != value) {
 122                         pr_debug("uda1380: READ BACK VAL %x\n",
 123                                         (data[0]<<8) | data[1]);
 124                         return -EIO;
 125                 }
 126                 if (reg >= 0x10)
 127                         clear_bit(reg - 0x10, &uda1380_cache_dirty);
 128                 return 0;
 129         } else
 130                 return -EIO;
 131 }
 132
 133 static void uda1380_sync_cache(struct snd_soc_codec *codec)
 134 {
 135         int reg;
 136         u8 data[3];
 137         u16 *cache = codec->reg_cache;
 138
 139         /* Sync reg_cache with the hardware */
 140         for (reg = 0; reg < UDA1380_MVOL; reg++) {
 141                 data[0] = reg;
 142                 data[1] = (cache[reg] & 0xff00) >> 8;
 143                 data[2] = cache[reg] & 0x00ff;
 144                 if (codec->hw_write(codec->control_data, data, 3) != 3)
 145                         dev_err(codec->dev, "%s: write to reg 0x%x failed\n",
 146                                 __func__, reg);
 147         }
 148 }
 149
 150 static int uda1380_reset(struct snd_soc_codec *codec)
 151 {
 152         struct uda1380_platform_data *pdata = codec->dev->platform_data;
 153
 154         if (gpio_is_valid(pdata->gpio_reset)) {
 155                 gpio_set_value(pdata->gpio_reset, 1);
 156                 mdelay(1);
 157                 gpio_set_value(pdata->gpio_reset, 0);
 158         } else {
 159                 u8 data[3];
 160
 161                 data[0] = UDA1380_RESET;
 162                 data[1] = 0;
 163                 data[2] = 0;
 164
 165                 if (codec->hw_write(codec->control_data, data, 3) != 3) {
 166                         dev_err(codec->dev, "%s: failed\n", __func__);
 167                         return -EIO;
 168                 }
 169         }
 170
 171         return 0;
 172 }
 173
 174 static void uda1380_flush_work(struct work_struct *work)
 175 {
 176         struct uda1380_priv *uda1380 = container_of(work, struct uda1380_priv, work);
 177         struct snd_soc_codec *uda1380_codec = uda1380->codec;
 178         int bit, reg;
 179
 180         for_each_set_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) {
 181                 reg = 0x10 + bit;
 182                 pr_debug("uda1380: flush reg %x val %x:\n", reg,
 183                                 uda1380_read_reg_cache(uda1380_codec, reg));
 184                 uda1380_write(uda1380_codec, reg,
 185                                 uda1380_read_reg_cache(uda1380_codec, reg));
 186                 clear_bit(bit, &uda1380_cache_dirty);
 187         }
 188
 189 }
 190
 191 /* declarations of ALSA reg_elem_REAL controls */
 192 static const char *uda1380_deemp[] = {
 193         "None",
 194         "32kHz",
 195         "44.1kHz",
 196         "48kHz",
 197         "96kHz",
 198 };
 199 static const char *uda1380_input_sel[] = {
 200         "Line",
 201         "Mic + Line R",
 202         "Line L",
 203         "Mic",
 204 };
 205 static const char *uda1380_output_sel[] = {
 206         "DAC",
 207         "Analog Mixer",
 208 };
 209 static const char *uda1380_spf_mode[] = {
 210         "Flat",
 211         "Minimum1",
 212         "Minimum2",
 213         "Maximum"
 214 };
 215 static const char *uda1380_capture_sel[] = {
 216         "ADC",
 217         "Digital Mixer"
 218 };
 219 static const char *uda1380_sel_ns[] = {
 220         "3rd-order",
 221         "5th-order"
 222 };
 223 static const char *uda1380_mix_control[] = {
 224         "off",
 225         "PCM only",
 226         "before sound processing",
 227         "after sound processing"
 228 };
 229 static const char *uda1380_sdet_setting[] = {
 230         "3200",
 231         "4800",
 232         "9600",
 233         "19200"
 234 };
 235 static const char *uda1380_os_setting[] = {
 236         "single-speed",
 237         "double-speed (no mixing)",
 238         "quad-speed (no mixing)"
 239 };
 240
 241 static const struct soc_enum uda1380_deemp_enum[] = {
 242         SOC_ENUM_SINGLE(UDA1380_DEEMP, 8, 5, uda1380_deemp),
 243         SOC_ENUM_SINGLE(UDA1380_DEEMP, 0, 5, uda1380_deemp),
 244 };
 245 static const struct soc_enum uda1380_input_sel_enum =
 246         SOC_ENUM_SINGLE(UDA1380_ADC, 2, 4, uda1380_input_sel);          /* SEL_MIC, SEL_LNA */
 247 static const struct soc_enum uda1380_output_sel_enum =
 248         SOC_ENUM_SINGLE(UDA1380_PM, 7, 2, uda1380_output_sel);          /* R02_EN_AVC */
 249 static const struct soc_enum uda1380_spf_enum =
 250         SOC_ENUM_SINGLE(UDA1380_MODE, 14, 4, uda1380_spf_mode);         /* M */
 251 static const struct soc_enum uda1380_capture_sel_enum =
 252         SOC_ENUM_SINGLE(UDA1380_IFACE, 6, 2, uda1380_capture_sel);      /* SEL_SOURCE */
 253 static const struct soc_enum uda1380_sel_ns_enum =
 254         SOC_ENUM_SINGLE(UDA1380_MIXER, 14, 2, uda1380_sel_ns);          /* SEL_NS */
 255 static const struct soc_enum uda1380_mix_enum =
 256         SOC_ENUM_SINGLE(UDA1380_MIXER, 12, 4, uda1380_mix_control);     /* MIX, MIX_POS */
 257 static const struct soc_enum uda1380_sdet_enum =
 258         SOC_ENUM_SINGLE(UDA1380_MIXER, 4, 4, uda1380_sdet_setting);     /* SD_VALUE */
 259 static const struct soc_enum uda1380_os_enum =
 260         SOC_ENUM_SINGLE(UDA1380_MIXER, 0, 3, uda1380_os_setting);       /* OS */
 261
 262 /*
 263  * from -48 dB in 1.5 dB steps (mute instead of -49.5 dB)
 264  */
 265 static DECLARE_TLV_DB_SCALE(amix_tlv, -4950, 150, 1);
 266
 267 /*
 268  * from -78 dB in 1 dB steps (3 dB steps, really. LSB are ignored),
 269  * from -66 dB in 0.5 dB steps (2 dB steps, really) and
 270  * from -52 dB in 0.25 dB steps
 271  */
 272 static const unsigned int mvol_tlv[] = {
 273         TLV_DB_RANGE_HEAD(3),
 274         0, 15, TLV_DB_SCALE_ITEM(-8200, 100, 1),
 275         16, 43, TLV_DB_SCALE_ITEM(-6600, 50, 0),
 276         44, 252, TLV_DB_SCALE_ITEM(-5200, 25, 0),
 277 };
 278
 279 /*
 280  * from -72 dB in 1.5 dB steps (6 dB steps really),
 281  * from -66 dB in 0.75 dB steps (3 dB steps really),
 282  * from -60 dB in 0.5 dB steps (2 dB steps really) and
 283  * from -46 dB in 0.25 dB steps
 284  */
 285 static const unsigned int vc_tlv[] = {
 286         TLV_DB_RANGE_HEAD(4),
 287         0, 7, TLV_DB_SCALE_ITEM(-7800, 150, 1),
 288         8, 15, TLV_DB_SCALE_ITEM(-6600, 75, 0),
 289         16, 43, TLV_DB_SCALE_ITEM(-6000, 50, 0),
 290         44, 228, TLV_DB_SCALE_ITEM(-4600, 25, 0),
 291 };
 292
 293 /* from 0 to 6 dB in 2 dB steps if SPF mode != flat */
 294 static DECLARE_TLV_DB_SCALE(tr_tlv, 0, 200, 0);
 295
 296 /* from 0 to 24 dB in 2 dB steps, if SPF mode == maximum, otherwise cuts
 297  * off at 18 dB max) */
 298 static DECLARE_TLV_DB_SCALE(bb_tlv, 0, 200, 0);
 299
 300 /* from -63 to 24 dB in 0.5 dB steps (-128...48) */
 301 static DECLARE_TLV_DB_SCALE(dec_tlv, -6400, 50, 1);
 302
 303 /* from 0 to 24 dB in 3 dB steps */
 304 static DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);
 305
 306 /* from 0 to 30 dB in 2 dB steps */
 307 static DECLARE_TLV_DB_SCALE(vga_tlv, 0, 200, 0);
 308
 309 static const struct snd_kcontrol_new uda1380_snd_controls[] = {
 310         SOC_DOUBLE_TLV("Analog Mixer Volume", UDA1380_AMIX, 0, 8, 44, 1, amix_tlv),     /* AVCR, AVCL */
 311         SOC_DOUBLE_TLV("Master Playback Volume", UDA1380_MVOL, 0, 8, 252, 1, mvol_tlv), /* MVCL, MVCR */
 312         SOC_SINGLE_TLV("ADC Playback Volume", UDA1380_MIXVOL, 8, 228, 1, vc_tlv),       /* VC2 */
 313         SOC_SINGLE_TLV("PCM Playback Volume", UDA1380_MIXVOL, 0, 228, 1, vc_tlv),       /* VC1 */
 314         SOC_ENUM("Sound Processing Filter", uda1380_spf_enum),                          /* M */
 315         SOC_DOUBLE_TLV("Tone Control - Treble", UDA1380_MODE, 4, 12, 3, 0, tr_tlv),     /* TRL, TRR */
 316         SOC_DOUBLE_TLV("Tone Control - Bass", UDA1380_MODE, 0, 8, 15, 0, bb_tlv),       /* BBL, BBR */
 317 /**/    SOC_SINGLE("Master Playback Switch", UDA1380_DEEMP, 14, 1, 1),          /* MTM */
 318         SOC_SINGLE("ADC Playback Switch", UDA1380_DEEMP, 11, 1, 1),             /* MT2 from decimation filter */
 319         SOC_ENUM("ADC Playback De-emphasis", uda1380_deemp_enum[0]),            /* DE2 */
 320         SOC_SINGLE("PCM Playback Switch", UDA1380_DEEMP, 3, 1, 1),              /* MT1, from digital data input */
 321         SOC_ENUM("PCM Playback De-emphasis", uda1380_deemp_enum[1]),            /* DE1 */
 322         SOC_SINGLE("DAC Polarity inverting Switch", UDA1380_MIXER, 15, 1, 0),   /* DA_POL_INV */
 323         SOC_ENUM("Noise Shaper", uda1380_sel_ns_enum),                          /* SEL_NS */
 324         SOC_ENUM("Digital Mixer Signal Control", uda1380_mix_enum),             /* MIX_POS, MIX */
 325         SOC_SINGLE("Silence Detector Switch", UDA1380_MIXER, 6, 1, 0),          /* SDET_ON */
 326         SOC_ENUM("Silence Detector Setting", uda1380_sdet_enum),                /* SD_VALUE */
 327         SOC_ENUM("Oversampling Input", uda1380_os_enum),                        /* OS */
 328         SOC_DOUBLE_S8_TLV("ADC Capture Volume", UDA1380_DEC, -128, 48, dec_tlv),        /* ML_DEC, MR_DEC */
 329 /**/    SOC_SINGLE("ADC Capture Switch", UDA1380_PGA, 15, 1, 1),                /* MT_ADC */
 330         SOC_DOUBLE_TLV("Line Capture Volume", UDA1380_PGA, 0, 8, 8, 0, pga_tlv), /* PGA_GAINCTRLL, PGA_GAINCTRLR */
 331         SOC_SINGLE("ADC Polarity inverting Switch", UDA1380_ADC, 12, 1, 0),     /* ADCPOL_INV */
 332         SOC_SINGLE_TLV("Mic Capture Volume", UDA1380_ADC, 8, 15, 0, vga_tlv),   /* VGA_CTRL */
 333         SOC_SINGLE("DC Filter Bypass Switch", UDA1380_ADC, 1, 1, 0),            /* SKIP_DCFIL (before decimator) */
 334         SOC_SINGLE("DC Filter Enable Switch", UDA1380_ADC, 0, 1, 0),            /* EN_DCFIL (at output of decimator) */
 335         SOC_SINGLE("AGC Timing", UDA1380_AGC, 8, 7, 0),                 /* TODO: enum, see table 62 */
 336         SOC_SINGLE("AGC Target level", UDA1380_AGC, 2, 3, 1),                   /* AGC_LEVEL */
 337         /* -5.5, -8, -11.5, -14 dBFS */
 338         SOC_SINGLE("AGC Switch", UDA1380_AGC, 0, 1, 0),
 339 };
 340
 341 /* Input mux */
 342 static const struct snd_kcontrol_new uda1380_input_mux_control =
 343         SOC_DAPM_ENUM("Route", uda1380_input_sel_enum);
 344
 345 /* Output mux */
 346 static const struct snd_kcontrol_new uda1380_output_mux_control =
 347         SOC_DAPM_ENUM("Route", uda1380_output_sel_enum);
 348
 349 /* Capture mux */
 350 static const struct snd_kcontrol_new uda1380_capture_mux_control =
 351         SOC_DAPM_ENUM("Route", uda1380_capture_sel_enum);
 352
 353
 354 static const struct snd_soc_dapm_widget uda1380_dapm_widgets[] = {
 355         SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
 356                 &uda1380_input_mux_control),
 357         SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM, 0, 0,
 358                 &uda1380_output_mux_control),
 359         SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
 360                 &uda1380_capture_mux_control),
 361         SND_SOC_DAPM_PGA("Left PGA", UDA1380_PM, 3, 0, NULL, 0),
 362         SND_SOC_DAPM_PGA("Right PGA", UDA1380_PM, 1, 0, NULL, 0),
 363         SND_SOC_DAPM_PGA("Mic LNA", UDA1380_PM, 4, 0, NULL, 0),
 364         SND_SOC_DAPM_ADC("Left ADC", "Left Capture", UDA1380_PM, 2, 0),
 365         SND_SOC_DAPM_ADC("Right ADC", "Right Capture", UDA1380_PM, 0, 0),
 366         SND_SOC_DAPM_INPUT("VINM"),
 367         SND_SOC_DAPM_INPUT("VINL"),
 368         SND_SOC_DAPM_INPUT("VINR"),
 369         SND_SOC_DAPM_MIXER("Analog Mixer", UDA1380_PM, 6, 0, NULL, 0),
 370         SND_SOC_DAPM_OUTPUT("VOUTLHP"),
 371         SND_SOC_DAPM_OUTPUT("VOUTRHP"),
 372         SND_SOC_DAPM_OUTPUT("VOUTL"),
 373         SND_SOC_DAPM_OUTPUT("VOUTR"),
 374         SND_SOC_DAPM_DAC("DAC", "Playback", UDA1380_PM, 10, 0),
 375         SND_SOC_DAPM_PGA("HeadPhone Driver", UDA1380_PM, 13, 0, NULL, 0),
 376 };
 377
 378 static const struct snd_soc_dapm_route audio_map[] = {
 379
 380         /* output mux */
 381         {"HeadPhone Driver", NULL, "Output Mux"},
 382         {"VOUTR", NULL, "Output Mux"},
 383         {"VOUTL", NULL, "Output Mux"},
 384
 385         {"Analog Mixer", NULL, "VINR"},
 386         {"Analog Mixer", NULL, "VINL"},
 387         {"Analog Mixer", NULL, "DAC"},
 388
 389         {"Output Mux", "DAC", "DAC"},
 390         {"Output Mux", "Analog Mixer", "Analog Mixer"},
 391
 392         /* {"DAC", "Digital Mixer", "I2S" } */
 393
 394         /* headphone driver */
 395         {"VOUTLHP", NULL, "HeadPhone Driver"},
 396         {"VOUTRHP", NULL, "HeadPhone Driver"},
 397
 398         /* input mux */
 399         {"Left ADC", NULL, "Input Mux"},
 400         {"Input Mux", "Mic", "Mic LNA"},
 401         {"Input Mux", "Mic + Line R", "Mic LNA"},
 402         {"Input Mux", "Line L", "Left PGA"},
 403         {"Input Mux", "Line", "Left PGA"},
 404
 405         /* right input */
 406         {"Right ADC", "Mic + Line R", "Right PGA"},
 407         {"Right ADC", "Line", "Right PGA"},
 408
 409         /* inputs */
 410         {"Mic LNA", NULL, "VINM"},
 411         {"Left PGA", NULL, "VINL"},
 412         {"Right PGA", NULL, "VINR"},
 413 };
 414
 415 static int uda1380_add_widgets(struct snd_soc_codec *codec)
 416 {
 417         snd_soc_dapm_new_controls(codec, uda1380_dapm_widgets,
 418                                   ARRAY_SIZE(uda1380_dapm_widgets));
 419
 420         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
 421
 422         return 0;
 423 }
 424
 425 static int uda1380_set_dai_fmt_both(struct snd_soc_dai *codec_dai,
 426                 unsigned int fmt)
 427 {
 428         struct snd_soc_codec *codec = codec_dai->codec;
 429         int iface;
 430
 431         /* set up DAI based upon fmt */
 432         iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
 433         iface &= ~(R01_SFORI_MASK | R01_SIM | R01_SFORO_MASK);
 434
 435         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 436         case SND_SOC_DAIFMT_I2S:
 437                 iface |= R01_SFORI_I2S | R01_SFORO_I2S;
 438                 break;
 439         case SND_SOC_DAIFMT_LSB:
 440                 iface |= R01_SFORI_LSB16 | R01_SFORO_LSB16;
 441                 break;
 442         case SND_SOC_DAIFMT_MSB:
 443                 iface |= R01_SFORI_MSB | R01_SFORO_MSB;
 444         }
 445
 446         /* DATAI is slave only, so in single-link mode, this has to be slave */
 447         if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
 448                 return -EINVAL;
 449
 450         uda1380_write(codec, UDA1380_IFACE, iface);
 451
 452         return 0;
 453 }
 454
 455 static int uda1380_set_dai_fmt_playback(struct snd_soc_dai *codec_dai,
 456                 unsigned int fmt)
 457 {
 458         struct snd_soc_codec *codec = codec_dai->codec;
 459         int iface;
 460
 461         /* set up DAI based upon fmt */
 462         iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
 463         iface &= ~R01_SFORI_MASK;
 464
 465         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 466         case SND_SOC_DAIFMT_I2S:
 467                 iface |= R01_SFORI_I2S;
 468                 break;
 469         case SND_SOC_DAIFMT_LSB:
 470                 iface |= R01_SFORI_LSB16;
 471                 break;
 472         case SND_SOC_DAIFMT_MSB:
 473                 iface |= R01_SFORI_MSB;
 474         }
 475
 476         /* DATAI is slave only, so this has to be slave */
 477         if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
 478                 return -EINVAL;
 479
 480         uda1380_write(codec, UDA1380_IFACE, iface);
 481
 482         return 0;
 483 }
 484
 485 static int uda1380_set_dai_fmt_capture(struct snd_soc_dai *codec_dai,
 486                 unsigned int fmt)
 487 {
 488         struct snd_soc_codec *codec = codec_dai->codec;
 489         int iface;
 490
 491         /* set up DAI based upon fmt */
 492         iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
 493         iface &= ~(R01_SIM | R01_SFORO_MASK);
 494
 495         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 496         case SND_SOC_DAIFMT_I2S:
 497                 iface |= R01_SFORO_I2S;
 498                 break;
 499         case SND_SOC_DAIFMT_LSB:
 500                 iface |= R01_SFORO_LSB16;
 501                 break;
 502         case SND_SOC_DAIFMT_MSB:
 503                 iface |= R01_SFORO_MSB;
 504         }
 505
 506         if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM)
 507                 iface |= R01_SIM;
 508
 509         uda1380_write(codec, UDA1380_IFACE, iface);
 510
 511         return 0;
 512 }
 513
 514 static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd,
 515                 struct snd_soc_dai *dai)
 516 {
 517         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 518         struct snd_soc_codec *codec = rtd->codec;
 519         struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
 520         int mixer = uda1380_read_reg_cache(codec, UDA1380_MIXER);
 521
 522         switch (cmd) {
 523         case SNDRV_PCM_TRIGGER_START:
 524         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 525                 uda1380_write_reg_cache(codec, UDA1380_MIXER,
 526                                         mixer & ~R14_SILENCE);
 527                 schedule_work(&uda1380->work);
 528                 break;
 529         case SNDRV_PCM_TRIGGER_STOP:
 530         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 531                 uda1380_write_reg_cache(codec, UDA1380_MIXER,
 532                                         mixer | R14_SILENCE);
 533                 schedule_work(&uda1380->work);
 534                 break;
 535         }
 536         return 0;
 537 }
 538
 539 static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream,
 540                                  struct snd_pcm_hw_params *params,
 541                                  struct snd_soc_dai *dai)
 542 {
 543         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 544         struct snd_soc_codec *codec = rtd->codec;
 545         u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
 546
 547         /* set WSPLL power and divider if running from this clock */
 548         if (clk & R00_DAC_CLK) {
 549                 int rate = params_rate(params);
 550                 u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
 551                 clk &= ~0x3; /* clear SEL_LOOP_DIV */
 552                 switch (rate) {
 553                 case 6250 ... 12500:
 554                         clk |= 0x0;
 555                         break;
 556                 case 12501 ... 25000:
 557                         clk |= 0x1;
 558                         break;
 559                 case 25001 ... 50000:
 560                         clk |= 0x2;
 561                         break;
 562                 case 50001 ... 100000:
 563                         clk |= 0x3;
 564                         break;
 565                 }
 566                 uda1380_write(codec, UDA1380_PM, R02_PON_PLL | pm);
 567         }
 568
 569         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 570                 clk |= R00_EN_DAC | R00_EN_INT;
 571         else
 572                 clk |= R00_EN_ADC | R00_EN_DEC;
 573
 574         uda1380_write(codec, UDA1380_CLK, clk);
 575         return 0;
 576 }
 577
 578 static void uda1380_pcm_shutdown(struct snd_pcm_substream *substream,
 579                                  struct snd_soc_dai *dai)
 580 {
 581         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 582         struct snd_soc_codec *codec = rtd->codec;
 583         u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
 584
 585         /* shut down WSPLL power if running from this clock */
 586         if (clk & R00_DAC_CLK) {
 587                 u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
 588                 uda1380_write(codec, UDA1380_PM, ~R02_PON_PLL & pm);
 589         }
 590
 591         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 592                 clk &= ~(R00_EN_DAC | R00_EN_INT);
 593         else
 594                 clk &= ~(R00_EN_ADC | R00_EN_DEC);
 595
 596         uda1380_write(codec, UDA1380_CLK, clk);
 597 }
 598
 599 static int uda1380_set_bias_level(struct snd_soc_codec *codec,
 600         enum snd_soc_bias_level level)
 601 {
 602         int pm = uda1380_read_reg_cache(codec, UDA1380_PM);
 603         int reg;
 604         struct uda1380_platform_data *pdata = codec->dev->platform_data;
 605
 606         if (codec->bias_level == level)
 607                 return 0;
 608
 609         switch (level) {
 610         case SND_SOC_BIAS_ON:
 611         case SND_SOC_BIAS_PREPARE:
 612                 /* ADC, DAC on */
 613                 uda1380_write(codec, UDA1380_PM, R02_PON_BIAS | pm);
 614                 break;
 615         case SND_SOC_BIAS_STANDBY:
 616                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
 617                         if (gpio_is_valid(pdata->gpio_power)) {
 618                                 gpio_set_value(pdata->gpio_power, 1);
 619                                 mdelay(1);
 620                                 uda1380_reset(codec);
 621                         }
 622
 623                         uda1380_sync_cache(codec);
 624                 }
 625                 uda1380_write(codec, UDA1380_PM, 0x0);
 626                 break;
 627         case SND_SOC_BIAS_OFF:
 628                 if (!gpio_is_valid(pdata->gpio_power))
 629                         break;
 630
 631                 gpio_set_value(pdata->gpio_power, 0);
 632
 633                 /* Mark mixer regs cache dirty to sync them with
 634                  * codec regs on power on.
 635                  */
 636                 for (reg = UDA1380_MVOL; reg < UDA1380_CACHEREGNUM; reg++)
 637                         set_bit(reg - 0x10, &uda1380_cache_dirty);
 638         }
 639         codec->bias_level = level;
 640         return 0;
 641 }
 642
 643 #define UDA1380_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
 644                        SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
 645                        SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
 646
 647 static struct snd_soc_dai_ops uda1380_dai_ops = {
 648         .hw_params      = uda1380_pcm_hw_params,
 649         .shutdown       = uda1380_pcm_shutdown,
 650         .trigger        = uda1380_trigger,
 651         .set_fmt        = uda1380_set_dai_fmt_both,
 652 };
 653
 654 static struct snd_soc_dai_ops uda1380_dai_ops_playback = {
 655         .hw_params      = uda1380_pcm_hw_params,
 656         .shutdown       = uda1380_pcm_shutdown,
 657         .trigger        = uda1380_trigger,
 658         .set_fmt        = uda1380_set_dai_fmt_playback,
 659 };
 660
 661 static struct snd_soc_dai_ops uda1380_dai_ops_capture = {
 662         .hw_params      = uda1380_pcm_hw_params,
 663         .shutdown       = uda1380_pcm_shutdown,
 664         .trigger        = uda1380_trigger,
 665         .set_fmt        = uda1380_set_dai_fmt_capture,
 666 };
 667
 668 static struct snd_soc_dai_driver uda1380_dai[] = {
 669 {
 670         .name = "uda1380-hifi",
 671         .playback = {
 672                 .stream_name = "Playback",
 673                 .channels_min = 1,
 674                 .channels_max = 2,
 675                 .rates = UDA1380_RATES,
 676                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 677         .capture = {
 678                 .stream_name = "Capture",
 679                 .channels_min = 1,
 680                 .channels_max = 2,
 681                 .rates = UDA1380_RATES,
 682                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 683         .ops = &uda1380_dai_ops,
 684 },
 685 { /* playback only - dual interface */
 686         .name = "uda1380-hifi-playback",
 687         .playback = {
 688                 .stream_name = "Playback",
 689                 .channels_min = 1,
 690                 .channels_max = 2,
 691                 .rates = UDA1380_RATES,
 692                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 693         },
 694         .ops = &uda1380_dai_ops_playback,
 695 },
 696 { /* capture only - dual interface*/
 697         .name = "uda1380-hifi-capture",
 698         .capture = {
 699                 .stream_name = "Capture",
 700                 .channels_min = 1,
 701                 .channels_max = 2,
 702                 .rates = UDA1380_RATES,
 703                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 704         },
 705         .ops = &uda1380_dai_ops_capture,
 706 },
 707 };
 708
 709 static int uda1380_suspend(struct snd_soc_codec *codec, pm_message_t state)
 710 {
 711         uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
 712         return 0;
 713 }
 714
 715 static int uda1380_resume(struct snd_soc_codec *codec)
 716 {
 717         uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 718         return 0;
 719 }
 720
 721 static int uda1380_probe(struct snd_soc_codec *codec)
 722 {
 723         struct uda1380_platform_data *pdata =codec->dev->platform_data;
 724         struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
 725         int ret;
 726
 727         uda1380->codec = codec;
 728
 729         codec->hw_write = (hw_write_t)i2c_master_send;
 730         codec->control_data = uda1380->control_data;
 731
 732         if (!pdata)
 733                 return -EINVAL;
 734
 735         if (gpio_is_valid(pdata->gpio_reset)) {
 736                 ret = gpio_request(pdata->gpio_reset, "uda1380 reset");
 737                 if (ret)
 738                         goto err_out;
 739                 ret = gpio_direction_output(pdata->gpio_reset, 0);
 740                 if (ret)
 741                         goto err_gpio_reset_conf;
 742         }
 743
 744         if (gpio_is_valid(pdata->gpio_power)) {
 745                 ret = gpio_request(pdata->gpio_power, "uda1380 power");
 746                 if (ret)
 747                         goto err_gpio;
 748                 ret = gpio_direction_output(pdata->gpio_power, 0);
 749                 if (ret)
 750                         goto err_gpio_power_conf;
 751         } else {
 752                 ret = uda1380_reset(codec);
 753                 if (ret) {
 754                         dev_err(codec->dev, "Failed to issue reset\n");
 755                         goto err_reset;
 756                 }
 757         }
 758
 759         INIT_WORK(&uda1380->work, uda1380_flush_work);
 760
 761         /* power on device */
 762         uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 763         /* set clock input */
 764         switch (pdata->dac_clk) {
 765         case UDA1380_DAC_CLK_SYSCLK:
 766                 uda1380_write_reg_cache(codec, UDA1380_CLK, 0);
 767                 break;
 768         case UDA1380_DAC_CLK_WSPLL:
 769                 uda1380_write_reg_cache(codec, UDA1380_CLK,
 770                         R00_DAC_CLK);
 771                 break;
 772         }
 773
 774         snd_soc_add_controls(codec, uda1380_snd_controls,
 775                                 ARRAY_SIZE(uda1380_snd_controls));
 776         uda1380_add_widgets(codec);
 777
 778         return 0;
 779
 780 err_reset:
 781 err_gpio_power_conf:
 782         if (gpio_is_valid(pdata->gpio_power))
 783                 gpio_free(pdata->gpio_power);
 784
 785 err_gpio_reset_conf:
 786 err_gpio:
 787         if (gpio_is_valid(pdata->gpio_reset))
 788                 gpio_free(pdata->gpio_reset);
 789 err_out:
 790         return ret;
 791 }
 792
 793 /* power down chip */
 794 static int uda1380_remove(struct snd_soc_codec *codec)
 795 {
 796         struct uda1380_platform_data *pdata =codec->dev->platform_data;
 797
 798         uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
 799
 800         gpio_free(pdata->gpio_reset);
 801         gpio_free(pdata->gpio_power);
 802
 803         return 0;
 804 }
 805
 806 static struct snd_soc_codec_driver soc_codec_dev_uda1380 = {
 807         .probe =        uda1380_probe,
 808         .remove =       uda1380_remove,
 809         .suspend =      uda1380_suspend,
 810         .resume =       uda1380_resume,
 811         .read =         uda1380_read_reg_cache,
 812         .write =        uda1380_write,
 813         .set_bias_level = uda1380_set_bias_level,
 814         .reg_cache_size = ARRAY_SIZE(uda1380_reg),
 815         .reg_word_size = sizeof(u16),
 816         .reg_cache_default = uda1380_reg,
 817         .reg_cache_step = 1,
 818 };
 819
 820 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 821 static __devinit int uda1380_i2c_probe(struct i2c_client *i2c,
 822                                       const struct i2c_device_id *id)
 823 {
 824         struct uda1380_priv *uda1380;
 825         int ret;
 826
 827         uda1380 = kzalloc(sizeof(struct uda1380_priv), GFP_KERNEL);
 828         if (uda1380 == NULL)
 829                 return -ENOMEM;
 830
 831         i2c_set_clientdata(i2c, uda1380);
 832         uda1380->control_data = i2c;
 833
 834         ret =  snd_soc_register_codec(&i2c->dev,
 835                         &soc_codec_dev_uda1380, uda1380_dai, ARRAY_SIZE(uda1380_dai));
 836         if (ret < 0)
 837                 kfree(uda1380);
 838         return ret;
 839 }
 840
 841 static int __devexit uda1380_i2c_remove(struct i2c_client *i2c)
 842 {
 843         snd_soc_unregister_codec(&i2c->dev);
 844         kfree(i2c_get_clientdata(i2c));
 845         return 0;
 846 }
 847
 848 static const struct i2c_device_id uda1380_i2c_id[] = {
 849         { "uda1380", 0 },
 850         { }
 851 };
 852 MODULE_DEVICE_TABLE(i2c, uda1380_i2c_id);
 853
 854 static struct i2c_driver uda1380_i2c_driver = {
 855         .driver = {
 856                 .name =  "uda1380-codec",
 857                 .owner = THIS_MODULE,
 858         },
 859         .probe =    uda1380_i2c_probe,
 860         .remove =   __devexit_p(uda1380_i2c_remove),
 861         .id_table = uda1380_i2c_id,
 862 };
 863 #endif
 864
 865 static int __init uda1380_modinit(void)
 866 {
 867         int ret;
 868 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 869         ret = i2c_add_driver(&uda1380_i2c_driver);
 870         if (ret != 0)
 871                 pr_err("Failed to register UDA1380 I2C driver: %d\n", ret);
 872 #endif
 873         return 0;
 874 }
 875 module_init(uda1380_modinit);
 876
 877 static void __exit uda1380_exit(void)
 878 {
 879 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 880         i2c_del_driver(&uda1380_i2c_driver);
 881 #endif
 882 }
 883 module_exit(uda1380_exit);
 884
 885 MODULE_AUTHOR("Giorgio Padrin");
 886 MODULE_DESCRIPTION("Audio support for codec Philips UDA1380");
 887 MODULE_LICENSE("GPL");