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ASoC: tlv320aic3x: Reimplement output mixers
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / tlv320aic3x.c
1 /*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33, aic3007.
16 *
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
33 */
34
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/pm.h>
40 #include <linux/i2c.h>
41 #include <linux/gpio.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/platform_device.h>
44 #include <linux/slab.h>
45 #include <sound/core.h>
46 #include <sound/pcm.h>
47 #include <sound/pcm_params.h>
48 #include <sound/soc.h>
49 #include <sound/soc-dapm.h>
50 #include <sound/initval.h>
51 #include <sound/tlv.h>
52 #include <sound/tlv320aic3x.h>
53
54 #include "tlv320aic3x.h"
55
56 #define AIC3X_NUM_SUPPLIES 4
57 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
58 "IOVDD", /* I/O Voltage */
59 "DVDD", /* Digital Core Voltage */
60 "AVDD", /* Analog DAC Voltage */
61 "DRVDD", /* ADC Analog and Output Driver Voltage */
62 };
63
64 /* codec private data */
65 struct aic3x_priv {
66 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
67 enum snd_soc_control_type control_type;
68 struct aic3x_setup_data *setup;
69 void *control_data;
70 unsigned int sysclk;
71 int master;
72 int gpio_reset;
73 #define AIC3X_MODEL_3X 0
74 #define AIC3X_MODEL_33 1
75 #define AIC3X_MODEL_3007 2
76 u16 model;
77 };
78
79 /*
80 * AIC3X register cache
81 * We can't read the AIC3X register space when we are
82 * using 2 wire for device control, so we cache them instead.
83 * There is no point in caching the reset register
84 */
85 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
86 0x00, 0x00, 0x00, 0x10, /* 0 */
87 0x04, 0x00, 0x00, 0x00, /* 4 */
88 0x00, 0x00, 0x00, 0x01, /* 8 */
89 0x00, 0x00, 0x00, 0x80, /* 12 */
90 0x80, 0xff, 0xff, 0x78, /* 16 */
91 0x78, 0x78, 0x78, 0x78, /* 20 */
92 0x78, 0x00, 0x00, 0xfe, /* 24 */
93 0x00, 0x00, 0xfe, 0x00, /* 28 */
94 0x18, 0x18, 0x00, 0x00, /* 32 */
95 0x00, 0x00, 0x00, 0x00, /* 36 */
96 0x00, 0x00, 0x00, 0x80, /* 40 */
97 0x80, 0x00, 0x00, 0x00, /* 44 */
98 0x00, 0x00, 0x00, 0x04, /* 48 */
99 0x00, 0x00, 0x00, 0x00, /* 52 */
100 0x00, 0x00, 0x04, 0x00, /* 56 */
101 0x00, 0x00, 0x00, 0x00, /* 60 */
102 0x00, 0x04, 0x00, 0x00, /* 64 */
103 0x00, 0x00, 0x00, 0x00, /* 68 */
104 0x04, 0x00, 0x00, 0x00, /* 72 */
105 0x00, 0x00, 0x00, 0x00, /* 76 */
106 0x00, 0x00, 0x00, 0x00, /* 80 */
107 0x00, 0x00, 0x00, 0x00, /* 84 */
108 0x00, 0x00, 0x00, 0x00, /* 88 */
109 0x00, 0x00, 0x00, 0x00, /* 92 */
110 0x00, 0x00, 0x00, 0x00, /* 96 */
111 0x00, 0x00, 0x02, /* 100 */
112 };
113
114 /*
115 * read aic3x register cache
116 */
117 static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
118 unsigned int reg)
119 {
120 u8 *cache = codec->reg_cache;
121 if (reg >= AIC3X_CACHEREGNUM)
122 return -1;
123 return cache[reg];
124 }
125
126 /*
127 * write aic3x register cache
128 */
129 static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
130 u8 reg, u8 value)
131 {
132 u8 *cache = codec->reg_cache;
133 if (reg >= AIC3X_CACHEREGNUM)
134 return;
135 cache[reg] = value;
136 }
137
138 /*
139 * write to the aic3x register space
140 */
141 static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg,
142 unsigned int value)
143 {
144 u8 data[2];
145
146 /* data is
147 * D15..D8 aic3x register offset
148 * D7...D0 register data
149 */
150 data[0] = reg & 0xff;
151 data[1] = value & 0xff;
152
153 aic3x_write_reg_cache(codec, data[0], data[1]);
154 if (codec->hw_write(codec->control_data, data, 2) == 2)
155 return 0;
156 else
157 return -EIO;
158 }
159
160 /*
161 * read from the aic3x register space
162 */
163 static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
164 u8 *value)
165 {
166 *value = reg & 0xff;
167
168 value[0] = i2c_smbus_read_byte_data(codec->control_data, value[0]);
169
170 aic3x_write_reg_cache(codec, reg, *value);
171 return 0;
172 }
173
174 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
175 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
176 .info = snd_soc_info_volsw, \
177 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
178 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
179
180 /*
181 * All input lines are connected when !0xf and disconnected with 0xf bit field,
182 * so we have to use specific dapm_put call for input mixer
183 */
184 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
185 struct snd_ctl_elem_value *ucontrol)
186 {
187 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
188 struct soc_mixer_control *mc =
189 (struct soc_mixer_control *)kcontrol->private_value;
190 unsigned int reg = mc->reg;
191 unsigned int shift = mc->shift;
192 int max = mc->max;
193 unsigned int mask = (1 << fls(max)) - 1;
194 unsigned int invert = mc->invert;
195 unsigned short val, val_mask;
196 int ret;
197 struct snd_soc_dapm_path *path;
198 int found = 0;
199
200 val = (ucontrol->value.integer.value[0] & mask);
201
202 mask = 0xf;
203 if (val)
204 val = mask;
205
206 if (invert)
207 val = mask - val;
208 val_mask = mask << shift;
209 val = val << shift;
210
211 mutex_lock(&widget->codec->mutex);
212
213 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
214 /* find dapm widget path assoc with kcontrol */
215 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
216 if (path->kcontrol != kcontrol)
217 continue;
218
219 /* found, now check type */
220 found = 1;
221 if (val)
222 /* new connection */
223 path->connect = invert ? 0 : 1;
224 else
225 /* old connection must be powered down */
226 path->connect = invert ? 1 : 0;
227 break;
228 }
229
230 if (found)
231 snd_soc_dapm_sync(widget->codec);
232 }
233
234 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
235
236 mutex_unlock(&widget->codec->mutex);
237 return ret;
238 }
239
240 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
241 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
242 static const char *aic3x_left_hpcom_mux[] =
243 { "differential of HPLOUT", "constant VCM", "single-ended" };
244 static const char *aic3x_right_hpcom_mux[] =
245 { "differential of HPROUT", "constant VCM", "single-ended",
246 "differential of HPLCOM", "external feedback" };
247 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
248 static const char *aic3x_adc_hpf[] =
249 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
250
251 #define LDAC_ENUM 0
252 #define RDAC_ENUM 1
253 #define LHPCOM_ENUM 2
254 #define RHPCOM_ENUM 3
255 #define LINE1L_ENUM 4
256 #define LINE1R_ENUM 5
257 #define LINE2L_ENUM 6
258 #define LINE2R_ENUM 7
259 #define ADC_HPF_ENUM 8
260
261 static const struct soc_enum aic3x_enum[] = {
262 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
263 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
264 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
265 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
266 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
267 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
268 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
269 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
270 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
271 };
272
273 /*
274 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
275 */
276 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
277 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
278 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
279 /*
280 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
281 * Step size is approximately 0.5 dB over most of the scale but increasing
282 * near the very low levels.
283 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
284 * but having increasing dB difference below that (and where it doesn't count
285 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
286 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
287 */
288 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
289
290 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
291 /* Output */
292 SOC_DOUBLE_R_TLV("PCM Playback Volume",
293 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
294
295 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
296 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
297 0, 118, 1, output_stage_tlv),
298 SOC_SINGLE("LineL Playback Switch", LLOPM_CTRL, 3, 0x01, 0),
299 SOC_SINGLE("LineR Playback Switch", RLOPM_CTRL, 3, 0x01, 0),
300 SOC_DOUBLE_R_TLV("LineL DAC Playback Volume",
301 DACL1_2_LLOPM_VOL, DACR1_2_LLOPM_VOL,
302 0, 118, 1, output_stage_tlv),
303 SOC_SINGLE_TLV("LineL Left PGA Bypass Playback Volume",
304 PGAL_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
305 SOC_SINGLE_TLV("LineR Right PGA Bypass Playback Volume",
306 PGAR_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
307 SOC_DOUBLE_R_TLV("LineL Line2 Bypass Playback Volume",
308 LINE2L_2_LLOPM_VOL, LINE2R_2_LLOPM_VOL,
309 0, 118, 1, output_stage_tlv),
310 SOC_DOUBLE_R_TLV("LineR Line2 Bypass Playback Volume",
311 LINE2L_2_RLOPM_VOL, LINE2R_2_RLOPM_VOL,
312 0, 118, 1, output_stage_tlv),
313
314 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
315 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
316 0, 118, 1, output_stage_tlv),
317 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
318 SOC_DOUBLE_R_TLV("Mono PGA Bypass Playback Volume",
319 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
320 0, 118, 1, output_stage_tlv),
321 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Playback Volume",
322 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
323 0, 118, 1, output_stage_tlv),
324
325 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
326 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
327 0, 118, 1, output_stage_tlv),
328 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
329 0x01, 0),
330 SOC_DOUBLE_R_TLV("HP Right PGA Bypass Playback Volume",
331 PGAR_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
332 0, 118, 1, output_stage_tlv),
333 SOC_SINGLE_TLV("HPL PGA Bypass Playback Volume",
334 PGAL_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
335 SOC_SINGLE_TLV("HPR PGA Bypass Playback Volume",
336 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
337 SOC_DOUBLE_R_TLV("HP Line2 Bypass Playback Volume",
338 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
339 0, 118, 1, output_stage_tlv),
340
341 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
342 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
343 0, 118, 1, output_stage_tlv),
344 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
345 0x01, 0),
346 SOC_SINGLE_TLV("HPLCOM PGA Bypass Playback Volume",
347 PGAL_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
348 SOC_SINGLE_TLV("HPRCOM PGA Bypass Playback Volume",
349 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
350 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Playback Volume",
351 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
352 0, 118, 1, output_stage_tlv),
353
354 /*
355 * Note: enable Automatic input Gain Controller with care. It can
356 * adjust PGA to max value when ADC is on and will never go back.
357 */
358 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
359
360 /* Input */
361 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
362 0, 119, 0, adc_tlv),
363 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
364
365 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
366 };
367
368 /*
369 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
370 */
371 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
372
373 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
374 SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
375
376 /* Left DAC Mux */
377 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
378 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
379
380 /* Right DAC Mux */
381 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
382 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
383
384 /* Left HPCOM Mux */
385 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
386 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
387
388 /* Right HPCOM Mux */
389 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
390 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
391
392 /* Left Line Mixer */
393 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
394 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
395 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
396 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
397 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
398 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
399 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
400 };
401
402 /* Right Line Mixer */
403 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
404 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
405 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
406 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
407 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
408 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
409 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
410 };
411
412 /* Mono Mixer */
413 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
414 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
415 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
416 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
417 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
418 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
419 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
420 };
421
422 /* Left HP Mixer */
423 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
424 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
425 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
426 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
427 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
428 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
429 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
430 };
431
432 /* Right HP Mixer */
433 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
434 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
435 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
436 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
437 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
438 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
439 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
440 };
441
442 /* Left HPCOM Mixer */
443 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
444 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
445 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
446 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
447 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
448 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
449 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
450 };
451
452 /* Right HPCOM Mixer */
453 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
454 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
455 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
456 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
457 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
458 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
459 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
460 };
461
462 /* Left PGA Mixer */
463 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
464 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
465 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
466 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
467 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
468 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
469 };
470
471 /* Right PGA Mixer */
472 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
473 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
474 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
475 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
476 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
477 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
478 };
479
480 /* Left Line1 Mux */
481 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
482 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
483
484 /* Right Line1 Mux */
485 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
486 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
487
488 /* Left Line2 Mux */
489 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
490 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
491
492 /* Right Line2 Mux */
493 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
494 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
495
496 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
497 /* Left DAC to Left Outputs */
498 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
499 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
500 &aic3x_left_dac_mux_controls),
501 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
502 &aic3x_left_hpcom_mux_controls),
503 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
504 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
505 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
506
507 /* Right DAC to Right Outputs */
508 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
509 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
510 &aic3x_right_dac_mux_controls),
511 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
512 &aic3x_right_hpcom_mux_controls),
513 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
514 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
515 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
516
517 /* Mono Output */
518 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
519
520 /* Inputs to Left ADC */
521 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
522 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
523 &aic3x_left_pga_mixer_controls[0],
524 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
525 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
526 &aic3x_left_line1_mux_controls),
527 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
528 &aic3x_left_line1_mux_controls),
529 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
530 &aic3x_left_line2_mux_controls),
531
532 /* Inputs to Right ADC */
533 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
534 LINE1R_2_RADC_CTRL, 2, 0),
535 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
536 &aic3x_right_pga_mixer_controls[0],
537 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
538 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
539 &aic3x_right_line1_mux_controls),
540 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
541 &aic3x_right_line1_mux_controls),
542 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
543 &aic3x_right_line2_mux_controls),
544
545 /*
546 * Not a real mic bias widget but similar function. This is for dynamic
547 * control of GPIO1 digital mic modulator clock output function when
548 * using digital mic.
549 */
550 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
551 AIC3X_GPIO1_REG, 4, 0xf,
552 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
553 AIC3X_GPIO1_FUNC_DISABLED),
554
555 /*
556 * Also similar function like mic bias. Selects digital mic with
557 * configurable oversampling rate instead of ADC converter.
558 */
559 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
560 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
561 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
562 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
563 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
564 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
565
566 /* Mic Bias */
567 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
568 MICBIAS_CTRL, 6, 3, 1, 0),
569 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
570 MICBIAS_CTRL, 6, 3, 2, 0),
571 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
572 MICBIAS_CTRL, 6, 3, 3, 0),
573
574 /* Output mixers */
575 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
576 &aic3x_left_line_mixer_controls[0],
577 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
578 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
579 &aic3x_right_line_mixer_controls[0],
580 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
581 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
582 &aic3x_mono_mixer_controls[0],
583 ARRAY_SIZE(aic3x_mono_mixer_controls)),
584 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
585 &aic3x_left_hp_mixer_controls[0],
586 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
587 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
588 &aic3x_right_hp_mixer_controls[0],
589 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
590 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
591 &aic3x_left_hpcom_mixer_controls[0],
592 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
593 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
594 &aic3x_right_hpcom_mixer_controls[0],
595 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
596
597 SND_SOC_DAPM_OUTPUT("LLOUT"),
598 SND_SOC_DAPM_OUTPUT("RLOUT"),
599 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
600 SND_SOC_DAPM_OUTPUT("HPLOUT"),
601 SND_SOC_DAPM_OUTPUT("HPROUT"),
602 SND_SOC_DAPM_OUTPUT("HPLCOM"),
603 SND_SOC_DAPM_OUTPUT("HPRCOM"),
604
605 SND_SOC_DAPM_INPUT("MIC3L"),
606 SND_SOC_DAPM_INPUT("MIC3R"),
607 SND_SOC_DAPM_INPUT("LINE1L"),
608 SND_SOC_DAPM_INPUT("LINE1R"),
609 SND_SOC_DAPM_INPUT("LINE2L"),
610 SND_SOC_DAPM_INPUT("LINE2R"),
611 };
612
613 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
614 /* Class-D outputs */
615 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
616 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
617
618 SND_SOC_DAPM_OUTPUT("SPOP"),
619 SND_SOC_DAPM_OUTPUT("SPOM"),
620 };
621
622 static const struct snd_soc_dapm_route intercon[] = {
623 /* Left Input */
624 {"Left Line1L Mux", "single-ended", "LINE1L"},
625 {"Left Line1L Mux", "differential", "LINE1L"},
626
627 {"Left Line2L Mux", "single-ended", "LINE2L"},
628 {"Left Line2L Mux", "differential", "LINE2L"},
629
630 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
631 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
632 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
633 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
634 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
635
636 {"Left ADC", NULL, "Left PGA Mixer"},
637 {"Left ADC", NULL, "GPIO1 dmic modclk"},
638
639 /* Right Input */
640 {"Right Line1R Mux", "single-ended", "LINE1R"},
641 {"Right Line1R Mux", "differential", "LINE1R"},
642
643 {"Right Line2R Mux", "single-ended", "LINE2R"},
644 {"Right Line2R Mux", "differential", "LINE2R"},
645
646 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
647 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
648 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
649 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
650 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
651
652 {"Right ADC", NULL, "Right PGA Mixer"},
653 {"Right ADC", NULL, "GPIO1 dmic modclk"},
654
655 /*
656 * Logical path between digital mic enable and GPIO1 modulator clock
657 * output function
658 */
659 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
660 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
661 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
662
663 /* Left DAC Output */
664 {"Left DAC Mux", "DAC_L1", "Left DAC"},
665 {"Left DAC Mux", "DAC_L2", "Left DAC"},
666 {"Left DAC Mux", "DAC_L3", "Left DAC"},
667
668 /* Right DAC Output */
669 {"Right DAC Mux", "DAC_R1", "Right DAC"},
670 {"Right DAC Mux", "DAC_R2", "Right DAC"},
671 {"Right DAC Mux", "DAC_R3", "Right DAC"},
672
673 /* Left Line Output */
674 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
675 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
676 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
677 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
678 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
679 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
680
681 {"Left Line Out", NULL, "Left Line Mixer"},
682 {"Left Line Out", NULL, "Left DAC Mux"},
683 {"LLOUT", NULL, "Left Line Out"},
684
685 /* Right Line Output */
686 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
687 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
688 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
689 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
690 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
691 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
692
693 {"Right Line Out", NULL, "Right Line Mixer"},
694 {"Right Line Out", NULL, "Right DAC Mux"},
695 {"RLOUT", NULL, "Right Line Out"},
696
697 /* Mono Output */
698 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
699 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
700 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
701 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
702 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
703 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
704
705 {"Mono Out", NULL, "Mono Mixer"},
706 {"MONO_LOUT", NULL, "Mono Out"},
707
708 /* Left HP Output */
709 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
710 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
711 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
712 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
713 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
714 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
715
716 {"Left HP Out", NULL, "Left HP Mixer"},
717 {"Left HP Out", NULL, "Left DAC Mux"},
718 {"HPLOUT", NULL, "Left HP Out"},
719
720 /* Right HP Output */
721 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
722 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
723 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
724 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
725 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
726 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
727
728 {"Right HP Out", NULL, "Right HP Mixer"},
729 {"Right HP Out", NULL, "Right DAC Mux"},
730 {"HPROUT", NULL, "Right HP Out"},
731
732 /* Left HPCOM Output */
733 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
734 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
735 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
736 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
737 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
738 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
739
740 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
741 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
742 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
743 {"Left HP Com", NULL, "Left HPCOM Mux"},
744 {"HPLCOM", NULL, "Left HP Com"},
745
746 /* Right HPCOM Output */
747 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
748 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
749 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
750 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
751 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
752 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
753
754 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
755 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
756 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
757 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
758 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
759 {"Right HP Com", NULL, "Right HPCOM Mux"},
760 {"HPRCOM", NULL, "Right HP Com"},
761 };
762
763 static const struct snd_soc_dapm_route intercon_3007[] = {
764 /* Class-D outputs */
765 {"Left Class-D Out", NULL, "Left Line Out"},
766 {"Right Class-D Out", NULL, "Left Line Out"},
767 {"SPOP", NULL, "Left Class-D Out"},
768 {"SPOM", NULL, "Right Class-D Out"},
769 };
770
771 static int aic3x_add_widgets(struct snd_soc_codec *codec)
772 {
773 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
774
775 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
776 ARRAY_SIZE(aic3x_dapm_widgets));
777
778 /* set up audio path interconnects */
779 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
780
781 if (aic3x->model == AIC3X_MODEL_3007) {
782 snd_soc_dapm_new_controls(codec, aic3007_dapm_widgets,
783 ARRAY_SIZE(aic3007_dapm_widgets));
784 snd_soc_dapm_add_routes(codec, intercon_3007, ARRAY_SIZE(intercon_3007));
785 }
786
787 return 0;
788 }
789
790 static int aic3x_hw_params(struct snd_pcm_substream *substream,
791 struct snd_pcm_hw_params *params,
792 struct snd_soc_dai *dai)
793 {
794 struct snd_soc_pcm_runtime *rtd = substream->private_data;
795 struct snd_soc_codec *codec =rtd->codec;
796 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
797 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
798 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
799 u16 d, pll_d = 1;
800 u8 reg;
801 int clk;
802
803 /* select data word length */
804 data =
805 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
806 switch (params_format(params)) {
807 case SNDRV_PCM_FORMAT_S16_LE:
808 break;
809 case SNDRV_PCM_FORMAT_S20_3LE:
810 data |= (0x01 << 4);
811 break;
812 case SNDRV_PCM_FORMAT_S24_LE:
813 data |= (0x02 << 4);
814 break;
815 case SNDRV_PCM_FORMAT_S32_LE:
816 data |= (0x03 << 4);
817 break;
818 }
819 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
820
821 /* Fsref can be 44100 or 48000 */
822 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
823
824 /* Try to find a value for Q which allows us to bypass the PLL and
825 * generate CODEC_CLK directly. */
826 for (pll_q = 2; pll_q < 18; pll_q++)
827 if (aic3x->sysclk / (128 * pll_q) == fsref) {
828 bypass_pll = 1;
829 break;
830 }
831
832 if (bypass_pll) {
833 pll_q &= 0xf;
834 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
835 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
836 /* disable PLL if it is bypassed */
837 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
838 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
839
840 } else {
841 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
842 /* enable PLL when it is used */
843 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
844 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
845 }
846
847 /* Route Left DAC to left channel input and
848 * right DAC to right channel input */
849 data = (LDAC2LCH | RDAC2RCH);
850 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
851 if (params_rate(params) >= 64000)
852 data |= DUAL_RATE_MODE;
853 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
854
855 /* codec sample rate select */
856 data = (fsref * 20) / params_rate(params);
857 if (params_rate(params) < 64000)
858 data /= 2;
859 data /= 5;
860 data -= 2;
861 data |= (data << 4);
862 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
863
864 if (bypass_pll)
865 return 0;
866
867 /* Use PLL, compute apropriate setup for j, d, r and p, the closest
868 * one wins the game. Try with d==0 first, next with d!=0.
869 * Constraints for j are according to the datasheet.
870 * The sysclk is divided by 1000 to prevent integer overflows.
871 */
872
873 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
874
875 for (r = 1; r <= 16; r++)
876 for (p = 1; p <= 8; p++) {
877 for (j = 4; j <= 55; j++) {
878 /* This is actually 1000*((j+(d/10000))*r)/p
879 * The term had to be converted to get
880 * rid of the division by 10000; d = 0 here
881 */
882 int tmp_clk = (1000 * j * r) / p;
883
884 /* Check whether this values get closer than
885 * the best ones we had before
886 */
887 if (abs(codec_clk - tmp_clk) <
888 abs(codec_clk - last_clk)) {
889 pll_j = j; pll_d = 0;
890 pll_r = r; pll_p = p;
891 last_clk = tmp_clk;
892 }
893
894 /* Early exit for exact matches */
895 if (tmp_clk == codec_clk)
896 goto found;
897 }
898 }
899
900 /* try with d != 0 */
901 for (p = 1; p <= 8; p++) {
902 j = codec_clk * p / 1000;
903
904 if (j < 4 || j > 11)
905 continue;
906
907 /* do not use codec_clk here since we'd loose precision */
908 d = ((2048 * p * fsref) - j * aic3x->sysclk)
909 * 100 / (aic3x->sysclk/100);
910
911 clk = (10000 * j + d) / (10 * p);
912
913 /* check whether this values get closer than the best
914 * ones we had before */
915 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
916 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
917 last_clk = clk;
918 }
919
920 /* Early exit for exact matches */
921 if (clk == codec_clk)
922 goto found;
923 }
924
925 if (last_clk == 0) {
926 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
927 return -EINVAL;
928 }
929
930 found:
931 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
932 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
933 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
934 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
935 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
936 aic3x_write(codec, AIC3X_PLL_PROGD_REG,
937 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
938
939 return 0;
940 }
941
942 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
943 {
944 struct snd_soc_codec *codec = dai->codec;
945 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
946 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
947
948 if (mute) {
949 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
950 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
951 } else {
952 aic3x_write(codec, LDAC_VOL, ldac_reg);
953 aic3x_write(codec, RDAC_VOL, rdac_reg);
954 }
955
956 return 0;
957 }
958
959 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
960 int clk_id, unsigned int freq, int dir)
961 {
962 struct snd_soc_codec *codec = codec_dai->codec;
963 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
964
965 aic3x->sysclk = freq;
966 return 0;
967 }
968
969 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
970 unsigned int fmt)
971 {
972 struct snd_soc_codec *codec = codec_dai->codec;
973 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
974 u8 iface_areg, iface_breg;
975 int delay = 0;
976
977 iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
978 iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
979
980 /* set master/slave audio interface */
981 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
982 case SND_SOC_DAIFMT_CBM_CFM:
983 aic3x->master = 1;
984 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
985 break;
986 case SND_SOC_DAIFMT_CBS_CFS:
987 aic3x->master = 0;
988 break;
989 default:
990 return -EINVAL;
991 }
992
993 /*
994 * match both interface format and signal polarities since they
995 * are fixed
996 */
997 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
998 SND_SOC_DAIFMT_INV_MASK)) {
999 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1000 break;
1001 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1002 delay = 1;
1003 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1004 iface_breg |= (0x01 << 6);
1005 break;
1006 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1007 iface_breg |= (0x02 << 6);
1008 break;
1009 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1010 iface_breg |= (0x03 << 6);
1011 break;
1012 default:
1013 return -EINVAL;
1014 }
1015
1016 /* set iface */
1017 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1018 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1019 aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
1020
1021 return 0;
1022 }
1023
1024 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1025 enum snd_soc_bias_level level)
1026 {
1027 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1028 u8 reg;
1029
1030 switch (level) {
1031 case SND_SOC_BIAS_ON:
1032 break;
1033 case SND_SOC_BIAS_PREPARE:
1034 if (aic3x->master) {
1035 /* enable pll */
1036 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1037 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1038 reg | PLL_ENABLE);
1039 }
1040 break;
1041 case SND_SOC_BIAS_STANDBY:
1042 /* fall through and disable pll */
1043 case SND_SOC_BIAS_OFF:
1044 if (aic3x->master) {
1045 /* disable pll */
1046 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1047 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1048 reg & ~PLL_ENABLE);
1049 }
1050 break;
1051 }
1052 codec->bias_level = level;
1053
1054 return 0;
1055 }
1056
1057 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1058 {
1059 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1060 u8 bit = gpio ? 3: 0;
1061 u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit);
1062 aic3x_write(codec, reg, val | (!!state << bit));
1063 }
1064 EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1065
1066 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1067 {
1068 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1069 u8 val, bit = gpio ? 2: 1;
1070
1071 aic3x_read(codec, reg, &val);
1072 return (val >> bit) & 1;
1073 }
1074 EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1075
1076 void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1077 int headset_debounce, int button_debounce)
1078 {
1079 u8 val;
1080
1081 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1082 << AIC3X_HEADSET_DETECT_SHIFT) |
1083 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1084 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1085 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1086 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1087
1088 if (detect & AIC3X_HEADSET_DETECT_MASK)
1089 val |= AIC3X_HEADSET_DETECT_ENABLED;
1090
1091 aic3x_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
1092 }
1093 EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1094
1095 int aic3x_headset_detected(struct snd_soc_codec *codec)
1096 {
1097 u8 val;
1098 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1099 return (val >> 4) & 1;
1100 }
1101 EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1102
1103 int aic3x_button_pressed(struct snd_soc_codec *codec)
1104 {
1105 u8 val;
1106 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1107 return (val >> 5) & 1;
1108 }
1109 EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1110
1111 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1112 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1113 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1114
1115 static struct snd_soc_dai_ops aic3x_dai_ops = {
1116 .hw_params = aic3x_hw_params,
1117 .digital_mute = aic3x_mute,
1118 .set_sysclk = aic3x_set_dai_sysclk,
1119 .set_fmt = aic3x_set_dai_fmt,
1120 };
1121
1122 static struct snd_soc_dai_driver aic3x_dai = {
1123 .name = "tlv320aic3x-hifi",
1124 .playback = {
1125 .stream_name = "Playback",
1126 .channels_min = 1,
1127 .channels_max = 2,
1128 .rates = AIC3X_RATES,
1129 .formats = AIC3X_FORMATS,},
1130 .capture = {
1131 .stream_name = "Capture",
1132 .channels_min = 1,
1133 .channels_max = 2,
1134 .rates = AIC3X_RATES,
1135 .formats = AIC3X_FORMATS,},
1136 .ops = &aic3x_dai_ops,
1137 .symmetric_rates = 1,
1138 };
1139
1140 static int aic3x_suspend(struct snd_soc_codec *codec, pm_message_t state)
1141 {
1142 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1143
1144 return 0;
1145 }
1146
1147 static int aic3x_resume(struct snd_soc_codec *codec)
1148 {
1149 int i;
1150 u8 data[2];
1151 u8 *cache = codec->reg_cache;
1152
1153 /* Sync reg_cache with the hardware */
1154 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) {
1155 data[0] = i;
1156 data[1] = cache[i];
1157 codec->hw_write(codec->control_data, data, 2);
1158 }
1159
1160 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1161
1162 return 0;
1163 }
1164
1165 /*
1166 * initialise the AIC3X driver
1167 * register the mixer and dsp interfaces with the kernel
1168 */
1169 static int aic3x_init(struct snd_soc_codec *codec)
1170 {
1171 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1172 int reg;
1173
1174 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1175 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1176
1177 /* DAC default volume and mute */
1178 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1179 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1180
1181 /* DAC to HP default volume and route to Output mixer */
1182 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1183 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1184 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1185 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1186 /* DAC to Line Out default volume and route to Output mixer */
1187 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1188 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1189 /* DAC to Mono Line Out default volume and route to Output mixer */
1190 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1191 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1192
1193 /* unmute all outputs */
1194 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1195 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
1196 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1197 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
1198 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1199 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1200 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1201 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1202 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1203 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
1204 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1205 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1206 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1207 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1208
1209 /* ADC default volume and unmute */
1210 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
1211 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
1212 /* By default route Line1 to ADC PGA mixer */
1213 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1214 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1215
1216 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1217 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1218 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1219 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1220 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1221 /* PGA to Line Out default volume, disconnect from Output Mixer */
1222 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1223 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1224 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1225 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1226 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1227
1228 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1229 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1230 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1231 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1232 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1233 /* Line2 Line Out default volume, disconnect from Output Mixer */
1234 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1235 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1236 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1237 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1238 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1239
1240 if (aic3x->model == AIC3X_MODEL_3007) {
1241 /* Class-D speaker driver init; datasheet p. 46 */
1242 aic3x_write(codec, AIC3X_PAGE_SELECT, 0x0D);
1243 aic3x_write(codec, 0xD, 0x0D);
1244 aic3x_write(codec, 0x8, 0x5C);
1245 aic3x_write(codec, 0x8, 0x5D);
1246 aic3x_write(codec, 0x8, 0x5C);
1247 aic3x_write(codec, AIC3X_PAGE_SELECT, 0x00);
1248 aic3x_write(codec, CLASSD_CTRL, 0);
1249 }
1250
1251 /* off, with power on */
1252 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1253
1254 return 0;
1255 }
1256
1257 static int aic3x_probe(struct snd_soc_codec *codec)
1258 {
1259 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1260
1261 codec->hw_write = (hw_write_t) i2c_master_send;
1262 codec->control_data = aic3x->control_data;
1263
1264 aic3x_init(codec);
1265
1266 if (aic3x->setup) {
1267 /* setup GPIO functions */
1268 aic3x_write(codec, AIC3X_GPIO1_REG,
1269 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1270 aic3x_write(codec, AIC3X_GPIO2_REG,
1271 (aic3x->setup->gpio_func[1] & 0xf) << 4);
1272 }
1273
1274 snd_soc_add_controls(codec, aic3x_snd_controls,
1275 ARRAY_SIZE(aic3x_snd_controls));
1276 if (aic3x->model == AIC3X_MODEL_3007)
1277 snd_soc_add_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
1278
1279 aic3x_add_widgets(codec);
1280
1281 return 0;
1282 }
1283
1284 static int aic3x_remove(struct snd_soc_codec *codec)
1285 {
1286 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1287 return 0;
1288 }
1289
1290 static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
1291 .read = aic3x_read_reg_cache,
1292 .write = aic3x_write,
1293 .set_bias_level = aic3x_set_bias_level,
1294 .reg_cache_size = ARRAY_SIZE(aic3x_reg),
1295 .reg_word_size = sizeof(u8),
1296 .reg_cache_default = aic3x_reg,
1297 .probe = aic3x_probe,
1298 .remove = aic3x_remove,
1299 .suspend = aic3x_suspend,
1300 .resume = aic3x_resume,
1301 };
1302
1303 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1304 /*
1305 * AIC3X 2 wire address can be up to 4 devices with device addresses
1306 * 0x18, 0x19, 0x1A, 0x1B
1307 */
1308
1309 static const struct i2c_device_id aic3x_i2c_id[] = {
1310 [AIC3X_MODEL_3X] = { "tlv320aic3x", 0 },
1311 [AIC3X_MODEL_33] = { "tlv320aic33", 0 },
1312 [AIC3X_MODEL_3007] = { "tlv320aic3007", 0 },
1313 { }
1314 };
1315 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1316
1317 /*
1318 * If the i2c layer weren't so broken, we could pass this kind of data
1319 * around
1320 */
1321 static int aic3x_i2c_probe(struct i2c_client *i2c,
1322 const struct i2c_device_id *id)
1323 {
1324 struct aic3x_pdata *pdata = i2c->dev.platform_data;
1325 struct aic3x_setup_data *setup = pdata->setup;
1326 struct aic3x_priv *aic3x;
1327 int ret, i;
1328 const struct i2c_device_id *tbl;
1329
1330 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1331 if (aic3x == NULL) {
1332 dev_err(&i2c->dev, "failed to create private data\n");
1333 return -ENOMEM;
1334 }
1335
1336 aic3x->control_data = i2c;
1337 aic3x->setup = setup;
1338 i2c_set_clientdata(i2c, aic3x);
1339
1340 aic3x->gpio_reset = -1;
1341 if (pdata && pdata->gpio_reset >= 0) {
1342 ret = gpio_request(pdata->gpio_reset, "tlv320aic3x reset");
1343 if (ret != 0)
1344 goto err_gpio;
1345 aic3x->gpio_reset = pdata->gpio_reset;
1346 gpio_direction_output(aic3x->gpio_reset, 0);
1347 }
1348
1349 for (tbl = aic3x_i2c_id; tbl->name[0]; tbl++) {
1350 if (!strcmp(tbl->name, id->name))
1351 break;
1352 }
1353 aic3x->model = tbl - aic3x_i2c_id;
1354
1355 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1356 aic3x->supplies[i].supply = aic3x_supply_names[i];
1357
1358 ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies),
1359 aic3x->supplies);
1360 if (ret != 0) {
1361 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1362 goto err_get;
1363 }
1364
1365 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1366 aic3x->supplies);
1367 if (ret != 0) {
1368 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
1369 goto err_enable;
1370 }
1371
1372 if (aic3x->gpio_reset >= 0) {
1373 udelay(1);
1374 gpio_set_value(aic3x->gpio_reset, 1);
1375 }
1376
1377 ret = snd_soc_register_codec(&i2c->dev,
1378 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1379 if (ret < 0)
1380 goto err_enable;
1381 return ret;
1382
1383 err_enable:
1384 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1385 err_get:
1386 if (aic3x->gpio_reset >= 0)
1387 gpio_free(aic3x->gpio_reset);
1388 err_gpio:
1389 kfree(aic3x);
1390 return ret;
1391 }
1392
1393 static int aic3x_i2c_remove(struct i2c_client *client)
1394 {
1395 struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1396
1397 if (aic3x->gpio_reset >= 0) {
1398 gpio_set_value(aic3x->gpio_reset, 0);
1399 gpio_free(aic3x->gpio_reset);
1400 }
1401 regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1402 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1403
1404 snd_soc_unregister_codec(&client->dev);
1405 kfree(i2c_get_clientdata(client));
1406 return 0;
1407 }
1408
1409 /* machine i2c codec control layer */
1410 static struct i2c_driver aic3x_i2c_driver = {
1411 .driver = {
1412 .name = "tlv320aic3x-codec",
1413 .owner = THIS_MODULE,
1414 },
1415 .probe = aic3x_i2c_probe,
1416 .remove = aic3x_i2c_remove,
1417 .id_table = aic3x_i2c_id,
1418 };
1419
1420 static inline void aic3x_i2c_init(void)
1421 {
1422 int ret;
1423
1424 ret = i2c_add_driver(&aic3x_i2c_driver);
1425 if (ret)
1426 printk(KERN_ERR "%s: error regsitering i2c driver, %d\n",
1427 __func__, ret);
1428 }
1429
1430 static inline void aic3x_i2c_exit(void)
1431 {
1432 i2c_del_driver(&aic3x_i2c_driver);
1433 }
1434 #endif
1435
1436 static int __init aic3x_modinit(void)
1437 {
1438 int ret = 0;
1439 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1440 ret = i2c_add_driver(&aic3x_i2c_driver);
1441 if (ret != 0) {
1442 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n",
1443 ret);
1444 }
1445 #endif
1446 return ret;
1447 }
1448 module_init(aic3x_modinit);
1449
1450 static void __exit aic3x_exit(void)
1451 {
1452 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1453 i2c_del_driver(&aic3x_i2c_driver);
1454 #endif
1455 }
1456 module_exit(aic3x_exit);
1457
1458 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1459 MODULE_AUTHOR("Vladimir Barinov");
1460 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)