2 * ALSA SoC TLV320AIC3X codec driver
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33, aic3007.
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
40 #include <linux/i2c.h>
41 #include <linux/gpio.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/platform_device.h>
44 #include <linux/slab.h>
45 #include <sound/core.h>
46 #include <sound/pcm.h>
47 #include <sound/pcm_params.h>
48 #include <sound/soc.h>
49 #include <sound/soc-dapm.h>
50 #include <sound/initval.h>
51 #include <sound/tlv.h>
52 #include <sound/tlv320aic3x.h>
54 #include "tlv320aic3x.h"
56 #define AIC3X_NUM_SUPPLIES 4
57 static const char *aic3x_supply_names
[AIC3X_NUM_SUPPLIES
] = {
58 "IOVDD", /* I/O Voltage */
59 "DVDD", /* Digital Core Voltage */
60 "AVDD", /* Analog DAC Voltage */
61 "DRVDD", /* ADC Analog and Output Driver Voltage */
64 /* codec private data */
66 struct regulator_bulk_data supplies
[AIC3X_NUM_SUPPLIES
];
67 enum snd_soc_control_type control_type
;
68 struct aic3x_setup_data
*setup
;
73 #define AIC3X_MODEL_3X 0
74 #define AIC3X_MODEL_33 1
75 #define AIC3X_MODEL_3007 2
80 * AIC3X register cache
81 * We can't read the AIC3X register space when we are
82 * using 2 wire for device control, so we cache them instead.
83 * There is no point in caching the reset register
85 static const u8 aic3x_reg
[AIC3X_CACHEREGNUM
] = {
86 0x00, 0x00, 0x00, 0x10, /* 0 */
87 0x04, 0x00, 0x00, 0x00, /* 4 */
88 0x00, 0x00, 0x00, 0x01, /* 8 */
89 0x00, 0x00, 0x00, 0x80, /* 12 */
90 0x80, 0xff, 0xff, 0x78, /* 16 */
91 0x78, 0x78, 0x78, 0x78, /* 20 */
92 0x78, 0x00, 0x00, 0xfe, /* 24 */
93 0x00, 0x00, 0xfe, 0x00, /* 28 */
94 0x18, 0x18, 0x00, 0x00, /* 32 */
95 0x00, 0x00, 0x00, 0x00, /* 36 */
96 0x00, 0x00, 0x00, 0x80, /* 40 */
97 0x80, 0x00, 0x00, 0x00, /* 44 */
98 0x00, 0x00, 0x00, 0x04, /* 48 */
99 0x00, 0x00, 0x00, 0x00, /* 52 */
100 0x00, 0x00, 0x04, 0x00, /* 56 */
101 0x00, 0x00, 0x00, 0x00, /* 60 */
102 0x00, 0x04, 0x00, 0x00, /* 64 */
103 0x00, 0x00, 0x00, 0x00, /* 68 */
104 0x04, 0x00, 0x00, 0x00, /* 72 */
105 0x00, 0x00, 0x00, 0x00, /* 76 */
106 0x00, 0x00, 0x00, 0x00, /* 80 */
107 0x00, 0x00, 0x00, 0x00, /* 84 */
108 0x00, 0x00, 0x00, 0x00, /* 88 */
109 0x00, 0x00, 0x00, 0x00, /* 92 */
110 0x00, 0x00, 0x00, 0x00, /* 96 */
111 0x00, 0x00, 0x02, /* 100 */
115 * read from the aic3x register space. Only use for this function is if
116 * wanting to read volatile bits from those registers that has both read-only
117 * and read/write bits. All other cases should use snd_soc_read.
119 static int aic3x_read(struct snd_soc_codec
*codec
, unsigned int reg
,
122 u8
*cache
= codec
->reg_cache
;
124 if (reg
>= AIC3X_CACHEREGNUM
)
127 *value
= codec
->hw_read(codec
, reg
);
133 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
134 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
135 .info = snd_soc_info_volsw, \
136 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
137 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
140 * All input lines are connected when !0xf and disconnected with 0xf bit field,
141 * so we have to use specific dapm_put call for input mixer
143 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol
*kcontrol
,
144 struct snd_ctl_elem_value
*ucontrol
)
146 struct snd_soc_dapm_widget
*widget
= snd_kcontrol_chip(kcontrol
);
147 struct soc_mixer_control
*mc
=
148 (struct soc_mixer_control
*)kcontrol
->private_value
;
149 unsigned int reg
= mc
->reg
;
150 unsigned int shift
= mc
->shift
;
152 unsigned int mask
= (1 << fls(max
)) - 1;
153 unsigned int invert
= mc
->invert
;
154 unsigned short val
, val_mask
;
156 struct snd_soc_dapm_path
*path
;
159 val
= (ucontrol
->value
.integer
.value
[0] & mask
);
167 val_mask
= mask
<< shift
;
170 mutex_lock(&widget
->codec
->mutex
);
172 if (snd_soc_test_bits(widget
->codec
, reg
, val_mask
, val
)) {
173 /* find dapm widget path assoc with kcontrol */
174 list_for_each_entry(path
, &widget
->codec
->dapm_paths
, list
) {
175 if (path
->kcontrol
!= kcontrol
)
178 /* found, now check type */
182 path
->connect
= invert
? 0 : 1;
184 /* old connection must be powered down */
185 path
->connect
= invert
? 1 : 0;
190 snd_soc_dapm_sync(widget
->codec
);
193 ret
= snd_soc_update_bits(widget
->codec
, reg
, val_mask
, val
);
195 mutex_unlock(&widget
->codec
->mutex
);
199 static const char *aic3x_left_dac_mux
[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
200 static const char *aic3x_right_dac_mux
[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
201 static const char *aic3x_left_hpcom_mux
[] =
202 { "differential of HPLOUT", "constant VCM", "single-ended" };
203 static const char *aic3x_right_hpcom_mux
[] =
204 { "differential of HPROUT", "constant VCM", "single-ended",
205 "differential of HPLCOM", "external feedback" };
206 static const char *aic3x_linein_mode_mux
[] = { "single-ended", "differential" };
207 static const char *aic3x_adc_hpf
[] =
208 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
212 #define LHPCOM_ENUM 2
213 #define RHPCOM_ENUM 3
214 #define LINE1L_ENUM 4
215 #define LINE1R_ENUM 5
216 #define LINE2L_ENUM 6
217 #define LINE2R_ENUM 7
218 #define ADC_HPF_ENUM 8
220 static const struct soc_enum aic3x_enum
[] = {
221 SOC_ENUM_SINGLE(DAC_LINE_MUX
, 6, 3, aic3x_left_dac_mux
),
222 SOC_ENUM_SINGLE(DAC_LINE_MUX
, 4, 3, aic3x_right_dac_mux
),
223 SOC_ENUM_SINGLE(HPLCOM_CFG
, 4, 3, aic3x_left_hpcom_mux
),
224 SOC_ENUM_SINGLE(HPRCOM_CFG
, 3, 5, aic3x_right_hpcom_mux
),
225 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL
, 7, 2, aic3x_linein_mode_mux
),
226 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL
, 7, 2, aic3x_linein_mode_mux
),
227 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL
, 7, 2, aic3x_linein_mode_mux
),
228 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL
, 7, 2, aic3x_linein_mode_mux
),
229 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL
, 6, 4, 4, aic3x_adc_hpf
),
233 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
235 static DECLARE_TLV_DB_SCALE(dac_tlv
, -6350, 50, 0);
236 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
237 static DECLARE_TLV_DB_SCALE(adc_tlv
, 0, 50, 0);
239 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
240 * Step size is approximately 0.5 dB over most of the scale but increasing
241 * near the very low levels.
242 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
243 * but having increasing dB difference below that (and where it doesn't count
244 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
245 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
247 static DECLARE_TLV_DB_SCALE(output_stage_tlv
, -5900, 50, 1);
249 static const struct snd_kcontrol_new aic3x_snd_controls
[] = {
251 SOC_DOUBLE_R_TLV("PCM Playback Volume",
252 LDAC_VOL
, RDAC_VOL
, 0, 0x7f, 1, dac_tlv
),
255 * Output controls that map to output mixer switches. Note these are
256 * only for swapped L-to-R and R-to-L routes. See below stereo controls
257 * for direct L-to-L and R-to-R routes.
259 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
260 LINE2R_2_LLOPM_VOL
, 0, 118, 1, output_stage_tlv
),
261 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
262 PGAR_2_LLOPM_VOL
, 0, 118, 1, output_stage_tlv
),
263 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
264 DACR1_2_LLOPM_VOL
, 0, 118, 1, output_stage_tlv
),
266 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
267 LINE2L_2_RLOPM_VOL
, 0, 118, 1, output_stage_tlv
),
268 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
269 PGAL_2_RLOPM_VOL
, 0, 118, 1, output_stage_tlv
),
270 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
271 DACL1_2_RLOPM_VOL
, 0, 118, 1, output_stage_tlv
),
273 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
274 LINE2R_2_HPLOUT_VOL
, 0, 118, 1, output_stage_tlv
),
275 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
276 PGAR_2_HPLOUT_VOL
, 0, 118, 1, output_stage_tlv
),
277 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
278 DACR1_2_HPLOUT_VOL
, 0, 118, 1, output_stage_tlv
),
280 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
281 LINE2L_2_HPROUT_VOL
, 0, 118, 1, output_stage_tlv
),
282 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
283 PGAL_2_HPROUT_VOL
, 0, 118, 1, output_stage_tlv
),
284 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
285 DACL1_2_HPROUT_VOL
, 0, 118, 1, output_stage_tlv
),
287 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
288 LINE2R_2_HPLCOM_VOL
, 0, 118, 1, output_stage_tlv
),
289 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
290 PGAR_2_HPLCOM_VOL
, 0, 118, 1, output_stage_tlv
),
291 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
292 DACR1_2_HPLCOM_VOL
, 0, 118, 1, output_stage_tlv
),
294 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
295 LINE2L_2_HPRCOM_VOL
, 0, 118, 1, output_stage_tlv
),
296 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
297 PGAL_2_HPRCOM_VOL
, 0, 118, 1, output_stage_tlv
),
298 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
299 DACL1_2_HPRCOM_VOL
, 0, 118, 1, output_stage_tlv
),
301 /* Stereo output controls for direct L-to-L and R-to-R routes */
302 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
303 LINE2L_2_LLOPM_VOL
, LINE2R_2_RLOPM_VOL
,
304 0, 118, 1, output_stage_tlv
),
305 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
306 PGAL_2_LLOPM_VOL
, PGAR_2_RLOPM_VOL
,
307 0, 118, 1, output_stage_tlv
),
308 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
309 DACL1_2_LLOPM_VOL
, DACR1_2_RLOPM_VOL
,
310 0, 118, 1, output_stage_tlv
),
312 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
313 LINE2L_2_MONOLOPM_VOL
, LINE2R_2_MONOLOPM_VOL
,
314 0, 118, 1, output_stage_tlv
),
315 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
316 PGAL_2_MONOLOPM_VOL
, PGAR_2_MONOLOPM_VOL
,
317 0, 118, 1, output_stage_tlv
),
318 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
319 DACL1_2_MONOLOPM_VOL
, DACR1_2_MONOLOPM_VOL
,
320 0, 118, 1, output_stage_tlv
),
322 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
323 LINE2L_2_HPLOUT_VOL
, LINE2R_2_HPROUT_VOL
,
324 0, 118, 1, output_stage_tlv
),
325 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
326 PGAL_2_HPLOUT_VOL
, PGAR_2_HPROUT_VOL
,
327 0, 118, 1, output_stage_tlv
),
328 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
329 DACL1_2_HPLOUT_VOL
, DACR1_2_HPROUT_VOL
,
330 0, 118, 1, output_stage_tlv
),
332 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
333 LINE2L_2_HPLCOM_VOL
, LINE2R_2_HPRCOM_VOL
,
334 0, 118, 1, output_stage_tlv
),
335 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
336 PGAL_2_HPLCOM_VOL
, PGAR_2_HPRCOM_VOL
,
337 0, 118, 1, output_stage_tlv
),
338 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
339 DACL1_2_HPLCOM_VOL
, DACR1_2_HPRCOM_VOL
,
340 0, 118, 1, output_stage_tlv
),
342 /* Output pin mute controls */
343 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL
, RLOPM_CTRL
, 3,
345 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL
, 3, 0x01, 0),
346 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL
, HPROUT_CTRL
, 3,
348 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL
, HPRCOM_CTRL
, 3,
352 * Note: enable Automatic input Gain Controller with care. It can
353 * adjust PGA to max value when ADC is on and will never go back.
355 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A
, RAGC_CTRL_A
, 7, 0x01, 0),
358 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL
, RADC_VOL
,
360 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL
, RADC_VOL
, 7, 0x01, 1),
362 SOC_ENUM("ADC HPF Cut-off", aic3x_enum
[ADC_HPF_ENUM
]),
366 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
368 static DECLARE_TLV_DB_SCALE(classd_amp_tlv
, 0, 600, 0);
370 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl
=
371 SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL
, 6, 4, 3, 0, classd_amp_tlv
);
374 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls
=
375 SOC_DAPM_ENUM("Route", aic3x_enum
[LDAC_ENUM
]);
378 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls
=
379 SOC_DAPM_ENUM("Route", aic3x_enum
[RDAC_ENUM
]);
382 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls
=
383 SOC_DAPM_ENUM("Route", aic3x_enum
[LHPCOM_ENUM
]);
385 /* Right HPCOM Mux */
386 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls
=
387 SOC_DAPM_ENUM("Route", aic3x_enum
[RHPCOM_ENUM
]);
389 /* Left Line Mixer */
390 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls
[] = {
391 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL
, 7, 1, 0),
392 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL
, 7, 1, 0),
393 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL
, 7, 1, 0),
394 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL
, 7, 1, 0),
395 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL
, 7, 1, 0),
396 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL
, 7, 1, 0),
399 /* Right Line Mixer */
400 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls
[] = {
401 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL
, 7, 1, 0),
402 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL
, 7, 1, 0),
403 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL
, 7, 1, 0),
404 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL
, 7, 1, 0),
405 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL
, 7, 1, 0),
406 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL
, 7, 1, 0),
410 static const struct snd_kcontrol_new aic3x_mono_mixer_controls
[] = {
411 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL
, 7, 1, 0),
412 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL
, 7, 1, 0),
413 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL
, 7, 1, 0),
414 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL
, 7, 1, 0),
415 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL
, 7, 1, 0),
416 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL
, 7, 1, 0),
420 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls
[] = {
421 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL
, 7, 1, 0),
422 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL
, 7, 1, 0),
423 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL
, 7, 1, 0),
424 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL
, 7, 1, 0),
425 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL
, 7, 1, 0),
426 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL
, 7, 1, 0),
430 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls
[] = {
431 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL
, 7, 1, 0),
432 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL
, 7, 1, 0),
433 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL
, 7, 1, 0),
434 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL
, 7, 1, 0),
435 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL
, 7, 1, 0),
436 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL
, 7, 1, 0),
439 /* Left HPCOM Mixer */
440 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls
[] = {
441 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL
, 7, 1, 0),
442 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL
, 7, 1, 0),
443 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL
, 7, 1, 0),
444 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL
, 7, 1, 0),
445 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL
, 7, 1, 0),
446 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL
, 7, 1, 0),
449 /* Right HPCOM Mixer */
450 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls
[] = {
451 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL
, 7, 1, 0),
452 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL
, 7, 1, 0),
453 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL
, 7, 1, 0),
454 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL
, 7, 1, 0),
455 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL
, 7, 1, 0),
456 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL
, 7, 1, 0),
460 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls
[] = {
461 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL
, 3, 1, 1),
462 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL
, 3, 1, 1),
463 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL
, 3, 1, 1),
464 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL
, 4, 1, 1),
465 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL
, 0, 1, 1),
468 /* Right PGA Mixer */
469 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls
[] = {
470 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL
, 3, 1, 1),
471 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL
, 3, 1, 1),
472 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL
, 3, 1, 1),
473 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL
, 4, 1, 1),
474 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL
, 0, 1, 1),
478 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls
=
479 SOC_DAPM_ENUM("Route", aic3x_enum
[LINE1L_ENUM
]);
481 /* Right Line1 Mux */
482 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls
=
483 SOC_DAPM_ENUM("Route", aic3x_enum
[LINE1R_ENUM
]);
486 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls
=
487 SOC_DAPM_ENUM("Route", aic3x_enum
[LINE2L_ENUM
]);
489 /* Right Line2 Mux */
490 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls
=
491 SOC_DAPM_ENUM("Route", aic3x_enum
[LINE2R_ENUM
]);
493 static const struct snd_soc_dapm_widget aic3x_dapm_widgets
[] = {
494 /* Left DAC to Left Outputs */
495 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR
, 7, 0),
496 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM
, 0, 0,
497 &aic3x_left_dac_mux_controls
),
498 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM
, 0, 0,
499 &aic3x_left_hpcom_mux_controls
),
500 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL
, 0, 0, NULL
, 0),
501 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL
, 0, 0, NULL
, 0),
502 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL
, 0, 0, NULL
, 0),
504 /* Right DAC to Right Outputs */
505 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR
, 6, 0),
506 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM
, 0, 0,
507 &aic3x_right_dac_mux_controls
),
508 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM
, 0, 0,
509 &aic3x_right_hpcom_mux_controls
),
510 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL
, 0, 0, NULL
, 0),
511 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL
, 0, 0, NULL
, 0),
512 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL
, 0, 0, NULL
, 0),
515 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL
, 0, 0, NULL
, 0),
517 /* Inputs to Left ADC */
518 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL
, 2, 0),
519 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM
, 0, 0,
520 &aic3x_left_pga_mixer_controls
[0],
521 ARRAY_SIZE(aic3x_left_pga_mixer_controls
)),
522 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM
, 0, 0,
523 &aic3x_left_line1_mux_controls
),
524 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM
, 0, 0,
525 &aic3x_left_line1_mux_controls
),
526 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM
, 0, 0,
527 &aic3x_left_line2_mux_controls
),
529 /* Inputs to Right ADC */
530 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
531 LINE1R_2_RADC_CTRL
, 2, 0),
532 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM
, 0, 0,
533 &aic3x_right_pga_mixer_controls
[0],
534 ARRAY_SIZE(aic3x_right_pga_mixer_controls
)),
535 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM
, 0, 0,
536 &aic3x_right_line1_mux_controls
),
537 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM
, 0, 0,
538 &aic3x_right_line1_mux_controls
),
539 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM
, 0, 0,
540 &aic3x_right_line2_mux_controls
),
543 * Not a real mic bias widget but similar function. This is for dynamic
544 * control of GPIO1 digital mic modulator clock output function when
547 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "GPIO1 dmic modclk",
548 AIC3X_GPIO1_REG
, 4, 0xf,
549 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK
,
550 AIC3X_GPIO1_FUNC_DISABLED
),
553 * Also similar function like mic bias. Selects digital mic with
554 * configurable oversampling rate instead of ADC converter.
556 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "DMic Rate 128",
557 AIC3X_ASD_INTF_CTRLA
, 0, 3, 1, 0),
558 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "DMic Rate 64",
559 AIC3X_ASD_INTF_CTRLA
, 0, 3, 2, 0),
560 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "DMic Rate 32",
561 AIC3X_ASD_INTF_CTRLA
, 0, 3, 3, 0),
564 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "Mic Bias 2V",
565 MICBIAS_CTRL
, 6, 3, 1, 0),
566 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "Mic Bias 2.5V",
567 MICBIAS_CTRL
, 6, 3, 2, 0),
568 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "Mic Bias AVDD",
569 MICBIAS_CTRL
, 6, 3, 3, 0),
572 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM
, 0, 0,
573 &aic3x_left_line_mixer_controls
[0],
574 ARRAY_SIZE(aic3x_left_line_mixer_controls
)),
575 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM
, 0, 0,
576 &aic3x_right_line_mixer_controls
[0],
577 ARRAY_SIZE(aic3x_right_line_mixer_controls
)),
578 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM
, 0, 0,
579 &aic3x_mono_mixer_controls
[0],
580 ARRAY_SIZE(aic3x_mono_mixer_controls
)),
581 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM
, 0, 0,
582 &aic3x_left_hp_mixer_controls
[0],
583 ARRAY_SIZE(aic3x_left_hp_mixer_controls
)),
584 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM
, 0, 0,
585 &aic3x_right_hp_mixer_controls
[0],
586 ARRAY_SIZE(aic3x_right_hp_mixer_controls
)),
587 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM
, 0, 0,
588 &aic3x_left_hpcom_mixer_controls
[0],
589 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls
)),
590 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM
, 0, 0,
591 &aic3x_right_hpcom_mixer_controls
[0],
592 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls
)),
594 SND_SOC_DAPM_OUTPUT("LLOUT"),
595 SND_SOC_DAPM_OUTPUT("RLOUT"),
596 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
597 SND_SOC_DAPM_OUTPUT("HPLOUT"),
598 SND_SOC_DAPM_OUTPUT("HPROUT"),
599 SND_SOC_DAPM_OUTPUT("HPLCOM"),
600 SND_SOC_DAPM_OUTPUT("HPRCOM"),
602 SND_SOC_DAPM_INPUT("MIC3L"),
603 SND_SOC_DAPM_INPUT("MIC3R"),
604 SND_SOC_DAPM_INPUT("LINE1L"),
605 SND_SOC_DAPM_INPUT("LINE1R"),
606 SND_SOC_DAPM_INPUT("LINE2L"),
607 SND_SOC_DAPM_INPUT("LINE2R"),
610 * Virtual output pin to detection block inside codec. This can be
611 * used to keep codec bias on if gpio or detection features are needed.
612 * Force pin on or construct a path with an input jack and mic bias
615 SND_SOC_DAPM_OUTPUT("Detection"),
618 static const struct snd_soc_dapm_widget aic3007_dapm_widgets
[] = {
619 /* Class-D outputs */
620 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL
, 3, 0, NULL
, 0),
621 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL
, 2, 0, NULL
, 0),
623 SND_SOC_DAPM_OUTPUT("SPOP"),
624 SND_SOC_DAPM_OUTPUT("SPOM"),
627 static const struct snd_soc_dapm_route intercon
[] = {
629 {"Left Line1L Mux", "single-ended", "LINE1L"},
630 {"Left Line1L Mux", "differential", "LINE1L"},
632 {"Left Line2L Mux", "single-ended", "LINE2L"},
633 {"Left Line2L Mux", "differential", "LINE2L"},
635 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
636 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
637 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
638 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
639 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
641 {"Left ADC", NULL
, "Left PGA Mixer"},
642 {"Left ADC", NULL
, "GPIO1 dmic modclk"},
645 {"Right Line1R Mux", "single-ended", "LINE1R"},
646 {"Right Line1R Mux", "differential", "LINE1R"},
648 {"Right Line2R Mux", "single-ended", "LINE2R"},
649 {"Right Line2R Mux", "differential", "LINE2R"},
651 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
652 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
653 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
654 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
655 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
657 {"Right ADC", NULL
, "Right PGA Mixer"},
658 {"Right ADC", NULL
, "GPIO1 dmic modclk"},
661 * Logical path between digital mic enable and GPIO1 modulator clock
664 {"GPIO1 dmic modclk", NULL
, "DMic Rate 128"},
665 {"GPIO1 dmic modclk", NULL
, "DMic Rate 64"},
666 {"GPIO1 dmic modclk", NULL
, "DMic Rate 32"},
668 /* Left DAC Output */
669 {"Left DAC Mux", "DAC_L1", "Left DAC"},
670 {"Left DAC Mux", "DAC_L2", "Left DAC"},
671 {"Left DAC Mux", "DAC_L3", "Left DAC"},
673 /* Right DAC Output */
674 {"Right DAC Mux", "DAC_R1", "Right DAC"},
675 {"Right DAC Mux", "DAC_R2", "Right DAC"},
676 {"Right DAC Mux", "DAC_R3", "Right DAC"},
678 /* Left Line Output */
679 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
680 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
681 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
682 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
683 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
684 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
686 {"Left Line Out", NULL
, "Left Line Mixer"},
687 {"Left Line Out", NULL
, "Left DAC Mux"},
688 {"LLOUT", NULL
, "Left Line Out"},
690 /* Right Line Output */
691 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
692 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
693 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
694 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
695 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
696 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
698 {"Right Line Out", NULL
, "Right Line Mixer"},
699 {"Right Line Out", NULL
, "Right DAC Mux"},
700 {"RLOUT", NULL
, "Right Line Out"},
703 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
704 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
705 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
706 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
707 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
708 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
710 {"Mono Out", NULL
, "Mono Mixer"},
711 {"MONO_LOUT", NULL
, "Mono Out"},
714 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
715 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
716 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
717 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
718 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
719 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
721 {"Left HP Out", NULL
, "Left HP Mixer"},
722 {"Left HP Out", NULL
, "Left DAC Mux"},
723 {"HPLOUT", NULL
, "Left HP Out"},
725 /* Right HP Output */
726 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
727 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
728 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
729 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
730 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
731 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
733 {"Right HP Out", NULL
, "Right HP Mixer"},
734 {"Right HP Out", NULL
, "Right DAC Mux"},
735 {"HPROUT", NULL
, "Right HP Out"},
737 /* Left HPCOM Output */
738 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
739 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
740 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
741 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
742 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
743 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
745 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
746 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
747 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
748 {"Left HP Com", NULL
, "Left HPCOM Mux"},
749 {"HPLCOM", NULL
, "Left HP Com"},
751 /* Right HPCOM Output */
752 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
753 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
754 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
755 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
756 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
757 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
759 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
760 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
761 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
762 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
763 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
764 {"Right HP Com", NULL
, "Right HPCOM Mux"},
765 {"HPRCOM", NULL
, "Right HP Com"},
768 static const struct snd_soc_dapm_route intercon_3007
[] = {
769 /* Class-D outputs */
770 {"Left Class-D Out", NULL
, "Left Line Out"},
771 {"Right Class-D Out", NULL
, "Left Line Out"},
772 {"SPOP", NULL
, "Left Class-D Out"},
773 {"SPOM", NULL
, "Right Class-D Out"},
776 static int aic3x_add_widgets(struct snd_soc_codec
*codec
)
778 struct aic3x_priv
*aic3x
= snd_soc_codec_get_drvdata(codec
);
780 snd_soc_dapm_new_controls(codec
, aic3x_dapm_widgets
,
781 ARRAY_SIZE(aic3x_dapm_widgets
));
783 /* set up audio path interconnects */
784 snd_soc_dapm_add_routes(codec
, intercon
, ARRAY_SIZE(intercon
));
786 if (aic3x
->model
== AIC3X_MODEL_3007
) {
787 snd_soc_dapm_new_controls(codec
, aic3007_dapm_widgets
,
788 ARRAY_SIZE(aic3007_dapm_widgets
));
789 snd_soc_dapm_add_routes(codec
, intercon_3007
, ARRAY_SIZE(intercon_3007
));
795 static int aic3x_hw_params(struct snd_pcm_substream
*substream
,
796 struct snd_pcm_hw_params
*params
,
797 struct snd_soc_dai
*dai
)
799 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
800 struct snd_soc_codec
*codec
=rtd
->codec
;
801 struct aic3x_priv
*aic3x
= snd_soc_codec_get_drvdata(codec
);
802 int codec_clk
= 0, bypass_pll
= 0, fsref
, last_clk
= 0;
803 u8 data
, j
, r
, p
, pll_q
, pll_p
= 1, pll_r
= 1, pll_j
= 1;
808 /* select data word length */
809 data
= snd_soc_read(codec
, AIC3X_ASD_INTF_CTRLB
) & (~(0x3 << 4));
810 switch (params_format(params
)) {
811 case SNDRV_PCM_FORMAT_S16_LE
:
813 case SNDRV_PCM_FORMAT_S20_3LE
:
816 case SNDRV_PCM_FORMAT_S24_LE
:
819 case SNDRV_PCM_FORMAT_S32_LE
:
823 snd_soc_write(codec
, AIC3X_ASD_INTF_CTRLB
, data
);
825 /* Fsref can be 44100 or 48000 */
826 fsref
= (params_rate(params
) % 11025 == 0) ? 44100 : 48000;
828 /* Try to find a value for Q which allows us to bypass the PLL and
829 * generate CODEC_CLK directly. */
830 for (pll_q
= 2; pll_q
< 18; pll_q
++)
831 if (aic3x
->sysclk
/ (128 * pll_q
) == fsref
) {
838 snd_soc_write(codec
, AIC3X_PLL_PROGA_REG
, pll_q
<< PLLQ_SHIFT
);
839 snd_soc_write(codec
, AIC3X_GPIOB_REG
, CODEC_CLKIN_CLKDIV
);
840 /* disable PLL if it is bypassed */
841 reg
= snd_soc_read(codec
, AIC3X_PLL_PROGA_REG
);
842 snd_soc_write(codec
, AIC3X_PLL_PROGA_REG
, reg
& ~PLL_ENABLE
);
845 snd_soc_write(codec
, AIC3X_GPIOB_REG
, CODEC_CLKIN_PLLDIV
);
846 /* enable PLL when it is used */
847 reg
= snd_soc_read(codec
, AIC3X_PLL_PROGA_REG
);
848 snd_soc_write(codec
, AIC3X_PLL_PROGA_REG
, reg
| PLL_ENABLE
);
851 /* Route Left DAC to left channel input and
852 * right DAC to right channel input */
853 data
= (LDAC2LCH
| RDAC2RCH
);
854 data
|= (fsref
== 44100) ? FSREF_44100
: FSREF_48000
;
855 if (params_rate(params
) >= 64000)
856 data
|= DUAL_RATE_MODE
;
857 snd_soc_write(codec
, AIC3X_CODEC_DATAPATH_REG
, data
);
859 /* codec sample rate select */
860 data
= (fsref
* 20) / params_rate(params
);
861 if (params_rate(params
) < 64000)
866 snd_soc_write(codec
, AIC3X_SAMPLE_RATE_SEL_REG
, data
);
871 /* Use PLL, compute apropriate setup for j, d, r and p, the closest
872 * one wins the game. Try with d==0 first, next with d!=0.
873 * Constraints for j are according to the datasheet.
874 * The sysclk is divided by 1000 to prevent integer overflows.
877 codec_clk
= (2048 * fsref
) / (aic3x
->sysclk
/ 1000);
879 for (r
= 1; r
<= 16; r
++)
880 for (p
= 1; p
<= 8; p
++) {
881 for (j
= 4; j
<= 55; j
++) {
882 /* This is actually 1000*((j+(d/10000))*r)/p
883 * The term had to be converted to get
884 * rid of the division by 10000; d = 0 here
886 int tmp_clk
= (1000 * j
* r
) / p
;
888 /* Check whether this values get closer than
889 * the best ones we had before
891 if (abs(codec_clk
- tmp_clk
) <
892 abs(codec_clk
- last_clk
)) {
893 pll_j
= j
; pll_d
= 0;
894 pll_r
= r
; pll_p
= p
;
898 /* Early exit for exact matches */
899 if (tmp_clk
== codec_clk
)
904 /* try with d != 0 */
905 for (p
= 1; p
<= 8; p
++) {
906 j
= codec_clk
* p
/ 1000;
911 /* do not use codec_clk here since we'd loose precision */
912 d
= ((2048 * p
* fsref
) - j
* aic3x
->sysclk
)
913 * 100 / (aic3x
->sysclk
/100);
915 clk
= (10000 * j
+ d
) / (10 * p
);
917 /* check whether this values get closer than the best
918 * ones we had before */
919 if (abs(codec_clk
- clk
) < abs(codec_clk
- last_clk
)) {
920 pll_j
= j
; pll_d
= d
; pll_r
= 1; pll_p
= p
;
924 /* Early exit for exact matches */
925 if (clk
== codec_clk
)
930 printk(KERN_ERR
"%s(): unable to setup PLL\n", __func__
);
935 data
= snd_soc_read(codec
, AIC3X_PLL_PROGA_REG
);
936 snd_soc_write(codec
, AIC3X_PLL_PROGA_REG
,
937 data
| (pll_p
<< PLLP_SHIFT
));
938 snd_soc_write(codec
, AIC3X_OVRF_STATUS_AND_PLLR_REG
,
939 pll_r
<< PLLR_SHIFT
);
940 snd_soc_write(codec
, AIC3X_PLL_PROGB_REG
, pll_j
<< PLLJ_SHIFT
);
941 snd_soc_write(codec
, AIC3X_PLL_PROGC_REG
,
942 (pll_d
>> 6) << PLLD_MSB_SHIFT
);
943 snd_soc_write(codec
, AIC3X_PLL_PROGD_REG
,
944 (pll_d
& 0x3F) << PLLD_LSB_SHIFT
);
949 static int aic3x_mute(struct snd_soc_dai
*dai
, int mute
)
951 struct snd_soc_codec
*codec
= dai
->codec
;
952 u8 ldac_reg
= snd_soc_read(codec
, LDAC_VOL
) & ~MUTE_ON
;
953 u8 rdac_reg
= snd_soc_read(codec
, RDAC_VOL
) & ~MUTE_ON
;
956 snd_soc_write(codec
, LDAC_VOL
, ldac_reg
| MUTE_ON
);
957 snd_soc_write(codec
, RDAC_VOL
, rdac_reg
| MUTE_ON
);
959 snd_soc_write(codec
, LDAC_VOL
, ldac_reg
);
960 snd_soc_write(codec
, RDAC_VOL
, rdac_reg
);
966 static int aic3x_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
967 int clk_id
, unsigned int freq
, int dir
)
969 struct snd_soc_codec
*codec
= codec_dai
->codec
;
970 struct aic3x_priv
*aic3x
= snd_soc_codec_get_drvdata(codec
);
972 aic3x
->sysclk
= freq
;
976 static int aic3x_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
979 struct snd_soc_codec
*codec
= codec_dai
->codec
;
980 struct aic3x_priv
*aic3x
= snd_soc_codec_get_drvdata(codec
);
981 u8 iface_areg
, iface_breg
;
984 iface_areg
= snd_soc_read(codec
, AIC3X_ASD_INTF_CTRLA
) & 0x3f;
985 iface_breg
= snd_soc_read(codec
, AIC3X_ASD_INTF_CTRLB
) & 0x3f;
987 /* set master/slave audio interface */
988 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
989 case SND_SOC_DAIFMT_CBM_CFM
:
991 iface_areg
|= BIT_CLK_MASTER
| WORD_CLK_MASTER
;
993 case SND_SOC_DAIFMT_CBS_CFS
:
1001 * match both interface format and signal polarities since they
1004 switch (fmt
& (SND_SOC_DAIFMT_FORMAT_MASK
|
1005 SND_SOC_DAIFMT_INV_MASK
)) {
1006 case (SND_SOC_DAIFMT_I2S
| SND_SOC_DAIFMT_NB_NF
):
1008 case (SND_SOC_DAIFMT_DSP_A
| SND_SOC_DAIFMT_IB_NF
):
1010 case (SND_SOC_DAIFMT_DSP_B
| SND_SOC_DAIFMT_IB_NF
):
1011 iface_breg
|= (0x01 << 6);
1013 case (SND_SOC_DAIFMT_RIGHT_J
| SND_SOC_DAIFMT_NB_NF
):
1014 iface_breg
|= (0x02 << 6);
1016 case (SND_SOC_DAIFMT_LEFT_J
| SND_SOC_DAIFMT_NB_NF
):
1017 iface_breg
|= (0x03 << 6);
1024 snd_soc_write(codec
, AIC3X_ASD_INTF_CTRLA
, iface_areg
);
1025 snd_soc_write(codec
, AIC3X_ASD_INTF_CTRLB
, iface_breg
);
1026 snd_soc_write(codec
, AIC3X_ASD_INTF_CTRLC
, delay
);
1031 static int aic3x_set_bias_level(struct snd_soc_codec
*codec
,
1032 enum snd_soc_bias_level level
)
1034 struct aic3x_priv
*aic3x
= snd_soc_codec_get_drvdata(codec
);
1038 case SND_SOC_BIAS_ON
:
1040 case SND_SOC_BIAS_PREPARE
:
1041 if (codec
->bias_level
== SND_SOC_BIAS_STANDBY
&&
1044 reg
= snd_soc_read(codec
, AIC3X_PLL_PROGA_REG
);
1045 snd_soc_write(codec
, AIC3X_PLL_PROGA_REG
,
1049 case SND_SOC_BIAS_STANDBY
:
1050 if (codec
->bias_level
== SND_SOC_BIAS_PREPARE
&&
1053 reg
= snd_soc_read(codec
, AIC3X_PLL_PROGA_REG
);
1054 snd_soc_write(codec
, AIC3X_PLL_PROGA_REG
,
1058 case SND_SOC_BIAS_OFF
:
1061 codec
->bias_level
= level
;
1066 void aic3x_set_gpio(struct snd_soc_codec
*codec
, int gpio
, int state
)
1068 u8 reg
= gpio
? AIC3X_GPIO2_REG
: AIC3X_GPIO1_REG
;
1069 u8 bit
= gpio
? 3: 0;
1070 u8 val
= snd_soc_read(codec
, reg
) & ~(1 << bit
);
1071 snd_soc_write(codec
, reg
, val
| (!!state
<< bit
));
1073 EXPORT_SYMBOL_GPL(aic3x_set_gpio
);
1075 int aic3x_get_gpio(struct snd_soc_codec
*codec
, int gpio
)
1077 u8 reg
= gpio
? AIC3X_GPIO2_REG
: AIC3X_GPIO1_REG
;
1078 u8 val
, bit
= gpio
? 2: 1;
1080 aic3x_read(codec
, reg
, &val
);
1081 return (val
>> bit
) & 1;
1083 EXPORT_SYMBOL_GPL(aic3x_get_gpio
);
1085 void aic3x_set_headset_detection(struct snd_soc_codec
*codec
, int detect
,
1086 int headset_debounce
, int button_debounce
)
1090 val
= ((detect
& AIC3X_HEADSET_DETECT_MASK
)
1091 << AIC3X_HEADSET_DETECT_SHIFT
) |
1092 ((headset_debounce
& AIC3X_HEADSET_DEBOUNCE_MASK
)
1093 << AIC3X_HEADSET_DEBOUNCE_SHIFT
) |
1094 ((button_debounce
& AIC3X_BUTTON_DEBOUNCE_MASK
)
1095 << AIC3X_BUTTON_DEBOUNCE_SHIFT
);
1097 if (detect
& AIC3X_HEADSET_DETECT_MASK
)
1098 val
|= AIC3X_HEADSET_DETECT_ENABLED
;
1100 snd_soc_write(codec
, AIC3X_HEADSET_DETECT_CTRL_A
, val
);
1102 EXPORT_SYMBOL_GPL(aic3x_set_headset_detection
);
1104 int aic3x_headset_detected(struct snd_soc_codec
*codec
)
1107 aic3x_read(codec
, AIC3X_HEADSET_DETECT_CTRL_B
, &val
);
1108 return (val
>> 4) & 1;
1110 EXPORT_SYMBOL_GPL(aic3x_headset_detected
);
1112 int aic3x_button_pressed(struct snd_soc_codec
*codec
)
1115 aic3x_read(codec
, AIC3X_HEADSET_DETECT_CTRL_B
, &val
);
1116 return (val
>> 5) & 1;
1118 EXPORT_SYMBOL_GPL(aic3x_button_pressed
);
1120 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1121 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1122 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1124 static struct snd_soc_dai_ops aic3x_dai_ops
= {
1125 .hw_params
= aic3x_hw_params
,
1126 .digital_mute
= aic3x_mute
,
1127 .set_sysclk
= aic3x_set_dai_sysclk
,
1128 .set_fmt
= aic3x_set_dai_fmt
,
1131 static struct snd_soc_dai_driver aic3x_dai
= {
1132 .name
= "tlv320aic3x-hifi",
1134 .stream_name
= "Playback",
1137 .rates
= AIC3X_RATES
,
1138 .formats
= AIC3X_FORMATS
,},
1140 .stream_name
= "Capture",
1143 .rates
= AIC3X_RATES
,
1144 .formats
= AIC3X_FORMATS
,},
1145 .ops
= &aic3x_dai_ops
,
1146 .symmetric_rates
= 1,
1149 static int aic3x_suspend(struct snd_soc_codec
*codec
, pm_message_t state
)
1151 aic3x_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1156 static int aic3x_resume(struct snd_soc_codec
*codec
)
1160 u8
*cache
= codec
->reg_cache
;
1162 /* Sync reg_cache with the hardware */
1163 for (i
= 0; i
< ARRAY_SIZE(aic3x_reg
); i
++) {
1166 codec
->hw_write(codec
->control_data
, data
, 2);
1169 aic3x_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1175 * initialise the AIC3X driver
1176 * register the mixer and dsp interfaces with the kernel
1178 static int aic3x_init(struct snd_soc_codec
*codec
)
1180 struct aic3x_priv
*aic3x
= snd_soc_codec_get_drvdata(codec
);
1183 snd_soc_write(codec
, AIC3X_PAGE_SELECT
, PAGE0_SELECT
);
1184 snd_soc_write(codec
, AIC3X_RESET
, SOFT_RESET
);
1186 /* DAC default volume and mute */
1187 snd_soc_write(codec
, LDAC_VOL
, DEFAULT_VOL
| MUTE_ON
);
1188 snd_soc_write(codec
, RDAC_VOL
, DEFAULT_VOL
| MUTE_ON
);
1190 /* DAC to HP default volume and route to Output mixer */
1191 snd_soc_write(codec
, DACL1_2_HPLOUT_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1192 snd_soc_write(codec
, DACR1_2_HPROUT_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1193 snd_soc_write(codec
, DACL1_2_HPLCOM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1194 snd_soc_write(codec
, DACR1_2_HPRCOM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1195 /* DAC to Line Out default volume and route to Output mixer */
1196 snd_soc_write(codec
, DACL1_2_LLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1197 snd_soc_write(codec
, DACR1_2_RLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1198 /* DAC to Mono Line Out default volume and route to Output mixer */
1199 snd_soc_write(codec
, DACL1_2_MONOLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1200 snd_soc_write(codec
, DACR1_2_MONOLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1202 /* unmute all outputs */
1203 reg
= snd_soc_read(codec
, LLOPM_CTRL
);
1204 snd_soc_write(codec
, LLOPM_CTRL
, reg
| UNMUTE
);
1205 reg
= snd_soc_read(codec
, RLOPM_CTRL
);
1206 snd_soc_write(codec
, RLOPM_CTRL
, reg
| UNMUTE
);
1207 reg
= snd_soc_read(codec
, MONOLOPM_CTRL
);
1208 snd_soc_write(codec
, MONOLOPM_CTRL
, reg
| UNMUTE
);
1209 reg
= snd_soc_read(codec
, HPLOUT_CTRL
);
1210 snd_soc_write(codec
, HPLOUT_CTRL
, reg
| UNMUTE
);
1211 reg
= snd_soc_read(codec
, HPROUT_CTRL
);
1212 snd_soc_write(codec
, HPROUT_CTRL
, reg
| UNMUTE
);
1213 reg
= snd_soc_read(codec
, HPLCOM_CTRL
);
1214 snd_soc_write(codec
, HPLCOM_CTRL
, reg
| UNMUTE
);
1215 reg
= snd_soc_read(codec
, HPRCOM_CTRL
);
1216 snd_soc_write(codec
, HPRCOM_CTRL
, reg
| UNMUTE
);
1218 /* ADC default volume and unmute */
1219 snd_soc_write(codec
, LADC_VOL
, DEFAULT_GAIN
);
1220 snd_soc_write(codec
, RADC_VOL
, DEFAULT_GAIN
);
1221 /* By default route Line1 to ADC PGA mixer */
1222 snd_soc_write(codec
, LINE1L_2_LADC_CTRL
, 0x0);
1223 snd_soc_write(codec
, LINE1R_2_RADC_CTRL
, 0x0);
1225 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1226 snd_soc_write(codec
, PGAL_2_HPLOUT_VOL
, DEFAULT_VOL
);
1227 snd_soc_write(codec
, PGAR_2_HPROUT_VOL
, DEFAULT_VOL
);
1228 snd_soc_write(codec
, PGAL_2_HPLCOM_VOL
, DEFAULT_VOL
);
1229 snd_soc_write(codec
, PGAR_2_HPRCOM_VOL
, DEFAULT_VOL
);
1230 /* PGA to Line Out default volume, disconnect from Output Mixer */
1231 snd_soc_write(codec
, PGAL_2_LLOPM_VOL
, DEFAULT_VOL
);
1232 snd_soc_write(codec
, PGAR_2_RLOPM_VOL
, DEFAULT_VOL
);
1233 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1234 snd_soc_write(codec
, PGAL_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1235 snd_soc_write(codec
, PGAR_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1237 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1238 snd_soc_write(codec
, LINE2L_2_HPLOUT_VOL
, DEFAULT_VOL
);
1239 snd_soc_write(codec
, LINE2R_2_HPROUT_VOL
, DEFAULT_VOL
);
1240 snd_soc_write(codec
, LINE2L_2_HPLCOM_VOL
, DEFAULT_VOL
);
1241 snd_soc_write(codec
, LINE2R_2_HPRCOM_VOL
, DEFAULT_VOL
);
1242 /* Line2 Line Out default volume, disconnect from Output Mixer */
1243 snd_soc_write(codec
, LINE2L_2_LLOPM_VOL
, DEFAULT_VOL
);
1244 snd_soc_write(codec
, LINE2R_2_RLOPM_VOL
, DEFAULT_VOL
);
1245 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1246 snd_soc_write(codec
, LINE2L_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1247 snd_soc_write(codec
, LINE2R_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1249 if (aic3x
->model
== AIC3X_MODEL_3007
) {
1250 /* Class-D speaker driver init; datasheet p. 46 */
1251 snd_soc_write(codec
, AIC3X_PAGE_SELECT
, 0x0D);
1252 snd_soc_write(codec
, 0xD, 0x0D);
1253 snd_soc_write(codec
, 0x8, 0x5C);
1254 snd_soc_write(codec
, 0x8, 0x5D);
1255 snd_soc_write(codec
, 0x8, 0x5C);
1256 snd_soc_write(codec
, AIC3X_PAGE_SELECT
, 0x00);
1257 snd_soc_write(codec
, CLASSD_CTRL
, 0);
1260 /* off, with power on */
1261 aic3x_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1266 static int aic3x_probe(struct snd_soc_codec
*codec
)
1268 struct aic3x_priv
*aic3x
= snd_soc_codec_get_drvdata(codec
);
1271 codec
->control_data
= aic3x
->control_data
;
1273 ret
= snd_soc_codec_set_cache_io(codec
, 8, 8, aic3x
->control_type
);
1275 dev_err(codec
->dev
, "Failed to set cache I/O: %d\n", ret
);
1282 /* setup GPIO functions */
1283 snd_soc_write(codec
, AIC3X_GPIO1_REG
,
1284 (aic3x
->setup
->gpio_func
[0] & 0xf) << 4);
1285 snd_soc_write(codec
, AIC3X_GPIO2_REG
,
1286 (aic3x
->setup
->gpio_func
[1] & 0xf) << 4);
1289 snd_soc_add_controls(codec
, aic3x_snd_controls
,
1290 ARRAY_SIZE(aic3x_snd_controls
));
1291 if (aic3x
->model
== AIC3X_MODEL_3007
)
1292 snd_soc_add_controls(codec
, &aic3x_classd_amp_gain_ctrl
, 1);
1294 aic3x_add_widgets(codec
);
1299 static int aic3x_remove(struct snd_soc_codec
*codec
)
1301 aic3x_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1305 static struct snd_soc_codec_driver soc_codec_dev_aic3x
= {
1306 .set_bias_level
= aic3x_set_bias_level
,
1307 .reg_cache_size
= ARRAY_SIZE(aic3x_reg
),
1308 .reg_word_size
= sizeof(u8
),
1309 .reg_cache_default
= aic3x_reg
,
1310 .probe
= aic3x_probe
,
1311 .remove
= aic3x_remove
,
1312 .suspend
= aic3x_suspend
,
1313 .resume
= aic3x_resume
,
1316 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1318 * AIC3X 2 wire address can be up to 4 devices with device addresses
1319 * 0x18, 0x19, 0x1A, 0x1B
1322 static const struct i2c_device_id aic3x_i2c_id
[] = {
1323 [AIC3X_MODEL_3X
] = { "tlv320aic3x", 0 },
1324 [AIC3X_MODEL_33
] = { "tlv320aic33", 0 },
1325 [AIC3X_MODEL_3007
] = { "tlv320aic3007", 0 },
1328 MODULE_DEVICE_TABLE(i2c
, aic3x_i2c_id
);
1331 * If the i2c layer weren't so broken, we could pass this kind of data
1334 static int aic3x_i2c_probe(struct i2c_client
*i2c
,
1335 const struct i2c_device_id
*id
)
1337 struct aic3x_pdata
*pdata
= i2c
->dev
.platform_data
;
1338 struct aic3x_priv
*aic3x
;
1340 const struct i2c_device_id
*tbl
;
1342 aic3x
= kzalloc(sizeof(struct aic3x_priv
), GFP_KERNEL
);
1343 if (aic3x
== NULL
) {
1344 dev_err(&i2c
->dev
, "failed to create private data\n");
1348 aic3x
->control_data
= i2c
;
1349 aic3x
->control_type
= SND_SOC_I2C
;
1351 i2c_set_clientdata(i2c
, aic3x
);
1353 aic3x
->gpio_reset
= pdata
->gpio_reset
;
1354 aic3x
->setup
= pdata
->setup
;
1356 aic3x
->gpio_reset
= -1;
1359 if (aic3x
->gpio_reset
>= 0) {
1360 ret
= gpio_request(aic3x
->gpio_reset
, "tlv320aic3x reset");
1363 gpio_direction_output(aic3x
->gpio_reset
, 0);
1366 for (tbl
= aic3x_i2c_id
; tbl
->name
[0]; tbl
++) {
1367 if (!strcmp(tbl
->name
, id
->name
))
1370 aic3x
->model
= tbl
- aic3x_i2c_id
;
1372 for (i
= 0; i
< ARRAY_SIZE(aic3x
->supplies
); i
++)
1373 aic3x
->supplies
[i
].supply
= aic3x_supply_names
[i
];
1375 ret
= regulator_bulk_get(&i2c
->dev
, ARRAY_SIZE(aic3x
->supplies
),
1378 dev_err(&i2c
->dev
, "Failed to request supplies: %d\n", ret
);
1382 ret
= regulator_bulk_enable(ARRAY_SIZE(aic3x
->supplies
),
1385 dev_err(&i2c
->dev
, "Failed to enable supplies: %d\n", ret
);
1389 if (aic3x
->gpio_reset
>= 0) {
1391 gpio_set_value(aic3x
->gpio_reset
, 1);
1394 ret
= snd_soc_register_codec(&i2c
->dev
,
1395 &soc_codec_dev_aic3x
, &aic3x_dai
, 1);
1401 regulator_bulk_free(ARRAY_SIZE(aic3x
->supplies
), aic3x
->supplies
);
1403 if (aic3x
->gpio_reset
>= 0)
1404 gpio_free(aic3x
->gpio_reset
);
1410 static int aic3x_i2c_remove(struct i2c_client
*client
)
1412 struct aic3x_priv
*aic3x
= i2c_get_clientdata(client
);
1414 if (aic3x
->gpio_reset
>= 0) {
1415 gpio_set_value(aic3x
->gpio_reset
, 0);
1416 gpio_free(aic3x
->gpio_reset
);
1418 regulator_bulk_disable(ARRAY_SIZE(aic3x
->supplies
), aic3x
->supplies
);
1419 regulator_bulk_free(ARRAY_SIZE(aic3x
->supplies
), aic3x
->supplies
);
1421 snd_soc_unregister_codec(&client
->dev
);
1422 kfree(i2c_get_clientdata(client
));
1426 /* machine i2c codec control layer */
1427 static struct i2c_driver aic3x_i2c_driver
= {
1429 .name
= "tlv320aic3x-codec",
1430 .owner
= THIS_MODULE
,
1432 .probe
= aic3x_i2c_probe
,
1433 .remove
= aic3x_i2c_remove
,
1434 .id_table
= aic3x_i2c_id
,
1437 static inline void aic3x_i2c_init(void)
1441 ret
= i2c_add_driver(&aic3x_i2c_driver
);
1443 printk(KERN_ERR
"%s: error regsitering i2c driver, %d\n",
1447 static inline void aic3x_i2c_exit(void)
1449 i2c_del_driver(&aic3x_i2c_driver
);
1453 static int __init
aic3x_modinit(void)
1456 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1457 ret
= i2c_add_driver(&aic3x_i2c_driver
);
1459 printk(KERN_ERR
"Failed to register TLV320AIC3x I2C driver: %d\n",
1465 module_init(aic3x_modinit
);
1467 static void __exit
aic3x_exit(void)
1469 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1470 i2c_del_driver(&aic3x_i2c_driver
);
1473 module_exit(aic3x_exit
);
1475 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1476 MODULE_AUTHOR("Vladimir Barinov");
1477 MODULE_LICENSE("GPL");