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ALSA: ASoC: Fix some minor errors in mpc5200 psc i2s driver
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / tlv320aic3x.c
1 /*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33.
16 *
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 is as follows:
19 * aic32 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
33 */
34
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/pm.h>
40 #include <linux/i2c.h>
41 #include <linux/platform_device.h>
42 #include <sound/core.h>
43 #include <sound/pcm.h>
44 #include <sound/pcm_params.h>
45 #include <sound/soc.h>
46 #include <sound/soc-dapm.h>
47 #include <sound/initval.h>
48
49 #include "tlv320aic3x.h"
50
51 #define AIC3X_VERSION "0.2"
52
53 /* codec private data */
54 struct aic3x_priv {
55 unsigned int sysclk;
56 int master;
57 };
58
59 /*
60 * AIC3X register cache
61 * We can't read the AIC3X register space when we are
62 * using 2 wire for device control, so we cache them instead.
63 * There is no point in caching the reset register
64 */
65 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
66 0x00, 0x00, 0x00, 0x10, /* 0 */
67 0x04, 0x00, 0x00, 0x00, /* 4 */
68 0x00, 0x00, 0x00, 0x01, /* 8 */
69 0x00, 0x00, 0x00, 0x80, /* 12 */
70 0x80, 0xff, 0xff, 0x78, /* 16 */
71 0x78, 0x78, 0x78, 0x78, /* 20 */
72 0x78, 0x00, 0x00, 0xfe, /* 24 */
73 0x00, 0x00, 0xfe, 0x00, /* 28 */
74 0x18, 0x18, 0x00, 0x00, /* 32 */
75 0x00, 0x00, 0x00, 0x00, /* 36 */
76 0x00, 0x00, 0x00, 0x80, /* 40 */
77 0x80, 0x00, 0x00, 0x00, /* 44 */
78 0x00, 0x00, 0x00, 0x04, /* 48 */
79 0x00, 0x00, 0x00, 0x00, /* 52 */
80 0x00, 0x00, 0x04, 0x00, /* 56 */
81 0x00, 0x00, 0x00, 0x00, /* 60 */
82 0x00, 0x04, 0x00, 0x00, /* 64 */
83 0x00, 0x00, 0x00, 0x00, /* 68 */
84 0x04, 0x00, 0x00, 0x00, /* 72 */
85 0x00, 0x00, 0x00, 0x00, /* 76 */
86 0x00, 0x00, 0x00, 0x00, /* 80 */
87 0x00, 0x00, 0x00, 0x00, /* 84 */
88 0x00, 0x00, 0x00, 0x00, /* 88 */
89 0x00, 0x00, 0x00, 0x00, /* 92 */
90 0x00, 0x00, 0x00, 0x00, /* 96 */
91 0x00, 0x00, 0x02, /* 100 */
92 };
93
94 /*
95 * read aic3x register cache
96 */
97 static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
98 unsigned int reg)
99 {
100 u8 *cache = codec->reg_cache;
101 if (reg >= AIC3X_CACHEREGNUM)
102 return -1;
103 return cache[reg];
104 }
105
106 /*
107 * write aic3x register cache
108 */
109 static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
110 u8 reg, u8 value)
111 {
112 u8 *cache = codec->reg_cache;
113 if (reg >= AIC3X_CACHEREGNUM)
114 return;
115 cache[reg] = value;
116 }
117
118 /*
119 * write to the aic3x register space
120 */
121 static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg,
122 unsigned int value)
123 {
124 u8 data[2];
125
126 /* data is
127 * D15..D8 aic3x register offset
128 * D7...D0 register data
129 */
130 data[0] = reg & 0xff;
131 data[1] = value & 0xff;
132
133 aic3x_write_reg_cache(codec, data[0], data[1]);
134 if (codec->hw_write(codec->control_data, data, 2) == 2)
135 return 0;
136 else
137 return -EIO;
138 }
139
140 /*
141 * read from the aic3x register space
142 */
143 static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
144 u8 *value)
145 {
146 *value = reg & 0xff;
147 if (codec->hw_read(codec->control_data, value, 1) != 1)
148 return -EIO;
149
150 aic3x_write_reg_cache(codec, reg, *value);
151 return 0;
152 }
153
154 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
155 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
156 .info = snd_soc_info_volsw, \
157 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
158 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
159
160 /*
161 * All input lines are connected when !0xf and disconnected with 0xf bit field,
162 * so we have to use specific dapm_put call for input mixer
163 */
164 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
165 struct snd_ctl_elem_value *ucontrol)
166 {
167 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
168 int reg = kcontrol->private_value & 0xff;
169 int shift = (kcontrol->private_value >> 8) & 0x0f;
170 int mask = (kcontrol->private_value >> 16) & 0xff;
171 int invert = (kcontrol->private_value >> 24) & 0x01;
172 unsigned short val, val_mask;
173 int ret;
174 struct snd_soc_dapm_path *path;
175 int found = 0;
176
177 val = (ucontrol->value.integer.value[0] & mask);
178
179 mask = 0xf;
180 if (val)
181 val = mask;
182
183 if (invert)
184 val = mask - val;
185 val_mask = mask << shift;
186 val = val << shift;
187
188 mutex_lock(&widget->codec->mutex);
189
190 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
191 /* find dapm widget path assoc with kcontrol */
192 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
193 if (path->kcontrol != kcontrol)
194 continue;
195
196 /* found, now check type */
197 found = 1;
198 if (val)
199 /* new connection */
200 path->connect = invert ? 0 : 1;
201 else
202 /* old connection must be powered down */
203 path->connect = invert ? 1 : 0;
204 break;
205 }
206
207 if (found)
208 snd_soc_dapm_sync(widget->codec);
209 }
210
211 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
212
213 mutex_unlock(&widget->codec->mutex);
214 return ret;
215 }
216
217 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
218 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
219 static const char *aic3x_left_hpcom_mux[] =
220 { "differential of HPLOUT", "constant VCM", "single-ended" };
221 static const char *aic3x_right_hpcom_mux[] =
222 { "differential of HPROUT", "constant VCM", "single-ended",
223 "differential of HPLCOM", "external feedback" };
224 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
225 static const char *aic3x_adc_hpf[] =
226 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
227
228 #define LDAC_ENUM 0
229 #define RDAC_ENUM 1
230 #define LHPCOM_ENUM 2
231 #define RHPCOM_ENUM 3
232 #define LINE1L_ENUM 4
233 #define LINE1R_ENUM 5
234 #define LINE2L_ENUM 6
235 #define LINE2R_ENUM 7
236 #define ADC_HPF_ENUM 8
237
238 static const struct soc_enum aic3x_enum[] = {
239 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
240 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
241 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
242 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
243 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
244 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
245 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
246 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
247 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
248 };
249
250 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
251 /* Output */
252 SOC_DOUBLE_R("PCM Playback Volume", LDAC_VOL, RDAC_VOL, 0, 0x7f, 1),
253
254 SOC_DOUBLE_R("Line DAC Playback Volume", DACL1_2_LLOPM_VOL,
255 DACR1_2_RLOPM_VOL, 0, 0x7f, 1),
256 SOC_DOUBLE_R("Line DAC Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
257 0x01, 0),
258 SOC_DOUBLE_R("Line PGA Bypass Playback Volume", PGAL_2_LLOPM_VOL,
259 PGAR_2_RLOPM_VOL, 0, 0x7f, 1),
260 SOC_DOUBLE_R("Line Line2 Bypass Playback Volume", LINE2L_2_LLOPM_VOL,
261 LINE2R_2_RLOPM_VOL, 0, 0x7f, 1),
262
263 SOC_DOUBLE_R("Mono DAC Playback Volume", DACL1_2_MONOLOPM_VOL,
264 DACR1_2_MONOLOPM_VOL, 0, 0x7f, 1),
265 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
266 SOC_DOUBLE_R("Mono PGA Bypass Playback Volume", PGAL_2_MONOLOPM_VOL,
267 PGAR_2_MONOLOPM_VOL, 0, 0x7f, 1),
268 SOC_DOUBLE_R("Mono Line2 Bypass Playback Volume", LINE2L_2_MONOLOPM_VOL,
269 LINE2R_2_MONOLOPM_VOL, 0, 0x7f, 1),
270
271 SOC_DOUBLE_R("HP DAC Playback Volume", DACL1_2_HPLOUT_VOL,
272 DACR1_2_HPROUT_VOL, 0, 0x7f, 1),
273 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
274 0x01, 0),
275 SOC_DOUBLE_R("HP PGA Bypass Playback Volume", PGAL_2_HPLOUT_VOL,
276 PGAR_2_HPROUT_VOL, 0, 0x7f, 1),
277 SOC_DOUBLE_R("HP Line2 Bypass Playback Volume", LINE2L_2_HPLOUT_VOL,
278 LINE2R_2_HPROUT_VOL, 0, 0x7f, 1),
279
280 SOC_DOUBLE_R("HPCOM DAC Playback Volume", DACL1_2_HPLCOM_VOL,
281 DACR1_2_HPRCOM_VOL, 0, 0x7f, 1),
282 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
283 0x01, 0),
284 SOC_DOUBLE_R("HPCOM PGA Bypass Playback Volume", PGAL_2_HPLCOM_VOL,
285 PGAR_2_HPRCOM_VOL, 0, 0x7f, 1),
286 SOC_DOUBLE_R("HPCOM Line2 Bypass Playback Volume", LINE2L_2_HPLCOM_VOL,
287 LINE2R_2_HPRCOM_VOL, 0, 0x7f, 1),
288
289 /*
290 * Note: enable Automatic input Gain Controller with care. It can
291 * adjust PGA to max value when ADC is on and will never go back.
292 */
293 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
294
295 /* Input */
296 SOC_DOUBLE_R("PGA Capture Volume", LADC_VOL, RADC_VOL, 0, 0x7f, 0),
297 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
298
299 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
300 };
301
302 /* add non dapm controls */
303 static int aic3x_add_controls(struct snd_soc_codec *codec)
304 {
305 int err, i;
306
307 for (i = 0; i < ARRAY_SIZE(aic3x_snd_controls); i++) {
308 err = snd_ctl_add(codec->card,
309 snd_soc_cnew(&aic3x_snd_controls[i],
310 codec, NULL));
311 if (err < 0)
312 return err;
313 }
314
315 return 0;
316 }
317
318 /* Left DAC Mux */
319 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
320 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
321
322 /* Right DAC Mux */
323 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
324 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
325
326 /* Left HPCOM Mux */
327 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
328 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
329
330 /* Right HPCOM Mux */
331 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
332 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
333
334 /* Left DAC_L1 Mixer */
335 static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = {
336 SOC_DAPM_SINGLE("Line Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
337 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
338 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
339 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
340 };
341
342 /* Right DAC_R1 Mixer */
343 static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = {
344 SOC_DAPM_SINGLE("Line Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
345 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
346 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
347 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
348 };
349
350 /* Left PGA Mixer */
351 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
352 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
353 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
354 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
355 };
356
357 /* Right PGA Mixer */
358 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
359 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
360 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
361 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
362 };
363
364 /* Left Line1 Mux */
365 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
366 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
367
368 /* Right Line1 Mux */
369 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
370 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
371
372 /* Left Line2 Mux */
373 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
374 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
375
376 /* Right Line2 Mux */
377 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
378 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
379
380 /* Left PGA Bypass Mixer */
381 static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = {
382 SOC_DAPM_SINGLE("Line Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
383 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
384 SOC_DAPM_SINGLE("HP Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
385 SOC_DAPM_SINGLE("HPCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
386 };
387
388 /* Right PGA Bypass Mixer */
389 static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = {
390 SOC_DAPM_SINGLE("Line Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
391 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
392 SOC_DAPM_SINGLE("HP Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
393 SOC_DAPM_SINGLE("HPCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
394 };
395
396 /* Left Line2 Bypass Mixer */
397 static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = {
398 SOC_DAPM_SINGLE("Line Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
399 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
400 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
401 SOC_DAPM_SINGLE("HPCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
402 };
403
404 /* Right Line2 Bypass Mixer */
405 static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = {
406 SOC_DAPM_SINGLE("Line Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
407 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
408 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
409 SOC_DAPM_SINGLE("HPCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
410 };
411
412 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
413 /* Left DAC to Left Outputs */
414 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
415 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
416 &aic3x_left_dac_mux_controls),
417 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0,
418 &aic3x_left_dac_mixer_controls[0],
419 ARRAY_SIZE(aic3x_left_dac_mixer_controls)),
420 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
421 &aic3x_left_hpcom_mux_controls),
422 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
423 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
424 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
425
426 /* Right DAC to Right Outputs */
427 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
428 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
429 &aic3x_right_dac_mux_controls),
430 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0,
431 &aic3x_right_dac_mixer_controls[0],
432 ARRAY_SIZE(aic3x_right_dac_mixer_controls)),
433 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
434 &aic3x_right_hpcom_mux_controls),
435 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
436 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
437 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
438
439 /* Mono Output */
440 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
441
442 /* Left Inputs to Left ADC */
443 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
444 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
445 &aic3x_left_pga_mixer_controls[0],
446 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
447 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
448 &aic3x_left_line1_mux_controls),
449 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
450 &aic3x_left_line2_mux_controls),
451
452 /* Right Inputs to Right ADC */
453 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
454 LINE1R_2_RADC_CTRL, 2, 0),
455 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
456 &aic3x_right_pga_mixer_controls[0],
457 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
458 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
459 &aic3x_right_line1_mux_controls),
460 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
461 &aic3x_right_line2_mux_controls),
462
463 /*
464 * Not a real mic bias widget but similar function. This is for dynamic
465 * control of GPIO1 digital mic modulator clock output function when
466 * using digital mic.
467 */
468 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
469 AIC3X_GPIO1_REG, 4, 0xf,
470 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
471 AIC3X_GPIO1_FUNC_DISABLED),
472
473 /*
474 * Also similar function like mic bias. Selects digital mic with
475 * configurable oversampling rate instead of ADC converter.
476 */
477 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
478 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
479 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
480 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
481 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
482 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
483
484 /* Mic Bias */
485 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
486 MICBIAS_CTRL, 6, 3, 1, 0),
487 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
488 MICBIAS_CTRL, 6, 3, 2, 0),
489 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
490 MICBIAS_CTRL, 6, 3, 3, 0),
491
492 /* Left PGA to Left Output bypass */
493 SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
494 &aic3x_left_pga_bp_mixer_controls[0],
495 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)),
496
497 /* Right PGA to Right Output bypass */
498 SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
499 &aic3x_right_pga_bp_mixer_controls[0],
500 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)),
501
502 /* Left Line2 to Left Output bypass */
503 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
504 &aic3x_left_line2_bp_mixer_controls[0],
505 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)),
506
507 /* Right Line2 to Right Output bypass */
508 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
509 &aic3x_right_line2_bp_mixer_controls[0],
510 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)),
511
512 SND_SOC_DAPM_OUTPUT("LLOUT"),
513 SND_SOC_DAPM_OUTPUT("RLOUT"),
514 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
515 SND_SOC_DAPM_OUTPUT("HPLOUT"),
516 SND_SOC_DAPM_OUTPUT("HPROUT"),
517 SND_SOC_DAPM_OUTPUT("HPLCOM"),
518 SND_SOC_DAPM_OUTPUT("HPRCOM"),
519
520 SND_SOC_DAPM_INPUT("MIC3L"),
521 SND_SOC_DAPM_INPUT("MIC3R"),
522 SND_SOC_DAPM_INPUT("LINE1L"),
523 SND_SOC_DAPM_INPUT("LINE1R"),
524 SND_SOC_DAPM_INPUT("LINE2L"),
525 SND_SOC_DAPM_INPUT("LINE2R"),
526 };
527
528 static const struct snd_soc_dapm_route intercon[] = {
529 /* Left Output */
530 {"Left DAC Mux", "DAC_L1", "Left DAC"},
531 {"Left DAC Mux", "DAC_L2", "Left DAC"},
532 {"Left DAC Mux", "DAC_L3", "Left DAC"},
533
534 {"Left DAC_L1 Mixer", "Line Switch", "Left DAC Mux"},
535 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
536 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
537 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
538 {"Left Line Out", NULL, "Left DAC Mux"},
539 {"Left HP Out", NULL, "Left DAC Mux"},
540
541 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
542 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
543 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
544
545 {"Left Line Out", NULL, "Left DAC_L1 Mixer"},
546 {"Mono Out", NULL, "Left DAC_L1 Mixer"},
547 {"Left HP Out", NULL, "Left DAC_L1 Mixer"},
548 {"Left HP Com", NULL, "Left HPCOM Mux"},
549
550 {"LLOUT", NULL, "Left Line Out"},
551 {"LLOUT", NULL, "Left Line Out"},
552 {"HPLOUT", NULL, "Left HP Out"},
553 {"HPLCOM", NULL, "Left HP Com"},
554
555 /* Right Output */
556 {"Right DAC Mux", "DAC_R1", "Right DAC"},
557 {"Right DAC Mux", "DAC_R2", "Right DAC"},
558 {"Right DAC Mux", "DAC_R3", "Right DAC"},
559
560 {"Right DAC_R1 Mixer", "Line Switch", "Right DAC Mux"},
561 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
562 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
563 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
564 {"Right Line Out", NULL, "Right DAC Mux"},
565 {"Right HP Out", NULL, "Right DAC Mux"},
566
567 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
568 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
569 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
570 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
571 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
572
573 {"Right Line Out", NULL, "Right DAC_R1 Mixer"},
574 {"Mono Out", NULL, "Right DAC_R1 Mixer"},
575 {"Right HP Out", NULL, "Right DAC_R1 Mixer"},
576 {"Right HP Com", NULL, "Right HPCOM Mux"},
577
578 {"RLOUT", NULL, "Right Line Out"},
579 {"RLOUT", NULL, "Right Line Out"},
580 {"HPROUT", NULL, "Right HP Out"},
581 {"HPRCOM", NULL, "Right HP Com"},
582
583 /* Mono Output */
584 {"MONO_LOUT", NULL, "Mono Out"},
585 {"MONO_LOUT", NULL, "Mono Out"},
586
587 /* Left Input */
588 {"Left Line1L Mux", "single-ended", "LINE1L"},
589 {"Left Line1L Mux", "differential", "LINE1L"},
590
591 {"Left Line2L Mux", "single-ended", "LINE2L"},
592 {"Left Line2L Mux", "differential", "LINE2L"},
593
594 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
595 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
596 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
597
598 {"Left ADC", NULL, "Left PGA Mixer"},
599 {"Left ADC", NULL, "GPIO1 dmic modclk"},
600
601 /* Right Input */
602 {"Right Line1R Mux", "single-ended", "LINE1R"},
603 {"Right Line1R Mux", "differential", "LINE1R"},
604
605 {"Right Line2R Mux", "single-ended", "LINE2R"},
606 {"Right Line2R Mux", "differential", "LINE2R"},
607
608 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
609 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
610 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
611
612 {"Right ADC", NULL, "Right PGA Mixer"},
613 {"Right ADC", NULL, "GPIO1 dmic modclk"},
614
615 /* Left PGA Bypass */
616 {"Left PGA Bypass Mixer", "Line Switch", "Left PGA Mixer"},
617 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
618 {"Left PGA Bypass Mixer", "HP Switch", "Left PGA Mixer"},
619 {"Left PGA Bypass Mixer", "HPCOM Switch", "Left PGA Mixer"},
620
621 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
622 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
623 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
624
625 {"Left Line Out", NULL, "Left PGA Bypass Mixer"},
626 {"Mono Out", NULL, "Left PGA Bypass Mixer"},
627 {"Left HP Out", NULL, "Left PGA Bypass Mixer"},
628
629 /* Right PGA Bypass */
630 {"Right PGA Bypass Mixer", "Line Switch", "Right PGA Mixer"},
631 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
632 {"Right PGA Bypass Mixer", "HP Switch", "Right PGA Mixer"},
633 {"Right PGA Bypass Mixer", "HPCOM Switch", "Right PGA Mixer"},
634
635 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
636 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
637 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
638 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
639 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
640
641 {"Right Line Out", NULL, "Right PGA Bypass Mixer"},
642 {"Mono Out", NULL, "Right PGA Bypass Mixer"},
643 {"Right HP Out", NULL, "Right PGA Bypass Mixer"},
644
645 /* Left Line2 Bypass */
646 {"Left Line2 Bypass Mixer", "Line Switch", "Left Line2L Mux"},
647 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
648 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
649 {"Left Line2 Bypass Mixer", "HPCOM Switch", "Left Line2L Mux"},
650
651 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
652 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
653 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
654
655 {"Left Line Out", NULL, "Left Line2 Bypass Mixer"},
656 {"Mono Out", NULL, "Left Line2 Bypass Mixer"},
657 {"Left HP Out", NULL, "Left Line2 Bypass Mixer"},
658
659 /* Right Line2 Bypass */
660 {"Right Line2 Bypass Mixer", "Line Switch", "Right Line2R Mux"},
661 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
662 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
663 {"Right Line2 Bypass Mixer", "HPCOM Switch", "Right Line2R Mux"},
664
665 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
666 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
667 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
668 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
669 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
670
671 {"Right Line Out", NULL, "Right Line2 Bypass Mixer"},
672 {"Mono Out", NULL, "Right Line2 Bypass Mixer"},
673 {"Right HP Out", NULL, "Right Line2 Bypass Mixer"},
674
675 /*
676 * Logical path between digital mic enable and GPIO1 modulator clock
677 * output function
678 */
679 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
680 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
681 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
682 };
683
684 static int aic3x_add_widgets(struct snd_soc_codec *codec)
685 {
686 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
687 ARRAY_SIZE(aic3x_dapm_widgets));
688
689 /* set up audio path interconnects */
690 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
691
692 snd_soc_dapm_new_widgets(codec);
693 return 0;
694 }
695
696 static int aic3x_hw_params(struct snd_pcm_substream *substream,
697 struct snd_pcm_hw_params *params)
698 {
699 struct snd_soc_pcm_runtime *rtd = substream->private_data;
700 struct snd_soc_device *socdev = rtd->socdev;
701 struct snd_soc_codec *codec = socdev->codec;
702 struct aic3x_priv *aic3x = codec->private_data;
703 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
704 u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
705 u16 pll_d = 1;
706
707 /* select data word length */
708 data =
709 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
710 switch (params_format(params)) {
711 case SNDRV_PCM_FORMAT_S16_LE:
712 break;
713 case SNDRV_PCM_FORMAT_S20_3LE:
714 data |= (0x01 << 4);
715 break;
716 case SNDRV_PCM_FORMAT_S24_LE:
717 data |= (0x02 << 4);
718 break;
719 case SNDRV_PCM_FORMAT_S32_LE:
720 data |= (0x03 << 4);
721 break;
722 }
723 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
724
725 /* Fsref can be 44100 or 48000 */
726 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
727
728 /* Try to find a value for Q which allows us to bypass the PLL and
729 * generate CODEC_CLK directly. */
730 for (pll_q = 2; pll_q < 18; pll_q++)
731 if (aic3x->sysclk / (128 * pll_q) == fsref) {
732 bypass_pll = 1;
733 break;
734 }
735
736 if (bypass_pll) {
737 pll_q &= 0xf;
738 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
739 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
740 } else
741 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
742
743 /* Route Left DAC to left channel input and
744 * right DAC to right channel input */
745 data = (LDAC2LCH | RDAC2RCH);
746 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
747 if (params_rate(params) >= 64000)
748 data |= DUAL_RATE_MODE;
749 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
750
751 /* codec sample rate select */
752 data = (fsref * 20) / params_rate(params);
753 if (params_rate(params) < 64000)
754 data /= 2;
755 data /= 5;
756 data -= 2;
757 data |= (data << 4);
758 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
759
760 if (bypass_pll)
761 return 0;
762
763 /* Use PLL
764 * find an apropriate setup for j, d, r and p by iterating over
765 * p and r - j and d are calculated for each fraction.
766 * Up to 128 values are probed, the closest one wins the game.
767 * The sysclk is divided by 1000 to prevent integer overflows.
768 */
769 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
770
771 for (r = 1; r <= 16; r++)
772 for (p = 1; p <= 8; p++) {
773 int clk, tmp = (codec_clk * pll_r * 10) / pll_p;
774 u8 j = tmp / 10000;
775 u16 d = tmp % 10000;
776
777 if (j > 63)
778 continue;
779
780 if (d != 0 && aic3x->sysclk < 10000000)
781 continue;
782
783 /* This is actually 1000 * ((j + (d/10000)) * r) / p
784 * The term had to be converted to get rid of the
785 * division by 10000 */
786 clk = ((10000 * j * r) + (d * r)) / (10 * p);
787
788 /* check whether this values get closer than the best
789 * ones we had before */
790 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
791 pll_j = j; pll_d = d; pll_r = r; pll_p = p;
792 last_clk = clk;
793 }
794
795 /* Early exit for exact matches */
796 if (clk == codec_clk)
797 break;
798 }
799
800 if (last_clk == 0) {
801 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
802 return -EINVAL;
803 }
804
805 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
806 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
807 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
808 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
809 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
810 aic3x_write(codec, AIC3X_PLL_PROGD_REG,
811 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
812
813 return 0;
814 }
815
816 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
817 {
818 struct snd_soc_codec *codec = dai->codec;
819 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
820 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
821
822 if (mute) {
823 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
824 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
825 } else {
826 aic3x_write(codec, LDAC_VOL, ldac_reg);
827 aic3x_write(codec, RDAC_VOL, rdac_reg);
828 }
829
830 return 0;
831 }
832
833 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
834 int clk_id, unsigned int freq, int dir)
835 {
836 struct snd_soc_codec *codec = codec_dai->codec;
837 struct aic3x_priv *aic3x = codec->private_data;
838
839 aic3x->sysclk = freq;
840 return 0;
841 }
842
843 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
844 unsigned int fmt)
845 {
846 struct snd_soc_codec *codec = codec_dai->codec;
847 struct aic3x_priv *aic3x = codec->private_data;
848 u8 iface_areg, iface_breg;
849
850 iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
851 iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
852
853 /* set master/slave audio interface */
854 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
855 case SND_SOC_DAIFMT_CBM_CFM:
856 aic3x->master = 1;
857 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
858 break;
859 case SND_SOC_DAIFMT_CBS_CFS:
860 aic3x->master = 0;
861 break;
862 default:
863 return -EINVAL;
864 }
865
866 /*
867 * match both interface format and signal polarities since they
868 * are fixed
869 */
870 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
871 SND_SOC_DAIFMT_INV_MASK)) {
872 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
873 break;
874 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
875 iface_breg |= (0x01 << 6);
876 break;
877 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
878 iface_breg |= (0x02 << 6);
879 break;
880 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
881 iface_breg |= (0x03 << 6);
882 break;
883 default:
884 return -EINVAL;
885 }
886
887 /* set iface */
888 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
889 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
890
891 return 0;
892 }
893
894 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
895 enum snd_soc_bias_level level)
896 {
897 struct aic3x_priv *aic3x = codec->private_data;
898 u8 reg;
899
900 switch (level) {
901 case SND_SOC_BIAS_ON:
902 /* all power is driven by DAPM system */
903 if (aic3x->master) {
904 /* enable pll */
905 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
906 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
907 reg | PLL_ENABLE);
908 }
909 break;
910 case SND_SOC_BIAS_PREPARE:
911 break;
912 case SND_SOC_BIAS_STANDBY:
913 /*
914 * all power is driven by DAPM system,
915 * so output power is safe if bypass was set
916 */
917 if (aic3x->master) {
918 /* disable pll */
919 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
920 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
921 reg & ~PLL_ENABLE);
922 }
923 break;
924 case SND_SOC_BIAS_OFF:
925 /* force all power off */
926 reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL);
927 aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON);
928 reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL);
929 aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON);
930
931 reg = aic3x_read_reg_cache(codec, DAC_PWR);
932 aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON));
933
934 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
935 aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON);
936 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
937 aic3x_write(codec, HPROUT_CTRL, reg & ~HPROUT_PWR_ON);
938
939 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
940 aic3x_write(codec, HPLCOM_CTRL, reg & ~HPLCOM_PWR_ON);
941 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
942 aic3x_write(codec, HPRCOM_CTRL, reg & ~HPRCOM_PWR_ON);
943
944 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
945 aic3x_write(codec, MONOLOPM_CTRL, reg & ~MONOLOPM_PWR_ON);
946
947 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
948 aic3x_write(codec, LLOPM_CTRL, reg & ~LLOPM_PWR_ON);
949 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
950 aic3x_write(codec, RLOPM_CTRL, reg & ~RLOPM_PWR_ON);
951
952 if (aic3x->master) {
953 /* disable pll */
954 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
955 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
956 reg & ~PLL_ENABLE);
957 }
958 break;
959 }
960 codec->bias_level = level;
961
962 return 0;
963 }
964
965 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
966 {
967 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
968 u8 bit = gpio ? 3: 0;
969 u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit);
970 aic3x_write(codec, reg, val | (!!state << bit));
971 }
972 EXPORT_SYMBOL_GPL(aic3x_set_gpio);
973
974 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
975 {
976 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
977 u8 val, bit = gpio ? 2: 1;
978
979 aic3x_read(codec, reg, &val);
980 return (val >> bit) & 1;
981 }
982 EXPORT_SYMBOL_GPL(aic3x_get_gpio);
983
984 int aic3x_headset_detected(struct snd_soc_codec *codec)
985 {
986 u8 val;
987 aic3x_read(codec, AIC3X_RT_IRQ_FLAGS_REG, &val);
988 return (val >> 2) & 1;
989 }
990 EXPORT_SYMBOL_GPL(aic3x_headset_detected);
991
992 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
993 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
994 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
995
996 struct snd_soc_dai aic3x_dai = {
997 .name = "tlv320aic3x",
998 .playback = {
999 .stream_name = "Playback",
1000 .channels_min = 1,
1001 .channels_max = 2,
1002 .rates = AIC3X_RATES,
1003 .formats = AIC3X_FORMATS,},
1004 .capture = {
1005 .stream_name = "Capture",
1006 .channels_min = 1,
1007 .channels_max = 2,
1008 .rates = AIC3X_RATES,
1009 .formats = AIC3X_FORMATS,},
1010 .ops = {
1011 .hw_params = aic3x_hw_params,
1012 },
1013 .dai_ops = {
1014 .digital_mute = aic3x_mute,
1015 .set_sysclk = aic3x_set_dai_sysclk,
1016 .set_fmt = aic3x_set_dai_fmt,
1017 }
1018 };
1019 EXPORT_SYMBOL_GPL(aic3x_dai);
1020
1021 static int aic3x_suspend(struct platform_device *pdev, pm_message_t state)
1022 {
1023 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1024 struct snd_soc_codec *codec = socdev->codec;
1025
1026 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1027
1028 return 0;
1029 }
1030
1031 static int aic3x_resume(struct platform_device *pdev)
1032 {
1033 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1034 struct snd_soc_codec *codec = socdev->codec;
1035 int i;
1036 u8 data[2];
1037 u8 *cache = codec->reg_cache;
1038
1039 /* Sync reg_cache with the hardware */
1040 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) {
1041 data[0] = i;
1042 data[1] = cache[i];
1043 codec->hw_write(codec->control_data, data, 2);
1044 }
1045
1046 aic3x_set_bias_level(codec, codec->suspend_bias_level);
1047
1048 return 0;
1049 }
1050
1051 /*
1052 * initialise the AIC3X driver
1053 * register the mixer and dsp interfaces with the kernel
1054 */
1055 static int aic3x_init(struct snd_soc_device *socdev)
1056 {
1057 struct snd_soc_codec *codec = socdev->codec;
1058 struct aic3x_setup_data *setup = socdev->codec_data;
1059 int reg, ret = 0;
1060
1061 codec->name = "tlv320aic3x";
1062 codec->owner = THIS_MODULE;
1063 codec->read = aic3x_read_reg_cache;
1064 codec->write = aic3x_write;
1065 codec->set_bias_level = aic3x_set_bias_level;
1066 codec->dai = &aic3x_dai;
1067 codec->num_dai = 1;
1068 codec->reg_cache_size = ARRAY_SIZE(aic3x_reg);
1069 codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL);
1070 if (codec->reg_cache == NULL)
1071 return -ENOMEM;
1072
1073 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1074 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1075
1076 /* register pcms */
1077 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1078 if (ret < 0) {
1079 printk(KERN_ERR "aic3x: failed to create pcms\n");
1080 goto pcm_err;
1081 }
1082
1083 /* DAC default volume and mute */
1084 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1085 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1086
1087 /* DAC to HP default volume and route to Output mixer */
1088 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1089 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1090 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1091 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1092 /* DAC to Line Out default volume and route to Output mixer */
1093 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1094 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1095 /* DAC to Mono Line Out default volume and route to Output mixer */
1096 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1097 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1098
1099 /* unmute all outputs */
1100 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1101 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
1102 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1103 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
1104 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1105 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1106 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1107 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1108 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1109 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
1110 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1111 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1112 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1113 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1114
1115 /* ADC default volume and unmute */
1116 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
1117 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
1118 /* By default route Line1 to ADC PGA mixer */
1119 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1120 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1121
1122 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1123 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1124 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1125 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1126 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1127 /* PGA to Line Out default volume, disconnect from Output Mixer */
1128 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1129 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1130 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1131 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1132 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1133
1134 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1135 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1136 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1137 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1138 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1139 /* Line2 Line Out default volume, disconnect from Output Mixer */
1140 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1141 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1142 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1143 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1144 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1145
1146 /* off, with power on */
1147 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1148
1149 /* setup GPIO functions */
1150 aic3x_write(codec, AIC3X_GPIO1_REG, (setup->gpio_func[0] & 0xf) << 4);
1151 aic3x_write(codec, AIC3X_GPIO2_REG, (setup->gpio_func[1] & 0xf) << 4);
1152
1153 aic3x_add_controls(codec);
1154 aic3x_add_widgets(codec);
1155 ret = snd_soc_register_card(socdev);
1156 if (ret < 0) {
1157 printk(KERN_ERR "aic3x: failed to register card\n");
1158 goto card_err;
1159 }
1160
1161 return ret;
1162
1163 card_err:
1164 snd_soc_free_pcms(socdev);
1165 snd_soc_dapm_free(socdev);
1166 pcm_err:
1167 kfree(codec->reg_cache);
1168 return ret;
1169 }
1170
1171 static struct snd_soc_device *aic3x_socdev;
1172
1173 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1174 /*
1175 * AIC3X 2 wire address can be up to 4 devices with device addresses
1176 * 0x18, 0x19, 0x1A, 0x1B
1177 */
1178
1179 /*
1180 * If the i2c layer weren't so broken, we could pass this kind of data
1181 * around
1182 */
1183 static int aic3x_i2c_probe(struct i2c_client *i2c,
1184 const struct i2c_device_id *id)
1185 {
1186 struct snd_soc_device *socdev = aic3x_socdev;
1187 struct snd_soc_codec *codec = socdev->codec;
1188 int ret;
1189
1190 i2c_set_clientdata(i2c, codec);
1191 codec->control_data = i2c;
1192
1193 ret = aic3x_init(socdev);
1194 if (ret < 0)
1195 printk(KERN_ERR "aic3x: failed to initialise AIC3X\n");
1196 return ret;
1197 }
1198
1199 static int aic3x_i2c_remove(struct i2c_client *client)
1200 {
1201 struct snd_soc_codec *codec = i2c_get_clientdata(client);
1202 kfree(codec->reg_cache);
1203 return 0;
1204 }
1205
1206 static const struct i2c_device_id aic3x_i2c_id[] = {
1207 { "tlv320aic3x", 0 },
1208 { }
1209 };
1210 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1211
1212 /* machine i2c codec control layer */
1213 static struct i2c_driver aic3x_i2c_driver = {
1214 .driver = {
1215 .name = "aic3x I2C Codec",
1216 .owner = THIS_MODULE,
1217 },
1218 .probe = aic3x_i2c_probe,
1219 .remove = aic3x_i2c_remove,
1220 .id_table = aic3x_i2c_id,
1221 };
1222
1223 static int aic3x_i2c_read(struct i2c_client *client, u8 *value, int len)
1224 {
1225 value[0] = i2c_smbus_read_byte_data(client, value[0]);
1226 return (len == 1);
1227 }
1228
1229 static int aic3x_add_i2c_device(struct platform_device *pdev,
1230 const struct aic3x_setup_data *setup)
1231 {
1232 struct i2c_board_info info;
1233 struct i2c_adapter *adapter;
1234 struct i2c_client *client;
1235 int ret;
1236
1237 ret = i2c_add_driver(&aic3x_i2c_driver);
1238 if (ret != 0) {
1239 dev_err(&pdev->dev, "can't add i2c driver\n");
1240 return ret;
1241 }
1242
1243 memset(&info, 0, sizeof(struct i2c_board_info));
1244 info.addr = setup->i2c_address;
1245 strlcpy(info.type, "tlv320aic3x", I2C_NAME_SIZE);
1246
1247 adapter = i2c_get_adapter(setup->i2c_bus);
1248 if (!adapter) {
1249 dev_err(&pdev->dev, "can't get i2c adapter %d\n",
1250 setup->i2c_bus);
1251 goto err_driver;
1252 }
1253
1254 client = i2c_new_device(adapter, &info);
1255 i2c_put_adapter(adapter);
1256 if (!client) {
1257 dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
1258 (unsigned int)info.addr);
1259 goto err_driver;
1260 }
1261
1262 return 0;
1263
1264 err_driver:
1265 i2c_del_driver(&aic3x_i2c_driver);
1266 return -ENODEV;
1267 }
1268 #endif
1269
1270 static int aic3x_probe(struct platform_device *pdev)
1271 {
1272 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1273 struct aic3x_setup_data *setup;
1274 struct snd_soc_codec *codec;
1275 struct aic3x_priv *aic3x;
1276 int ret = 0;
1277
1278 printk(KERN_INFO "AIC3X Audio Codec %s\n", AIC3X_VERSION);
1279
1280 setup = socdev->codec_data;
1281 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1282 if (codec == NULL)
1283 return -ENOMEM;
1284
1285 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1286 if (aic3x == NULL) {
1287 kfree(codec);
1288 return -ENOMEM;
1289 }
1290
1291 codec->private_data = aic3x;
1292 socdev->codec = codec;
1293 mutex_init(&codec->mutex);
1294 INIT_LIST_HEAD(&codec->dapm_widgets);
1295 INIT_LIST_HEAD(&codec->dapm_paths);
1296
1297 aic3x_socdev = socdev;
1298 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1299 if (setup->i2c_address) {
1300 codec->hw_write = (hw_write_t) i2c_master_send;
1301 codec->hw_read = (hw_read_t) aic3x_i2c_read;
1302 ret = aic3x_add_i2c_device(pdev, setup);
1303 }
1304 #else
1305 /* Add other interfaces here */
1306 #endif
1307
1308 if (ret != 0) {
1309 kfree(codec->private_data);
1310 kfree(codec);
1311 }
1312 return ret;
1313 }
1314
1315 static int aic3x_remove(struct platform_device *pdev)
1316 {
1317 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1318 struct snd_soc_codec *codec = socdev->codec;
1319
1320 /* power down chip */
1321 if (codec->control_data)
1322 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1323
1324 snd_soc_free_pcms(socdev);
1325 snd_soc_dapm_free(socdev);
1326 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1327 i2c_unregister_device(codec->control_data);
1328 i2c_del_driver(&aic3x_i2c_driver);
1329 #endif
1330 kfree(codec->private_data);
1331 kfree(codec);
1332
1333 return 0;
1334 }
1335
1336 struct snd_soc_codec_device soc_codec_dev_aic3x = {
1337 .probe = aic3x_probe,
1338 .remove = aic3x_remove,
1339 .suspend = aic3x_suspend,
1340 .resume = aic3x_resume,
1341 };
1342 EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x);
1343
1344 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1345 MODULE_AUTHOR("Vladimir Barinov");
1346 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)