2 * ALSA SoC TLV320AIC3X codec driver
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33.
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 is as follows:
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
40 #include <linux/i2c.h>
41 #include <linux/platform_device.h>
42 #include <sound/core.h>
43 #include <sound/pcm.h>
44 #include <sound/pcm_params.h>
45 #include <sound/soc.h>
46 #include <sound/soc-dapm.h>
47 #include <sound/initval.h>
49 #include "tlv320aic3x.h"
51 #define AIC3X_VERSION "0.2"
53 /* codec private data */
60 * AIC3X register cache
61 * We can't read the AIC3X register space when we are
62 * using 2 wire for device control, so we cache them instead.
63 * There is no point in caching the reset register
65 static const u8 aic3x_reg
[AIC3X_CACHEREGNUM
] = {
66 0x00, 0x00, 0x00, 0x10, /* 0 */
67 0x04, 0x00, 0x00, 0x00, /* 4 */
68 0x00, 0x00, 0x00, 0x01, /* 8 */
69 0x00, 0x00, 0x00, 0x80, /* 12 */
70 0x80, 0xff, 0xff, 0x78, /* 16 */
71 0x78, 0x78, 0x78, 0x78, /* 20 */
72 0x78, 0x00, 0x00, 0xfe, /* 24 */
73 0x00, 0x00, 0xfe, 0x00, /* 28 */
74 0x18, 0x18, 0x00, 0x00, /* 32 */
75 0x00, 0x00, 0x00, 0x00, /* 36 */
76 0x00, 0x00, 0x00, 0x80, /* 40 */
77 0x80, 0x00, 0x00, 0x00, /* 44 */
78 0x00, 0x00, 0x00, 0x04, /* 48 */
79 0x00, 0x00, 0x00, 0x00, /* 52 */
80 0x00, 0x00, 0x04, 0x00, /* 56 */
81 0x00, 0x00, 0x00, 0x00, /* 60 */
82 0x00, 0x04, 0x00, 0x00, /* 64 */
83 0x00, 0x00, 0x00, 0x00, /* 68 */
84 0x04, 0x00, 0x00, 0x00, /* 72 */
85 0x00, 0x00, 0x00, 0x00, /* 76 */
86 0x00, 0x00, 0x00, 0x00, /* 80 */
87 0x00, 0x00, 0x00, 0x00, /* 84 */
88 0x00, 0x00, 0x00, 0x00, /* 88 */
89 0x00, 0x00, 0x00, 0x00, /* 92 */
90 0x00, 0x00, 0x00, 0x00, /* 96 */
91 0x00, 0x00, 0x02, /* 100 */
95 * read aic3x register cache
97 static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec
*codec
,
100 u8
*cache
= codec
->reg_cache
;
101 if (reg
>= AIC3X_CACHEREGNUM
)
107 * write aic3x register cache
109 static inline void aic3x_write_reg_cache(struct snd_soc_codec
*codec
,
112 u8
*cache
= codec
->reg_cache
;
113 if (reg
>= AIC3X_CACHEREGNUM
)
119 * write to the aic3x register space
121 static int aic3x_write(struct snd_soc_codec
*codec
, unsigned int reg
,
127 * D15..D8 aic3x register offset
128 * D7...D0 register data
130 data
[0] = reg
& 0xff;
131 data
[1] = value
& 0xff;
133 aic3x_write_reg_cache(codec
, data
[0], data
[1]);
134 if (codec
->hw_write(codec
->control_data
, data
, 2) == 2)
141 * read from the aic3x register space
143 static int aic3x_read(struct snd_soc_codec
*codec
, unsigned int reg
,
147 if (codec
->hw_read(codec
->control_data
, value
, 1) != 1)
150 aic3x_write_reg_cache(codec
, reg
, *value
);
154 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
155 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
156 .info = snd_soc_info_volsw, \
157 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
158 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
161 * All input lines are connected when !0xf and disconnected with 0xf bit field,
162 * so we have to use specific dapm_put call for input mixer
164 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol
*kcontrol
,
165 struct snd_ctl_elem_value
*ucontrol
)
167 struct snd_soc_dapm_widget
*widget
= snd_kcontrol_chip(kcontrol
);
168 int reg
= kcontrol
->private_value
& 0xff;
169 int shift
= (kcontrol
->private_value
>> 8) & 0x0f;
170 int mask
= (kcontrol
->private_value
>> 16) & 0xff;
171 int invert
= (kcontrol
->private_value
>> 24) & 0x01;
172 unsigned short val
, val_mask
;
174 struct snd_soc_dapm_path
*path
;
177 val
= (ucontrol
->value
.integer
.value
[0] & mask
);
185 val_mask
= mask
<< shift
;
188 mutex_lock(&widget
->codec
->mutex
);
190 if (snd_soc_test_bits(widget
->codec
, reg
, val_mask
, val
)) {
191 /* find dapm widget path assoc with kcontrol */
192 list_for_each_entry(path
, &widget
->codec
->dapm_paths
, list
) {
193 if (path
->kcontrol
!= kcontrol
)
196 /* found, now check type */
200 path
->connect
= invert
? 0 : 1;
202 /* old connection must be powered down */
203 path
->connect
= invert
? 1 : 0;
208 snd_soc_dapm_sync(widget
->codec
);
211 ret
= snd_soc_update_bits(widget
->codec
, reg
, val_mask
, val
);
213 mutex_unlock(&widget
->codec
->mutex
);
217 static const char *aic3x_left_dac_mux
[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
218 static const char *aic3x_right_dac_mux
[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
219 static const char *aic3x_left_hpcom_mux
[] =
220 { "differential of HPLOUT", "constant VCM", "single-ended" };
221 static const char *aic3x_right_hpcom_mux
[] =
222 { "differential of HPROUT", "constant VCM", "single-ended",
223 "differential of HPLCOM", "external feedback" };
224 static const char *aic3x_linein_mode_mux
[] = { "single-ended", "differential" };
225 static const char *aic3x_adc_hpf
[] =
226 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
230 #define LHPCOM_ENUM 2
231 #define RHPCOM_ENUM 3
232 #define LINE1L_ENUM 4
233 #define LINE1R_ENUM 5
234 #define LINE2L_ENUM 6
235 #define LINE2R_ENUM 7
236 #define ADC_HPF_ENUM 8
238 static const struct soc_enum aic3x_enum
[] = {
239 SOC_ENUM_SINGLE(DAC_LINE_MUX
, 6, 3, aic3x_left_dac_mux
),
240 SOC_ENUM_SINGLE(DAC_LINE_MUX
, 4, 3, aic3x_right_dac_mux
),
241 SOC_ENUM_SINGLE(HPLCOM_CFG
, 4, 3, aic3x_left_hpcom_mux
),
242 SOC_ENUM_SINGLE(HPRCOM_CFG
, 3, 5, aic3x_right_hpcom_mux
),
243 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL
, 7, 2, aic3x_linein_mode_mux
),
244 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL
, 7, 2, aic3x_linein_mode_mux
),
245 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL
, 7, 2, aic3x_linein_mode_mux
),
246 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL
, 7, 2, aic3x_linein_mode_mux
),
247 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL
, 6, 4, 4, aic3x_adc_hpf
),
250 static const struct snd_kcontrol_new aic3x_snd_controls
[] = {
252 SOC_DOUBLE_R("PCM Playback Volume", LDAC_VOL
, RDAC_VOL
, 0, 0x7f, 1),
254 SOC_DOUBLE_R("Line DAC Playback Volume", DACL1_2_LLOPM_VOL
,
255 DACR1_2_RLOPM_VOL
, 0, 0x7f, 1),
256 SOC_DOUBLE_R("Line DAC Playback Switch", LLOPM_CTRL
, RLOPM_CTRL
, 3,
258 SOC_DOUBLE_R("Line PGA Bypass Playback Volume", PGAL_2_LLOPM_VOL
,
259 PGAR_2_RLOPM_VOL
, 0, 0x7f, 1),
260 SOC_DOUBLE_R("Line Line2 Bypass Playback Volume", LINE2L_2_LLOPM_VOL
,
261 LINE2R_2_RLOPM_VOL
, 0, 0x7f, 1),
263 SOC_DOUBLE_R("Mono DAC Playback Volume", DACL1_2_MONOLOPM_VOL
,
264 DACR1_2_MONOLOPM_VOL
, 0, 0x7f, 1),
265 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL
, 3, 0x01, 0),
266 SOC_DOUBLE_R("Mono PGA Bypass Playback Volume", PGAL_2_MONOLOPM_VOL
,
267 PGAR_2_MONOLOPM_VOL
, 0, 0x7f, 1),
268 SOC_DOUBLE_R("Mono Line2 Bypass Playback Volume", LINE2L_2_MONOLOPM_VOL
,
269 LINE2R_2_MONOLOPM_VOL
, 0, 0x7f, 1),
271 SOC_DOUBLE_R("HP DAC Playback Volume", DACL1_2_HPLOUT_VOL
,
272 DACR1_2_HPROUT_VOL
, 0, 0x7f, 1),
273 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL
, HPROUT_CTRL
, 3,
275 SOC_DOUBLE_R("HP PGA Bypass Playback Volume", PGAL_2_HPLOUT_VOL
,
276 PGAR_2_HPROUT_VOL
, 0, 0x7f, 1),
277 SOC_DOUBLE_R("HP Line2 Bypass Playback Volume", LINE2L_2_HPLOUT_VOL
,
278 LINE2R_2_HPROUT_VOL
, 0, 0x7f, 1),
280 SOC_DOUBLE_R("HPCOM DAC Playback Volume", DACL1_2_HPLCOM_VOL
,
281 DACR1_2_HPRCOM_VOL
, 0, 0x7f, 1),
282 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL
, HPRCOM_CTRL
, 3,
284 SOC_DOUBLE_R("HPCOM PGA Bypass Playback Volume", PGAL_2_HPLCOM_VOL
,
285 PGAR_2_HPRCOM_VOL
, 0, 0x7f, 1),
286 SOC_DOUBLE_R("HPCOM Line2 Bypass Playback Volume", LINE2L_2_HPLCOM_VOL
,
287 LINE2R_2_HPRCOM_VOL
, 0, 0x7f, 1),
290 * Note: enable Automatic input Gain Controller with care. It can
291 * adjust PGA to max value when ADC is on and will never go back.
293 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A
, RAGC_CTRL_A
, 7, 0x01, 0),
296 SOC_DOUBLE_R("PGA Capture Volume", LADC_VOL
, RADC_VOL
, 0, 0x7f, 0),
297 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL
, RADC_VOL
, 7, 0x01, 1),
299 SOC_ENUM("ADC HPF Cut-off", aic3x_enum
[ADC_HPF_ENUM
]),
302 /* add non dapm controls */
303 static int aic3x_add_controls(struct snd_soc_codec
*codec
)
307 for (i
= 0; i
< ARRAY_SIZE(aic3x_snd_controls
); i
++) {
308 err
= snd_ctl_add(codec
->card
,
309 snd_soc_cnew(&aic3x_snd_controls
[i
],
319 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls
=
320 SOC_DAPM_ENUM("Route", aic3x_enum
[LDAC_ENUM
]);
323 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls
=
324 SOC_DAPM_ENUM("Route", aic3x_enum
[RDAC_ENUM
]);
327 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls
=
328 SOC_DAPM_ENUM("Route", aic3x_enum
[LHPCOM_ENUM
]);
330 /* Right HPCOM Mux */
331 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls
=
332 SOC_DAPM_ENUM("Route", aic3x_enum
[RHPCOM_ENUM
]);
334 /* Left DAC_L1 Mixer */
335 static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls
[] = {
336 SOC_DAPM_SINGLE("Line Switch", DACL1_2_LLOPM_VOL
, 7, 1, 0),
337 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL
, 7, 1, 0),
338 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL
, 7, 1, 0),
339 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL
, 7, 1, 0),
342 /* Right DAC_R1 Mixer */
343 static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls
[] = {
344 SOC_DAPM_SINGLE("Line Switch", DACR1_2_RLOPM_VOL
, 7, 1, 0),
345 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL
, 7, 1, 0),
346 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL
, 7, 1, 0),
347 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL
, 7, 1, 0),
351 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls
[] = {
352 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL
, 3, 1, 1),
353 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL
, 3, 1, 1),
354 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL
, 4, 1, 1),
357 /* Right PGA Mixer */
358 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls
[] = {
359 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL
, 3, 1, 1),
360 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL
, 3, 1, 1),
361 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL
, 0, 1, 1),
365 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls
=
366 SOC_DAPM_ENUM("Route", aic3x_enum
[LINE1L_ENUM
]);
368 /* Right Line1 Mux */
369 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls
=
370 SOC_DAPM_ENUM("Route", aic3x_enum
[LINE1R_ENUM
]);
373 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls
=
374 SOC_DAPM_ENUM("Route", aic3x_enum
[LINE2L_ENUM
]);
376 /* Right Line2 Mux */
377 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls
=
378 SOC_DAPM_ENUM("Route", aic3x_enum
[LINE2R_ENUM
]);
380 /* Left PGA Bypass Mixer */
381 static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls
[] = {
382 SOC_DAPM_SINGLE("Line Switch", PGAL_2_LLOPM_VOL
, 7, 1, 0),
383 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL
, 7, 1, 0),
384 SOC_DAPM_SINGLE("HP Switch", PGAL_2_HPLOUT_VOL
, 7, 1, 0),
385 SOC_DAPM_SINGLE("HPCOM Switch", PGAL_2_HPLCOM_VOL
, 7, 1, 0),
388 /* Right PGA Bypass Mixer */
389 static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls
[] = {
390 SOC_DAPM_SINGLE("Line Switch", PGAR_2_RLOPM_VOL
, 7, 1, 0),
391 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL
, 7, 1, 0),
392 SOC_DAPM_SINGLE("HP Switch", PGAR_2_HPROUT_VOL
, 7, 1, 0),
393 SOC_DAPM_SINGLE("HPCOM Switch", PGAR_2_HPRCOM_VOL
, 7, 1, 0),
396 /* Left Line2 Bypass Mixer */
397 static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls
[] = {
398 SOC_DAPM_SINGLE("Line Switch", LINE2L_2_LLOPM_VOL
, 7, 1, 0),
399 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL
, 7, 1, 0),
400 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL
, 7, 1, 0),
401 SOC_DAPM_SINGLE("HPCOM Switch", LINE2L_2_HPLCOM_VOL
, 7, 1, 0),
404 /* Right Line2 Bypass Mixer */
405 static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls
[] = {
406 SOC_DAPM_SINGLE("Line Switch", LINE2R_2_RLOPM_VOL
, 7, 1, 0),
407 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL
, 7, 1, 0),
408 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL
, 7, 1, 0),
409 SOC_DAPM_SINGLE("HPCOM Switch", LINE2R_2_HPRCOM_VOL
, 7, 1, 0),
412 static const struct snd_soc_dapm_widget aic3x_dapm_widgets
[] = {
413 /* Left DAC to Left Outputs */
414 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR
, 7, 0),
415 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM
, 0, 0,
416 &aic3x_left_dac_mux_controls
),
417 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM
, 0, 0,
418 &aic3x_left_dac_mixer_controls
[0],
419 ARRAY_SIZE(aic3x_left_dac_mixer_controls
)),
420 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM
, 0, 0,
421 &aic3x_left_hpcom_mux_controls
),
422 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL
, 0, 0, NULL
, 0),
423 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL
, 0, 0, NULL
, 0),
424 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL
, 0, 0, NULL
, 0),
426 /* Right DAC to Right Outputs */
427 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR
, 6, 0),
428 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM
, 0, 0,
429 &aic3x_right_dac_mux_controls
),
430 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM
, 0, 0,
431 &aic3x_right_dac_mixer_controls
[0],
432 ARRAY_SIZE(aic3x_right_dac_mixer_controls
)),
433 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM
, 0, 0,
434 &aic3x_right_hpcom_mux_controls
),
435 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL
, 0, 0, NULL
, 0),
436 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL
, 0, 0, NULL
, 0),
437 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL
, 0, 0, NULL
, 0),
440 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL
, 0, 0, NULL
, 0),
442 /* Left Inputs to Left ADC */
443 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL
, 2, 0),
444 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM
, 0, 0,
445 &aic3x_left_pga_mixer_controls
[0],
446 ARRAY_SIZE(aic3x_left_pga_mixer_controls
)),
447 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM
, 0, 0,
448 &aic3x_left_line1_mux_controls
),
449 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM
, 0, 0,
450 &aic3x_left_line2_mux_controls
),
452 /* Right Inputs to Right ADC */
453 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
454 LINE1R_2_RADC_CTRL
, 2, 0),
455 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM
, 0, 0,
456 &aic3x_right_pga_mixer_controls
[0],
457 ARRAY_SIZE(aic3x_right_pga_mixer_controls
)),
458 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM
, 0, 0,
459 &aic3x_right_line1_mux_controls
),
460 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM
, 0, 0,
461 &aic3x_right_line2_mux_controls
),
464 * Not a real mic bias widget but similar function. This is for dynamic
465 * control of GPIO1 digital mic modulator clock output function when
468 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "GPIO1 dmic modclk",
469 AIC3X_GPIO1_REG
, 4, 0xf,
470 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK
,
471 AIC3X_GPIO1_FUNC_DISABLED
),
474 * Also similar function like mic bias. Selects digital mic with
475 * configurable oversampling rate instead of ADC converter.
477 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "DMic Rate 128",
478 AIC3X_ASD_INTF_CTRLA
, 0, 3, 1, 0),
479 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "DMic Rate 64",
480 AIC3X_ASD_INTF_CTRLA
, 0, 3, 2, 0),
481 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "DMic Rate 32",
482 AIC3X_ASD_INTF_CTRLA
, 0, 3, 3, 0),
485 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "Mic Bias 2V",
486 MICBIAS_CTRL
, 6, 3, 1, 0),
487 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "Mic Bias 2.5V",
488 MICBIAS_CTRL
, 6, 3, 2, 0),
489 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "Mic Bias AVDD",
490 MICBIAS_CTRL
, 6, 3, 3, 0),
492 /* Left PGA to Left Output bypass */
493 SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM
, 0, 0,
494 &aic3x_left_pga_bp_mixer_controls
[0],
495 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls
)),
497 /* Right PGA to Right Output bypass */
498 SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM
, 0, 0,
499 &aic3x_right_pga_bp_mixer_controls
[0],
500 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls
)),
502 /* Left Line2 to Left Output bypass */
503 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM
, 0, 0,
504 &aic3x_left_line2_bp_mixer_controls
[0],
505 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls
)),
507 /* Right Line2 to Right Output bypass */
508 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM
, 0, 0,
509 &aic3x_right_line2_bp_mixer_controls
[0],
510 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls
)),
512 SND_SOC_DAPM_OUTPUT("LLOUT"),
513 SND_SOC_DAPM_OUTPUT("RLOUT"),
514 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
515 SND_SOC_DAPM_OUTPUT("HPLOUT"),
516 SND_SOC_DAPM_OUTPUT("HPROUT"),
517 SND_SOC_DAPM_OUTPUT("HPLCOM"),
518 SND_SOC_DAPM_OUTPUT("HPRCOM"),
520 SND_SOC_DAPM_INPUT("MIC3L"),
521 SND_SOC_DAPM_INPUT("MIC3R"),
522 SND_SOC_DAPM_INPUT("LINE1L"),
523 SND_SOC_DAPM_INPUT("LINE1R"),
524 SND_SOC_DAPM_INPUT("LINE2L"),
525 SND_SOC_DAPM_INPUT("LINE2R"),
528 static const struct snd_soc_dapm_route intercon
[] = {
530 {"Left DAC Mux", "DAC_L1", "Left DAC"},
531 {"Left DAC Mux", "DAC_L2", "Left DAC"},
532 {"Left DAC Mux", "DAC_L3", "Left DAC"},
534 {"Left DAC_L1 Mixer", "Line Switch", "Left DAC Mux"},
535 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
536 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
537 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
538 {"Left Line Out", NULL
, "Left DAC Mux"},
539 {"Left HP Out", NULL
, "Left DAC Mux"},
541 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
542 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
543 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
545 {"Left Line Out", NULL
, "Left DAC_L1 Mixer"},
546 {"Mono Out", NULL
, "Left DAC_L1 Mixer"},
547 {"Left HP Out", NULL
, "Left DAC_L1 Mixer"},
548 {"Left HP Com", NULL
, "Left HPCOM Mux"},
550 {"LLOUT", NULL
, "Left Line Out"},
551 {"LLOUT", NULL
, "Left Line Out"},
552 {"HPLOUT", NULL
, "Left HP Out"},
553 {"HPLCOM", NULL
, "Left HP Com"},
556 {"Right DAC Mux", "DAC_R1", "Right DAC"},
557 {"Right DAC Mux", "DAC_R2", "Right DAC"},
558 {"Right DAC Mux", "DAC_R3", "Right DAC"},
560 {"Right DAC_R1 Mixer", "Line Switch", "Right DAC Mux"},
561 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
562 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
563 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
564 {"Right Line Out", NULL
, "Right DAC Mux"},
565 {"Right HP Out", NULL
, "Right DAC Mux"},
567 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
568 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
569 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
570 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
571 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
573 {"Right Line Out", NULL
, "Right DAC_R1 Mixer"},
574 {"Mono Out", NULL
, "Right DAC_R1 Mixer"},
575 {"Right HP Out", NULL
, "Right DAC_R1 Mixer"},
576 {"Right HP Com", NULL
, "Right HPCOM Mux"},
578 {"RLOUT", NULL
, "Right Line Out"},
579 {"RLOUT", NULL
, "Right Line Out"},
580 {"HPROUT", NULL
, "Right HP Out"},
581 {"HPRCOM", NULL
, "Right HP Com"},
584 {"MONO_LOUT", NULL
, "Mono Out"},
585 {"MONO_LOUT", NULL
, "Mono Out"},
588 {"Left Line1L Mux", "single-ended", "LINE1L"},
589 {"Left Line1L Mux", "differential", "LINE1L"},
591 {"Left Line2L Mux", "single-ended", "LINE2L"},
592 {"Left Line2L Mux", "differential", "LINE2L"},
594 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
595 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
596 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
598 {"Left ADC", NULL
, "Left PGA Mixer"},
599 {"Left ADC", NULL
, "GPIO1 dmic modclk"},
602 {"Right Line1R Mux", "single-ended", "LINE1R"},
603 {"Right Line1R Mux", "differential", "LINE1R"},
605 {"Right Line2R Mux", "single-ended", "LINE2R"},
606 {"Right Line2R Mux", "differential", "LINE2R"},
608 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
609 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
610 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
612 {"Right ADC", NULL
, "Right PGA Mixer"},
613 {"Right ADC", NULL
, "GPIO1 dmic modclk"},
615 /* Left PGA Bypass */
616 {"Left PGA Bypass Mixer", "Line Switch", "Left PGA Mixer"},
617 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
618 {"Left PGA Bypass Mixer", "HP Switch", "Left PGA Mixer"},
619 {"Left PGA Bypass Mixer", "HPCOM Switch", "Left PGA Mixer"},
621 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
622 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
623 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
625 {"Left Line Out", NULL
, "Left PGA Bypass Mixer"},
626 {"Mono Out", NULL
, "Left PGA Bypass Mixer"},
627 {"Left HP Out", NULL
, "Left PGA Bypass Mixer"},
629 /* Right PGA Bypass */
630 {"Right PGA Bypass Mixer", "Line Switch", "Right PGA Mixer"},
631 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
632 {"Right PGA Bypass Mixer", "HP Switch", "Right PGA Mixer"},
633 {"Right PGA Bypass Mixer", "HPCOM Switch", "Right PGA Mixer"},
635 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
636 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
637 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
638 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
639 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
641 {"Right Line Out", NULL
, "Right PGA Bypass Mixer"},
642 {"Mono Out", NULL
, "Right PGA Bypass Mixer"},
643 {"Right HP Out", NULL
, "Right PGA Bypass Mixer"},
645 /* Left Line2 Bypass */
646 {"Left Line2 Bypass Mixer", "Line Switch", "Left Line2L Mux"},
647 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
648 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
649 {"Left Line2 Bypass Mixer", "HPCOM Switch", "Left Line2L Mux"},
651 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
652 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
653 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
655 {"Left Line Out", NULL
, "Left Line2 Bypass Mixer"},
656 {"Mono Out", NULL
, "Left Line2 Bypass Mixer"},
657 {"Left HP Out", NULL
, "Left Line2 Bypass Mixer"},
659 /* Right Line2 Bypass */
660 {"Right Line2 Bypass Mixer", "Line Switch", "Right Line2R Mux"},
661 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
662 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
663 {"Right Line2 Bypass Mixer", "HPCOM Switch", "Right Line2R Mux"},
665 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
666 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
667 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
668 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
669 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
671 {"Right Line Out", NULL
, "Right Line2 Bypass Mixer"},
672 {"Mono Out", NULL
, "Right Line2 Bypass Mixer"},
673 {"Right HP Out", NULL
, "Right Line2 Bypass Mixer"},
676 * Logical path between digital mic enable and GPIO1 modulator clock
679 {"GPIO1 dmic modclk", NULL
, "DMic Rate 128"},
680 {"GPIO1 dmic modclk", NULL
, "DMic Rate 64"},
681 {"GPIO1 dmic modclk", NULL
, "DMic Rate 32"},
684 static int aic3x_add_widgets(struct snd_soc_codec
*codec
)
686 snd_soc_dapm_new_controls(codec
, aic3x_dapm_widgets
,
687 ARRAY_SIZE(aic3x_dapm_widgets
));
689 /* set up audio path interconnects */
690 snd_soc_dapm_add_routes(codec
, intercon
, ARRAY_SIZE(intercon
));
692 snd_soc_dapm_new_widgets(codec
);
696 static int aic3x_hw_params(struct snd_pcm_substream
*substream
,
697 struct snd_pcm_hw_params
*params
,
698 struct snd_soc_dai
*dai
)
700 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
701 struct snd_soc_device
*socdev
= rtd
->socdev
;
702 struct snd_soc_codec
*codec
= socdev
->codec
;
703 struct aic3x_priv
*aic3x
= codec
->private_data
;
704 int codec_clk
= 0, bypass_pll
= 0, fsref
, last_clk
= 0;
705 u8 data
, r
, p
, pll_q
, pll_p
= 1, pll_r
= 1, pll_j
= 1;
708 /* select data word length */
710 aic3x_read_reg_cache(codec
, AIC3X_ASD_INTF_CTRLB
) & (~(0x3 << 4));
711 switch (params_format(params
)) {
712 case SNDRV_PCM_FORMAT_S16_LE
:
714 case SNDRV_PCM_FORMAT_S20_3LE
:
717 case SNDRV_PCM_FORMAT_S24_LE
:
720 case SNDRV_PCM_FORMAT_S32_LE
:
724 aic3x_write(codec
, AIC3X_ASD_INTF_CTRLB
, data
);
726 /* Fsref can be 44100 or 48000 */
727 fsref
= (params_rate(params
) % 11025 == 0) ? 44100 : 48000;
729 /* Try to find a value for Q which allows us to bypass the PLL and
730 * generate CODEC_CLK directly. */
731 for (pll_q
= 2; pll_q
< 18; pll_q
++)
732 if (aic3x
->sysclk
/ (128 * pll_q
) == fsref
) {
739 aic3x_write(codec
, AIC3X_PLL_PROGA_REG
, pll_q
<< PLLQ_SHIFT
);
740 aic3x_write(codec
, AIC3X_GPIOB_REG
, CODEC_CLKIN_CLKDIV
);
742 aic3x_write(codec
, AIC3X_GPIOB_REG
, CODEC_CLKIN_PLLDIV
);
744 /* Route Left DAC to left channel input and
745 * right DAC to right channel input */
746 data
= (LDAC2LCH
| RDAC2RCH
);
747 data
|= (fsref
== 44100) ? FSREF_44100
: FSREF_48000
;
748 if (params_rate(params
) >= 64000)
749 data
|= DUAL_RATE_MODE
;
750 aic3x_write(codec
, AIC3X_CODEC_DATAPATH_REG
, data
);
752 /* codec sample rate select */
753 data
= (fsref
* 20) / params_rate(params
);
754 if (params_rate(params
) < 64000)
759 aic3x_write(codec
, AIC3X_SAMPLE_RATE_SEL_REG
, data
);
765 * find an apropriate setup for j, d, r and p by iterating over
766 * p and r - j and d are calculated for each fraction.
767 * Up to 128 values are probed, the closest one wins the game.
768 * The sysclk is divided by 1000 to prevent integer overflows.
770 codec_clk
= (2048 * fsref
) / (aic3x
->sysclk
/ 1000);
772 for (r
= 1; r
<= 16; r
++)
773 for (p
= 1; p
<= 8; p
++) {
774 int clk
, tmp
= (codec_clk
* pll_r
* 10) / pll_p
;
781 if (d
!= 0 && aic3x
->sysclk
< 10000000)
784 /* This is actually 1000 * ((j + (d/10000)) * r) / p
785 * The term had to be converted to get rid of the
786 * division by 10000 */
787 clk
= ((10000 * j
* r
) + (d
* r
)) / (10 * p
);
789 /* check whether this values get closer than the best
790 * ones we had before */
791 if (abs(codec_clk
- clk
) < abs(codec_clk
- last_clk
)) {
792 pll_j
= j
; pll_d
= d
; pll_r
= r
; pll_p
= p
;
796 /* Early exit for exact matches */
797 if (clk
== codec_clk
)
802 printk(KERN_ERR
"%s(): unable to setup PLL\n", __func__
);
806 data
= aic3x_read_reg_cache(codec
, AIC3X_PLL_PROGA_REG
);
807 aic3x_write(codec
, AIC3X_PLL_PROGA_REG
, data
| (pll_p
<< PLLP_SHIFT
));
808 aic3x_write(codec
, AIC3X_OVRF_STATUS_AND_PLLR_REG
, pll_r
<< PLLR_SHIFT
);
809 aic3x_write(codec
, AIC3X_PLL_PROGB_REG
, pll_j
<< PLLJ_SHIFT
);
810 aic3x_write(codec
, AIC3X_PLL_PROGC_REG
, (pll_d
>> 6) << PLLD_MSB_SHIFT
);
811 aic3x_write(codec
, AIC3X_PLL_PROGD_REG
,
812 (pll_d
& 0x3F) << PLLD_LSB_SHIFT
);
817 static int aic3x_mute(struct snd_soc_dai
*dai
, int mute
)
819 struct snd_soc_codec
*codec
= dai
->codec
;
820 u8 ldac_reg
= aic3x_read_reg_cache(codec
, LDAC_VOL
) & ~MUTE_ON
;
821 u8 rdac_reg
= aic3x_read_reg_cache(codec
, RDAC_VOL
) & ~MUTE_ON
;
824 aic3x_write(codec
, LDAC_VOL
, ldac_reg
| MUTE_ON
);
825 aic3x_write(codec
, RDAC_VOL
, rdac_reg
| MUTE_ON
);
827 aic3x_write(codec
, LDAC_VOL
, ldac_reg
);
828 aic3x_write(codec
, RDAC_VOL
, rdac_reg
);
834 static int aic3x_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
835 int clk_id
, unsigned int freq
, int dir
)
837 struct snd_soc_codec
*codec
= codec_dai
->codec
;
838 struct aic3x_priv
*aic3x
= codec
->private_data
;
840 aic3x
->sysclk
= freq
;
844 static int aic3x_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
847 struct snd_soc_codec
*codec
= codec_dai
->codec
;
848 struct aic3x_priv
*aic3x
= codec
->private_data
;
849 u8 iface_areg
, iface_breg
;
851 iface_areg
= aic3x_read_reg_cache(codec
, AIC3X_ASD_INTF_CTRLA
) & 0x3f;
852 iface_breg
= aic3x_read_reg_cache(codec
, AIC3X_ASD_INTF_CTRLB
) & 0x3f;
854 /* set master/slave audio interface */
855 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
856 case SND_SOC_DAIFMT_CBM_CFM
:
858 iface_areg
|= BIT_CLK_MASTER
| WORD_CLK_MASTER
;
860 case SND_SOC_DAIFMT_CBS_CFS
:
868 * match both interface format and signal polarities since they
871 switch (fmt
& (SND_SOC_DAIFMT_FORMAT_MASK
|
872 SND_SOC_DAIFMT_INV_MASK
)) {
873 case (SND_SOC_DAIFMT_I2S
| SND_SOC_DAIFMT_NB_NF
):
875 case (SND_SOC_DAIFMT_DSP_B
| SND_SOC_DAIFMT_IB_NF
):
876 iface_breg
|= (0x01 << 6);
878 case (SND_SOC_DAIFMT_RIGHT_J
| SND_SOC_DAIFMT_NB_NF
):
879 iface_breg
|= (0x02 << 6);
881 case (SND_SOC_DAIFMT_LEFT_J
| SND_SOC_DAIFMT_NB_NF
):
882 iface_breg
|= (0x03 << 6);
889 aic3x_write(codec
, AIC3X_ASD_INTF_CTRLA
, iface_areg
);
890 aic3x_write(codec
, AIC3X_ASD_INTF_CTRLB
, iface_breg
);
895 static int aic3x_set_bias_level(struct snd_soc_codec
*codec
,
896 enum snd_soc_bias_level level
)
898 struct aic3x_priv
*aic3x
= codec
->private_data
;
902 case SND_SOC_BIAS_ON
:
903 /* all power is driven by DAPM system */
906 reg
= aic3x_read_reg_cache(codec
, AIC3X_PLL_PROGA_REG
);
907 aic3x_write(codec
, AIC3X_PLL_PROGA_REG
,
911 case SND_SOC_BIAS_PREPARE
:
913 case SND_SOC_BIAS_STANDBY
:
915 * all power is driven by DAPM system,
916 * so output power is safe if bypass was set
920 reg
= aic3x_read_reg_cache(codec
, AIC3X_PLL_PROGA_REG
);
921 aic3x_write(codec
, AIC3X_PLL_PROGA_REG
,
925 case SND_SOC_BIAS_OFF
:
926 /* force all power off */
927 reg
= aic3x_read_reg_cache(codec
, LINE1L_2_LADC_CTRL
);
928 aic3x_write(codec
, LINE1L_2_LADC_CTRL
, reg
& ~LADC_PWR_ON
);
929 reg
= aic3x_read_reg_cache(codec
, LINE1R_2_RADC_CTRL
);
930 aic3x_write(codec
, LINE1R_2_RADC_CTRL
, reg
& ~RADC_PWR_ON
);
932 reg
= aic3x_read_reg_cache(codec
, DAC_PWR
);
933 aic3x_write(codec
, DAC_PWR
, reg
& ~(LDAC_PWR_ON
| RDAC_PWR_ON
));
935 reg
= aic3x_read_reg_cache(codec
, HPLOUT_CTRL
);
936 aic3x_write(codec
, HPLOUT_CTRL
, reg
& ~HPLOUT_PWR_ON
);
937 reg
= aic3x_read_reg_cache(codec
, HPROUT_CTRL
);
938 aic3x_write(codec
, HPROUT_CTRL
, reg
& ~HPROUT_PWR_ON
);
940 reg
= aic3x_read_reg_cache(codec
, HPLCOM_CTRL
);
941 aic3x_write(codec
, HPLCOM_CTRL
, reg
& ~HPLCOM_PWR_ON
);
942 reg
= aic3x_read_reg_cache(codec
, HPRCOM_CTRL
);
943 aic3x_write(codec
, HPRCOM_CTRL
, reg
& ~HPRCOM_PWR_ON
);
945 reg
= aic3x_read_reg_cache(codec
, MONOLOPM_CTRL
);
946 aic3x_write(codec
, MONOLOPM_CTRL
, reg
& ~MONOLOPM_PWR_ON
);
948 reg
= aic3x_read_reg_cache(codec
, LLOPM_CTRL
);
949 aic3x_write(codec
, LLOPM_CTRL
, reg
& ~LLOPM_PWR_ON
);
950 reg
= aic3x_read_reg_cache(codec
, RLOPM_CTRL
);
951 aic3x_write(codec
, RLOPM_CTRL
, reg
& ~RLOPM_PWR_ON
);
955 reg
= aic3x_read_reg_cache(codec
, AIC3X_PLL_PROGA_REG
);
956 aic3x_write(codec
, AIC3X_PLL_PROGA_REG
,
961 codec
->bias_level
= level
;
966 void aic3x_set_gpio(struct snd_soc_codec
*codec
, int gpio
, int state
)
968 u8 reg
= gpio
? AIC3X_GPIO2_REG
: AIC3X_GPIO1_REG
;
969 u8 bit
= gpio
? 3: 0;
970 u8 val
= aic3x_read_reg_cache(codec
, reg
) & ~(1 << bit
);
971 aic3x_write(codec
, reg
, val
| (!!state
<< bit
));
973 EXPORT_SYMBOL_GPL(aic3x_set_gpio
);
975 int aic3x_get_gpio(struct snd_soc_codec
*codec
, int gpio
)
977 u8 reg
= gpio
? AIC3X_GPIO2_REG
: AIC3X_GPIO1_REG
;
978 u8 val
, bit
= gpio
? 2: 1;
980 aic3x_read(codec
, reg
, &val
);
981 return (val
>> bit
) & 1;
983 EXPORT_SYMBOL_GPL(aic3x_get_gpio
);
985 int aic3x_headset_detected(struct snd_soc_codec
*codec
)
988 aic3x_read(codec
, AIC3X_RT_IRQ_FLAGS_REG
, &val
);
989 return (val
>> 2) & 1;
991 EXPORT_SYMBOL_GPL(aic3x_headset_detected
);
993 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
994 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
995 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
997 struct snd_soc_dai aic3x_dai
= {
998 .name
= "tlv320aic3x",
1000 .stream_name
= "Playback",
1003 .rates
= AIC3X_RATES
,
1004 .formats
= AIC3X_FORMATS
,},
1006 .stream_name
= "Capture",
1009 .rates
= AIC3X_RATES
,
1010 .formats
= AIC3X_FORMATS
,},
1012 .hw_params
= aic3x_hw_params
,
1013 .digital_mute
= aic3x_mute
,
1014 .set_sysclk
= aic3x_set_dai_sysclk
,
1015 .set_fmt
= aic3x_set_dai_fmt
,
1018 EXPORT_SYMBOL_GPL(aic3x_dai
);
1020 static int aic3x_suspend(struct platform_device
*pdev
, pm_message_t state
)
1022 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1023 struct snd_soc_codec
*codec
= socdev
->codec
;
1025 aic3x_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1030 static int aic3x_resume(struct platform_device
*pdev
)
1032 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1033 struct snd_soc_codec
*codec
= socdev
->codec
;
1036 u8
*cache
= codec
->reg_cache
;
1038 /* Sync reg_cache with the hardware */
1039 for (i
= 0; i
< ARRAY_SIZE(aic3x_reg
); i
++) {
1042 codec
->hw_write(codec
->control_data
, data
, 2);
1045 aic3x_set_bias_level(codec
, codec
->suspend_bias_level
);
1051 * initialise the AIC3X driver
1052 * register the mixer and dsp interfaces with the kernel
1054 static int aic3x_init(struct snd_soc_device
*socdev
)
1056 struct snd_soc_codec
*codec
= socdev
->codec
;
1057 struct aic3x_setup_data
*setup
= socdev
->codec_data
;
1060 codec
->name
= "tlv320aic3x";
1061 codec
->owner
= THIS_MODULE
;
1062 codec
->read
= aic3x_read_reg_cache
;
1063 codec
->write
= aic3x_write
;
1064 codec
->set_bias_level
= aic3x_set_bias_level
;
1065 codec
->dai
= &aic3x_dai
;
1067 codec
->reg_cache_size
= ARRAY_SIZE(aic3x_reg
);
1068 codec
->reg_cache
= kmemdup(aic3x_reg
, sizeof(aic3x_reg
), GFP_KERNEL
);
1069 if (codec
->reg_cache
== NULL
)
1072 aic3x_write(codec
, AIC3X_PAGE_SELECT
, PAGE0_SELECT
);
1073 aic3x_write(codec
, AIC3X_RESET
, SOFT_RESET
);
1076 ret
= snd_soc_new_pcms(socdev
, SNDRV_DEFAULT_IDX1
, SNDRV_DEFAULT_STR1
);
1078 printk(KERN_ERR
"aic3x: failed to create pcms\n");
1082 /* DAC default volume and mute */
1083 aic3x_write(codec
, LDAC_VOL
, DEFAULT_VOL
| MUTE_ON
);
1084 aic3x_write(codec
, RDAC_VOL
, DEFAULT_VOL
| MUTE_ON
);
1086 /* DAC to HP default volume and route to Output mixer */
1087 aic3x_write(codec
, DACL1_2_HPLOUT_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1088 aic3x_write(codec
, DACR1_2_HPROUT_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1089 aic3x_write(codec
, DACL1_2_HPLCOM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1090 aic3x_write(codec
, DACR1_2_HPRCOM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1091 /* DAC to Line Out default volume and route to Output mixer */
1092 aic3x_write(codec
, DACL1_2_LLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1093 aic3x_write(codec
, DACR1_2_RLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1094 /* DAC to Mono Line Out default volume and route to Output mixer */
1095 aic3x_write(codec
, DACL1_2_MONOLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1096 aic3x_write(codec
, DACR1_2_MONOLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1098 /* unmute all outputs */
1099 reg
= aic3x_read_reg_cache(codec
, LLOPM_CTRL
);
1100 aic3x_write(codec
, LLOPM_CTRL
, reg
| UNMUTE
);
1101 reg
= aic3x_read_reg_cache(codec
, RLOPM_CTRL
);
1102 aic3x_write(codec
, RLOPM_CTRL
, reg
| UNMUTE
);
1103 reg
= aic3x_read_reg_cache(codec
, MONOLOPM_CTRL
);
1104 aic3x_write(codec
, MONOLOPM_CTRL
, reg
| UNMUTE
);
1105 reg
= aic3x_read_reg_cache(codec
, HPLOUT_CTRL
);
1106 aic3x_write(codec
, HPLOUT_CTRL
, reg
| UNMUTE
);
1107 reg
= aic3x_read_reg_cache(codec
, HPROUT_CTRL
);
1108 aic3x_write(codec
, HPROUT_CTRL
, reg
| UNMUTE
);
1109 reg
= aic3x_read_reg_cache(codec
, HPLCOM_CTRL
);
1110 aic3x_write(codec
, HPLCOM_CTRL
, reg
| UNMUTE
);
1111 reg
= aic3x_read_reg_cache(codec
, HPRCOM_CTRL
);
1112 aic3x_write(codec
, HPRCOM_CTRL
, reg
| UNMUTE
);
1114 /* ADC default volume and unmute */
1115 aic3x_write(codec
, LADC_VOL
, DEFAULT_GAIN
);
1116 aic3x_write(codec
, RADC_VOL
, DEFAULT_GAIN
);
1117 /* By default route Line1 to ADC PGA mixer */
1118 aic3x_write(codec
, LINE1L_2_LADC_CTRL
, 0x0);
1119 aic3x_write(codec
, LINE1R_2_RADC_CTRL
, 0x0);
1121 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1122 aic3x_write(codec
, PGAL_2_HPLOUT_VOL
, DEFAULT_VOL
);
1123 aic3x_write(codec
, PGAR_2_HPROUT_VOL
, DEFAULT_VOL
);
1124 aic3x_write(codec
, PGAL_2_HPLCOM_VOL
, DEFAULT_VOL
);
1125 aic3x_write(codec
, PGAR_2_HPRCOM_VOL
, DEFAULT_VOL
);
1126 /* PGA to Line Out default volume, disconnect from Output Mixer */
1127 aic3x_write(codec
, PGAL_2_LLOPM_VOL
, DEFAULT_VOL
);
1128 aic3x_write(codec
, PGAR_2_RLOPM_VOL
, DEFAULT_VOL
);
1129 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1130 aic3x_write(codec
, PGAL_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1131 aic3x_write(codec
, PGAR_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1133 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1134 aic3x_write(codec
, LINE2L_2_HPLOUT_VOL
, DEFAULT_VOL
);
1135 aic3x_write(codec
, LINE2R_2_HPROUT_VOL
, DEFAULT_VOL
);
1136 aic3x_write(codec
, LINE2L_2_HPLCOM_VOL
, DEFAULT_VOL
);
1137 aic3x_write(codec
, LINE2R_2_HPRCOM_VOL
, DEFAULT_VOL
);
1138 /* Line2 Line Out default volume, disconnect from Output Mixer */
1139 aic3x_write(codec
, LINE2L_2_LLOPM_VOL
, DEFAULT_VOL
);
1140 aic3x_write(codec
, LINE2R_2_RLOPM_VOL
, DEFAULT_VOL
);
1141 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1142 aic3x_write(codec
, LINE2L_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1143 aic3x_write(codec
, LINE2R_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1145 /* off, with power on */
1146 aic3x_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1148 /* setup GPIO functions */
1149 aic3x_write(codec
, AIC3X_GPIO1_REG
, (setup
->gpio_func
[0] & 0xf) << 4);
1150 aic3x_write(codec
, AIC3X_GPIO2_REG
, (setup
->gpio_func
[1] & 0xf) << 4);
1152 aic3x_add_controls(codec
);
1153 aic3x_add_widgets(codec
);
1154 ret
= snd_soc_register_card(socdev
);
1156 printk(KERN_ERR
"aic3x: failed to register card\n");
1163 snd_soc_free_pcms(socdev
);
1164 snd_soc_dapm_free(socdev
);
1166 kfree(codec
->reg_cache
);
1170 static struct snd_soc_device
*aic3x_socdev
;
1172 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1174 * AIC3X 2 wire address can be up to 4 devices with device addresses
1175 * 0x18, 0x19, 0x1A, 0x1B
1179 * If the i2c layer weren't so broken, we could pass this kind of data
1182 static int aic3x_i2c_probe(struct i2c_client
*i2c
,
1183 const struct i2c_device_id
*id
)
1185 struct snd_soc_device
*socdev
= aic3x_socdev
;
1186 struct snd_soc_codec
*codec
= socdev
->codec
;
1189 i2c_set_clientdata(i2c
, codec
);
1190 codec
->control_data
= i2c
;
1192 ret
= aic3x_init(socdev
);
1194 printk(KERN_ERR
"aic3x: failed to initialise AIC3X\n");
1198 static int aic3x_i2c_remove(struct i2c_client
*client
)
1200 struct snd_soc_codec
*codec
= i2c_get_clientdata(client
);
1201 kfree(codec
->reg_cache
);
1205 static const struct i2c_device_id aic3x_i2c_id
[] = {
1206 { "tlv320aic3x", 0 },
1209 MODULE_DEVICE_TABLE(i2c
, aic3x_i2c_id
);
1211 /* machine i2c codec control layer */
1212 static struct i2c_driver aic3x_i2c_driver
= {
1214 .name
= "aic3x I2C Codec",
1215 .owner
= THIS_MODULE
,
1217 .probe
= aic3x_i2c_probe
,
1218 .remove
= aic3x_i2c_remove
,
1219 .id_table
= aic3x_i2c_id
,
1222 static int aic3x_i2c_read(struct i2c_client
*client
, u8
*value
, int len
)
1224 value
[0] = i2c_smbus_read_byte_data(client
, value
[0]);
1228 static int aic3x_add_i2c_device(struct platform_device
*pdev
,
1229 const struct aic3x_setup_data
*setup
)
1231 struct i2c_board_info info
;
1232 struct i2c_adapter
*adapter
;
1233 struct i2c_client
*client
;
1236 ret
= i2c_add_driver(&aic3x_i2c_driver
);
1238 dev_err(&pdev
->dev
, "can't add i2c driver\n");
1242 memset(&info
, 0, sizeof(struct i2c_board_info
));
1243 info
.addr
= setup
->i2c_address
;
1244 strlcpy(info
.type
, "tlv320aic3x", I2C_NAME_SIZE
);
1246 adapter
= i2c_get_adapter(setup
->i2c_bus
);
1248 dev_err(&pdev
->dev
, "can't get i2c adapter %d\n",
1253 client
= i2c_new_device(adapter
, &info
);
1254 i2c_put_adapter(adapter
);
1256 dev_err(&pdev
->dev
, "can't add i2c device at 0x%x\n",
1257 (unsigned int)info
.addr
);
1264 i2c_del_driver(&aic3x_i2c_driver
);
1269 static int aic3x_probe(struct platform_device
*pdev
)
1271 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1272 struct aic3x_setup_data
*setup
;
1273 struct snd_soc_codec
*codec
;
1274 struct aic3x_priv
*aic3x
;
1277 printk(KERN_INFO
"AIC3X Audio Codec %s\n", AIC3X_VERSION
);
1279 setup
= socdev
->codec_data
;
1280 codec
= kzalloc(sizeof(struct snd_soc_codec
), GFP_KERNEL
);
1284 aic3x
= kzalloc(sizeof(struct aic3x_priv
), GFP_KERNEL
);
1285 if (aic3x
== NULL
) {
1290 codec
->private_data
= aic3x
;
1291 socdev
->codec
= codec
;
1292 mutex_init(&codec
->mutex
);
1293 INIT_LIST_HEAD(&codec
->dapm_widgets
);
1294 INIT_LIST_HEAD(&codec
->dapm_paths
);
1296 aic3x_socdev
= socdev
;
1297 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1298 if (setup
->i2c_address
) {
1299 codec
->hw_write
= (hw_write_t
) i2c_master_send
;
1300 codec
->hw_read
= (hw_read_t
) aic3x_i2c_read
;
1301 ret
= aic3x_add_i2c_device(pdev
, setup
);
1304 /* Add other interfaces here */
1308 kfree(codec
->private_data
);
1314 static int aic3x_remove(struct platform_device
*pdev
)
1316 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1317 struct snd_soc_codec
*codec
= socdev
->codec
;
1319 /* power down chip */
1320 if (codec
->control_data
)
1321 aic3x_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1323 snd_soc_free_pcms(socdev
);
1324 snd_soc_dapm_free(socdev
);
1325 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1326 i2c_unregister_device(codec
->control_data
);
1327 i2c_del_driver(&aic3x_i2c_driver
);
1329 kfree(codec
->private_data
);
1335 struct snd_soc_codec_device soc_codec_dev_aic3x
= {
1336 .probe
= aic3x_probe
,
1337 .remove
= aic3x_remove
,
1338 .suspend
= aic3x_suspend
,
1339 .resume
= aic3x_resume
,
1341 EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x
);
1343 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1344 MODULE_AUTHOR("Vladimir Barinov");
1345 MODULE_LICENSE("GPL");