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ASoC: Decouple DAPM from CODECs
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / tlv320aic3x.c
1 /*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33, aic3007.
16 *
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
33 */
34
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/pm.h>
40 #include <linux/i2c.h>
41 #include <linux/gpio.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/platform_device.h>
44 #include <linux/slab.h>
45 #include <sound/core.h>
46 #include <sound/pcm.h>
47 #include <sound/pcm_params.h>
48 #include <sound/soc.h>
49 #include <sound/soc-dapm.h>
50 #include <sound/initval.h>
51 #include <sound/tlv.h>
52 #include <sound/tlv320aic3x.h>
53
54 #include "tlv320aic3x.h"
55
56 #define AIC3X_NUM_SUPPLIES 4
57 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
58 "IOVDD", /* I/O Voltage */
59 "DVDD", /* Digital Core Voltage */
60 "AVDD", /* Analog DAC Voltage */
61 "DRVDD", /* ADC Analog and Output Driver Voltage */
62 };
63
64 struct aic3x_priv;
65
66 struct aic3x_disable_nb {
67 struct notifier_block nb;
68 struct aic3x_priv *aic3x;
69 };
70
71 /* codec private data */
72 struct aic3x_priv {
73 struct snd_soc_codec *codec;
74 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
75 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
76 enum snd_soc_control_type control_type;
77 struct aic3x_setup_data *setup;
78 void *control_data;
79 unsigned int sysclk;
80 int master;
81 int gpio_reset;
82 int power;
83 #define AIC3X_MODEL_3X 0
84 #define AIC3X_MODEL_33 1
85 #define AIC3X_MODEL_3007 2
86 u16 model;
87 };
88
89 /*
90 * AIC3X register cache
91 * We can't read the AIC3X register space when we are
92 * using 2 wire for device control, so we cache them instead.
93 * There is no point in caching the reset register
94 */
95 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
96 0x00, 0x00, 0x00, 0x10, /* 0 */
97 0x04, 0x00, 0x00, 0x00, /* 4 */
98 0x00, 0x00, 0x00, 0x01, /* 8 */
99 0x00, 0x00, 0x00, 0x80, /* 12 */
100 0x80, 0xff, 0xff, 0x78, /* 16 */
101 0x78, 0x78, 0x78, 0x78, /* 20 */
102 0x78, 0x00, 0x00, 0xfe, /* 24 */
103 0x00, 0x00, 0xfe, 0x00, /* 28 */
104 0x18, 0x18, 0x00, 0x00, /* 32 */
105 0x00, 0x00, 0x00, 0x00, /* 36 */
106 0x00, 0x00, 0x00, 0x80, /* 40 */
107 0x80, 0x00, 0x00, 0x00, /* 44 */
108 0x00, 0x00, 0x00, 0x04, /* 48 */
109 0x00, 0x00, 0x00, 0x00, /* 52 */
110 0x00, 0x00, 0x04, 0x00, /* 56 */
111 0x00, 0x00, 0x00, 0x00, /* 60 */
112 0x00, 0x04, 0x00, 0x00, /* 64 */
113 0x00, 0x00, 0x00, 0x00, /* 68 */
114 0x04, 0x00, 0x00, 0x00, /* 72 */
115 0x00, 0x00, 0x00, 0x00, /* 76 */
116 0x00, 0x00, 0x00, 0x00, /* 80 */
117 0x00, 0x00, 0x00, 0x00, /* 84 */
118 0x00, 0x00, 0x00, 0x00, /* 88 */
119 0x00, 0x00, 0x00, 0x00, /* 92 */
120 0x00, 0x00, 0x00, 0x00, /* 96 */
121 0x00, 0x00, 0x02, /* 100 */
122 };
123
124 /*
125 * read from the aic3x register space. Only use for this function is if
126 * wanting to read volatile bits from those registers that has both read-only
127 * and read/write bits. All other cases should use snd_soc_read.
128 */
129 static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
130 u8 *value)
131 {
132 u8 *cache = codec->reg_cache;
133
134 if (codec->cache_only)
135 return -EINVAL;
136 if (reg >= AIC3X_CACHEREGNUM)
137 return -1;
138
139 *value = codec->hw_read(codec, reg);
140 cache[reg] = *value;
141
142 return 0;
143 }
144
145 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
146 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
147 .info = snd_soc_info_volsw, \
148 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
149 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
150
151 /*
152 * All input lines are connected when !0xf and disconnected with 0xf bit field,
153 * so we have to use specific dapm_put call for input mixer
154 */
155 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
156 struct snd_ctl_elem_value *ucontrol)
157 {
158 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
159 struct soc_mixer_control *mc =
160 (struct soc_mixer_control *)kcontrol->private_value;
161 unsigned int reg = mc->reg;
162 unsigned int shift = mc->shift;
163 int max = mc->max;
164 unsigned int mask = (1 << fls(max)) - 1;
165 unsigned int invert = mc->invert;
166 unsigned short val, val_mask;
167 int ret;
168 struct snd_soc_dapm_path *path;
169 int found = 0;
170
171 val = (ucontrol->value.integer.value[0] & mask);
172
173 mask = 0xf;
174 if (val)
175 val = mask;
176
177 if (invert)
178 val = mask - val;
179 val_mask = mask << shift;
180 val = val << shift;
181
182 mutex_lock(&widget->codec->mutex);
183
184 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
185 /* find dapm widget path assoc with kcontrol */
186 list_for_each_entry(path, &widget->dapm->paths, list) {
187 if (path->kcontrol != kcontrol)
188 continue;
189
190 /* found, now check type */
191 found = 1;
192 if (val)
193 /* new connection */
194 path->connect = invert ? 0 : 1;
195 else
196 /* old connection must be powered down */
197 path->connect = invert ? 1 : 0;
198 break;
199 }
200
201 if (found)
202 snd_soc_dapm_sync(widget->dapm);
203 }
204
205 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
206
207 mutex_unlock(&widget->codec->mutex);
208 return ret;
209 }
210
211 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
212 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
213 static const char *aic3x_left_hpcom_mux[] =
214 { "differential of HPLOUT", "constant VCM", "single-ended" };
215 static const char *aic3x_right_hpcom_mux[] =
216 { "differential of HPROUT", "constant VCM", "single-ended",
217 "differential of HPLCOM", "external feedback" };
218 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
219 static const char *aic3x_adc_hpf[] =
220 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
221
222 #define LDAC_ENUM 0
223 #define RDAC_ENUM 1
224 #define LHPCOM_ENUM 2
225 #define RHPCOM_ENUM 3
226 #define LINE1L_ENUM 4
227 #define LINE1R_ENUM 5
228 #define LINE2L_ENUM 6
229 #define LINE2R_ENUM 7
230 #define ADC_HPF_ENUM 8
231
232 static const struct soc_enum aic3x_enum[] = {
233 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
234 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
235 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
236 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
237 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
238 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
239 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
240 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
241 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
242 };
243
244 /*
245 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
246 */
247 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
248 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
249 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
250 /*
251 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
252 * Step size is approximately 0.5 dB over most of the scale but increasing
253 * near the very low levels.
254 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
255 * but having increasing dB difference below that (and where it doesn't count
256 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
257 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
258 */
259 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
260
261 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
262 /* Output */
263 SOC_DOUBLE_R_TLV("PCM Playback Volume",
264 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
265
266 /*
267 * Output controls that map to output mixer switches. Note these are
268 * only for swapped L-to-R and R-to-L routes. See below stereo controls
269 * for direct L-to-L and R-to-R routes.
270 */
271 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
272 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
273 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
274 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
275 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
276 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
277
278 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
279 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
280 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
281 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
282 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
283 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
284
285 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
286 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
287 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
288 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
289 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
290 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
291
292 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
293 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
294 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
295 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
296 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
297 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
298
299 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
300 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
301 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
302 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
303 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
304 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
305
306 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
307 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
308 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
309 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
310 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
311 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
312
313 /* Stereo output controls for direct L-to-L and R-to-R routes */
314 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
315 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
316 0, 118, 1, output_stage_tlv),
317 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
318 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
319 0, 118, 1, output_stage_tlv),
320 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
321 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
322 0, 118, 1, output_stage_tlv),
323
324 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
325 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
326 0, 118, 1, output_stage_tlv),
327 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
328 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
329 0, 118, 1, output_stage_tlv),
330 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
331 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
332 0, 118, 1, output_stage_tlv),
333
334 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
335 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
336 0, 118, 1, output_stage_tlv),
337 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
338 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
339 0, 118, 1, output_stage_tlv),
340 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
341 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
342 0, 118, 1, output_stage_tlv),
343
344 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
345 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
346 0, 118, 1, output_stage_tlv),
347 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
348 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
349 0, 118, 1, output_stage_tlv),
350 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
351 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
352 0, 118, 1, output_stage_tlv),
353
354 /* Output pin mute controls */
355 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
356 0x01, 0),
357 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
358 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
359 0x01, 0),
360 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
361 0x01, 0),
362
363 /*
364 * Note: enable Automatic input Gain Controller with care. It can
365 * adjust PGA to max value when ADC is on and will never go back.
366 */
367 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
368
369 /* Input */
370 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
371 0, 119, 0, adc_tlv),
372 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
373
374 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
375 };
376
377 /*
378 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
379 */
380 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
381
382 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
383 SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
384
385 /* Left DAC Mux */
386 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
387 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
388
389 /* Right DAC Mux */
390 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
391 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
392
393 /* Left HPCOM Mux */
394 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
395 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
396
397 /* Right HPCOM Mux */
398 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
399 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
400
401 /* Left Line Mixer */
402 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
403 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
404 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
405 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
406 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
407 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
408 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
409 };
410
411 /* Right Line Mixer */
412 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
413 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
414 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
415 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
416 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
417 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
418 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
419 };
420
421 /* Mono Mixer */
422 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
423 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
424 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
425 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
426 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
427 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
428 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
429 };
430
431 /* Left HP Mixer */
432 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
433 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
434 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
435 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
436 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
437 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
438 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
439 };
440
441 /* Right HP Mixer */
442 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
443 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
444 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
445 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
446 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
447 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
448 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
449 };
450
451 /* Left HPCOM Mixer */
452 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
453 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
454 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
455 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
456 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
457 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
458 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
459 };
460
461 /* Right HPCOM Mixer */
462 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
463 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
464 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
465 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
466 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
467 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
468 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
469 };
470
471 /* Left PGA Mixer */
472 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
473 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
474 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
475 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
476 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
477 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
478 };
479
480 /* Right PGA Mixer */
481 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
482 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
483 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
484 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
485 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
486 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
487 };
488
489 /* Left Line1 Mux */
490 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
491 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
492
493 /* Right Line1 Mux */
494 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
495 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
496
497 /* Left Line2 Mux */
498 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
499 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
500
501 /* Right Line2 Mux */
502 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
503 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
504
505 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
506 /* Left DAC to Left Outputs */
507 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
508 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
509 &aic3x_left_dac_mux_controls),
510 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
511 &aic3x_left_hpcom_mux_controls),
512 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
513 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
514 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
515
516 /* Right DAC to Right Outputs */
517 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
518 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
519 &aic3x_right_dac_mux_controls),
520 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
521 &aic3x_right_hpcom_mux_controls),
522 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
523 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
524 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
525
526 /* Mono Output */
527 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
528
529 /* Inputs to Left ADC */
530 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
531 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
532 &aic3x_left_pga_mixer_controls[0],
533 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
534 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
535 &aic3x_left_line1_mux_controls),
536 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
537 &aic3x_left_line1_mux_controls),
538 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
539 &aic3x_left_line2_mux_controls),
540
541 /* Inputs to Right ADC */
542 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
543 LINE1R_2_RADC_CTRL, 2, 0),
544 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
545 &aic3x_right_pga_mixer_controls[0],
546 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
547 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
548 &aic3x_right_line1_mux_controls),
549 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
550 &aic3x_right_line1_mux_controls),
551 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
552 &aic3x_right_line2_mux_controls),
553
554 /*
555 * Not a real mic bias widget but similar function. This is for dynamic
556 * control of GPIO1 digital mic modulator clock output function when
557 * using digital mic.
558 */
559 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
560 AIC3X_GPIO1_REG, 4, 0xf,
561 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
562 AIC3X_GPIO1_FUNC_DISABLED),
563
564 /*
565 * Also similar function like mic bias. Selects digital mic with
566 * configurable oversampling rate instead of ADC converter.
567 */
568 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
569 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
570 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
571 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
572 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
573 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
574
575 /* Mic Bias */
576 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
577 MICBIAS_CTRL, 6, 3, 1, 0),
578 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
579 MICBIAS_CTRL, 6, 3, 2, 0),
580 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
581 MICBIAS_CTRL, 6, 3, 3, 0),
582
583 /* Output mixers */
584 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
585 &aic3x_left_line_mixer_controls[0],
586 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
587 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
588 &aic3x_right_line_mixer_controls[0],
589 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
590 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
591 &aic3x_mono_mixer_controls[0],
592 ARRAY_SIZE(aic3x_mono_mixer_controls)),
593 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
594 &aic3x_left_hp_mixer_controls[0],
595 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
596 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
597 &aic3x_right_hp_mixer_controls[0],
598 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
599 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
600 &aic3x_left_hpcom_mixer_controls[0],
601 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
602 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
603 &aic3x_right_hpcom_mixer_controls[0],
604 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
605
606 SND_SOC_DAPM_OUTPUT("LLOUT"),
607 SND_SOC_DAPM_OUTPUT("RLOUT"),
608 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
609 SND_SOC_DAPM_OUTPUT("HPLOUT"),
610 SND_SOC_DAPM_OUTPUT("HPROUT"),
611 SND_SOC_DAPM_OUTPUT("HPLCOM"),
612 SND_SOC_DAPM_OUTPUT("HPRCOM"),
613
614 SND_SOC_DAPM_INPUT("MIC3L"),
615 SND_SOC_DAPM_INPUT("MIC3R"),
616 SND_SOC_DAPM_INPUT("LINE1L"),
617 SND_SOC_DAPM_INPUT("LINE1R"),
618 SND_SOC_DAPM_INPUT("LINE2L"),
619 SND_SOC_DAPM_INPUT("LINE2R"),
620
621 /*
622 * Virtual output pin to detection block inside codec. This can be
623 * used to keep codec bias on if gpio or detection features are needed.
624 * Force pin on or construct a path with an input jack and mic bias
625 * widgets.
626 */
627 SND_SOC_DAPM_OUTPUT("Detection"),
628 };
629
630 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
631 /* Class-D outputs */
632 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
633 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
634
635 SND_SOC_DAPM_OUTPUT("SPOP"),
636 SND_SOC_DAPM_OUTPUT("SPOM"),
637 };
638
639 static const struct snd_soc_dapm_route intercon[] = {
640 /* Left Input */
641 {"Left Line1L Mux", "single-ended", "LINE1L"},
642 {"Left Line1L Mux", "differential", "LINE1L"},
643
644 {"Left Line2L Mux", "single-ended", "LINE2L"},
645 {"Left Line2L Mux", "differential", "LINE2L"},
646
647 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
648 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
649 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
650 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
651 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
652
653 {"Left ADC", NULL, "Left PGA Mixer"},
654 {"Left ADC", NULL, "GPIO1 dmic modclk"},
655
656 /* Right Input */
657 {"Right Line1R Mux", "single-ended", "LINE1R"},
658 {"Right Line1R Mux", "differential", "LINE1R"},
659
660 {"Right Line2R Mux", "single-ended", "LINE2R"},
661 {"Right Line2R Mux", "differential", "LINE2R"},
662
663 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
664 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
665 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
666 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
667 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
668
669 {"Right ADC", NULL, "Right PGA Mixer"},
670 {"Right ADC", NULL, "GPIO1 dmic modclk"},
671
672 /*
673 * Logical path between digital mic enable and GPIO1 modulator clock
674 * output function
675 */
676 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
677 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
678 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
679
680 /* Left DAC Output */
681 {"Left DAC Mux", "DAC_L1", "Left DAC"},
682 {"Left DAC Mux", "DAC_L2", "Left DAC"},
683 {"Left DAC Mux", "DAC_L3", "Left DAC"},
684
685 /* Right DAC Output */
686 {"Right DAC Mux", "DAC_R1", "Right DAC"},
687 {"Right DAC Mux", "DAC_R2", "Right DAC"},
688 {"Right DAC Mux", "DAC_R3", "Right DAC"},
689
690 /* Left Line Output */
691 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
692 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
693 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
694 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
695 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
696 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
697
698 {"Left Line Out", NULL, "Left Line Mixer"},
699 {"Left Line Out", NULL, "Left DAC Mux"},
700 {"LLOUT", NULL, "Left Line Out"},
701
702 /* Right Line Output */
703 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
704 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
705 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
706 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
707 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
708 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
709
710 {"Right Line Out", NULL, "Right Line Mixer"},
711 {"Right Line Out", NULL, "Right DAC Mux"},
712 {"RLOUT", NULL, "Right Line Out"},
713
714 /* Mono Output */
715 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
716 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
717 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
718 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
719 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
720 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
721
722 {"Mono Out", NULL, "Mono Mixer"},
723 {"MONO_LOUT", NULL, "Mono Out"},
724
725 /* Left HP Output */
726 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
727 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
728 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
729 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
730 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
731 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
732
733 {"Left HP Out", NULL, "Left HP Mixer"},
734 {"Left HP Out", NULL, "Left DAC Mux"},
735 {"HPLOUT", NULL, "Left HP Out"},
736
737 /* Right HP Output */
738 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
739 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
740 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
741 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
742 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
743 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
744
745 {"Right HP Out", NULL, "Right HP Mixer"},
746 {"Right HP Out", NULL, "Right DAC Mux"},
747 {"HPROUT", NULL, "Right HP Out"},
748
749 /* Left HPCOM Output */
750 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
751 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
752 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
753 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
754 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
755 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
756
757 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
758 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
759 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
760 {"Left HP Com", NULL, "Left HPCOM Mux"},
761 {"HPLCOM", NULL, "Left HP Com"},
762
763 /* Right HPCOM Output */
764 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
765 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
766 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
767 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
768 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
769 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
770
771 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
772 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
773 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
774 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
775 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
776 {"Right HP Com", NULL, "Right HPCOM Mux"},
777 {"HPRCOM", NULL, "Right HP Com"},
778 };
779
780 static const struct snd_soc_dapm_route intercon_3007[] = {
781 /* Class-D outputs */
782 {"Left Class-D Out", NULL, "Left Line Out"},
783 {"Right Class-D Out", NULL, "Left Line Out"},
784 {"SPOP", NULL, "Left Class-D Out"},
785 {"SPOM", NULL, "Right Class-D Out"},
786 };
787
788 static int aic3x_add_widgets(struct snd_soc_codec *codec)
789 {
790 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
791 struct snd_soc_dapm_context *dapm = &codec->dapm;
792
793 snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
794 ARRAY_SIZE(aic3x_dapm_widgets));
795
796 /* set up audio path interconnects */
797 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
798
799 if (aic3x->model == AIC3X_MODEL_3007) {
800 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
801 ARRAY_SIZE(aic3007_dapm_widgets));
802 snd_soc_dapm_add_routes(dapm, intercon_3007,
803 ARRAY_SIZE(intercon_3007));
804 }
805
806 return 0;
807 }
808
809 static int aic3x_hw_params(struct snd_pcm_substream *substream,
810 struct snd_pcm_hw_params *params,
811 struct snd_soc_dai *dai)
812 {
813 struct snd_soc_pcm_runtime *rtd = substream->private_data;
814 struct snd_soc_codec *codec =rtd->codec;
815 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
816 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
817 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
818 u16 d, pll_d = 1;
819 u8 reg;
820 int clk;
821
822 /* select data word length */
823 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
824 switch (params_format(params)) {
825 case SNDRV_PCM_FORMAT_S16_LE:
826 break;
827 case SNDRV_PCM_FORMAT_S20_3LE:
828 data |= (0x01 << 4);
829 break;
830 case SNDRV_PCM_FORMAT_S24_LE:
831 data |= (0x02 << 4);
832 break;
833 case SNDRV_PCM_FORMAT_S32_LE:
834 data |= (0x03 << 4);
835 break;
836 }
837 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
838
839 /* Fsref can be 44100 or 48000 */
840 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
841
842 /* Try to find a value for Q which allows us to bypass the PLL and
843 * generate CODEC_CLK directly. */
844 for (pll_q = 2; pll_q < 18; pll_q++)
845 if (aic3x->sysclk / (128 * pll_q) == fsref) {
846 bypass_pll = 1;
847 break;
848 }
849
850 if (bypass_pll) {
851 pll_q &= 0xf;
852 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
853 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
854 /* disable PLL if it is bypassed */
855 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
856 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
857
858 } else {
859 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
860 /* enable PLL when it is used */
861 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
862 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
863 }
864
865 /* Route Left DAC to left channel input and
866 * right DAC to right channel input */
867 data = (LDAC2LCH | RDAC2RCH);
868 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
869 if (params_rate(params) >= 64000)
870 data |= DUAL_RATE_MODE;
871 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
872
873 /* codec sample rate select */
874 data = (fsref * 20) / params_rate(params);
875 if (params_rate(params) < 64000)
876 data /= 2;
877 data /= 5;
878 data -= 2;
879 data |= (data << 4);
880 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
881
882 if (bypass_pll)
883 return 0;
884
885 /* Use PLL, compute apropriate setup for j, d, r and p, the closest
886 * one wins the game. Try with d==0 first, next with d!=0.
887 * Constraints for j are according to the datasheet.
888 * The sysclk is divided by 1000 to prevent integer overflows.
889 */
890
891 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
892
893 for (r = 1; r <= 16; r++)
894 for (p = 1; p <= 8; p++) {
895 for (j = 4; j <= 55; j++) {
896 /* This is actually 1000*((j+(d/10000))*r)/p
897 * The term had to be converted to get
898 * rid of the division by 10000; d = 0 here
899 */
900 int tmp_clk = (1000 * j * r) / p;
901
902 /* Check whether this values get closer than
903 * the best ones we had before
904 */
905 if (abs(codec_clk - tmp_clk) <
906 abs(codec_clk - last_clk)) {
907 pll_j = j; pll_d = 0;
908 pll_r = r; pll_p = p;
909 last_clk = tmp_clk;
910 }
911
912 /* Early exit for exact matches */
913 if (tmp_clk == codec_clk)
914 goto found;
915 }
916 }
917
918 /* try with d != 0 */
919 for (p = 1; p <= 8; p++) {
920 j = codec_clk * p / 1000;
921
922 if (j < 4 || j > 11)
923 continue;
924
925 /* do not use codec_clk here since we'd loose precision */
926 d = ((2048 * p * fsref) - j * aic3x->sysclk)
927 * 100 / (aic3x->sysclk/100);
928
929 clk = (10000 * j + d) / (10 * p);
930
931 /* check whether this values get closer than the best
932 * ones we had before */
933 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
934 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
935 last_clk = clk;
936 }
937
938 /* Early exit for exact matches */
939 if (clk == codec_clk)
940 goto found;
941 }
942
943 if (last_clk == 0) {
944 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
945 return -EINVAL;
946 }
947
948 found:
949 data = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
950 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
951 data | (pll_p << PLLP_SHIFT));
952 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
953 pll_r << PLLR_SHIFT);
954 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
955 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
956 (pll_d >> 6) << PLLD_MSB_SHIFT);
957 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
958 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
959
960 return 0;
961 }
962
963 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
964 {
965 struct snd_soc_codec *codec = dai->codec;
966 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
967 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
968
969 if (mute) {
970 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
971 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
972 } else {
973 snd_soc_write(codec, LDAC_VOL, ldac_reg);
974 snd_soc_write(codec, RDAC_VOL, rdac_reg);
975 }
976
977 return 0;
978 }
979
980 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
981 int clk_id, unsigned int freq, int dir)
982 {
983 struct snd_soc_codec *codec = codec_dai->codec;
984 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
985
986 aic3x->sysclk = freq;
987 return 0;
988 }
989
990 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
991 unsigned int fmt)
992 {
993 struct snd_soc_codec *codec = codec_dai->codec;
994 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
995 u8 iface_areg, iface_breg;
996 int delay = 0;
997
998 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
999 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
1000
1001 /* set master/slave audio interface */
1002 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1003 case SND_SOC_DAIFMT_CBM_CFM:
1004 aic3x->master = 1;
1005 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1006 break;
1007 case SND_SOC_DAIFMT_CBS_CFS:
1008 aic3x->master = 0;
1009 break;
1010 default:
1011 return -EINVAL;
1012 }
1013
1014 /*
1015 * match both interface format and signal polarities since they
1016 * are fixed
1017 */
1018 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1019 SND_SOC_DAIFMT_INV_MASK)) {
1020 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1021 break;
1022 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1023 delay = 1;
1024 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1025 iface_breg |= (0x01 << 6);
1026 break;
1027 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1028 iface_breg |= (0x02 << 6);
1029 break;
1030 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1031 iface_breg |= (0x03 << 6);
1032 break;
1033 default:
1034 return -EINVAL;
1035 }
1036
1037 /* set iface */
1038 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1039 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1040 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
1041
1042 return 0;
1043 }
1044
1045 static int aic3x_init_3007(struct snd_soc_codec *codec)
1046 {
1047 u8 tmp1, tmp2, *cache = codec->reg_cache;
1048
1049 /*
1050 * There is no need to cache writes to undocumented page 0xD but
1051 * respective page 0 register cache entries must be preserved
1052 */
1053 tmp1 = cache[0xD];
1054 tmp2 = cache[0x8];
1055 /* Class-D speaker driver init; datasheet p. 46 */
1056 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D);
1057 snd_soc_write(codec, 0xD, 0x0D);
1058 snd_soc_write(codec, 0x8, 0x5C);
1059 snd_soc_write(codec, 0x8, 0x5D);
1060 snd_soc_write(codec, 0x8, 0x5C);
1061 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00);
1062 cache[0xD] = tmp1;
1063 cache[0x8] = tmp2;
1064
1065 return 0;
1066 }
1067
1068 static int aic3x_regulator_event(struct notifier_block *nb,
1069 unsigned long event, void *data)
1070 {
1071 struct aic3x_disable_nb *disable_nb =
1072 container_of(nb, struct aic3x_disable_nb, nb);
1073 struct aic3x_priv *aic3x = disable_nb->aic3x;
1074
1075 if (event & REGULATOR_EVENT_DISABLE) {
1076 /*
1077 * Put codec to reset and require cache sync as at least one
1078 * of the supplies was disabled
1079 */
1080 if (aic3x->gpio_reset >= 0)
1081 gpio_set_value(aic3x->gpio_reset, 0);
1082 aic3x->codec->cache_sync = 1;
1083 }
1084
1085 return 0;
1086 }
1087
1088 static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1089 {
1090 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1091 int i, ret;
1092 u8 *cache = codec->reg_cache;
1093
1094 if (power) {
1095 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1096 aic3x->supplies);
1097 if (ret)
1098 goto out;
1099 aic3x->power = 1;
1100 /*
1101 * Reset release and cache sync is necessary only if some
1102 * supply was off or if there were cached writes
1103 */
1104 if (!codec->cache_sync)
1105 goto out;
1106
1107 if (aic3x->gpio_reset >= 0) {
1108 udelay(1);
1109 gpio_set_value(aic3x->gpio_reset, 1);
1110 }
1111
1112 /* Sync reg_cache with the hardware */
1113 codec->cache_only = 0;
1114 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++)
1115 snd_soc_write(codec, i, cache[i]);
1116 if (aic3x->model == AIC3X_MODEL_3007)
1117 aic3x_init_3007(codec);
1118 codec->cache_sync = 0;
1119 } else {
1120 aic3x->power = 0;
1121 /* HW writes are needless when bias is off */
1122 codec->cache_only = 1;
1123 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1124 aic3x->supplies);
1125 }
1126 out:
1127 return ret;
1128 }
1129
1130 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1131 enum snd_soc_bias_level level)
1132 {
1133 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1134 u8 reg;
1135
1136 switch (level) {
1137 case SND_SOC_BIAS_ON:
1138 break;
1139 case SND_SOC_BIAS_PREPARE:
1140 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
1141 aic3x->master) {
1142 /* enable pll */
1143 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
1144 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
1145 reg | PLL_ENABLE);
1146 }
1147 break;
1148 case SND_SOC_BIAS_STANDBY:
1149 if (!aic3x->power)
1150 aic3x_set_power(codec, 1);
1151 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
1152 aic3x->master) {
1153 /* disable pll */
1154 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
1155 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
1156 reg & ~PLL_ENABLE);
1157 }
1158 break;
1159 case SND_SOC_BIAS_OFF:
1160 if (aic3x->power)
1161 aic3x_set_power(codec, 0);
1162 break;
1163 }
1164 codec->dapm.bias_level = level;
1165
1166 return 0;
1167 }
1168
1169 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1170 {
1171 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1172 u8 bit = gpio ? 3: 0;
1173 u8 val = snd_soc_read(codec, reg) & ~(1 << bit);
1174 snd_soc_write(codec, reg, val | (!!state << bit));
1175 }
1176 EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1177
1178 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1179 {
1180 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1181 u8 val, bit = gpio ? 2: 1;
1182
1183 aic3x_read(codec, reg, &val);
1184 return (val >> bit) & 1;
1185 }
1186 EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1187
1188 void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1189 int headset_debounce, int button_debounce)
1190 {
1191 u8 val;
1192
1193 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1194 << AIC3X_HEADSET_DETECT_SHIFT) |
1195 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1196 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1197 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1198 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1199
1200 if (detect & AIC3X_HEADSET_DETECT_MASK)
1201 val |= AIC3X_HEADSET_DETECT_ENABLED;
1202
1203 snd_soc_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
1204 }
1205 EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1206
1207 int aic3x_headset_detected(struct snd_soc_codec *codec)
1208 {
1209 u8 val;
1210 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1211 return (val >> 4) & 1;
1212 }
1213 EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1214
1215 int aic3x_button_pressed(struct snd_soc_codec *codec)
1216 {
1217 u8 val;
1218 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1219 return (val >> 5) & 1;
1220 }
1221 EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1222
1223 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1224 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1225 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1226
1227 static struct snd_soc_dai_ops aic3x_dai_ops = {
1228 .hw_params = aic3x_hw_params,
1229 .digital_mute = aic3x_mute,
1230 .set_sysclk = aic3x_set_dai_sysclk,
1231 .set_fmt = aic3x_set_dai_fmt,
1232 };
1233
1234 static struct snd_soc_dai_driver aic3x_dai = {
1235 .name = "tlv320aic3x-hifi",
1236 .playback = {
1237 .stream_name = "Playback",
1238 .channels_min = 1,
1239 .channels_max = 2,
1240 .rates = AIC3X_RATES,
1241 .formats = AIC3X_FORMATS,},
1242 .capture = {
1243 .stream_name = "Capture",
1244 .channels_min = 1,
1245 .channels_max = 2,
1246 .rates = AIC3X_RATES,
1247 .formats = AIC3X_FORMATS,},
1248 .ops = &aic3x_dai_ops,
1249 .symmetric_rates = 1,
1250 };
1251
1252 static int aic3x_suspend(struct snd_soc_codec *codec, pm_message_t state)
1253 {
1254 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1255
1256 return 0;
1257 }
1258
1259 static int aic3x_resume(struct snd_soc_codec *codec)
1260 {
1261 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1262
1263 return 0;
1264 }
1265
1266 /*
1267 * initialise the AIC3X driver
1268 * register the mixer and dsp interfaces with the kernel
1269 */
1270 static int aic3x_init(struct snd_soc_codec *codec)
1271 {
1272 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1273 int reg;
1274
1275 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1276 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1277
1278 /* DAC default volume and mute */
1279 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1280 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1281
1282 /* DAC to HP default volume and route to Output mixer */
1283 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1284 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1285 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1286 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1287 /* DAC to Line Out default volume and route to Output mixer */
1288 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1289 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1290 /* DAC to Mono Line Out default volume and route to Output mixer */
1291 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1292 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1293
1294 /* unmute all outputs */
1295 reg = snd_soc_read(codec, LLOPM_CTRL);
1296 snd_soc_write(codec, LLOPM_CTRL, reg | UNMUTE);
1297 reg = snd_soc_read(codec, RLOPM_CTRL);
1298 snd_soc_write(codec, RLOPM_CTRL, reg | UNMUTE);
1299 reg = snd_soc_read(codec, MONOLOPM_CTRL);
1300 snd_soc_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1301 reg = snd_soc_read(codec, HPLOUT_CTRL);
1302 snd_soc_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1303 reg = snd_soc_read(codec, HPROUT_CTRL);
1304 snd_soc_write(codec, HPROUT_CTRL, reg | UNMUTE);
1305 reg = snd_soc_read(codec, HPLCOM_CTRL);
1306 snd_soc_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1307 reg = snd_soc_read(codec, HPRCOM_CTRL);
1308 snd_soc_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1309
1310 /* ADC default volume and unmute */
1311 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1312 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
1313 /* By default route Line1 to ADC PGA mixer */
1314 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1315 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1316
1317 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1318 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1319 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1320 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1321 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1322 /* PGA to Line Out default volume, disconnect from Output Mixer */
1323 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1324 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1325 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1326 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1327 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1328
1329 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1330 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1331 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1332 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1333 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1334 /* Line2 Line Out default volume, disconnect from Output Mixer */
1335 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1336 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1337 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1338 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1339 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1340
1341 if (aic3x->model == AIC3X_MODEL_3007) {
1342 aic3x_init_3007(codec);
1343 snd_soc_write(codec, CLASSD_CTRL, 0);
1344 }
1345
1346 return 0;
1347 }
1348
1349 static int aic3x_probe(struct snd_soc_codec *codec)
1350 {
1351 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1352 int ret, i;
1353
1354 codec->control_data = aic3x->control_data;
1355 aic3x->codec = codec;
1356 codec->dapm.idle_bias_off = 1;
1357
1358 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type);
1359 if (ret != 0) {
1360 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1361 return ret;
1362 }
1363
1364 if (aic3x->gpio_reset >= 0) {
1365 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1366 if (ret != 0)
1367 goto err_gpio;
1368 gpio_direction_output(aic3x->gpio_reset, 0);
1369 }
1370
1371 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1372 aic3x->supplies[i].supply = aic3x_supply_names[i];
1373
1374 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies),
1375 aic3x->supplies);
1376 if (ret != 0) {
1377 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1378 goto err_get;
1379 }
1380 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1381 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1382 aic3x->disable_nb[i].aic3x = aic3x;
1383 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1384 &aic3x->disable_nb[i].nb);
1385 if (ret) {
1386 dev_err(codec->dev,
1387 "Failed to request regulator notifier: %d\n",
1388 ret);
1389 goto err_notif;
1390 }
1391 }
1392
1393 codec->cache_only = 1;
1394 aic3x_init(codec);
1395
1396 if (aic3x->setup) {
1397 /* setup GPIO functions */
1398 snd_soc_write(codec, AIC3X_GPIO1_REG,
1399 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1400 snd_soc_write(codec, AIC3X_GPIO2_REG,
1401 (aic3x->setup->gpio_func[1] & 0xf) << 4);
1402 }
1403
1404 snd_soc_add_controls(codec, aic3x_snd_controls,
1405 ARRAY_SIZE(aic3x_snd_controls));
1406 if (aic3x->model == AIC3X_MODEL_3007)
1407 snd_soc_add_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
1408
1409 aic3x_add_widgets(codec);
1410
1411 return 0;
1412
1413 err_notif:
1414 while (i--)
1415 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1416 &aic3x->disable_nb[i].nb);
1417 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1418 err_get:
1419 if (aic3x->gpio_reset >= 0)
1420 gpio_free(aic3x->gpio_reset);
1421 err_gpio:
1422 kfree(aic3x);
1423 return ret;
1424 }
1425
1426 static int aic3x_remove(struct snd_soc_codec *codec)
1427 {
1428 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1429 int i;
1430
1431 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1432 if (aic3x->gpio_reset >= 0) {
1433 gpio_set_value(aic3x->gpio_reset, 0);
1434 gpio_free(aic3x->gpio_reset);
1435 }
1436 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1437 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1438 &aic3x->disable_nb[i].nb);
1439 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1440
1441 return 0;
1442 }
1443
1444 static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
1445 .set_bias_level = aic3x_set_bias_level,
1446 .reg_cache_size = ARRAY_SIZE(aic3x_reg),
1447 .reg_word_size = sizeof(u8),
1448 .reg_cache_default = aic3x_reg,
1449 .probe = aic3x_probe,
1450 .remove = aic3x_remove,
1451 .suspend = aic3x_suspend,
1452 .resume = aic3x_resume,
1453 };
1454
1455 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1456 /*
1457 * AIC3X 2 wire address can be up to 4 devices with device addresses
1458 * 0x18, 0x19, 0x1A, 0x1B
1459 */
1460
1461 static const struct i2c_device_id aic3x_i2c_id[] = {
1462 [AIC3X_MODEL_3X] = { "tlv320aic3x", 0 },
1463 [AIC3X_MODEL_33] = { "tlv320aic33", 0 },
1464 [AIC3X_MODEL_3007] = { "tlv320aic3007", 0 },
1465 { }
1466 };
1467 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1468
1469 /*
1470 * If the i2c layer weren't so broken, we could pass this kind of data
1471 * around
1472 */
1473 static int aic3x_i2c_probe(struct i2c_client *i2c,
1474 const struct i2c_device_id *id)
1475 {
1476 struct aic3x_pdata *pdata = i2c->dev.platform_data;
1477 struct aic3x_priv *aic3x;
1478 int ret;
1479 const struct i2c_device_id *tbl;
1480
1481 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1482 if (aic3x == NULL) {
1483 dev_err(&i2c->dev, "failed to create private data\n");
1484 return -ENOMEM;
1485 }
1486
1487 aic3x->control_data = i2c;
1488 aic3x->control_type = SND_SOC_I2C;
1489
1490 i2c_set_clientdata(i2c, aic3x);
1491 if (pdata) {
1492 aic3x->gpio_reset = pdata->gpio_reset;
1493 aic3x->setup = pdata->setup;
1494 } else {
1495 aic3x->gpio_reset = -1;
1496 }
1497
1498 for (tbl = aic3x_i2c_id; tbl->name[0]; tbl++) {
1499 if (!strcmp(tbl->name, id->name))
1500 break;
1501 }
1502 aic3x->model = tbl - aic3x_i2c_id;
1503
1504 ret = snd_soc_register_codec(&i2c->dev,
1505 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1506 if (ret < 0)
1507 kfree(aic3x);
1508 return ret;
1509 }
1510
1511 static int aic3x_i2c_remove(struct i2c_client *client)
1512 {
1513 snd_soc_unregister_codec(&client->dev);
1514 kfree(i2c_get_clientdata(client));
1515 return 0;
1516 }
1517
1518 /* machine i2c codec control layer */
1519 static struct i2c_driver aic3x_i2c_driver = {
1520 .driver = {
1521 .name = "tlv320aic3x-codec",
1522 .owner = THIS_MODULE,
1523 },
1524 .probe = aic3x_i2c_probe,
1525 .remove = aic3x_i2c_remove,
1526 .id_table = aic3x_i2c_id,
1527 };
1528
1529 static inline void aic3x_i2c_init(void)
1530 {
1531 int ret;
1532
1533 ret = i2c_add_driver(&aic3x_i2c_driver);
1534 if (ret)
1535 printk(KERN_ERR "%s: error regsitering i2c driver, %d\n",
1536 __func__, ret);
1537 }
1538
1539 static inline void aic3x_i2c_exit(void)
1540 {
1541 i2c_del_driver(&aic3x_i2c_driver);
1542 }
1543 #endif
1544
1545 static int __init aic3x_modinit(void)
1546 {
1547 int ret = 0;
1548 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1549 ret = i2c_add_driver(&aic3x_i2c_driver);
1550 if (ret != 0) {
1551 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n",
1552 ret);
1553 }
1554 #endif
1555 return ret;
1556 }
1557 module_init(aic3x_modinit);
1558
1559 static void __exit aic3x_exit(void)
1560 {
1561 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1562 i2c_del_driver(&aic3x_i2c_driver);
1563 #endif
1564 }
1565 module_exit(aic3x_exit);
1566
1567 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1568 MODULE_AUTHOR("Vladimir Barinov");
1569 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)