2 * ALSA SoC TLV320AIC3X codec driver
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33.
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 is as follows:
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
40 #include <linux/i2c.h>
41 #include <linux/platform_device.h>
42 #include <sound/core.h>
43 #include <sound/pcm.h>
44 #include <sound/pcm_params.h>
45 #include <sound/soc.h>
46 #include <sound/soc-dapm.h>
47 #include <sound/initval.h>
49 #include "tlv320aic3x.h"
51 #define AIC3X_VERSION "0.2"
53 /* codec private data */
60 * AIC3X register cache
61 * We can't read the AIC3X register space when we are
62 * using 2 wire for device control, so we cache them instead.
63 * There is no point in caching the reset register
65 static const u8 aic3x_reg
[AIC3X_CACHEREGNUM
] = {
66 0x00, 0x00, 0x00, 0x10, /* 0 */
67 0x04, 0x00, 0x00, 0x00, /* 4 */
68 0x00, 0x00, 0x00, 0x01, /* 8 */
69 0x00, 0x00, 0x00, 0x80, /* 12 */
70 0x80, 0xff, 0xff, 0x78, /* 16 */
71 0x78, 0x78, 0x78, 0x78, /* 20 */
72 0x78, 0x00, 0x00, 0xfe, /* 24 */
73 0x00, 0x00, 0xfe, 0x00, /* 28 */
74 0x18, 0x18, 0x00, 0x00, /* 32 */
75 0x00, 0x00, 0x00, 0x00, /* 36 */
76 0x00, 0x00, 0x00, 0x80, /* 40 */
77 0x80, 0x00, 0x00, 0x00, /* 44 */
78 0x00, 0x00, 0x00, 0x04, /* 48 */
79 0x00, 0x00, 0x00, 0x00, /* 52 */
80 0x00, 0x00, 0x04, 0x00, /* 56 */
81 0x00, 0x00, 0x00, 0x00, /* 60 */
82 0x00, 0x04, 0x00, 0x00, /* 64 */
83 0x00, 0x00, 0x00, 0x00, /* 68 */
84 0x04, 0x00, 0x00, 0x00, /* 72 */
85 0x00, 0x00, 0x00, 0x00, /* 76 */
86 0x00, 0x00, 0x00, 0x00, /* 80 */
87 0x00, 0x00, 0x00, 0x00, /* 84 */
88 0x00, 0x00, 0x00, 0x00, /* 88 */
89 0x00, 0x00, 0x00, 0x00, /* 92 */
90 0x00, 0x00, 0x00, 0x00, /* 96 */
91 0x00, 0x00, 0x02, /* 100 */
95 * read aic3x register cache
97 static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec
*codec
,
100 u8
*cache
= codec
->reg_cache
;
101 if (reg
>= AIC3X_CACHEREGNUM
)
107 * write aic3x register cache
109 static inline void aic3x_write_reg_cache(struct snd_soc_codec
*codec
,
112 u8
*cache
= codec
->reg_cache
;
113 if (reg
>= AIC3X_CACHEREGNUM
)
119 * write to the aic3x register space
121 static int aic3x_write(struct snd_soc_codec
*codec
, unsigned int reg
,
127 * D15..D8 aic3x register offset
128 * D7...D0 register data
130 data
[0] = reg
& 0xff;
131 data
[1] = value
& 0xff;
133 aic3x_write_reg_cache(codec
, data
[0], data
[1]);
134 if (codec
->hw_write(codec
->control_data
, data
, 2) == 2)
141 * read from the aic3x register space
143 static int aic3x_read(struct snd_soc_codec
*codec
, unsigned int reg
,
147 if (codec
->hw_read(codec
->control_data
, value
, 1) != 1)
150 aic3x_write_reg_cache(codec
, reg
, *value
);
154 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
155 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
156 .info = snd_soc_info_volsw, \
157 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
158 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
161 * All input lines are connected when !0xf and disconnected with 0xf bit field,
162 * so we have to use specific dapm_put call for input mixer
164 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol
*kcontrol
,
165 struct snd_ctl_elem_value
*ucontrol
)
167 struct snd_soc_dapm_widget
*widget
= snd_kcontrol_chip(kcontrol
);
168 int reg
= kcontrol
->private_value
& 0xff;
169 int shift
= (kcontrol
->private_value
>> 8) & 0x0f;
170 int mask
= (kcontrol
->private_value
>> 16) & 0xff;
171 int invert
= (kcontrol
->private_value
>> 24) & 0x01;
172 unsigned short val
, val_mask
;
174 struct snd_soc_dapm_path
*path
;
177 val
= (ucontrol
->value
.integer
.value
[0] & mask
);
185 val_mask
= mask
<< shift
;
188 mutex_lock(&widget
->codec
->mutex
);
190 if (snd_soc_test_bits(widget
->codec
, reg
, val_mask
, val
)) {
191 /* find dapm widget path assoc with kcontrol */
192 list_for_each_entry(path
, &widget
->codec
->dapm_paths
, list
) {
193 if (path
->kcontrol
!= kcontrol
)
196 /* found, now check type */
200 path
->connect
= invert
? 0 : 1;
202 /* old connection must be powered down */
203 path
->connect
= invert
? 1 : 0;
208 snd_soc_dapm_sync(widget
->codec
);
211 ret
= snd_soc_update_bits(widget
->codec
, reg
, val_mask
, val
);
213 mutex_unlock(&widget
->codec
->mutex
);
217 static const char *aic3x_left_dac_mux
[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
218 static const char *aic3x_right_dac_mux
[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
219 static const char *aic3x_left_hpcom_mux
[] =
220 { "differential of HPLOUT", "constant VCM", "single-ended" };
221 static const char *aic3x_right_hpcom_mux
[] =
222 { "differential of HPROUT", "constant VCM", "single-ended",
223 "differential of HPLCOM", "external feedback" };
224 static const char *aic3x_linein_mode_mux
[] = { "single-ended", "differential" };
225 static const char *aic3x_adc_hpf
[] =
226 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
230 #define LHPCOM_ENUM 2
231 #define RHPCOM_ENUM 3
232 #define LINE1L_ENUM 4
233 #define LINE1R_ENUM 5
234 #define LINE2L_ENUM 6
235 #define LINE2R_ENUM 7
236 #define ADC_HPF_ENUM 8
238 static const struct soc_enum aic3x_enum
[] = {
239 SOC_ENUM_SINGLE(DAC_LINE_MUX
, 6, 3, aic3x_left_dac_mux
),
240 SOC_ENUM_SINGLE(DAC_LINE_MUX
, 4, 3, aic3x_right_dac_mux
),
241 SOC_ENUM_SINGLE(HPLCOM_CFG
, 4, 3, aic3x_left_hpcom_mux
),
242 SOC_ENUM_SINGLE(HPRCOM_CFG
, 3, 5, aic3x_right_hpcom_mux
),
243 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL
, 7, 2, aic3x_linein_mode_mux
),
244 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL
, 7, 2, aic3x_linein_mode_mux
),
245 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL
, 7, 2, aic3x_linein_mode_mux
),
246 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL
, 7, 2, aic3x_linein_mode_mux
),
247 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL
, 6, 4, 4, aic3x_adc_hpf
),
250 static const struct snd_kcontrol_new aic3x_snd_controls
[] = {
252 SOC_DOUBLE_R("PCM Playback Volume", LDAC_VOL
, RDAC_VOL
, 0, 0x7f, 1),
254 SOC_DOUBLE_R("Line DAC Playback Volume", DACL1_2_LLOPM_VOL
,
255 DACR1_2_RLOPM_VOL
, 0, 0x7f, 1),
256 SOC_SINGLE("LineL Playback Switch", LLOPM_CTRL
, 3, 0x01, 0),
257 SOC_SINGLE("LineR Playback Switch", RLOPM_CTRL
, 3, 0x01, 0),
258 SOC_DOUBLE_R("LineL DAC Playback Volume", DACL1_2_LLOPM_VOL
,
259 DACR1_2_LLOPM_VOL
, 0, 0x7f, 1),
260 SOC_SINGLE("LineL Left PGA Bypass Playback Volume", PGAL_2_LLOPM_VOL
,
262 SOC_SINGLE("LineR Right PGA Bypass Playback Volume", PGAR_2_RLOPM_VOL
,
264 SOC_DOUBLE_R("LineL Line2 Bypass Playback Volume", LINE2L_2_LLOPM_VOL
,
265 LINE2R_2_LLOPM_VOL
, 0, 0x7f, 1),
266 SOC_DOUBLE_R("LineR Line2 Bypass Playback Volume", LINE2L_2_RLOPM_VOL
,
267 LINE2R_2_RLOPM_VOL
, 0, 0x7f, 1),
269 SOC_DOUBLE_R("Mono DAC Playback Volume", DACL1_2_MONOLOPM_VOL
,
270 DACR1_2_MONOLOPM_VOL
, 0, 0x7f, 1),
271 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL
, 3, 0x01, 0),
272 SOC_DOUBLE_R("Mono PGA Bypass Playback Volume", PGAL_2_MONOLOPM_VOL
,
273 PGAR_2_MONOLOPM_VOL
, 0, 0x7f, 1),
274 SOC_DOUBLE_R("Mono Line2 Bypass Playback Volume", LINE2L_2_MONOLOPM_VOL
,
275 LINE2R_2_MONOLOPM_VOL
, 0, 0x7f, 1),
277 SOC_DOUBLE_R("HP DAC Playback Volume", DACL1_2_HPLOUT_VOL
,
278 DACR1_2_HPROUT_VOL
, 0, 0x7f, 1),
279 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL
, HPROUT_CTRL
, 3,
281 SOC_DOUBLE_R("HP Right PGA Bypass Playback Volume", PGAR_2_HPLOUT_VOL
,
282 PGAR_2_HPROUT_VOL
, 0, 0x7f, 1),
283 SOC_SINGLE("HPL PGA Bypass Playback Volume", PGAL_2_HPLOUT_VOL
,
285 SOC_SINGLE("HPR PGA Bypass Playback Volume", PGAL_2_HPROUT_VOL
,
287 SOC_DOUBLE_R("HP Line2 Bypass Playback Volume", LINE2L_2_HPLOUT_VOL
,
288 LINE2R_2_HPROUT_VOL
, 0, 0x7f, 1),
290 SOC_DOUBLE_R("HPCOM DAC Playback Volume", DACL1_2_HPLCOM_VOL
,
291 DACR1_2_HPRCOM_VOL
, 0, 0x7f, 1),
292 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL
, HPRCOM_CTRL
, 3,
294 SOC_SINGLE("HPLCOM PGA Bypass Playback Volume", PGAL_2_HPLCOM_VOL
,
296 SOC_SINGLE("HPRCOM PGA Bypass Playback Volume", PGAL_2_HPRCOM_VOL
,
298 SOC_DOUBLE_R("HPCOM Line2 Bypass Playback Volume", LINE2L_2_HPLCOM_VOL
,
299 LINE2R_2_HPRCOM_VOL
, 0, 0x7f, 1),
302 * Note: enable Automatic input Gain Controller with care. It can
303 * adjust PGA to max value when ADC is on and will never go back.
305 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A
, RAGC_CTRL_A
, 7, 0x01, 0),
308 SOC_DOUBLE_R("PGA Capture Volume", LADC_VOL
, RADC_VOL
, 0, 0x7f, 0),
309 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL
, RADC_VOL
, 7, 0x01, 1),
311 SOC_ENUM("ADC HPF Cut-off", aic3x_enum
[ADC_HPF_ENUM
]),
315 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls
=
316 SOC_DAPM_ENUM("Route", aic3x_enum
[LDAC_ENUM
]);
319 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls
=
320 SOC_DAPM_ENUM("Route", aic3x_enum
[RDAC_ENUM
]);
323 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls
=
324 SOC_DAPM_ENUM("Route", aic3x_enum
[LHPCOM_ENUM
]);
326 /* Right HPCOM Mux */
327 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls
=
328 SOC_DAPM_ENUM("Route", aic3x_enum
[RHPCOM_ENUM
]);
330 /* Left DAC_L1 Mixer */
331 static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls
[] = {
332 SOC_DAPM_SINGLE("LineL Switch", DACL1_2_LLOPM_VOL
, 7, 1, 0),
333 SOC_DAPM_SINGLE("LineR Switch", DACL1_2_RLOPM_VOL
, 7, 1, 0),
334 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL
, 7, 1, 0),
335 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL
, 7, 1, 0),
336 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL
, 7, 1, 0),
339 /* Right DAC_R1 Mixer */
340 static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls
[] = {
341 SOC_DAPM_SINGLE("LineL Switch", DACR1_2_LLOPM_VOL
, 7, 1, 0),
342 SOC_DAPM_SINGLE("LineR Switch", DACR1_2_RLOPM_VOL
, 7, 1, 0),
343 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL
, 7, 1, 0),
344 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL
, 7, 1, 0),
345 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL
, 7, 1, 0),
349 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls
[] = {
350 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL
, 3, 1, 1),
351 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL
, 3, 1, 1),
352 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL
, 3, 1, 1),
353 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL
, 4, 1, 1),
354 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL
, 0, 1, 1),
357 /* Right PGA Mixer */
358 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls
[] = {
359 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL
, 3, 1, 1),
360 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL
, 3, 1, 1),
361 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL
, 3, 1, 1),
362 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL
, 4, 1, 1),
363 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL
, 0, 1, 1),
367 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls
=
368 SOC_DAPM_ENUM("Route", aic3x_enum
[LINE1L_ENUM
]);
370 /* Right Line1 Mux */
371 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls
=
372 SOC_DAPM_ENUM("Route", aic3x_enum
[LINE1R_ENUM
]);
375 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls
=
376 SOC_DAPM_ENUM("Route", aic3x_enum
[LINE2L_ENUM
]);
378 /* Right Line2 Mux */
379 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls
=
380 SOC_DAPM_ENUM("Route", aic3x_enum
[LINE2R_ENUM
]);
382 /* Left PGA Bypass Mixer */
383 static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls
[] = {
384 SOC_DAPM_SINGLE("LineL Switch", PGAL_2_LLOPM_VOL
, 7, 1, 0),
385 SOC_DAPM_SINGLE("LineR Switch", PGAL_2_RLOPM_VOL
, 7, 1, 0),
386 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL
, 7, 1, 0),
387 SOC_DAPM_SINGLE("HPL Switch", PGAL_2_HPLOUT_VOL
, 7, 1, 0),
388 SOC_DAPM_SINGLE("HPR Switch", PGAL_2_HPROUT_VOL
, 7, 1, 0),
389 SOC_DAPM_SINGLE("HPLCOM Switch", PGAL_2_HPLCOM_VOL
, 7, 1, 0),
390 SOC_DAPM_SINGLE("HPRCOM Switch", PGAL_2_HPRCOM_VOL
, 7, 1, 0),
393 /* Right PGA Bypass Mixer */
394 static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls
[] = {
395 SOC_DAPM_SINGLE("LineL Switch", PGAR_2_LLOPM_VOL
, 7, 1, 0),
396 SOC_DAPM_SINGLE("LineR Switch", PGAR_2_RLOPM_VOL
, 7, 1, 0),
397 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL
, 7, 1, 0),
398 SOC_DAPM_SINGLE("HPL Switch", PGAR_2_HPLOUT_VOL
, 7, 1, 0),
399 SOC_DAPM_SINGLE("HPR Switch", PGAR_2_HPROUT_VOL
, 7, 1, 0),
400 SOC_DAPM_SINGLE("HPLCOM Switch", PGAR_2_HPLCOM_VOL
, 7, 1, 0),
401 SOC_DAPM_SINGLE("HPRCOM Switch", PGAR_2_HPRCOM_VOL
, 7, 1, 0),
404 /* Left Line2 Bypass Mixer */
405 static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls
[] = {
406 SOC_DAPM_SINGLE("LineL Switch", LINE2L_2_LLOPM_VOL
, 7, 1, 0),
407 SOC_DAPM_SINGLE("LineR Switch", LINE2L_2_RLOPM_VOL
, 7, 1, 0),
408 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL
, 7, 1, 0),
409 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL
, 7, 1, 0),
410 SOC_DAPM_SINGLE("HPLCOM Switch", LINE2L_2_HPLCOM_VOL
, 7, 1, 0),
413 /* Right Line2 Bypass Mixer */
414 static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls
[] = {
415 SOC_DAPM_SINGLE("LineL Switch", LINE2R_2_LLOPM_VOL
, 7, 1, 0),
416 SOC_DAPM_SINGLE("LineR Switch", LINE2R_2_RLOPM_VOL
, 7, 1, 0),
417 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL
, 7, 1, 0),
418 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL
, 7, 1, 0),
419 SOC_DAPM_SINGLE("HPRCOM Switch", LINE2R_2_HPRCOM_VOL
, 7, 1, 0),
422 static const struct snd_soc_dapm_widget aic3x_dapm_widgets
[] = {
423 /* Left DAC to Left Outputs */
424 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR
, 7, 0),
425 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM
, 0, 0,
426 &aic3x_left_dac_mux_controls
),
427 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM
, 0, 0,
428 &aic3x_left_dac_mixer_controls
[0],
429 ARRAY_SIZE(aic3x_left_dac_mixer_controls
)),
430 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM
, 0, 0,
431 &aic3x_left_hpcom_mux_controls
),
432 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL
, 0, 0, NULL
, 0),
433 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL
, 0, 0, NULL
, 0),
434 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL
, 0, 0, NULL
, 0),
436 /* Right DAC to Right Outputs */
437 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR
, 6, 0),
438 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM
, 0, 0,
439 &aic3x_right_dac_mux_controls
),
440 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM
, 0, 0,
441 &aic3x_right_dac_mixer_controls
[0],
442 ARRAY_SIZE(aic3x_right_dac_mixer_controls
)),
443 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM
, 0, 0,
444 &aic3x_right_hpcom_mux_controls
),
445 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL
, 0, 0, NULL
, 0),
446 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL
, 0, 0, NULL
, 0),
447 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL
, 0, 0, NULL
, 0),
450 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL
, 0, 0, NULL
, 0),
452 /* Inputs to Left ADC */
453 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL
, 2, 0),
454 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM
, 0, 0,
455 &aic3x_left_pga_mixer_controls
[0],
456 ARRAY_SIZE(aic3x_left_pga_mixer_controls
)),
457 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM
, 0, 0,
458 &aic3x_left_line1_mux_controls
),
459 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM
, 0, 0,
460 &aic3x_left_line1_mux_controls
),
461 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM
, 0, 0,
462 &aic3x_left_line2_mux_controls
),
464 /* Inputs to Right ADC */
465 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
466 LINE1R_2_RADC_CTRL
, 2, 0),
467 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM
, 0, 0,
468 &aic3x_right_pga_mixer_controls
[0],
469 ARRAY_SIZE(aic3x_right_pga_mixer_controls
)),
470 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM
, 0, 0,
471 &aic3x_right_line1_mux_controls
),
472 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM
, 0, 0,
473 &aic3x_right_line1_mux_controls
),
474 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM
, 0, 0,
475 &aic3x_right_line2_mux_controls
),
478 * Not a real mic bias widget but similar function. This is for dynamic
479 * control of GPIO1 digital mic modulator clock output function when
482 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "GPIO1 dmic modclk",
483 AIC3X_GPIO1_REG
, 4, 0xf,
484 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK
,
485 AIC3X_GPIO1_FUNC_DISABLED
),
488 * Also similar function like mic bias. Selects digital mic with
489 * configurable oversampling rate instead of ADC converter.
491 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "DMic Rate 128",
492 AIC3X_ASD_INTF_CTRLA
, 0, 3, 1, 0),
493 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "DMic Rate 64",
494 AIC3X_ASD_INTF_CTRLA
, 0, 3, 2, 0),
495 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "DMic Rate 32",
496 AIC3X_ASD_INTF_CTRLA
, 0, 3, 3, 0),
499 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "Mic Bias 2V",
500 MICBIAS_CTRL
, 6, 3, 1, 0),
501 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "Mic Bias 2.5V",
502 MICBIAS_CTRL
, 6, 3, 2, 0),
503 SND_SOC_DAPM_REG(snd_soc_dapm_micbias
, "Mic Bias AVDD",
504 MICBIAS_CTRL
, 6, 3, 3, 0),
506 /* Left PGA to Left Output bypass */
507 SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM
, 0, 0,
508 &aic3x_left_pga_bp_mixer_controls
[0],
509 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls
)),
511 /* Right PGA to Right Output bypass */
512 SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM
, 0, 0,
513 &aic3x_right_pga_bp_mixer_controls
[0],
514 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls
)),
516 /* Left Line2 to Left Output bypass */
517 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM
, 0, 0,
518 &aic3x_left_line2_bp_mixer_controls
[0],
519 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls
)),
521 /* Right Line2 to Right Output bypass */
522 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM
, 0, 0,
523 &aic3x_right_line2_bp_mixer_controls
[0],
524 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls
)),
526 SND_SOC_DAPM_OUTPUT("LLOUT"),
527 SND_SOC_DAPM_OUTPUT("RLOUT"),
528 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
529 SND_SOC_DAPM_OUTPUT("HPLOUT"),
530 SND_SOC_DAPM_OUTPUT("HPROUT"),
531 SND_SOC_DAPM_OUTPUT("HPLCOM"),
532 SND_SOC_DAPM_OUTPUT("HPRCOM"),
534 SND_SOC_DAPM_INPUT("MIC3L"),
535 SND_SOC_DAPM_INPUT("MIC3R"),
536 SND_SOC_DAPM_INPUT("LINE1L"),
537 SND_SOC_DAPM_INPUT("LINE1R"),
538 SND_SOC_DAPM_INPUT("LINE2L"),
539 SND_SOC_DAPM_INPUT("LINE2R"),
542 static const struct snd_soc_dapm_route intercon
[] = {
544 {"Left DAC Mux", "DAC_L1", "Left DAC"},
545 {"Left DAC Mux", "DAC_L2", "Left DAC"},
546 {"Left DAC Mux", "DAC_L3", "Left DAC"},
548 {"Left DAC_L1 Mixer", "LineL Switch", "Left DAC Mux"},
549 {"Left DAC_L1 Mixer", "LineR Switch", "Left DAC Mux"},
550 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
551 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
552 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
553 {"Left Line Out", NULL
, "Left DAC Mux"},
554 {"Left HP Out", NULL
, "Left DAC Mux"},
556 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
557 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
558 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
560 {"Left Line Out", NULL
, "Left DAC_L1 Mixer"},
561 {"Mono Out", NULL
, "Left DAC_L1 Mixer"},
562 {"Left HP Out", NULL
, "Left DAC_L1 Mixer"},
563 {"Left HP Com", NULL
, "Left HPCOM Mux"},
565 {"LLOUT", NULL
, "Left Line Out"},
566 {"LLOUT", NULL
, "Left Line Out"},
567 {"HPLOUT", NULL
, "Left HP Out"},
568 {"HPLCOM", NULL
, "Left HP Com"},
571 {"Right DAC Mux", "DAC_R1", "Right DAC"},
572 {"Right DAC Mux", "DAC_R2", "Right DAC"},
573 {"Right DAC Mux", "DAC_R3", "Right DAC"},
575 {"Right DAC_R1 Mixer", "LineL Switch", "Right DAC Mux"},
576 {"Right DAC_R1 Mixer", "LineR Switch", "Right DAC Mux"},
577 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
578 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
579 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
580 {"Right Line Out", NULL
, "Right DAC Mux"},
581 {"Right HP Out", NULL
, "Right DAC Mux"},
583 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
584 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
585 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
586 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
587 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
589 {"Right Line Out", NULL
, "Right DAC_R1 Mixer"},
590 {"Mono Out", NULL
, "Right DAC_R1 Mixer"},
591 {"Right HP Out", NULL
, "Right DAC_R1 Mixer"},
592 {"Right HP Com", NULL
, "Right HPCOM Mux"},
594 {"RLOUT", NULL
, "Right Line Out"},
595 {"RLOUT", NULL
, "Right Line Out"},
596 {"HPROUT", NULL
, "Right HP Out"},
597 {"HPRCOM", NULL
, "Right HP Com"},
600 {"MONO_LOUT", NULL
, "Mono Out"},
601 {"MONO_LOUT", NULL
, "Mono Out"},
604 {"Left Line1L Mux", "single-ended", "LINE1L"},
605 {"Left Line1L Mux", "differential", "LINE1L"},
607 {"Left Line2L Mux", "single-ended", "LINE2L"},
608 {"Left Line2L Mux", "differential", "LINE2L"},
610 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
611 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
612 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
613 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
614 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
616 {"Left ADC", NULL
, "Left PGA Mixer"},
617 {"Left ADC", NULL
, "GPIO1 dmic modclk"},
620 {"Right Line1R Mux", "single-ended", "LINE1R"},
621 {"Right Line1R Mux", "differential", "LINE1R"},
623 {"Right Line2R Mux", "single-ended", "LINE2R"},
624 {"Right Line2R Mux", "differential", "LINE2R"},
626 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
627 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
628 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
629 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
630 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
632 {"Right ADC", NULL
, "Right PGA Mixer"},
633 {"Right ADC", NULL
, "GPIO1 dmic modclk"},
635 /* Left PGA Bypass */
636 {"Left PGA Bypass Mixer", "LineL Switch", "Left PGA Mixer"},
637 {"Left PGA Bypass Mixer", "LineR Switch", "Left PGA Mixer"},
638 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
639 {"Left PGA Bypass Mixer", "HPL Switch", "Left PGA Mixer"},
640 {"Left PGA Bypass Mixer", "HPR Switch", "Left PGA Mixer"},
641 {"Left PGA Bypass Mixer", "HPLCOM Switch", "Left PGA Mixer"},
642 {"Left PGA Bypass Mixer", "HPRCOM Switch", "Left PGA Mixer"},
644 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
645 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
646 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
648 {"Left Line Out", NULL
, "Left PGA Bypass Mixer"},
649 {"Mono Out", NULL
, "Left PGA Bypass Mixer"},
650 {"Left HP Out", NULL
, "Left PGA Bypass Mixer"},
652 /* Right PGA Bypass */
653 {"Right PGA Bypass Mixer", "LineL Switch", "Right PGA Mixer"},
654 {"Right PGA Bypass Mixer", "LineR Switch", "Right PGA Mixer"},
655 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
656 {"Right PGA Bypass Mixer", "HPL Switch", "Right PGA Mixer"},
657 {"Right PGA Bypass Mixer", "HPR Switch", "Right PGA Mixer"},
658 {"Right PGA Bypass Mixer", "HPLCOM Switch", "Right PGA Mixer"},
659 {"Right PGA Bypass Mixer", "HPRCOM Switch", "Right PGA Mixer"},
661 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
662 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
663 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
664 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
665 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
667 {"Right Line Out", NULL
, "Right PGA Bypass Mixer"},
668 {"Mono Out", NULL
, "Right PGA Bypass Mixer"},
669 {"Right HP Out", NULL
, "Right PGA Bypass Mixer"},
671 /* Left Line2 Bypass */
672 {"Left Line2 Bypass Mixer", "LineL Switch", "Left Line2L Mux"},
673 {"Left Line2 Bypass Mixer", "LineR Switch", "Left Line2L Mux"},
674 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
675 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
676 {"Left Line2 Bypass Mixer", "HPLCOM Switch", "Left Line2L Mux"},
678 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
679 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
680 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
682 {"Left Line Out", NULL
, "Left Line2 Bypass Mixer"},
683 {"Mono Out", NULL
, "Left Line2 Bypass Mixer"},
684 {"Left HP Out", NULL
, "Left Line2 Bypass Mixer"},
686 /* Right Line2 Bypass */
687 {"Right Line2 Bypass Mixer", "LineL Switch", "Right Line2R Mux"},
688 {"Right Line2 Bypass Mixer", "LineR Switch", "Right Line2R Mux"},
689 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
690 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
691 {"Right Line2 Bypass Mixer", "HPRCOM Switch", "Right Line2R Mux"},
693 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
694 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
695 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
696 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
697 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
699 {"Right Line Out", NULL
, "Right Line2 Bypass Mixer"},
700 {"Mono Out", NULL
, "Right Line2 Bypass Mixer"},
701 {"Right HP Out", NULL
, "Right Line2 Bypass Mixer"},
704 * Logical path between digital mic enable and GPIO1 modulator clock
707 {"GPIO1 dmic modclk", NULL
, "DMic Rate 128"},
708 {"GPIO1 dmic modclk", NULL
, "DMic Rate 64"},
709 {"GPIO1 dmic modclk", NULL
, "DMic Rate 32"},
712 static int aic3x_add_widgets(struct snd_soc_codec
*codec
)
714 snd_soc_dapm_new_controls(codec
, aic3x_dapm_widgets
,
715 ARRAY_SIZE(aic3x_dapm_widgets
));
717 /* set up audio path interconnects */
718 snd_soc_dapm_add_routes(codec
, intercon
, ARRAY_SIZE(intercon
));
720 snd_soc_dapm_new_widgets(codec
);
724 static int aic3x_hw_params(struct snd_pcm_substream
*substream
,
725 struct snd_pcm_hw_params
*params
,
726 struct snd_soc_dai
*dai
)
728 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
729 struct snd_soc_device
*socdev
= rtd
->socdev
;
730 struct snd_soc_codec
*codec
= socdev
->codec
;
731 struct aic3x_priv
*aic3x
= codec
->private_data
;
732 int codec_clk
= 0, bypass_pll
= 0, fsref
, last_clk
= 0;
733 u8 data
, r
, p
, pll_q
, pll_p
= 1, pll_r
= 1, pll_j
= 1;
736 /* select data word length */
738 aic3x_read_reg_cache(codec
, AIC3X_ASD_INTF_CTRLB
) & (~(0x3 << 4));
739 switch (params_format(params
)) {
740 case SNDRV_PCM_FORMAT_S16_LE
:
742 case SNDRV_PCM_FORMAT_S20_3LE
:
745 case SNDRV_PCM_FORMAT_S24_LE
:
748 case SNDRV_PCM_FORMAT_S32_LE
:
752 aic3x_write(codec
, AIC3X_ASD_INTF_CTRLB
, data
);
754 /* Fsref can be 44100 or 48000 */
755 fsref
= (params_rate(params
) % 11025 == 0) ? 44100 : 48000;
757 /* Try to find a value for Q which allows us to bypass the PLL and
758 * generate CODEC_CLK directly. */
759 for (pll_q
= 2; pll_q
< 18; pll_q
++)
760 if (aic3x
->sysclk
/ (128 * pll_q
) == fsref
) {
767 aic3x_write(codec
, AIC3X_PLL_PROGA_REG
, pll_q
<< PLLQ_SHIFT
);
768 aic3x_write(codec
, AIC3X_GPIOB_REG
, CODEC_CLKIN_CLKDIV
);
770 aic3x_write(codec
, AIC3X_GPIOB_REG
, CODEC_CLKIN_PLLDIV
);
772 /* Route Left DAC to left channel input and
773 * right DAC to right channel input */
774 data
= (LDAC2LCH
| RDAC2RCH
);
775 data
|= (fsref
== 44100) ? FSREF_44100
: FSREF_48000
;
776 if (params_rate(params
) >= 64000)
777 data
|= DUAL_RATE_MODE
;
778 aic3x_write(codec
, AIC3X_CODEC_DATAPATH_REG
, data
);
780 /* codec sample rate select */
781 data
= (fsref
* 20) / params_rate(params
);
782 if (params_rate(params
) < 64000)
787 aic3x_write(codec
, AIC3X_SAMPLE_RATE_SEL_REG
, data
);
793 * find an apropriate setup for j, d, r and p by iterating over
794 * p and r - j and d are calculated for each fraction.
795 * Up to 128 values are probed, the closest one wins the game.
796 * The sysclk is divided by 1000 to prevent integer overflows.
798 codec_clk
= (2048 * fsref
) / (aic3x
->sysclk
/ 1000);
800 for (r
= 1; r
<= 16; r
++)
801 for (p
= 1; p
<= 8; p
++) {
802 int clk
, tmp
= (codec_clk
* pll_r
* 10) / pll_p
;
809 if (d
!= 0 && aic3x
->sysclk
< 10000000)
812 /* This is actually 1000 * ((j + (d/10000)) * r) / p
813 * The term had to be converted to get rid of the
814 * division by 10000 */
815 clk
= ((10000 * j
* r
) + (d
* r
)) / (10 * p
);
817 /* check whether this values get closer than the best
818 * ones we had before */
819 if (abs(codec_clk
- clk
) < abs(codec_clk
- last_clk
)) {
820 pll_j
= j
; pll_d
= d
; pll_r
= r
; pll_p
= p
;
824 /* Early exit for exact matches */
825 if (clk
== codec_clk
)
830 printk(KERN_ERR
"%s(): unable to setup PLL\n", __func__
);
834 data
= aic3x_read_reg_cache(codec
, AIC3X_PLL_PROGA_REG
);
835 aic3x_write(codec
, AIC3X_PLL_PROGA_REG
, data
| (pll_p
<< PLLP_SHIFT
));
836 aic3x_write(codec
, AIC3X_OVRF_STATUS_AND_PLLR_REG
, pll_r
<< PLLR_SHIFT
);
837 aic3x_write(codec
, AIC3X_PLL_PROGB_REG
, pll_j
<< PLLJ_SHIFT
);
838 aic3x_write(codec
, AIC3X_PLL_PROGC_REG
, (pll_d
>> 6) << PLLD_MSB_SHIFT
);
839 aic3x_write(codec
, AIC3X_PLL_PROGD_REG
,
840 (pll_d
& 0x3F) << PLLD_LSB_SHIFT
);
845 static int aic3x_mute(struct snd_soc_dai
*dai
, int mute
)
847 struct snd_soc_codec
*codec
= dai
->codec
;
848 u8 ldac_reg
= aic3x_read_reg_cache(codec
, LDAC_VOL
) & ~MUTE_ON
;
849 u8 rdac_reg
= aic3x_read_reg_cache(codec
, RDAC_VOL
) & ~MUTE_ON
;
852 aic3x_write(codec
, LDAC_VOL
, ldac_reg
| MUTE_ON
);
853 aic3x_write(codec
, RDAC_VOL
, rdac_reg
| MUTE_ON
);
855 aic3x_write(codec
, LDAC_VOL
, ldac_reg
);
856 aic3x_write(codec
, RDAC_VOL
, rdac_reg
);
862 static int aic3x_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
863 int clk_id
, unsigned int freq
, int dir
)
865 struct snd_soc_codec
*codec
= codec_dai
->codec
;
866 struct aic3x_priv
*aic3x
= codec
->private_data
;
868 aic3x
->sysclk
= freq
;
872 static int aic3x_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
875 struct snd_soc_codec
*codec
= codec_dai
->codec
;
876 struct aic3x_priv
*aic3x
= codec
->private_data
;
877 u8 iface_areg
, iface_breg
;
880 iface_areg
= aic3x_read_reg_cache(codec
, AIC3X_ASD_INTF_CTRLA
) & 0x3f;
881 iface_breg
= aic3x_read_reg_cache(codec
, AIC3X_ASD_INTF_CTRLB
) & 0x3f;
883 /* set master/slave audio interface */
884 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
885 case SND_SOC_DAIFMT_CBM_CFM
:
887 iface_areg
|= BIT_CLK_MASTER
| WORD_CLK_MASTER
;
889 case SND_SOC_DAIFMT_CBS_CFS
:
897 * match both interface format and signal polarities since they
900 switch (fmt
& (SND_SOC_DAIFMT_FORMAT_MASK
|
901 SND_SOC_DAIFMT_INV_MASK
)) {
902 case (SND_SOC_DAIFMT_I2S
| SND_SOC_DAIFMT_NB_NF
):
904 case (SND_SOC_DAIFMT_DSP_A
| SND_SOC_DAIFMT_IB_NF
):
906 case (SND_SOC_DAIFMT_DSP_B
| SND_SOC_DAIFMT_IB_NF
):
907 iface_breg
|= (0x01 << 6);
909 case (SND_SOC_DAIFMT_RIGHT_J
| SND_SOC_DAIFMT_NB_NF
):
910 iface_breg
|= (0x02 << 6);
912 case (SND_SOC_DAIFMT_LEFT_J
| SND_SOC_DAIFMT_NB_NF
):
913 iface_breg
|= (0x03 << 6);
920 aic3x_write(codec
, AIC3X_ASD_INTF_CTRLA
, iface_areg
);
921 aic3x_write(codec
, AIC3X_ASD_INTF_CTRLB
, iface_breg
);
922 aic3x_write(codec
, AIC3X_ASD_INTF_CTRLC
, delay
);
927 static int aic3x_set_bias_level(struct snd_soc_codec
*codec
,
928 enum snd_soc_bias_level level
)
930 struct aic3x_priv
*aic3x
= codec
->private_data
;
934 case SND_SOC_BIAS_ON
:
935 /* all power is driven by DAPM system */
938 reg
= aic3x_read_reg_cache(codec
, AIC3X_PLL_PROGA_REG
);
939 aic3x_write(codec
, AIC3X_PLL_PROGA_REG
,
943 case SND_SOC_BIAS_PREPARE
:
945 case SND_SOC_BIAS_STANDBY
:
947 * all power is driven by DAPM system,
948 * so output power is safe if bypass was set
952 reg
= aic3x_read_reg_cache(codec
, AIC3X_PLL_PROGA_REG
);
953 aic3x_write(codec
, AIC3X_PLL_PROGA_REG
,
957 case SND_SOC_BIAS_OFF
:
958 /* force all power off */
959 reg
= aic3x_read_reg_cache(codec
, LINE1L_2_LADC_CTRL
);
960 aic3x_write(codec
, LINE1L_2_LADC_CTRL
, reg
& ~LADC_PWR_ON
);
961 reg
= aic3x_read_reg_cache(codec
, LINE1R_2_RADC_CTRL
);
962 aic3x_write(codec
, LINE1R_2_RADC_CTRL
, reg
& ~RADC_PWR_ON
);
964 reg
= aic3x_read_reg_cache(codec
, DAC_PWR
);
965 aic3x_write(codec
, DAC_PWR
, reg
& ~(LDAC_PWR_ON
| RDAC_PWR_ON
));
967 reg
= aic3x_read_reg_cache(codec
, HPLOUT_CTRL
);
968 aic3x_write(codec
, HPLOUT_CTRL
, reg
& ~HPLOUT_PWR_ON
);
969 reg
= aic3x_read_reg_cache(codec
, HPROUT_CTRL
);
970 aic3x_write(codec
, HPROUT_CTRL
, reg
& ~HPROUT_PWR_ON
);
972 reg
= aic3x_read_reg_cache(codec
, HPLCOM_CTRL
);
973 aic3x_write(codec
, HPLCOM_CTRL
, reg
& ~HPLCOM_PWR_ON
);
974 reg
= aic3x_read_reg_cache(codec
, HPRCOM_CTRL
);
975 aic3x_write(codec
, HPRCOM_CTRL
, reg
& ~HPRCOM_PWR_ON
);
977 reg
= aic3x_read_reg_cache(codec
, MONOLOPM_CTRL
);
978 aic3x_write(codec
, MONOLOPM_CTRL
, reg
& ~MONOLOPM_PWR_ON
);
980 reg
= aic3x_read_reg_cache(codec
, LLOPM_CTRL
);
981 aic3x_write(codec
, LLOPM_CTRL
, reg
& ~LLOPM_PWR_ON
);
982 reg
= aic3x_read_reg_cache(codec
, RLOPM_CTRL
);
983 aic3x_write(codec
, RLOPM_CTRL
, reg
& ~RLOPM_PWR_ON
);
987 reg
= aic3x_read_reg_cache(codec
, AIC3X_PLL_PROGA_REG
);
988 aic3x_write(codec
, AIC3X_PLL_PROGA_REG
,
993 codec
->bias_level
= level
;
998 void aic3x_set_gpio(struct snd_soc_codec
*codec
, int gpio
, int state
)
1000 u8 reg
= gpio
? AIC3X_GPIO2_REG
: AIC3X_GPIO1_REG
;
1001 u8 bit
= gpio
? 3: 0;
1002 u8 val
= aic3x_read_reg_cache(codec
, reg
) & ~(1 << bit
);
1003 aic3x_write(codec
, reg
, val
| (!!state
<< bit
));
1005 EXPORT_SYMBOL_GPL(aic3x_set_gpio
);
1007 int aic3x_get_gpio(struct snd_soc_codec
*codec
, int gpio
)
1009 u8 reg
= gpio
? AIC3X_GPIO2_REG
: AIC3X_GPIO1_REG
;
1010 u8 val
, bit
= gpio
? 2: 1;
1012 aic3x_read(codec
, reg
, &val
);
1013 return (val
>> bit
) & 1;
1015 EXPORT_SYMBOL_GPL(aic3x_get_gpio
);
1017 void aic3x_set_headset_detection(struct snd_soc_codec
*codec
, int detect
,
1018 int headset_debounce
, int button_debounce
)
1022 val
= ((detect
& AIC3X_HEADSET_DETECT_MASK
)
1023 << AIC3X_HEADSET_DETECT_SHIFT
) |
1024 ((headset_debounce
& AIC3X_HEADSET_DEBOUNCE_MASK
)
1025 << AIC3X_HEADSET_DEBOUNCE_SHIFT
) |
1026 ((button_debounce
& AIC3X_BUTTON_DEBOUNCE_MASK
)
1027 << AIC3X_BUTTON_DEBOUNCE_SHIFT
);
1029 if (detect
& AIC3X_HEADSET_DETECT_MASK
)
1030 val
|= AIC3X_HEADSET_DETECT_ENABLED
;
1032 aic3x_write(codec
, AIC3X_HEADSET_DETECT_CTRL_A
, val
);
1034 EXPORT_SYMBOL_GPL(aic3x_set_headset_detection
);
1036 int aic3x_headset_detected(struct snd_soc_codec
*codec
)
1039 aic3x_read(codec
, AIC3X_HEADSET_DETECT_CTRL_B
, &val
);
1040 return (val
>> 4) & 1;
1042 EXPORT_SYMBOL_GPL(aic3x_headset_detected
);
1044 int aic3x_button_pressed(struct snd_soc_codec
*codec
)
1047 aic3x_read(codec
, AIC3X_HEADSET_DETECT_CTRL_B
, &val
);
1048 return (val
>> 5) & 1;
1050 EXPORT_SYMBOL_GPL(aic3x_button_pressed
);
1052 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1053 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1054 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1056 struct snd_soc_dai aic3x_dai
= {
1057 .name
= "tlv320aic3x",
1059 .stream_name
= "Playback",
1062 .rates
= AIC3X_RATES
,
1063 .formats
= AIC3X_FORMATS
,},
1065 .stream_name
= "Capture",
1068 .rates
= AIC3X_RATES
,
1069 .formats
= AIC3X_FORMATS
,},
1071 .hw_params
= aic3x_hw_params
,
1072 .digital_mute
= aic3x_mute
,
1073 .set_sysclk
= aic3x_set_dai_sysclk
,
1074 .set_fmt
= aic3x_set_dai_fmt
,
1077 EXPORT_SYMBOL_GPL(aic3x_dai
);
1079 static int aic3x_suspend(struct platform_device
*pdev
, pm_message_t state
)
1081 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1082 struct snd_soc_codec
*codec
= socdev
->codec
;
1084 aic3x_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1089 static int aic3x_resume(struct platform_device
*pdev
)
1091 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1092 struct snd_soc_codec
*codec
= socdev
->codec
;
1095 u8
*cache
= codec
->reg_cache
;
1097 /* Sync reg_cache with the hardware */
1098 for (i
= 0; i
< ARRAY_SIZE(aic3x_reg
); i
++) {
1101 codec
->hw_write(codec
->control_data
, data
, 2);
1104 aic3x_set_bias_level(codec
, codec
->suspend_bias_level
);
1110 * initialise the AIC3X driver
1111 * register the mixer and dsp interfaces with the kernel
1113 static int aic3x_init(struct snd_soc_device
*socdev
)
1115 struct snd_soc_codec
*codec
= socdev
->codec
;
1116 struct aic3x_setup_data
*setup
= socdev
->codec_data
;
1119 codec
->name
= "tlv320aic3x";
1120 codec
->owner
= THIS_MODULE
;
1121 codec
->read
= aic3x_read_reg_cache
;
1122 codec
->write
= aic3x_write
;
1123 codec
->set_bias_level
= aic3x_set_bias_level
;
1124 codec
->dai
= &aic3x_dai
;
1126 codec
->reg_cache_size
= ARRAY_SIZE(aic3x_reg
);
1127 codec
->reg_cache
= kmemdup(aic3x_reg
, sizeof(aic3x_reg
), GFP_KERNEL
);
1128 if (codec
->reg_cache
== NULL
)
1131 aic3x_write(codec
, AIC3X_PAGE_SELECT
, PAGE0_SELECT
);
1132 aic3x_write(codec
, AIC3X_RESET
, SOFT_RESET
);
1135 ret
= snd_soc_new_pcms(socdev
, SNDRV_DEFAULT_IDX1
, SNDRV_DEFAULT_STR1
);
1137 printk(KERN_ERR
"aic3x: failed to create pcms\n");
1141 /* DAC default volume and mute */
1142 aic3x_write(codec
, LDAC_VOL
, DEFAULT_VOL
| MUTE_ON
);
1143 aic3x_write(codec
, RDAC_VOL
, DEFAULT_VOL
| MUTE_ON
);
1145 /* DAC to HP default volume and route to Output mixer */
1146 aic3x_write(codec
, DACL1_2_HPLOUT_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1147 aic3x_write(codec
, DACR1_2_HPROUT_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1148 aic3x_write(codec
, DACL1_2_HPLCOM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1149 aic3x_write(codec
, DACR1_2_HPRCOM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1150 /* DAC to Line Out default volume and route to Output mixer */
1151 aic3x_write(codec
, DACL1_2_LLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1152 aic3x_write(codec
, DACR1_2_RLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1153 /* DAC to Mono Line Out default volume and route to Output mixer */
1154 aic3x_write(codec
, DACL1_2_MONOLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1155 aic3x_write(codec
, DACR1_2_MONOLOPM_VOL
, DEFAULT_VOL
| ROUTE_ON
);
1157 /* unmute all outputs */
1158 reg
= aic3x_read_reg_cache(codec
, LLOPM_CTRL
);
1159 aic3x_write(codec
, LLOPM_CTRL
, reg
| UNMUTE
);
1160 reg
= aic3x_read_reg_cache(codec
, RLOPM_CTRL
);
1161 aic3x_write(codec
, RLOPM_CTRL
, reg
| UNMUTE
);
1162 reg
= aic3x_read_reg_cache(codec
, MONOLOPM_CTRL
);
1163 aic3x_write(codec
, MONOLOPM_CTRL
, reg
| UNMUTE
);
1164 reg
= aic3x_read_reg_cache(codec
, HPLOUT_CTRL
);
1165 aic3x_write(codec
, HPLOUT_CTRL
, reg
| UNMUTE
);
1166 reg
= aic3x_read_reg_cache(codec
, HPROUT_CTRL
);
1167 aic3x_write(codec
, HPROUT_CTRL
, reg
| UNMUTE
);
1168 reg
= aic3x_read_reg_cache(codec
, HPLCOM_CTRL
);
1169 aic3x_write(codec
, HPLCOM_CTRL
, reg
| UNMUTE
);
1170 reg
= aic3x_read_reg_cache(codec
, HPRCOM_CTRL
);
1171 aic3x_write(codec
, HPRCOM_CTRL
, reg
| UNMUTE
);
1173 /* ADC default volume and unmute */
1174 aic3x_write(codec
, LADC_VOL
, DEFAULT_GAIN
);
1175 aic3x_write(codec
, RADC_VOL
, DEFAULT_GAIN
);
1176 /* By default route Line1 to ADC PGA mixer */
1177 aic3x_write(codec
, LINE1L_2_LADC_CTRL
, 0x0);
1178 aic3x_write(codec
, LINE1R_2_RADC_CTRL
, 0x0);
1180 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1181 aic3x_write(codec
, PGAL_2_HPLOUT_VOL
, DEFAULT_VOL
);
1182 aic3x_write(codec
, PGAR_2_HPROUT_VOL
, DEFAULT_VOL
);
1183 aic3x_write(codec
, PGAL_2_HPLCOM_VOL
, DEFAULT_VOL
);
1184 aic3x_write(codec
, PGAR_2_HPRCOM_VOL
, DEFAULT_VOL
);
1185 /* PGA to Line Out default volume, disconnect from Output Mixer */
1186 aic3x_write(codec
, PGAL_2_LLOPM_VOL
, DEFAULT_VOL
);
1187 aic3x_write(codec
, PGAR_2_RLOPM_VOL
, DEFAULT_VOL
);
1188 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1189 aic3x_write(codec
, PGAL_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1190 aic3x_write(codec
, PGAR_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1192 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1193 aic3x_write(codec
, LINE2L_2_HPLOUT_VOL
, DEFAULT_VOL
);
1194 aic3x_write(codec
, LINE2R_2_HPROUT_VOL
, DEFAULT_VOL
);
1195 aic3x_write(codec
, LINE2L_2_HPLCOM_VOL
, DEFAULT_VOL
);
1196 aic3x_write(codec
, LINE2R_2_HPRCOM_VOL
, DEFAULT_VOL
);
1197 /* Line2 Line Out default volume, disconnect from Output Mixer */
1198 aic3x_write(codec
, LINE2L_2_LLOPM_VOL
, DEFAULT_VOL
);
1199 aic3x_write(codec
, LINE2R_2_RLOPM_VOL
, DEFAULT_VOL
);
1200 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1201 aic3x_write(codec
, LINE2L_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1202 aic3x_write(codec
, LINE2R_2_MONOLOPM_VOL
, DEFAULT_VOL
);
1204 /* off, with power on */
1205 aic3x_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1207 /* setup GPIO functions */
1208 aic3x_write(codec
, AIC3X_GPIO1_REG
, (setup
->gpio_func
[0] & 0xf) << 4);
1209 aic3x_write(codec
, AIC3X_GPIO2_REG
, (setup
->gpio_func
[1] & 0xf) << 4);
1211 snd_soc_add_controls(codec
, aic3x_snd_controls
,
1212 ARRAY_SIZE(aic3x_snd_controls
));
1213 aic3x_add_widgets(codec
);
1214 ret
= snd_soc_init_card(socdev
);
1216 printk(KERN_ERR
"aic3x: failed to register card\n");
1223 snd_soc_free_pcms(socdev
);
1224 snd_soc_dapm_free(socdev
);
1226 kfree(codec
->reg_cache
);
1230 static struct snd_soc_device
*aic3x_socdev
;
1232 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1234 * AIC3X 2 wire address can be up to 4 devices with device addresses
1235 * 0x18, 0x19, 0x1A, 0x1B
1239 * If the i2c layer weren't so broken, we could pass this kind of data
1242 static int aic3x_i2c_probe(struct i2c_client
*i2c
,
1243 const struct i2c_device_id
*id
)
1245 struct snd_soc_device
*socdev
= aic3x_socdev
;
1246 struct snd_soc_codec
*codec
= socdev
->codec
;
1249 i2c_set_clientdata(i2c
, codec
);
1250 codec
->control_data
= i2c
;
1252 ret
= aic3x_init(socdev
);
1254 printk(KERN_ERR
"aic3x: failed to initialise AIC3X\n");
1258 static int aic3x_i2c_remove(struct i2c_client
*client
)
1260 struct snd_soc_codec
*codec
= i2c_get_clientdata(client
);
1261 kfree(codec
->reg_cache
);
1265 static const struct i2c_device_id aic3x_i2c_id
[] = {
1266 { "tlv320aic3x", 0 },
1269 MODULE_DEVICE_TABLE(i2c
, aic3x_i2c_id
);
1271 /* machine i2c codec control layer */
1272 static struct i2c_driver aic3x_i2c_driver
= {
1274 .name
= "aic3x I2C Codec",
1275 .owner
= THIS_MODULE
,
1277 .probe
= aic3x_i2c_probe
,
1278 .remove
= aic3x_i2c_remove
,
1279 .id_table
= aic3x_i2c_id
,
1282 static int aic3x_i2c_read(struct i2c_client
*client
, u8
*value
, int len
)
1284 value
[0] = i2c_smbus_read_byte_data(client
, value
[0]);
1288 static int aic3x_add_i2c_device(struct platform_device
*pdev
,
1289 const struct aic3x_setup_data
*setup
)
1291 struct i2c_board_info info
;
1292 struct i2c_adapter
*adapter
;
1293 struct i2c_client
*client
;
1296 ret
= i2c_add_driver(&aic3x_i2c_driver
);
1298 dev_err(&pdev
->dev
, "can't add i2c driver\n");
1302 memset(&info
, 0, sizeof(struct i2c_board_info
));
1303 info
.addr
= setup
->i2c_address
;
1304 strlcpy(info
.type
, "tlv320aic3x", I2C_NAME_SIZE
);
1306 adapter
= i2c_get_adapter(setup
->i2c_bus
);
1308 dev_err(&pdev
->dev
, "can't get i2c adapter %d\n",
1313 client
= i2c_new_device(adapter
, &info
);
1314 i2c_put_adapter(adapter
);
1316 dev_err(&pdev
->dev
, "can't add i2c device at 0x%x\n",
1317 (unsigned int)info
.addr
);
1324 i2c_del_driver(&aic3x_i2c_driver
);
1329 static int aic3x_probe(struct platform_device
*pdev
)
1331 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1332 struct aic3x_setup_data
*setup
;
1333 struct snd_soc_codec
*codec
;
1334 struct aic3x_priv
*aic3x
;
1337 printk(KERN_INFO
"AIC3X Audio Codec %s\n", AIC3X_VERSION
);
1339 setup
= socdev
->codec_data
;
1340 codec
= kzalloc(sizeof(struct snd_soc_codec
), GFP_KERNEL
);
1344 aic3x
= kzalloc(sizeof(struct aic3x_priv
), GFP_KERNEL
);
1345 if (aic3x
== NULL
) {
1350 codec
->private_data
= aic3x
;
1351 socdev
->codec
= codec
;
1352 mutex_init(&codec
->mutex
);
1353 INIT_LIST_HEAD(&codec
->dapm_widgets
);
1354 INIT_LIST_HEAD(&codec
->dapm_paths
);
1356 aic3x_socdev
= socdev
;
1357 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1358 if (setup
->i2c_address
) {
1359 codec
->hw_write
= (hw_write_t
) i2c_master_send
;
1360 codec
->hw_read
= (hw_read_t
) aic3x_i2c_read
;
1361 ret
= aic3x_add_i2c_device(pdev
, setup
);
1364 /* Add other interfaces here */
1368 kfree(codec
->private_data
);
1374 static int aic3x_remove(struct platform_device
*pdev
)
1376 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1377 struct snd_soc_codec
*codec
= socdev
->codec
;
1379 /* power down chip */
1380 if (codec
->control_data
)
1381 aic3x_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1383 snd_soc_free_pcms(socdev
);
1384 snd_soc_dapm_free(socdev
);
1385 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1386 i2c_unregister_device(codec
->control_data
);
1387 i2c_del_driver(&aic3x_i2c_driver
);
1389 kfree(codec
->private_data
);
1395 struct snd_soc_codec_device soc_codec_dev_aic3x
= {
1396 .probe
= aic3x_probe
,
1397 .remove
= aic3x_remove
,
1398 .suspend
= aic3x_suspend
,
1399 .resume
= aic3x_resume
,
1401 EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x
);
1403 static int __init
aic3x_modinit(void)
1405 return snd_soc_register_dai(&aic3x_dai
);
1407 module_init(aic3x_modinit
);
1409 static void __exit
aic3x_exit(void)
1411 snd_soc_unregister_dai(&aic3x_dai
);
1413 module_exit(aic3x_exit
);
1415 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1416 MODULE_AUTHOR("Vladimir Barinov");
1417 MODULE_LICENSE("GPL");