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Merge 4.14.24 into android-4.14
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / sound / soc / codecs / nau8825.c
1 /*
2 * Nuvoton NAU8825 audio codec driver
3 *
4 * Copyright 2015 Google Chromium project.
5 * Author: Anatol Pomozov <anatol@chromium.org>
6 * Copyright 2015 Nuvoton Technology Corp.
7 * Co-author: Meng-Huang Kuo <mhkuo@nuvoton.com>
8 *
9 * Licensed under the GPL-2.
10 */
11
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/i2c.h>
16 #include <linux/regmap.h>
17 #include <linux/slab.h>
18 #include <linux/clk.h>
19 #include <linux/acpi.h>
20 #include <linux/math64.h>
21 #include <linux/semaphore.h>
22
23 #include <sound/initval.h>
24 #include <sound/tlv.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/jack.h>
30
31
32 #include "nau8825.h"
33
34
35 #define NUVOTON_CODEC_DAI "nau8825-hifi"
36
37 #define NAU_FREF_MAX 13500000
38 #define NAU_FVCO_MAX 124000000
39 #define NAU_FVCO_MIN 90000000
40
41 /* cross talk suppression detection */
42 #define LOG10_MAGIC 646456993
43 #define GAIN_AUGMENT 22500
44 #define SIDETONE_BASE 207000
45
46 /* the maximum frequency of CLK_ADC and CLK_DAC */
47 #define CLK_DA_AD_MAX 6144000
48
49 static int nau8825_configure_sysclk(struct nau8825 *nau8825,
50 int clk_id, unsigned int freq);
51
52 struct nau8825_fll {
53 int mclk_src;
54 int ratio;
55 int fll_frac;
56 int fll_int;
57 int clk_ref_div;
58 };
59
60 struct nau8825_fll_attr {
61 unsigned int param;
62 unsigned int val;
63 };
64
65 /* scaling for mclk from sysclk_src output */
66 static const struct nau8825_fll_attr mclk_src_scaling[] = {
67 { 1, 0x0 },
68 { 2, 0x2 },
69 { 4, 0x3 },
70 { 8, 0x4 },
71 { 16, 0x5 },
72 { 32, 0x6 },
73 { 3, 0x7 },
74 { 6, 0xa },
75 { 12, 0xb },
76 { 24, 0xc },
77 { 48, 0xd },
78 { 96, 0xe },
79 { 5, 0xf },
80 };
81
82 /* ratio for input clk freq */
83 static const struct nau8825_fll_attr fll_ratio[] = {
84 { 512000, 0x01 },
85 { 256000, 0x02 },
86 { 128000, 0x04 },
87 { 64000, 0x08 },
88 { 32000, 0x10 },
89 { 8000, 0x20 },
90 { 4000, 0x40 },
91 };
92
93 static const struct nau8825_fll_attr fll_pre_scalar[] = {
94 { 1, 0x0 },
95 { 2, 0x1 },
96 { 4, 0x2 },
97 { 8, 0x3 },
98 };
99
100 /* over sampling rate */
101 struct nau8825_osr_attr {
102 unsigned int osr;
103 unsigned int clk_src;
104 };
105
106 static const struct nau8825_osr_attr osr_dac_sel[] = {
107 { 64, 2 }, /* OSR 64, SRC 1/4 */
108 { 256, 0 }, /* OSR 256, SRC 1 */
109 { 128, 1 }, /* OSR 128, SRC 1/2 */
110 { 0, 0 },
111 { 32, 3 }, /* OSR 32, SRC 1/8 */
112 };
113
114 static const struct nau8825_osr_attr osr_adc_sel[] = {
115 { 32, 3 }, /* OSR 32, SRC 1/8 */
116 { 64, 2 }, /* OSR 64, SRC 1/4 */
117 { 128, 1 }, /* OSR 128, SRC 1/2 */
118 { 256, 0 }, /* OSR 256, SRC 1 */
119 };
120
121 static const struct reg_default nau8825_reg_defaults[] = {
122 { NAU8825_REG_ENA_CTRL, 0x00ff },
123 { NAU8825_REG_IIC_ADDR_SET, 0x0 },
124 { NAU8825_REG_CLK_DIVIDER, 0x0050 },
125 { NAU8825_REG_FLL1, 0x0 },
126 { NAU8825_REG_FLL2, 0x3126 },
127 { NAU8825_REG_FLL3, 0x0008 },
128 { NAU8825_REG_FLL4, 0x0010 },
129 { NAU8825_REG_FLL5, 0x0 },
130 { NAU8825_REG_FLL6, 0x6000 },
131 { NAU8825_REG_FLL_VCO_RSV, 0xf13c },
132 { NAU8825_REG_HSD_CTRL, 0x000c },
133 { NAU8825_REG_JACK_DET_CTRL, 0x0 },
134 { NAU8825_REG_INTERRUPT_MASK, 0x0 },
135 { NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff },
136 { NAU8825_REG_SAR_CTRL, 0x0015 },
137 { NAU8825_REG_KEYDET_CTRL, 0x0110 },
138 { NAU8825_REG_VDET_THRESHOLD_1, 0x0 },
139 { NAU8825_REG_VDET_THRESHOLD_2, 0x0 },
140 { NAU8825_REG_VDET_THRESHOLD_3, 0x0 },
141 { NAU8825_REG_VDET_THRESHOLD_4, 0x0 },
142 { NAU8825_REG_GPIO34_CTRL, 0x0 },
143 { NAU8825_REG_GPIO12_CTRL, 0x0 },
144 { NAU8825_REG_TDM_CTRL, 0x0 },
145 { NAU8825_REG_I2S_PCM_CTRL1, 0x000b },
146 { NAU8825_REG_I2S_PCM_CTRL2, 0x8010 },
147 { NAU8825_REG_LEFT_TIME_SLOT, 0x0 },
148 { NAU8825_REG_RIGHT_TIME_SLOT, 0x0 },
149 { NAU8825_REG_BIQ_CTRL, 0x0 },
150 { NAU8825_REG_BIQ_COF1, 0x0 },
151 { NAU8825_REG_BIQ_COF2, 0x0 },
152 { NAU8825_REG_BIQ_COF3, 0x0 },
153 { NAU8825_REG_BIQ_COF4, 0x0 },
154 { NAU8825_REG_BIQ_COF5, 0x0 },
155 { NAU8825_REG_BIQ_COF6, 0x0 },
156 { NAU8825_REG_BIQ_COF7, 0x0 },
157 { NAU8825_REG_BIQ_COF8, 0x0 },
158 { NAU8825_REG_BIQ_COF9, 0x0 },
159 { NAU8825_REG_BIQ_COF10, 0x0 },
160 { NAU8825_REG_ADC_RATE, 0x0010 },
161 { NAU8825_REG_DAC_CTRL1, 0x0001 },
162 { NAU8825_REG_DAC_CTRL2, 0x0 },
163 { NAU8825_REG_DAC_DGAIN_CTRL, 0x0 },
164 { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf },
165 { NAU8825_REG_MUTE_CTRL, 0x0 },
166 { NAU8825_REG_HSVOL_CTRL, 0x0 },
167 { NAU8825_REG_DACL_CTRL, 0x02cf },
168 { NAU8825_REG_DACR_CTRL, 0x00cf },
169 { NAU8825_REG_ADC_DRC_KNEE_IP12, 0x1486 },
170 { NAU8825_REG_ADC_DRC_KNEE_IP34, 0x0f12 },
171 { NAU8825_REG_ADC_DRC_SLOPES, 0x25ff },
172 { NAU8825_REG_ADC_DRC_ATKDCY, 0x3457 },
173 { NAU8825_REG_DAC_DRC_KNEE_IP12, 0x1486 },
174 { NAU8825_REG_DAC_DRC_KNEE_IP34, 0x0f12 },
175 { NAU8825_REG_DAC_DRC_SLOPES, 0x25f9 },
176 { NAU8825_REG_DAC_DRC_ATKDCY, 0x3457 },
177 { NAU8825_REG_IMM_MODE_CTRL, 0x0 },
178 { NAU8825_REG_CLASSG_CTRL, 0x0 },
179 { NAU8825_REG_OPT_EFUSE_CTRL, 0x0 },
180 { NAU8825_REG_MISC_CTRL, 0x0 },
181 { NAU8825_REG_BIAS_ADJ, 0x0 },
182 { NAU8825_REG_TRIM_SETTINGS, 0x0 },
183 { NAU8825_REG_ANALOG_CONTROL_1, 0x0 },
184 { NAU8825_REG_ANALOG_CONTROL_2, 0x0 },
185 { NAU8825_REG_ANALOG_ADC_1, 0x0011 },
186 { NAU8825_REG_ANALOG_ADC_2, 0x0020 },
187 { NAU8825_REG_RDAC, 0x0008 },
188 { NAU8825_REG_MIC_BIAS, 0x0006 },
189 { NAU8825_REG_BOOST, 0x0 },
190 { NAU8825_REG_FEPGA, 0x0 },
191 { NAU8825_REG_POWER_UP_CONTROL, 0x0 },
192 { NAU8825_REG_CHARGE_PUMP, 0x0 },
193 };
194
195 /* register backup table when cross talk detection */
196 static struct reg_default nau8825_xtalk_baktab[] = {
197 { NAU8825_REG_ADC_DGAIN_CTRL, 0 },
198 { NAU8825_REG_HSVOL_CTRL, 0 },
199 { NAU8825_REG_DACL_CTRL, 0 },
200 { NAU8825_REG_DACR_CTRL, 0 },
201 };
202
203 static const unsigned short logtable[256] = {
204 0x0000, 0x0171, 0x02e0, 0x044e, 0x05ba, 0x0725, 0x088e, 0x09f7,
205 0x0b5d, 0x0cc3, 0x0e27, 0x0f8a, 0x10eb, 0x124b, 0x13aa, 0x1508,
206 0x1664, 0x17bf, 0x1919, 0x1a71, 0x1bc8, 0x1d1e, 0x1e73, 0x1fc6,
207 0x2119, 0x226a, 0x23ba, 0x2508, 0x2656, 0x27a2, 0x28ed, 0x2a37,
208 0x2b80, 0x2cc8, 0x2e0f, 0x2f54, 0x3098, 0x31dc, 0x331e, 0x345f,
209 0x359f, 0x36de, 0x381b, 0x3958, 0x3a94, 0x3bce, 0x3d08, 0x3e41,
210 0x3f78, 0x40af, 0x41e4, 0x4319, 0x444c, 0x457f, 0x46b0, 0x47e1,
211 0x4910, 0x4a3f, 0x4b6c, 0x4c99, 0x4dc5, 0x4eef, 0x5019, 0x5142,
212 0x526a, 0x5391, 0x54b7, 0x55dc, 0x5700, 0x5824, 0x5946, 0x5a68,
213 0x5b89, 0x5ca8, 0x5dc7, 0x5ee5, 0x6003, 0x611f, 0x623a, 0x6355,
214 0x646f, 0x6588, 0x66a0, 0x67b7, 0x68ce, 0x69e4, 0x6af8, 0x6c0c,
215 0x6d20, 0x6e32, 0x6f44, 0x7055, 0x7165, 0x7274, 0x7383, 0x7490,
216 0x759d, 0x76aa, 0x77b5, 0x78c0, 0x79ca, 0x7ad3, 0x7bdb, 0x7ce3,
217 0x7dea, 0x7ef0, 0x7ff6, 0x80fb, 0x81ff, 0x8302, 0x8405, 0x8507,
218 0x8608, 0x8709, 0x8809, 0x8908, 0x8a06, 0x8b04, 0x8c01, 0x8cfe,
219 0x8dfa, 0x8ef5, 0x8fef, 0x90e9, 0x91e2, 0x92db, 0x93d2, 0x94ca,
220 0x95c0, 0x96b6, 0x97ab, 0x98a0, 0x9994, 0x9a87, 0x9b7a, 0x9c6c,
221 0x9d5e, 0x9e4f, 0x9f3f, 0xa02e, 0xa11e, 0xa20c, 0xa2fa, 0xa3e7,
222 0xa4d4, 0xa5c0, 0xa6ab, 0xa796, 0xa881, 0xa96a, 0xaa53, 0xab3c,
223 0xac24, 0xad0c, 0xadf2, 0xaed9, 0xafbe, 0xb0a4, 0xb188, 0xb26c,
224 0xb350, 0xb433, 0xb515, 0xb5f7, 0xb6d9, 0xb7ba, 0xb89a, 0xb97a,
225 0xba59, 0xbb38, 0xbc16, 0xbcf4, 0xbdd1, 0xbead, 0xbf8a, 0xc065,
226 0xc140, 0xc21b, 0xc2f5, 0xc3cf, 0xc4a8, 0xc580, 0xc658, 0xc730,
227 0xc807, 0xc8de, 0xc9b4, 0xca8a, 0xcb5f, 0xcc34, 0xcd08, 0xcddc,
228 0xceaf, 0xcf82, 0xd054, 0xd126, 0xd1f7, 0xd2c8, 0xd399, 0xd469,
229 0xd538, 0xd607, 0xd6d6, 0xd7a4, 0xd872, 0xd93f, 0xda0c, 0xdad9,
230 0xdba5, 0xdc70, 0xdd3b, 0xde06, 0xded0, 0xdf9a, 0xe063, 0xe12c,
231 0xe1f5, 0xe2bd, 0xe385, 0xe44c, 0xe513, 0xe5d9, 0xe69f, 0xe765,
232 0xe82a, 0xe8ef, 0xe9b3, 0xea77, 0xeb3b, 0xebfe, 0xecc1, 0xed83,
233 0xee45, 0xef06, 0xefc8, 0xf088, 0xf149, 0xf209, 0xf2c8, 0xf387,
234 0xf446, 0xf505, 0xf5c3, 0xf680, 0xf73e, 0xf7fb, 0xf8b7, 0xf973,
235 0xfa2f, 0xfaea, 0xfba5, 0xfc60, 0xfd1a, 0xfdd4, 0xfe8e, 0xff47
236 };
237
238 /**
239 * nau8825_sema_acquire - acquire the semaphore of nau88l25
240 * @nau8825: component to register the codec private data with
241 * @timeout: how long in jiffies to wait before failure or zero to wait
242 * until release
243 *
244 * Attempts to acquire the semaphore with number of jiffies. If no more
245 * tasks are allowed to acquire the semaphore, calling this function will
246 * put the task to sleep. If the semaphore is not released within the
247 * specified number of jiffies, this function returns.
248 * Acquires the semaphore without jiffies. If no more tasks are allowed
249 * to acquire the semaphore, calling this function will put the task to
250 * sleep until the semaphore is released.
251 * If the semaphore is not released within the specified number of jiffies,
252 * this function returns -ETIME.
253 * If the sleep is interrupted by a signal, this function will return -EINTR.
254 * It returns 0 if the semaphore was acquired successfully.
255 */
256 static int nau8825_sema_acquire(struct nau8825 *nau8825, long timeout)
257 {
258 int ret;
259
260 if (timeout) {
261 ret = down_timeout(&nau8825->xtalk_sem, timeout);
262 if (ret < 0)
263 dev_warn(nau8825->dev, "Acquire semaphore timeout\n");
264 } else {
265 ret = down_interruptible(&nau8825->xtalk_sem);
266 if (ret < 0)
267 dev_warn(nau8825->dev, "Acquire semaphore fail\n");
268 }
269
270 return ret;
271 }
272
273 /**
274 * nau8825_sema_release - release the semaphore of nau88l25
275 * @nau8825: component to register the codec private data with
276 *
277 * Release the semaphore which may be called from any context and
278 * even by tasks which have never called down().
279 */
280 static inline void nau8825_sema_release(struct nau8825 *nau8825)
281 {
282 up(&nau8825->xtalk_sem);
283 }
284
285 /**
286 * nau8825_sema_reset - reset the semaphore for nau88l25
287 * @nau8825: component to register the codec private data with
288 *
289 * Reset the counter of the semaphore. Call this function to restart
290 * a new round task management.
291 */
292 static inline void nau8825_sema_reset(struct nau8825 *nau8825)
293 {
294 nau8825->xtalk_sem.count = 1;
295 }
296
297 /**
298 * Ramp up the headphone volume change gradually to target level.
299 *
300 * @nau8825: component to register the codec private data with
301 * @vol_from: the volume to start up
302 * @vol_to: the target volume
303 * @step: the volume span to move on
304 *
305 * The headphone volume is from 0dB to minimum -54dB and -1dB per step.
306 * If the volume changes sharp, there is a pop noise heard in headphone. We
307 * provide the function to ramp up the volume up or down by delaying 10ms
308 * per step.
309 */
310 static void nau8825_hpvol_ramp(struct nau8825 *nau8825,
311 unsigned int vol_from, unsigned int vol_to, unsigned int step)
312 {
313 unsigned int value, volume, ramp_up, from, to;
314
315 if (vol_from == vol_to || step == 0) {
316 return;
317 } else if (vol_from < vol_to) {
318 ramp_up = true;
319 from = vol_from;
320 to = vol_to;
321 } else {
322 ramp_up = false;
323 from = vol_to;
324 to = vol_from;
325 }
326 /* only handle volume from 0dB to minimum -54dB */
327 if (to > NAU8825_HP_VOL_MIN)
328 to = NAU8825_HP_VOL_MIN;
329
330 for (volume = from; volume < to; volume += step) {
331 if (ramp_up)
332 value = volume;
333 else
334 value = to - volume + from;
335 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
336 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
337 (value << NAU8825_HPL_VOL_SFT) | value);
338 usleep_range(10000, 10500);
339 }
340 if (ramp_up)
341 value = to;
342 else
343 value = from;
344 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
345 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
346 (value << NAU8825_HPL_VOL_SFT) | value);
347 }
348
349 /**
350 * Computes log10 of a value; the result is round off to 3 decimal. This func-
351 * tion takes reference to dvb-math. The source code locates as the following.
352 * Linux/drivers/media/dvb-core/dvb_math.c
353 *
354 * return log10(value) * 1000
355 */
356 static u32 nau8825_intlog10_dec3(u32 value)
357 {
358 u32 msb, logentry, significand, interpolation, log10val;
359 u64 log2val;
360
361 /* first detect the msb (count begins at 0) */
362 msb = fls(value) - 1;
363 /**
364 * now we use a logtable after the following method:
365 *
366 * log2(2^x * y) * 2^24 = x * 2^24 + log2(y) * 2^24
367 * where x = msb and therefore 1 <= y < 2
368 * first y is determined by shifting the value left
369 * so that msb is bit 31
370 * 0x00231f56 -> 0x8C7D5800
371 * the result is y * 2^31 -> "significand"
372 * then the highest 9 bits are used for a table lookup
373 * the highest bit is discarded because it's always set
374 * the highest nine bits in our example are 100011000
375 * so we would use the entry 0x18
376 */
377 significand = value << (31 - msb);
378 logentry = (significand >> 23) & 0xff;
379 /**
380 * last step we do is interpolation because of the
381 * limitations of the log table the error is that part of
382 * the significand which isn't used for lookup then we
383 * compute the ratio between the error and the next table entry
384 * and interpolate it between the log table entry used and the
385 * next one the biggest error possible is 0x7fffff
386 * (in our example it's 0x7D5800)
387 * needed value for next table entry is 0x800000
388 * so the interpolation is
389 * (error / 0x800000) * (logtable_next - logtable_current)
390 * in the implementation the division is moved to the end for
391 * better accuracy there is also an overflow correction if
392 * logtable_next is 256
393 */
394 interpolation = ((significand & 0x7fffff) *
395 ((logtable[(logentry + 1) & 0xff] -
396 logtable[logentry]) & 0xffff)) >> 15;
397
398 log2val = ((msb << 24) + (logtable[logentry] << 8) + interpolation);
399 /**
400 * log10(x) = log2(x) * log10(2)
401 */
402 log10val = (log2val * LOG10_MAGIC) >> 31;
403 /**
404 * the result is round off to 3 decimal
405 */
406 return log10val / ((1 << 24) / 1000);
407 }
408
409 /**
410 * computes cross talk suppression sidetone gain.
411 *
412 * @sig_org: orignal signal level
413 * @sig_cros: cross talk signal level
414 *
415 * The orignal and cross talk signal vlues need to be characterized.
416 * Once these values have been characterized, this sidetone value
417 * can be converted to decibel with the equation below.
418 * sidetone = 20 * log (original signal level / crosstalk signal level)
419 *
420 * return cross talk sidetone gain
421 */
422 static u32 nau8825_xtalk_sidetone(u32 sig_org, u32 sig_cros)
423 {
424 u32 gain, sidetone;
425
426 if (unlikely(sig_org == 0) || unlikely(sig_cros == 0)) {
427 WARN_ON(1);
428 return 0;
429 }
430
431 sig_org = nau8825_intlog10_dec3(sig_org);
432 sig_cros = nau8825_intlog10_dec3(sig_cros);
433 if (sig_org >= sig_cros)
434 gain = (sig_org - sig_cros) * 20 + GAIN_AUGMENT;
435 else
436 gain = (sig_cros - sig_org) * 20 + GAIN_AUGMENT;
437 sidetone = SIDETONE_BASE - gain * 2;
438 sidetone /= 1000;
439
440 return sidetone;
441 }
442
443 static int nau8825_xtalk_baktab_index_by_reg(unsigned int reg)
444 {
445 int index;
446
447 for (index = 0; index < ARRAY_SIZE(nau8825_xtalk_baktab); index++)
448 if (nau8825_xtalk_baktab[index].reg == reg)
449 return index;
450 return -EINVAL;
451 }
452
453 static void nau8825_xtalk_backup(struct nau8825 *nau8825)
454 {
455 int i;
456
457 /* Backup some register values to backup table */
458 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++)
459 regmap_read(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
460 &nau8825_xtalk_baktab[i].def);
461 }
462
463 static void nau8825_xtalk_restore(struct nau8825 *nau8825)
464 {
465 int i, volume;
466
467 /* Restore register values from backup table; When the driver restores
468 * the headphone volumem, it needs recover to original level gradually
469 * with 3dB per step for less pop noise.
470 */
471 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) {
472 if (nau8825_xtalk_baktab[i].reg == NAU8825_REG_HSVOL_CTRL) {
473 /* Ramping up the volume change to reduce pop noise */
474 volume = nau8825_xtalk_baktab[i].def &
475 NAU8825_HPR_VOL_MASK;
476 nau8825_hpvol_ramp(nau8825, 0, volume, 3);
477 continue;
478 }
479 regmap_write(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
480 nau8825_xtalk_baktab[i].def);
481 }
482 }
483
484 static void nau8825_xtalk_prepare_dac(struct nau8825 *nau8825)
485 {
486 /* Enable power of DAC path */
487 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
488 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
489 NAU8825_ENABLE_ADC | NAU8825_ENABLE_ADC_CLK |
490 NAU8825_ENABLE_DAC_CLK, NAU8825_ENABLE_DACR |
491 NAU8825_ENABLE_DACL | NAU8825_ENABLE_ADC |
492 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK);
493 /* Prevent startup click by letting charge pump to ramp up and
494 * change bump enable
495 */
496 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
497 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN,
498 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN);
499 /* Enable clock sync of DAC and DAC clock */
500 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
501 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN |
502 NAU8825_RDAC_FS_BCLK_ENB,
503 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN);
504 /* Power up output driver with 2 stage */
505 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
506 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
507 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L,
508 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
509 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L);
510 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
511 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L,
512 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L);
513 /* HP outputs not shouted to ground */
514 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
515 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 0);
516 /* Enable HP boost driver */
517 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
518 NAU8825_HP_BOOST_DIS, NAU8825_HP_BOOST_DIS);
519 /* Enable class G compare path to supply 1.8V or 0.9V. */
520 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLASSG_CTRL,
521 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN,
522 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN);
523 }
524
525 static void nau8825_xtalk_prepare_adc(struct nau8825 *nau8825)
526 {
527 /* Power up left ADC and raise 5dB than Vmid for Vref */
528 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
529 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK,
530 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB);
531 }
532
533 static void nau8825_xtalk_clock(struct nau8825 *nau8825)
534 {
535 /* Recover FLL default value */
536 regmap_write(nau8825->regmap, NAU8825_REG_FLL1, 0x0);
537 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, 0x3126);
538 regmap_write(nau8825->regmap, NAU8825_REG_FLL3, 0x0008);
539 regmap_write(nau8825->regmap, NAU8825_REG_FLL4, 0x0010);
540 regmap_write(nau8825->regmap, NAU8825_REG_FLL5, 0x0);
541 regmap_write(nau8825->regmap, NAU8825_REG_FLL6, 0x6000);
542 /* Enable internal VCO clock for detection signal generated */
543 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
544 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
545 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN,
546 NAU8825_DCO_EN);
547 /* Given specific clock frequency of internal clock to
548 * generate signal.
549 */
550 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
551 NAU8825_CLK_MCLK_SRC_MASK, 0xf);
552 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
553 NAU8825_FLL_RATIO_MASK, 0x10);
554 }
555
556 static void nau8825_xtalk_prepare(struct nau8825 *nau8825)
557 {
558 int volume, index;
559
560 /* Backup those registers changed by cross talk detection */
561 nau8825_xtalk_backup(nau8825);
562 /* Config IIS as master to output signal by codec */
563 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
564 NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK |
565 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_MASTER |
566 (0x2 << NAU8825_I2S_LRC_DIV_SFT) | 0x1);
567 /* Ramp up headphone volume to 0dB to get better performance and
568 * avoid pop noise in headphone.
569 */
570 index = nau8825_xtalk_baktab_index_by_reg(NAU8825_REG_HSVOL_CTRL);
571 if (index != -EINVAL) {
572 volume = nau8825_xtalk_baktab[index].def &
573 NAU8825_HPR_VOL_MASK;
574 nau8825_hpvol_ramp(nau8825, volume, 0, 3);
575 }
576 nau8825_xtalk_clock(nau8825);
577 nau8825_xtalk_prepare_dac(nau8825);
578 nau8825_xtalk_prepare_adc(nau8825);
579 /* Config channel path and digital gain */
580 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
581 NAU8825_DACL_CH_SEL_MASK | NAU8825_DACL_CH_VOL_MASK,
582 NAU8825_DACL_CH_SEL_L | 0xab);
583 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
584 NAU8825_DACR_CH_SEL_MASK | NAU8825_DACR_CH_VOL_MASK,
585 NAU8825_DACR_CH_SEL_R | 0xab);
586 /* Config cross talk parameters and generate the 23Hz sine wave with
587 * 1/16 full scale of signal level for impedance measurement.
588 */
589 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
590 NAU8825_IMM_THD_MASK | NAU8825_IMM_GEN_VOL_MASK |
591 NAU8825_IMM_CYC_MASK | NAU8825_IMM_DAC_SRC_MASK,
592 (0x9 << NAU8825_IMM_THD_SFT) | NAU8825_IMM_GEN_VOL_1_16th |
593 NAU8825_IMM_CYC_8192 | NAU8825_IMM_DAC_SRC_SIN);
594 /* RMS intrruption enable */
595 regmap_update_bits(nau8825->regmap,
596 NAU8825_REG_INTERRUPT_MASK, NAU8825_IRQ_RMS_EN, 0);
597 /* Power up left and right DAC */
598 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
599 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
600 }
601
602 static void nau8825_xtalk_clean_dac(struct nau8825 *nau8825)
603 {
604 /* Disable HP boost driver */
605 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
606 NAU8825_HP_BOOST_DIS, 0);
607 /* HP outputs shouted to ground */
608 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
609 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
610 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
611 /* Power down left and right DAC */
612 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
613 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
614 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
615 /* Enable the TESTDAC and disable L/R HP impedance */
616 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
617 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP |
618 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
619 /* Power down output driver with 2 stage */
620 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
621 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L, 0);
622 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
623 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
624 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L, 0);
625 /* Disable clock sync of DAC and DAC clock */
626 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
627 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN, 0);
628 /* Disable charge pump ramp up function and change bump */
629 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
630 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN, 0);
631 /* Disable power of DAC path */
632 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
633 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
634 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK, 0);
635 if (!nau8825->irq)
636 regmap_update_bits(nau8825->regmap,
637 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
638 }
639
640 static void nau8825_xtalk_clean_adc(struct nau8825 *nau8825)
641 {
642 /* Power down left ADC and restore voltage to Vmid */
643 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
644 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, 0);
645 }
646
647 static void nau8825_xtalk_clean(struct nau8825 *nau8825)
648 {
649 /* Enable internal VCO needed for interruptions */
650 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
651 nau8825_xtalk_clean_dac(nau8825);
652 nau8825_xtalk_clean_adc(nau8825);
653 /* Clear cross talk parameters and disable */
654 regmap_write(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 0);
655 /* RMS intrruption disable */
656 regmap_update_bits(nau8825->regmap, NAU8825_REG_INTERRUPT_MASK,
657 NAU8825_IRQ_RMS_EN, NAU8825_IRQ_RMS_EN);
658 /* Recover default value for IIS */
659 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
660 NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK |
661 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_SLAVE);
662 /* Restore value of specific register for cross talk */
663 nau8825_xtalk_restore(nau8825);
664 }
665
666 static void nau8825_xtalk_imm_start(struct nau8825 *nau8825, int vol)
667 {
668 /* Apply ADC volume for better cross talk performance */
669 regmap_update_bits(nau8825->regmap, NAU8825_REG_ADC_DGAIN_CTRL,
670 NAU8825_ADC_DIG_VOL_MASK, vol);
671 /* Disables JKTIP(HPL) DAC channel for right to left measurement.
672 * Do it before sending signal in order to erase pop noise.
673 */
674 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
675 NAU8825_BIAS_TESTDACR_EN | NAU8825_BIAS_TESTDACL_EN,
676 NAU8825_BIAS_TESTDACL_EN);
677 switch (nau8825->xtalk_state) {
678 case NAU8825_XTALK_HPR_R2L:
679 /* Enable right headphone impedance */
680 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
681 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
682 NAU8825_BIAS_HPR_IMP);
683 break;
684 case NAU8825_XTALK_HPL_R2L:
685 /* Enable left headphone impedance */
686 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
687 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
688 NAU8825_BIAS_HPL_IMP);
689 break;
690 default:
691 break;
692 }
693 msleep(100);
694 /* Impedance measurement mode enable */
695 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
696 NAU8825_IMM_EN, NAU8825_IMM_EN);
697 }
698
699 static void nau8825_xtalk_imm_stop(struct nau8825 *nau8825)
700 {
701 /* Impedance measurement mode disable */
702 regmap_update_bits(nau8825->regmap,
703 NAU8825_REG_IMM_MODE_CTRL, NAU8825_IMM_EN, 0);
704 }
705
706 /* The cross talk measurement function can reduce cross talk across the
707 * JKTIP(HPL) and JKR1(HPR) outputs which measures the cross talk signal
708 * level to determine what cross talk reduction gain is. This system works by
709 * sending a 23Hz -24dBV sine wave into the headset output DAC and through
710 * the PGA. The output of the PGA is then connected to an internal current
711 * sense which measures the attenuated 23Hz signal and passing the output to
712 * an ADC which converts the measurement to a binary code. With two separated
713 * measurement, one for JKR1(HPR) and the other JKTIP(HPL), measurement data
714 * can be separated read in IMM_RMS_L for HSR and HSL after each measurement.
715 * Thus, the measurement function has four states to complete whole sequence.
716 * 1. Prepare state : Prepare the resource for detection and transfer to HPR
717 * IMM stat to make JKR1(HPR) impedance measure.
718 * 2. HPR IMM state : Read out orignal signal level of JKR1(HPR) and transfer
719 * to HPL IMM state to make JKTIP(HPL) impedance measure.
720 * 3. HPL IMM state : Read out cross talk signal level of JKTIP(HPL) and
721 * transfer to IMM state to determine suppression sidetone gain.
722 * 4. IMM state : Computes cross talk suppression sidetone gain with orignal
723 * and cross talk signal level. Apply this gain and then restore codec
724 * configuration. Then transfer to Done state for ending.
725 */
726 static void nau8825_xtalk_measure(struct nau8825 *nau8825)
727 {
728 u32 sidetone;
729
730 switch (nau8825->xtalk_state) {
731 case NAU8825_XTALK_PREPARE:
732 /* In prepare state, set up clock, intrruption, DAC path, ADC
733 * path and cross talk detection parameters for preparation.
734 */
735 nau8825_xtalk_prepare(nau8825);
736 msleep(280);
737 /* Trigger right headphone impedance detection */
738 nau8825->xtalk_state = NAU8825_XTALK_HPR_R2L;
739 nau8825_xtalk_imm_start(nau8825, 0x00d2);
740 break;
741 case NAU8825_XTALK_HPR_R2L:
742 /* In right headphone IMM state, read out right headphone
743 * impedance measure result, and then start up left side.
744 */
745 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
746 &nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
747 dev_dbg(nau8825->dev, "HPR_R2L imm: %x\n",
748 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
749 /* Disable then re-enable IMM mode to update */
750 nau8825_xtalk_imm_stop(nau8825);
751 /* Trigger left headphone impedance detection */
752 nau8825->xtalk_state = NAU8825_XTALK_HPL_R2L;
753 nau8825_xtalk_imm_start(nau8825, 0x00ff);
754 break;
755 case NAU8825_XTALK_HPL_R2L:
756 /* In left headphone IMM state, read out left headphone
757 * impedance measure result, and delay some time to wait
758 * detection sine wave output finish. Then, we can calculate
759 * the cross talk suppresstion side tone according to the L/R
760 * headphone imedance.
761 */
762 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
763 &nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
764 dev_dbg(nau8825->dev, "HPL_R2L imm: %x\n",
765 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
766 nau8825_xtalk_imm_stop(nau8825);
767 msleep(150);
768 nau8825->xtalk_state = NAU8825_XTALK_IMM;
769 break;
770 case NAU8825_XTALK_IMM:
771 /* In impedance measure state, the orignal and cross talk
772 * signal level vlues are ready. The side tone gain is deter-
773 * mined with these signal level. After all, restore codec
774 * configuration.
775 */
776 sidetone = nau8825_xtalk_sidetone(
777 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L],
778 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
779 dev_dbg(nau8825->dev, "cross talk sidetone: %x\n", sidetone);
780 regmap_write(nau8825->regmap, NAU8825_REG_DAC_DGAIN_CTRL,
781 (sidetone << 8) | sidetone);
782 nau8825_xtalk_clean(nau8825);
783 nau8825->xtalk_state = NAU8825_XTALK_DONE;
784 break;
785 default:
786 break;
787 }
788 }
789
790 static void nau8825_xtalk_work(struct work_struct *work)
791 {
792 struct nau8825 *nau8825 = container_of(
793 work, struct nau8825, xtalk_work);
794
795 nau8825_xtalk_measure(nau8825);
796 /* To determine the cross talk side tone gain when reach
797 * the impedance measure state.
798 */
799 if (nau8825->xtalk_state == NAU8825_XTALK_IMM)
800 nau8825_xtalk_measure(nau8825);
801
802 /* Delay jack report until cross talk detection process
803 * completed. It can avoid application to do playback
804 * preparation before cross talk detection is still working.
805 * Meanwhile, the protection of the cross talk detection
806 * is released.
807 */
808 if (nau8825->xtalk_state == NAU8825_XTALK_DONE) {
809 snd_soc_jack_report(nau8825->jack, nau8825->xtalk_event,
810 nau8825->xtalk_event_mask);
811 nau8825_sema_release(nau8825);
812 nau8825->xtalk_protect = false;
813 }
814 }
815
816 static void nau8825_xtalk_cancel(struct nau8825 *nau8825)
817 {
818 /* If the xtalk_protect is true, that means the process is still
819 * on going. The driver forces to cancel the cross talk task and
820 * restores the configuration to original status.
821 */
822 if (nau8825->xtalk_protect) {
823 cancel_work_sync(&nau8825->xtalk_work);
824 nau8825_xtalk_clean(nau8825);
825 }
826 /* Reset parameters for cross talk suppression function */
827 nau8825_sema_reset(nau8825);
828 nau8825->xtalk_state = NAU8825_XTALK_DONE;
829 nau8825->xtalk_protect = false;
830 }
831
832 static bool nau8825_readable_reg(struct device *dev, unsigned int reg)
833 {
834 switch (reg) {
835 case NAU8825_REG_ENA_CTRL ... NAU8825_REG_FLL_VCO_RSV:
836 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
837 case NAU8825_REG_INTERRUPT_MASK ... NAU8825_REG_KEYDET_CTRL:
838 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
839 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
840 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
841 case NAU8825_REG_IMM_MODE_CTRL ... NAU8825_REG_IMM_RMS_R:
842 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
843 case NAU8825_REG_MISC_CTRL:
844 case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_SARDOUT_RAM_STATUS:
845 case NAU8825_REG_BIAS_ADJ:
846 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
847 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
848 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
849 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_GENERAL_STATUS:
850 return true;
851 default:
852 return false;
853 }
854
855 }
856
857 static bool nau8825_writeable_reg(struct device *dev, unsigned int reg)
858 {
859 switch (reg) {
860 case NAU8825_REG_RESET ... NAU8825_REG_FLL_VCO_RSV:
861 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
862 case NAU8825_REG_INTERRUPT_MASK:
863 case NAU8825_REG_INT_CLR_KEY_STATUS ... NAU8825_REG_KEYDET_CTRL:
864 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
865 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
866 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
867 case NAU8825_REG_IMM_MODE_CTRL:
868 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
869 case NAU8825_REG_MISC_CTRL:
870 case NAU8825_REG_BIAS_ADJ:
871 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
872 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
873 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
874 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_CHARGE_PUMP:
875 return true;
876 default:
877 return false;
878 }
879 }
880
881 static bool nau8825_volatile_reg(struct device *dev, unsigned int reg)
882 {
883 switch (reg) {
884 case NAU8825_REG_RESET:
885 case NAU8825_REG_IRQ_STATUS:
886 case NAU8825_REG_INT_CLR_KEY_STATUS:
887 case NAU8825_REG_IMM_RMS_L:
888 case NAU8825_REG_IMM_RMS_R:
889 case NAU8825_REG_I2C_DEVICE_ID:
890 case NAU8825_REG_SARDOUT_RAM_STATUS:
891 case NAU8825_REG_CHARGE_PUMP_INPUT_READ:
892 case NAU8825_REG_GENERAL_STATUS:
893 case NAU8825_REG_BIQ_CTRL ... NAU8825_REG_BIQ_COF10:
894 return true;
895 default:
896 return false;
897 }
898 }
899
900 static int nau8825_adc_event(struct snd_soc_dapm_widget *w,
901 struct snd_kcontrol *kcontrol, int event)
902 {
903 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
904 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
905
906 switch (event) {
907 case SND_SOC_DAPM_POST_PMU:
908 msleep(125);
909 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
910 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
911 break;
912 case SND_SOC_DAPM_POST_PMD:
913 if (!nau8825->irq)
914 regmap_update_bits(nau8825->regmap,
915 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
916 break;
917 default:
918 return -EINVAL;
919 }
920
921 return 0;
922 }
923
924 static int nau8825_pump_event(struct snd_soc_dapm_widget *w,
925 struct snd_kcontrol *kcontrol, int event)
926 {
927 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
928 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
929
930 switch (event) {
931 case SND_SOC_DAPM_POST_PMU:
932 /* Prevent startup click by letting charge pump to ramp up */
933 msleep(10);
934 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
935 NAU8825_JAMNODCLOW, NAU8825_JAMNODCLOW);
936 break;
937 case SND_SOC_DAPM_PRE_PMD:
938 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
939 NAU8825_JAMNODCLOW, 0);
940 break;
941 default:
942 return -EINVAL;
943 }
944
945 return 0;
946 }
947
948 static int nau8825_output_dac_event(struct snd_soc_dapm_widget *w,
949 struct snd_kcontrol *kcontrol, int event)
950 {
951 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
952 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
953
954 switch (event) {
955 case SND_SOC_DAPM_PRE_PMU:
956 /* Disables the TESTDAC to let DAC signal pass through. */
957 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
958 NAU8825_BIAS_TESTDAC_EN, 0);
959 break;
960 case SND_SOC_DAPM_POST_PMD:
961 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
962 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
963 break;
964 default:
965 return -EINVAL;
966 }
967
968 return 0;
969 }
970
971 static int nau8825_biq_coeff_get(struct snd_kcontrol *kcontrol,
972 struct snd_ctl_elem_value *ucontrol)
973 {
974 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
975 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
976
977 if (!component->regmap)
978 return -EINVAL;
979
980 regmap_raw_read(component->regmap, NAU8825_REG_BIQ_COF1,
981 ucontrol->value.bytes.data, params->max);
982 return 0;
983 }
984
985 static int nau8825_biq_coeff_put(struct snd_kcontrol *kcontrol,
986 struct snd_ctl_elem_value *ucontrol)
987 {
988 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
989 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
990 void *data;
991
992 if (!component->regmap)
993 return -EINVAL;
994
995 data = kmemdup(ucontrol->value.bytes.data,
996 params->max, GFP_KERNEL | GFP_DMA);
997 if (!data)
998 return -ENOMEM;
999
1000 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
1001 NAU8825_BIQ_WRT_EN, 0);
1002 regmap_raw_write(component->regmap, NAU8825_REG_BIQ_COF1,
1003 data, params->max);
1004 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
1005 NAU8825_BIQ_WRT_EN, NAU8825_BIQ_WRT_EN);
1006
1007 kfree(data);
1008 return 0;
1009 }
1010
1011 static const char * const nau8825_biq_path[] = {
1012 "ADC", "DAC"
1013 };
1014
1015 static const struct soc_enum nau8825_biq_path_enum =
1016 SOC_ENUM_SINGLE(NAU8825_REG_BIQ_CTRL, NAU8825_BIQ_PATH_SFT,
1017 ARRAY_SIZE(nau8825_biq_path), nau8825_biq_path);
1018
1019 static const char * const nau8825_adc_decimation[] = {
1020 "32", "64", "128", "256"
1021 };
1022
1023 static const struct soc_enum nau8825_adc_decimation_enum =
1024 SOC_ENUM_SINGLE(NAU8825_REG_ADC_RATE, NAU8825_ADC_SYNC_DOWN_SFT,
1025 ARRAY_SIZE(nau8825_adc_decimation), nau8825_adc_decimation);
1026
1027 static const char * const nau8825_dac_oversampl[] = {
1028 "64", "256", "128", "", "32"
1029 };
1030
1031 static const struct soc_enum nau8825_dac_oversampl_enum =
1032 SOC_ENUM_SINGLE(NAU8825_REG_DAC_CTRL1, NAU8825_DAC_OVERSAMPLE_SFT,
1033 ARRAY_SIZE(nau8825_dac_oversampl), nau8825_dac_oversampl);
1034
1035 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -10300, 2400);
1036 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
1037 static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -5400, 0);
1038 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
1039 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -9600, 2400);
1040
1041 static const struct snd_kcontrol_new nau8825_controls[] = {
1042 SOC_SINGLE_TLV("Mic Volume", NAU8825_REG_ADC_DGAIN_CTRL,
1043 0, 0xff, 0, adc_vol_tlv),
1044 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8825_REG_ADC_DGAIN_CTRL,
1045 12, 8, 0x0f, 0, sidetone_vol_tlv),
1046 SOC_DOUBLE_TLV("Headphone Volume", NAU8825_REG_HSVOL_CTRL,
1047 6, 0, 0x3f, 1, dac_vol_tlv),
1048 SOC_SINGLE_TLV("Frontend PGA Volume", NAU8825_REG_POWER_UP_CONTROL,
1049 8, 37, 0, fepga_gain_tlv),
1050 SOC_DOUBLE_TLV("Headphone Crosstalk Volume", NAU8825_REG_DAC_DGAIN_CTRL,
1051 0, 8, 0xff, 0, crosstalk_vol_tlv),
1052
1053 SOC_ENUM("ADC Decimation Rate", nau8825_adc_decimation_enum),
1054 SOC_ENUM("DAC Oversampling Rate", nau8825_dac_oversampl_enum),
1055 /* programmable biquad filter */
1056 SOC_ENUM("BIQ Path Select", nau8825_biq_path_enum),
1057 SND_SOC_BYTES_EXT("BIQ Coefficients", 20,
1058 nau8825_biq_coeff_get, nau8825_biq_coeff_put),
1059 };
1060
1061 /* DAC Mux 0x33[9] and 0x34[9] */
1062 static const char * const nau8825_dac_src[] = {
1063 "DACL", "DACR",
1064 };
1065
1066 static SOC_ENUM_SINGLE_DECL(
1067 nau8825_dacl_enum, NAU8825_REG_DACL_CTRL,
1068 NAU8825_DACL_CH_SEL_SFT, nau8825_dac_src);
1069
1070 static SOC_ENUM_SINGLE_DECL(
1071 nau8825_dacr_enum, NAU8825_REG_DACR_CTRL,
1072 NAU8825_DACR_CH_SEL_SFT, nau8825_dac_src);
1073
1074 static const struct snd_kcontrol_new nau8825_dacl_mux =
1075 SOC_DAPM_ENUM("DACL Source", nau8825_dacl_enum);
1076
1077 static const struct snd_kcontrol_new nau8825_dacr_mux =
1078 SOC_DAPM_ENUM("DACR Source", nau8825_dacr_enum);
1079
1080
1081 static const struct snd_soc_dapm_widget nau8825_dapm_widgets[] = {
1082 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8825_REG_I2S_PCM_CTRL2,
1083 15, 1),
1084
1085 SND_SOC_DAPM_INPUT("MIC"),
1086 SND_SOC_DAPM_MICBIAS("MICBIAS", NAU8825_REG_MIC_BIAS, 8, 0),
1087
1088 SND_SOC_DAPM_PGA("Frontend PGA", NAU8825_REG_POWER_UP_CONTROL, 14, 0,
1089 NULL, 0),
1090
1091 SND_SOC_DAPM_ADC_E("ADC", NULL, SND_SOC_NOPM, 0, 0,
1092 nau8825_adc_event, SND_SOC_DAPM_POST_PMU |
1093 SND_SOC_DAPM_POST_PMD),
1094 SND_SOC_DAPM_SUPPLY("ADC Clock", NAU8825_REG_ENA_CTRL, 7, 0, NULL, 0),
1095 SND_SOC_DAPM_SUPPLY("ADC Power", NAU8825_REG_ANALOG_ADC_2, 6, 0, NULL,
1096 0),
1097
1098 /* ADC for button press detection. A dapm supply widget is used to
1099 * prevent dapm_power_widgets keeping the codec at SND_SOC_BIAS_ON
1100 * during suspend.
1101 */
1102 SND_SOC_DAPM_SUPPLY("SAR", NAU8825_REG_SAR_CTRL,
1103 NAU8825_SAR_ADC_EN_SFT, 0, NULL, 0),
1104
1105 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8825_REG_RDAC, 12, 0, NULL, 0),
1106 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8825_REG_RDAC, 13, 0, NULL, 0),
1107 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8825_REG_RDAC, 8, 0, NULL, 0),
1108 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8825_REG_RDAC, 9, 0, NULL, 0),
1109
1110 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8825_REG_ENA_CTRL,
1111 NAU8825_ENABLE_DACR_SFT, 0),
1112 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8825_REG_ENA_CTRL,
1113 NAU8825_ENABLE_DACL_SFT, 0),
1114 SND_SOC_DAPM_SUPPLY("DDAC Clock", NAU8825_REG_ENA_CTRL, 6, 0, NULL, 0),
1115
1116 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacl_mux),
1117 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacr_mux),
1118
1119 SND_SOC_DAPM_PGA_S("HP amp L", 0,
1120 NAU8825_REG_CLASSG_CTRL, 1, 0, NULL, 0),
1121 SND_SOC_DAPM_PGA_S("HP amp R", 0,
1122 NAU8825_REG_CLASSG_CTRL, 2, 0, NULL, 0),
1123
1124 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8825_REG_CHARGE_PUMP, 5, 0,
1125 nau8825_pump_event, SND_SOC_DAPM_POST_PMU |
1126 SND_SOC_DAPM_PRE_PMD),
1127
1128 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4,
1129 NAU8825_REG_POWER_UP_CONTROL, 5, 0, NULL, 0),
1130 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4,
1131 NAU8825_REG_POWER_UP_CONTROL, 4, 0, NULL, 0),
1132 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5,
1133 NAU8825_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),
1134 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5,
1135 NAU8825_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),
1136 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6,
1137 NAU8825_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),
1138 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6,
1139 NAU8825_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
1140
1141 SND_SOC_DAPM_PGA_S("Output DACL", 7,
1142 NAU8825_REG_CHARGE_PUMP, 8, 1, nau8825_output_dac_event,
1143 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1144 SND_SOC_DAPM_PGA_S("Output DACR", 7,
1145 NAU8825_REG_CHARGE_PUMP, 9, 1, nau8825_output_dac_event,
1146 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1147
1148 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
1149 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8,
1150 NAU8825_REG_HSD_CTRL, 0, 1, NULL, 0),
1151 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8,
1152 NAU8825_REG_HSD_CTRL, 1, 1, NULL, 0),
1153
1154 /* High current HPOL/R boost driver */
1155 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9,
1156 NAU8825_REG_BOOST, 9, 1, NULL, 0),
1157
1158 /* Class G operation control*/
1159 SND_SOC_DAPM_PGA_S("Class G", 10,
1160 NAU8825_REG_CLASSG_CTRL, 0, 0, NULL, 0),
1161
1162 SND_SOC_DAPM_OUTPUT("HPOL"),
1163 SND_SOC_DAPM_OUTPUT("HPOR"),
1164 };
1165
1166 static const struct snd_soc_dapm_route nau8825_dapm_routes[] = {
1167 {"Frontend PGA", NULL, "MIC"},
1168 {"ADC", NULL, "Frontend PGA"},
1169 {"ADC", NULL, "ADC Clock"},
1170 {"ADC", NULL, "ADC Power"},
1171 {"AIFTX", NULL, "ADC"},
1172
1173 {"DDACL", NULL, "Playback"},
1174 {"DDACR", NULL, "Playback"},
1175 {"DDACL", NULL, "DDAC Clock"},
1176 {"DDACR", NULL, "DDAC Clock"},
1177 {"DACL Mux", "DACL", "DDACL"},
1178 {"DACL Mux", "DACR", "DDACR"},
1179 {"DACR Mux", "DACL", "DDACL"},
1180 {"DACR Mux", "DACR", "DDACR"},
1181 {"HP amp L", NULL, "DACL Mux"},
1182 {"HP amp R", NULL, "DACR Mux"},
1183 {"Charge Pump", NULL, "HP amp L"},
1184 {"Charge Pump", NULL, "HP amp R"},
1185 {"ADACL", NULL, "Charge Pump"},
1186 {"ADACR", NULL, "Charge Pump"},
1187 {"ADACL Clock", NULL, "ADACL"},
1188 {"ADACR Clock", NULL, "ADACR"},
1189 {"Output Driver L Stage 1", NULL, "ADACL Clock"},
1190 {"Output Driver R Stage 1", NULL, "ADACR Clock"},
1191 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"},
1192 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"},
1193 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"},
1194 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"},
1195 {"Output DACL", NULL, "Output Driver L Stage 3"},
1196 {"Output DACR", NULL, "Output Driver R Stage 3"},
1197 {"HPOL Pulldown", NULL, "Output DACL"},
1198 {"HPOR Pulldown", NULL, "Output DACR"},
1199 {"HP Boost Driver", NULL, "HPOL Pulldown"},
1200 {"HP Boost Driver", NULL, "HPOR Pulldown"},
1201 {"Class G", NULL, "HP Boost Driver"},
1202 {"HPOL", NULL, "Class G"},
1203 {"HPOR", NULL, "Class G"},
1204 };
1205
1206 static int nau8825_clock_check(struct nau8825 *nau8825,
1207 int stream, int rate, int osr)
1208 {
1209 int osrate;
1210
1211 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1212 if (osr >= ARRAY_SIZE(osr_dac_sel))
1213 return -EINVAL;
1214 osrate = osr_dac_sel[osr].osr;
1215 } else {
1216 if (osr >= ARRAY_SIZE(osr_adc_sel))
1217 return -EINVAL;
1218 osrate = osr_adc_sel[osr].osr;
1219 }
1220
1221 if (!osrate || rate * osr > CLK_DA_AD_MAX) {
1222 dev_err(nau8825->dev, "exceed the maximum frequency of CLK_ADC or CLK_DAC\n");
1223 return -EINVAL;
1224 }
1225
1226 return 0;
1227 }
1228
1229 static int nau8825_hw_params(struct snd_pcm_substream *substream,
1230 struct snd_pcm_hw_params *params,
1231 struct snd_soc_dai *dai)
1232 {
1233 struct snd_soc_codec *codec = dai->codec;
1234 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1235 unsigned int val_len = 0, osr, ctrl_val, bclk_fs, bclk_div;
1236
1237 nau8825_sema_acquire(nau8825, 3 * HZ);
1238
1239 /* CLK_DAC or CLK_ADC = OSR * FS
1240 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)
1241 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
1242 * values must be selected such that the maximum frequency is less
1243 * than 6.144 MHz.
1244 */
1245 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1246 regmap_read(nau8825->regmap, NAU8825_REG_DAC_CTRL1, &osr);
1247 osr &= NAU8825_DAC_OVERSAMPLE_MASK;
1248 if (nau8825_clock_check(nau8825, substream->stream,
1249 params_rate(params), osr))
1250 return -EINVAL;
1251 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1252 NAU8825_CLK_DAC_SRC_MASK,
1253 osr_dac_sel[osr].clk_src << NAU8825_CLK_DAC_SRC_SFT);
1254 } else {
1255 regmap_read(nau8825->regmap, NAU8825_REG_ADC_RATE, &osr);
1256 osr &= NAU8825_ADC_SYNC_DOWN_MASK;
1257 if (nau8825_clock_check(nau8825, substream->stream,
1258 params_rate(params), osr))
1259 return -EINVAL;
1260 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1261 NAU8825_CLK_ADC_SRC_MASK,
1262 osr_adc_sel[osr].clk_src << NAU8825_CLK_ADC_SRC_SFT);
1263 }
1264
1265 /* make BCLK and LRC divde configuration if the codec as master. */
1266 regmap_read(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, &ctrl_val);
1267 if (ctrl_val & NAU8825_I2S_MS_MASTER) {
1268 /* get the bclk and fs ratio */
1269 bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params);
1270 if (bclk_fs <= 32)
1271 bclk_div = 2;
1272 else if (bclk_fs <= 64)
1273 bclk_div = 1;
1274 else if (bclk_fs <= 128)
1275 bclk_div = 0;
1276 else
1277 return -EINVAL;
1278 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
1279 NAU8825_I2S_LRC_DIV_MASK | NAU8825_I2S_BLK_DIV_MASK,
1280 ((bclk_div + 1) << NAU8825_I2S_LRC_DIV_SFT) | bclk_div);
1281 }
1282
1283 switch (params_width(params)) {
1284 case 16:
1285 val_len |= NAU8825_I2S_DL_16;
1286 break;
1287 case 20:
1288 val_len |= NAU8825_I2S_DL_20;
1289 break;
1290 case 24:
1291 val_len |= NAU8825_I2S_DL_24;
1292 break;
1293 case 32:
1294 val_len |= NAU8825_I2S_DL_32;
1295 break;
1296 default:
1297 return -EINVAL;
1298 }
1299
1300 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
1301 NAU8825_I2S_DL_MASK, val_len);
1302
1303 /* Release the semaphore. */
1304 nau8825_sema_release(nau8825);
1305
1306 return 0;
1307 }
1308
1309 static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1310 {
1311 struct snd_soc_codec *codec = codec_dai->codec;
1312 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1313 unsigned int ctrl1_val = 0, ctrl2_val = 0;
1314
1315 nau8825_sema_acquire(nau8825, 3 * HZ);
1316
1317 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1318 case SND_SOC_DAIFMT_CBM_CFM:
1319 ctrl2_val |= NAU8825_I2S_MS_MASTER;
1320 break;
1321 case SND_SOC_DAIFMT_CBS_CFS:
1322 break;
1323 default:
1324 return -EINVAL;
1325 }
1326
1327 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1328 case SND_SOC_DAIFMT_NB_NF:
1329 break;
1330 case SND_SOC_DAIFMT_IB_NF:
1331 ctrl1_val |= NAU8825_I2S_BP_INV;
1332 break;
1333 default:
1334 return -EINVAL;
1335 }
1336
1337 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1338 case SND_SOC_DAIFMT_I2S:
1339 ctrl1_val |= NAU8825_I2S_DF_I2S;
1340 break;
1341 case SND_SOC_DAIFMT_LEFT_J:
1342 ctrl1_val |= NAU8825_I2S_DF_LEFT;
1343 break;
1344 case SND_SOC_DAIFMT_RIGHT_J:
1345 ctrl1_val |= NAU8825_I2S_DF_RIGTH;
1346 break;
1347 case SND_SOC_DAIFMT_DSP_A:
1348 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
1349 break;
1350 case SND_SOC_DAIFMT_DSP_B:
1351 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
1352 ctrl1_val |= NAU8825_I2S_PCMB_EN;
1353 break;
1354 default:
1355 return -EINVAL;
1356 }
1357
1358 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
1359 NAU8825_I2S_DL_MASK | NAU8825_I2S_DF_MASK |
1360 NAU8825_I2S_BP_MASK | NAU8825_I2S_PCMB_MASK,
1361 ctrl1_val);
1362 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
1363 NAU8825_I2S_MS_MASK, ctrl2_val);
1364
1365 /* Release the semaphore. */
1366 nau8825_sema_release(nau8825);
1367
1368 return 0;
1369 }
1370
1371 static const struct snd_soc_dai_ops nau8825_dai_ops = {
1372 .hw_params = nau8825_hw_params,
1373 .set_fmt = nau8825_set_dai_fmt,
1374 };
1375
1376 #define NAU8825_RATES SNDRV_PCM_RATE_8000_192000
1377 #define NAU8825_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
1378 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1379
1380 static struct snd_soc_dai_driver nau8825_dai = {
1381 .name = "nau8825-hifi",
1382 .playback = {
1383 .stream_name = "Playback",
1384 .channels_min = 1,
1385 .channels_max = 2,
1386 .rates = NAU8825_RATES,
1387 .formats = NAU8825_FORMATS,
1388 },
1389 .capture = {
1390 .stream_name = "Capture",
1391 .channels_min = 1,
1392 .channels_max = 1,
1393 .rates = NAU8825_RATES,
1394 .formats = NAU8825_FORMATS,
1395 },
1396 .ops = &nau8825_dai_ops,
1397 };
1398
1399 /**
1400 * nau8825_enable_jack_detect - Specify a jack for event reporting
1401 *
1402 * @component: component to register the jack with
1403 * @jack: jack to use to report headset and button events on
1404 *
1405 * After this function has been called the headset insert/remove and button
1406 * events will be routed to the given jack. Jack can be null to stop
1407 * reporting.
1408 */
1409 int nau8825_enable_jack_detect(struct snd_soc_codec *codec,
1410 struct snd_soc_jack *jack)
1411 {
1412 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1413 struct regmap *regmap = nau8825->regmap;
1414
1415 nau8825->jack = jack;
1416
1417 /* Ground HP Outputs[1:0], needed for headset auto detection
1418 * Enable Automatic Mic/Gnd switching reading on insert interrupt[6]
1419 */
1420 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
1421 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
1422 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
1423
1424 return 0;
1425 }
1426 EXPORT_SYMBOL_GPL(nau8825_enable_jack_detect);
1427
1428
1429 static bool nau8825_is_jack_inserted(struct regmap *regmap)
1430 {
1431 bool active_high, is_high;
1432 int status, jkdet;
1433
1434 regmap_read(regmap, NAU8825_REG_JACK_DET_CTRL, &jkdet);
1435 active_high = jkdet & NAU8825_JACK_POLARITY;
1436 regmap_read(regmap, NAU8825_REG_I2C_DEVICE_ID, &status);
1437 is_high = status & NAU8825_GPIO2JD1;
1438 /* return jack connection status according to jack insertion logic
1439 * active high or active low.
1440 */
1441 return active_high == is_high;
1442 }
1443
1444 static void nau8825_restart_jack_detection(struct regmap *regmap)
1445 {
1446 /* this will restart the entire jack detection process including MIC/GND
1447 * switching and create interrupts. We have to go from 0 to 1 and back
1448 * to 0 to restart.
1449 */
1450 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1451 NAU8825_JACK_DET_RESTART, NAU8825_JACK_DET_RESTART);
1452 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1453 NAU8825_JACK_DET_RESTART, 0);
1454 }
1455
1456 static void nau8825_int_status_clear_all(struct regmap *regmap)
1457 {
1458 int active_irq, clear_irq, i;
1459
1460 /* Reset the intrruption status from rightmost bit if the corres-
1461 * ponding irq event occurs.
1462 */
1463 regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq);
1464 for (i = 0; i < NAU8825_REG_DATA_LEN; i++) {
1465 clear_irq = (0x1 << i);
1466 if (active_irq & clear_irq)
1467 regmap_write(regmap,
1468 NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
1469 }
1470 }
1471
1472 static void nau8825_eject_jack(struct nau8825 *nau8825)
1473 {
1474 struct snd_soc_dapm_context *dapm = nau8825->dapm;
1475 struct regmap *regmap = nau8825->regmap;
1476
1477 /* Force to cancel the cross talk detection process */
1478 nau8825_xtalk_cancel(nau8825);
1479
1480 snd_soc_dapm_disable_pin(dapm, "SAR");
1481 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
1482 /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */
1483 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1484 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0);
1485 /* ground HPL/HPR, MICGRND1/2 */
1486 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 0xf, 0xf);
1487
1488 snd_soc_dapm_sync(dapm);
1489
1490 /* Clear all interruption status */
1491 nau8825_int_status_clear_all(regmap);
1492
1493 /* Enable the insertion interruption, disable the ejection inter-
1494 * ruption, and then bypass de-bounce circuit.
1495 */
1496 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
1497 NAU8825_IRQ_EJECT_DIS | NAU8825_IRQ_INSERT_DIS,
1498 NAU8825_IRQ_EJECT_DIS);
1499 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1500 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
1501 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_INSERT_EN,
1502 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
1503 NAU8825_IRQ_HEADSET_COMPLETE_EN);
1504 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1505 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
1506
1507 /* Disable ADC needed for interruptions at audo mode */
1508 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
1509 NAU8825_ENABLE_ADC, 0);
1510
1511 /* Close clock for jack type detection at manual mode */
1512 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
1513 }
1514
1515 /* Enable audo mode interruptions with internal clock. */
1516 static void nau8825_setup_auto_irq(struct nau8825 *nau8825)
1517 {
1518 struct regmap *regmap = nau8825->regmap;
1519
1520 /* Enable headset jack type detection complete interruption and
1521 * jack ejection interruption.
1522 */
1523 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1524 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_EJECT_EN, 0);
1525
1526 /* Enable internal VCO needed for interruptions */
1527 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
1528
1529 /* Enable ADC needed for interruptions */
1530 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
1531 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
1532
1533 /* Chip needs one FSCLK cycle in order to generate interruptions,
1534 * as we cannot guarantee one will be provided by the system. Turning
1535 * master mode on then off enables us to generate that FSCLK cycle
1536 * with a minimum of contention on the clock bus.
1537 */
1538 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
1539 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_MASTER);
1540 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
1541 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE);
1542
1543 /* Not bypass de-bounce circuit */
1544 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1545 NAU8825_JACK_DET_DB_BYPASS, 0);
1546
1547 /* Unmask all interruptions */
1548 regmap_write(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 0);
1549
1550 /* Restart the jack detection process at auto mode */
1551 nau8825_restart_jack_detection(regmap);
1552 }
1553
1554 static int nau8825_button_decode(int value)
1555 {
1556 int buttons = 0;
1557
1558 /* The chip supports up to 8 buttons, but ALSA defines only 6 buttons */
1559 if (value & BIT(0))
1560 buttons |= SND_JACK_BTN_0;
1561 if (value & BIT(1))
1562 buttons |= SND_JACK_BTN_1;
1563 if (value & BIT(2))
1564 buttons |= SND_JACK_BTN_2;
1565 if (value & BIT(3))
1566 buttons |= SND_JACK_BTN_3;
1567 if (value & BIT(4))
1568 buttons |= SND_JACK_BTN_4;
1569 if (value & BIT(5))
1570 buttons |= SND_JACK_BTN_5;
1571
1572 return buttons;
1573 }
1574
1575 static int nau8825_jack_insert(struct nau8825 *nau8825)
1576 {
1577 struct regmap *regmap = nau8825->regmap;
1578 struct snd_soc_dapm_context *dapm = nau8825->dapm;
1579 int jack_status_reg, mic_detected;
1580 int type = 0;
1581
1582 regmap_read(regmap, NAU8825_REG_GENERAL_STATUS, &jack_status_reg);
1583 mic_detected = (jack_status_reg >> 10) & 3;
1584 /* The JKSLV and JKR2 all detected in high impedance headset */
1585 if (mic_detected == 0x3)
1586 nau8825->high_imped = true;
1587 else
1588 nau8825->high_imped = false;
1589
1590 switch (mic_detected) {
1591 case 0:
1592 /* no mic */
1593 type = SND_JACK_HEADPHONE;
1594 break;
1595 case 1:
1596 dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n");
1597 type = SND_JACK_HEADSET;
1598
1599 /* Unground MICGND1 */
1600 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
1601 1 << 2);
1602 /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */
1603 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1604 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1605 NAU8825_MICBIAS_JKR2);
1606 /* Attach SARADC to MICGND1 */
1607 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1608 NAU8825_SAR_INPUT_MASK,
1609 NAU8825_SAR_INPUT_JKR2);
1610
1611 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
1612 snd_soc_dapm_force_enable_pin(dapm, "SAR");
1613 snd_soc_dapm_sync(dapm);
1614 break;
1615 case 2:
1616 dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n");
1617 type = SND_JACK_HEADSET;
1618
1619 /* Unground MICGND2 */
1620 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
1621 2 << 2);
1622 /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */
1623 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1624 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1625 NAU8825_MICBIAS_JKSLV);
1626 /* Attach SARADC to MICGND2 */
1627 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1628 NAU8825_SAR_INPUT_MASK,
1629 NAU8825_SAR_INPUT_JKSLV);
1630
1631 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
1632 snd_soc_dapm_force_enable_pin(dapm, "SAR");
1633 snd_soc_dapm_sync(dapm);
1634 break;
1635 case 3:
1636 /* detect error case */
1637 dev_err(nau8825->dev, "detection error; disable mic function\n");
1638 type = SND_JACK_HEADPHONE;
1639 break;
1640 }
1641
1642 /* Leaving HPOL/R grounded after jack insert by default. They will be
1643 * ungrounded as part of the widget power up sequence at the beginning
1644 * of playback to reduce pop.
1645 */
1646 return type;
1647 }
1648
1649 #define NAU8825_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
1650 SND_JACK_BTN_2 | SND_JACK_BTN_3)
1651
1652 static irqreturn_t nau8825_interrupt(int irq, void *data)
1653 {
1654 struct nau8825 *nau8825 = (struct nau8825 *)data;
1655 struct regmap *regmap = nau8825->regmap;
1656 int active_irq, clear_irq = 0, event = 0, event_mask = 0;
1657
1658 if (regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq)) {
1659 dev_err(nau8825->dev, "failed to read irq status\n");
1660 return IRQ_NONE;
1661 }
1662
1663 if ((active_irq & NAU8825_JACK_EJECTION_IRQ_MASK) ==
1664 NAU8825_JACK_EJECTION_DETECTED) {
1665
1666 nau8825_eject_jack(nau8825);
1667 event_mask |= SND_JACK_HEADSET;
1668 clear_irq = NAU8825_JACK_EJECTION_IRQ_MASK;
1669 } else if (active_irq & NAU8825_KEY_SHORT_PRESS_IRQ) {
1670 int key_status;
1671
1672 regmap_read(regmap, NAU8825_REG_INT_CLR_KEY_STATUS,
1673 &key_status);
1674
1675 /* upper 8 bits of the register are for short pressed keys,
1676 * lower 8 bits - for long pressed buttons
1677 */
1678 nau8825->button_pressed = nau8825_button_decode(
1679 key_status >> 8);
1680
1681 event |= nau8825->button_pressed;
1682 event_mask |= NAU8825_BUTTONS;
1683 clear_irq = NAU8825_KEY_SHORT_PRESS_IRQ;
1684 } else if (active_irq & NAU8825_KEY_RELEASE_IRQ) {
1685 event_mask = NAU8825_BUTTONS;
1686 clear_irq = NAU8825_KEY_RELEASE_IRQ;
1687 } else if (active_irq & NAU8825_HEADSET_COMPLETION_IRQ) {
1688 if (nau8825_is_jack_inserted(regmap)) {
1689 event |= nau8825_jack_insert(nau8825);
1690 if (!nau8825->xtalk_bypass && !nau8825->high_imped) {
1691 /* Apply the cross talk suppression in the
1692 * headset without high impedance.
1693 */
1694 if (!nau8825->xtalk_protect) {
1695 /* Raise protection for cross talk de-
1696 * tection if no protection before.
1697 * The driver has to cancel the pro-
1698 * cess and restore changes if process
1699 * is ongoing when ejection.
1700 */
1701 int ret;
1702 nau8825->xtalk_protect = true;
1703 ret = nau8825_sema_acquire(nau8825, 0);
1704 if (ret < 0)
1705 nau8825->xtalk_protect = false;
1706 }
1707 /* Startup cross talk detection process */
1708 nau8825->xtalk_state = NAU8825_XTALK_PREPARE;
1709 schedule_work(&nau8825->xtalk_work);
1710 } else {
1711 /* The cross talk suppression shouldn't apply
1712 * in the headset with high impedance. Thus,
1713 * relieve the protection raised before.
1714 */
1715 if (nau8825->xtalk_protect) {
1716 nau8825_sema_release(nau8825);
1717 nau8825->xtalk_protect = false;
1718 }
1719 }
1720 } else {
1721 dev_warn(nau8825->dev, "Headset completion IRQ fired but no headset connected\n");
1722 nau8825_eject_jack(nau8825);
1723 }
1724
1725 event_mask |= SND_JACK_HEADSET;
1726 clear_irq = NAU8825_HEADSET_COMPLETION_IRQ;
1727 /* Record the interruption report event for driver to report
1728 * the event later. The jack report will delay until cross
1729 * talk detection process is done.
1730 */
1731 if (nau8825->xtalk_state == NAU8825_XTALK_PREPARE) {
1732 nau8825->xtalk_event = event;
1733 nau8825->xtalk_event_mask = event_mask;
1734 }
1735 } else if (active_irq & NAU8825_IMPEDANCE_MEAS_IRQ) {
1736 schedule_work(&nau8825->xtalk_work);
1737 clear_irq = NAU8825_IMPEDANCE_MEAS_IRQ;
1738 } else if ((active_irq & NAU8825_JACK_INSERTION_IRQ_MASK) ==
1739 NAU8825_JACK_INSERTION_DETECTED) {
1740 /* One more step to check GPIO status directly. Thus, the
1741 * driver can confirm the real insertion interruption because
1742 * the intrruption at manual mode has bypassed debounce
1743 * circuit which can get rid of unstable status.
1744 */
1745 if (nau8825_is_jack_inserted(regmap)) {
1746 /* Turn off insertion interruption at manual mode */
1747 regmap_update_bits(regmap,
1748 NAU8825_REG_INTERRUPT_DIS_CTRL,
1749 NAU8825_IRQ_INSERT_DIS,
1750 NAU8825_IRQ_INSERT_DIS);
1751 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1752 NAU8825_IRQ_INSERT_EN, NAU8825_IRQ_INSERT_EN);
1753 /* Enable interruption for jack type detection at audo
1754 * mode which can detect microphone and jack type.
1755 */
1756 nau8825_setup_auto_irq(nau8825);
1757 }
1758 }
1759
1760 if (!clear_irq)
1761 clear_irq = active_irq;
1762 /* clears the rightmost interruption */
1763 regmap_write(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
1764
1765 /* Delay jack report until cross talk detection is done. It can avoid
1766 * application to do playback preparation when cross talk detection
1767 * process is still working. Otherwise, the resource like clock and
1768 * power will be issued by them at the same time and conflict happens.
1769 */
1770 if (event_mask && nau8825->xtalk_state == NAU8825_XTALK_DONE)
1771 snd_soc_jack_report(nau8825->jack, event, event_mask);
1772
1773 return IRQ_HANDLED;
1774 }
1775
1776 static void nau8825_setup_buttons(struct nau8825 *nau8825)
1777 {
1778 struct regmap *regmap = nau8825->regmap;
1779
1780 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1781 NAU8825_SAR_TRACKING_GAIN_MASK,
1782 nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT);
1783 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1784 NAU8825_SAR_COMPARE_TIME_MASK,
1785 nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT);
1786 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1787 NAU8825_SAR_SAMPLING_TIME_MASK,
1788 nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT);
1789
1790 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1791 NAU8825_KEYDET_LEVELS_NR_MASK,
1792 (nau8825->sar_threshold_num - 1) << NAU8825_KEYDET_LEVELS_NR_SFT);
1793 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1794 NAU8825_KEYDET_HYSTERESIS_MASK,
1795 nau8825->sar_hysteresis << NAU8825_KEYDET_HYSTERESIS_SFT);
1796 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1797 NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK,
1798 nau8825->key_debounce << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT);
1799
1800 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_1,
1801 (nau8825->sar_threshold[0] << 8) | nau8825->sar_threshold[1]);
1802 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_2,
1803 (nau8825->sar_threshold[2] << 8) | nau8825->sar_threshold[3]);
1804 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_3,
1805 (nau8825->sar_threshold[4] << 8) | nau8825->sar_threshold[5]);
1806 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_4,
1807 (nau8825->sar_threshold[6] << 8) | nau8825->sar_threshold[7]);
1808
1809 /* Enable short press and release interruptions */
1810 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1811 NAU8825_IRQ_KEY_SHORT_PRESS_EN | NAU8825_IRQ_KEY_RELEASE_EN,
1812 0);
1813 }
1814
1815 static void nau8825_init_regs(struct nau8825 *nau8825)
1816 {
1817 struct regmap *regmap = nau8825->regmap;
1818
1819 /* Latch IIC LSB value */
1820 regmap_write(regmap, NAU8825_REG_IIC_ADDR_SET, 0x0001);
1821 /* Enable Bias/Vmid */
1822 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
1823 NAU8825_BIAS_VMID, NAU8825_BIAS_VMID);
1824 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
1825 NAU8825_GLOBAL_BIAS_EN, NAU8825_GLOBAL_BIAS_EN);
1826
1827 /* VMID Tieoff */
1828 regmap_update_bits(regmap, NAU8825_REG_BIAS_ADJ,
1829 NAU8825_BIAS_VMID_SEL_MASK,
1830 nau8825->vref_impedance << NAU8825_BIAS_VMID_SEL_SFT);
1831 /* Disable Boost Driver, Automatic Short circuit protection enable */
1832 regmap_update_bits(regmap, NAU8825_REG_BOOST,
1833 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
1834 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN,
1835 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
1836 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN);
1837
1838 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1839 NAU8825_JKDET_OUTPUT_EN,
1840 nau8825->jkdet_enable ? 0 : NAU8825_JKDET_OUTPUT_EN);
1841 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1842 NAU8825_JKDET_PULL_EN,
1843 nau8825->jkdet_pull_enable ? 0 : NAU8825_JKDET_PULL_EN);
1844 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1845 NAU8825_JKDET_PULL_UP,
1846 nau8825->jkdet_pull_up ? NAU8825_JKDET_PULL_UP : 0);
1847 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1848 NAU8825_JACK_POLARITY,
1849 /* jkdet_polarity - 1 is for active-low */
1850 nau8825->jkdet_polarity ? 0 : NAU8825_JACK_POLARITY);
1851
1852 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1853 NAU8825_JACK_INSERT_DEBOUNCE_MASK,
1854 nau8825->jack_insert_debounce << NAU8825_JACK_INSERT_DEBOUNCE_SFT);
1855 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1856 NAU8825_JACK_EJECT_DEBOUNCE_MASK,
1857 nau8825->jack_eject_debounce << NAU8825_JACK_EJECT_DEBOUNCE_SFT);
1858
1859 /* Mask unneeded IRQs: 1 - disable, 0 - enable */
1860 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 0x7ff, 0x7ff);
1861
1862 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1863 NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage);
1864
1865 if (nau8825->sar_threshold_num)
1866 nau8825_setup_buttons(nau8825);
1867
1868 /* Default oversampling/decimations settings are unusable
1869 * (audible hiss). Set it to something better.
1870 */
1871 regmap_update_bits(regmap, NAU8825_REG_ADC_RATE,
1872 NAU8825_ADC_SYNC_DOWN_MASK | NAU8825_ADC_SINC4_EN,
1873 NAU8825_ADC_SYNC_DOWN_64);
1874 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
1875 NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_64);
1876 /* Disable DACR/L power */
1877 regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP,
1878 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
1879 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
1880 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input
1881 * signal to avoid any glitches due to power up transients in both
1882 * the analog and digital DAC circuit.
1883 */
1884 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
1885 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
1886 /* CICCLP off */
1887 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
1888 NAU8825_DAC_CLIP_OFF, NAU8825_DAC_CLIP_OFF);
1889
1890 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */
1891 regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_2,
1892 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
1893 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB,
1894 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
1895 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB);
1896 /* Class G timer 64ms */
1897 regmap_update_bits(regmap, NAU8825_REG_CLASSG_CTRL,
1898 NAU8825_CLASSG_TIMER_MASK,
1899 0x20 << NAU8825_CLASSG_TIMER_SFT);
1900 /* DAC clock delay 2ns, VREF */
1901 regmap_update_bits(regmap, NAU8825_REG_RDAC,
1902 NAU8825_RDAC_CLK_DELAY_MASK | NAU8825_RDAC_VREF_MASK,
1903 (0x2 << NAU8825_RDAC_CLK_DELAY_SFT) |
1904 (0x3 << NAU8825_RDAC_VREF_SFT));
1905 /* Config L/R channel */
1906 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
1907 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_L);
1908 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
1909 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_R);
1910 /* Disable short Frame Sync detection logic */
1911 regmap_update_bits(regmap, NAU8825_REG_LEFT_TIME_SLOT,
1912 NAU8825_DIS_FS_SHORT_DET, NAU8825_DIS_FS_SHORT_DET);
1913 }
1914
1915 static const struct regmap_config nau8825_regmap_config = {
1916 .val_bits = NAU8825_REG_DATA_LEN,
1917 .reg_bits = NAU8825_REG_ADDR_LEN,
1918
1919 .max_register = NAU8825_REG_MAX,
1920 .readable_reg = nau8825_readable_reg,
1921 .writeable_reg = nau8825_writeable_reg,
1922 .volatile_reg = nau8825_volatile_reg,
1923
1924 .cache_type = REGCACHE_RBTREE,
1925 .reg_defaults = nau8825_reg_defaults,
1926 .num_reg_defaults = ARRAY_SIZE(nau8825_reg_defaults),
1927 };
1928
1929 static int nau8825_codec_probe(struct snd_soc_codec *codec)
1930 {
1931 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1932 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1933
1934 nau8825->dapm = dapm;
1935
1936 return 0;
1937 }
1938
1939 static int nau8825_codec_remove(struct snd_soc_codec *codec)
1940 {
1941 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1942
1943 /* Cancel and reset cross tak suppresstion detection funciton */
1944 nau8825_xtalk_cancel(nau8825);
1945
1946 return 0;
1947 }
1948
1949 /**
1950 * nau8825_calc_fll_param - Calculate FLL parameters.
1951 * @fll_in: external clock provided to codec.
1952 * @fs: sampling rate.
1953 * @fll_param: Pointer to structure of FLL parameters.
1954 *
1955 * Calculate FLL parameters to configure codec.
1956 *
1957 * Returns 0 for success or negative error code.
1958 */
1959 static int nau8825_calc_fll_param(unsigned int fll_in, unsigned int fs,
1960 struct nau8825_fll *fll_param)
1961 {
1962 u64 fvco, fvco_max;
1963 unsigned int fref, i, fvco_sel;
1964
1965 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
1966 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
1967 * FREF = freq_in / NAU8825_FLL_REF_DIV_MASK
1968 */
1969 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
1970 fref = fll_in / fll_pre_scalar[i].param;
1971 if (fref <= NAU_FREF_MAX)
1972 break;
1973 }
1974 if (i == ARRAY_SIZE(fll_pre_scalar))
1975 return -EINVAL;
1976 fll_param->clk_ref_div = fll_pre_scalar[i].val;
1977
1978 /* Choose the FLL ratio based on FREF */
1979 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
1980 if (fref >= fll_ratio[i].param)
1981 break;
1982 }
1983 if (i == ARRAY_SIZE(fll_ratio))
1984 return -EINVAL;
1985 fll_param->ratio = fll_ratio[i].val;
1986
1987 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
1988 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
1989 * guaranteed across the full range of operation.
1990 * FDCO = freq_out * 2 * mclk_src_scaling
1991 */
1992 fvco_max = 0;
1993 fvco_sel = ARRAY_SIZE(mclk_src_scaling);
1994 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
1995 fvco = 256 * fs * 2 * mclk_src_scaling[i].param;
1996 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
1997 fvco_max < fvco) {
1998 fvco_max = fvco;
1999 fvco_sel = i;
2000 }
2001 }
2002 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
2003 return -EINVAL;
2004 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
2005
2006 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
2007 * input based on FDCO, FREF and FLL ratio.
2008 */
2009 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
2010 fll_param->fll_int = (fvco >> 16) & 0x3FF;
2011 fll_param->fll_frac = fvco & 0xFFFF;
2012 return 0;
2013 }
2014
2015 static void nau8825_fll_apply(struct nau8825 *nau8825,
2016 struct nau8825_fll *fll_param)
2017 {
2018 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
2019 NAU8825_CLK_SRC_MASK | NAU8825_CLK_MCLK_SRC_MASK,
2020 NAU8825_CLK_SRC_MCLK | fll_param->mclk_src);
2021 /* Make DSP operate at high speed for better performance. */
2022 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
2023 NAU8825_FLL_RATIO_MASK | NAU8825_ICTRL_LATCH_MASK,
2024 fll_param->ratio | (0x6 << NAU8825_ICTRL_LATCH_SFT));
2025 /* FLL 16-bit fractional input */
2026 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, fll_param->fll_frac);
2027 /* FLL 10-bit integer input */
2028 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL3,
2029 NAU8825_FLL_INTEGER_MASK, fll_param->fll_int);
2030 /* FLL pre-scaler */
2031 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL4,
2032 NAU8825_FLL_REF_DIV_MASK,
2033 fll_param->clk_ref_div << NAU8825_FLL_REF_DIV_SFT);
2034 /* select divided VCO input */
2035 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
2036 NAU8825_FLL_CLK_SW_MASK, NAU8825_FLL_CLK_SW_REF);
2037 /* Disable free-running mode */
2038 regmap_update_bits(nau8825->regmap,
2039 NAU8825_REG_FLL6, NAU8825_DCO_EN, 0);
2040 if (fll_param->fll_frac) {
2041 /* set FLL loop filter enable and cutoff frequency at 500Khz */
2042 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
2043 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
2044 NAU8825_FLL_FTR_SW_MASK,
2045 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
2046 NAU8825_FLL_FTR_SW_FILTER);
2047 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
2048 NAU8825_SDM_EN | NAU8825_CUTOFF500,
2049 NAU8825_SDM_EN | NAU8825_CUTOFF500);
2050 } else {
2051 /* disable FLL loop filter and cutoff frequency */
2052 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
2053 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
2054 NAU8825_FLL_FTR_SW_MASK, NAU8825_FLL_FTR_SW_ACCU);
2055 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
2056 NAU8825_SDM_EN | NAU8825_CUTOFF500, 0);
2057 }
2058 }
2059
2060 /* freq_out must be 256*Fs in order to achieve the best performance */
2061 static int nau8825_set_pll(struct snd_soc_codec *codec, int pll_id, int source,
2062 unsigned int freq_in, unsigned int freq_out)
2063 {
2064 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2065 struct nau8825_fll fll_param;
2066 int ret, fs;
2067
2068 fs = freq_out / 256;
2069 ret = nau8825_calc_fll_param(freq_in, fs, &fll_param);
2070 if (ret < 0) {
2071 dev_err(codec->dev, "Unsupported input clock %d\n", freq_in);
2072 return ret;
2073 }
2074 dev_dbg(codec->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
2075 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
2076 fll_param.fll_int, fll_param.clk_ref_div);
2077
2078 nau8825_fll_apply(nau8825, &fll_param);
2079 mdelay(2);
2080 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
2081 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
2082 return 0;
2083 }
2084
2085 static int nau8825_mclk_prepare(struct nau8825 *nau8825, unsigned int freq)
2086 {
2087 int ret = 0;
2088
2089 nau8825->mclk = devm_clk_get(nau8825->dev, "mclk");
2090 if (IS_ERR(nau8825->mclk)) {
2091 dev_info(nau8825->dev, "No 'mclk' clock found, assume MCLK is managed externally");
2092 return 0;
2093 }
2094
2095 if (!nau8825->mclk_freq) {
2096 ret = clk_prepare_enable(nau8825->mclk);
2097 if (ret) {
2098 dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
2099 return ret;
2100 }
2101 }
2102
2103 if (nau8825->mclk_freq != freq) {
2104 freq = clk_round_rate(nau8825->mclk, freq);
2105 ret = clk_set_rate(nau8825->mclk, freq);
2106 if (ret) {
2107 dev_err(nau8825->dev, "Unable to set mclk rate\n");
2108 return ret;
2109 }
2110 nau8825->mclk_freq = freq;
2111 }
2112
2113 return 0;
2114 }
2115
2116 static void nau8825_configure_mclk_as_sysclk(struct regmap *regmap)
2117 {
2118 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2119 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK);
2120 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2121 NAU8825_DCO_EN, 0);
2122 /* Make DSP operate as default setting for power saving. */
2123 regmap_update_bits(regmap, NAU8825_REG_FLL1,
2124 NAU8825_ICTRL_LATCH_MASK, 0);
2125 }
2126
2127 static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
2128 unsigned int freq)
2129 {
2130 struct regmap *regmap = nau8825->regmap;
2131 int ret;
2132
2133 switch (clk_id) {
2134 case NAU8825_CLK_DIS:
2135 /* Clock provided externally and disable internal VCO clock */
2136 nau8825_configure_mclk_as_sysclk(regmap);
2137 if (nau8825->mclk_freq) {
2138 clk_disable_unprepare(nau8825->mclk);
2139 nau8825->mclk_freq = 0;
2140 }
2141
2142 break;
2143 case NAU8825_CLK_MCLK:
2144 /* Acquire the semaphore to synchronize the playback and
2145 * interrupt handler. In order to avoid the playback inter-
2146 * fered by cross talk process, the driver make the playback
2147 * preparation halted until cross talk process finish.
2148 */
2149 nau8825_sema_acquire(nau8825, 3 * HZ);
2150 nau8825_configure_mclk_as_sysclk(regmap);
2151 /* MCLK not changed by clock tree */
2152 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2153 NAU8825_CLK_MCLK_SRC_MASK, 0);
2154 /* Release the semaphore. */
2155 nau8825_sema_release(nau8825);
2156
2157 ret = nau8825_mclk_prepare(nau8825, freq);
2158 if (ret)
2159 return ret;
2160
2161 break;
2162 case NAU8825_CLK_INTERNAL:
2163 if (nau8825_is_jack_inserted(nau8825->regmap)) {
2164 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2165 NAU8825_DCO_EN, NAU8825_DCO_EN);
2166 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2167 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
2168 /* Decrease the VCO frequency and make DSP operate
2169 * as default setting for power saving.
2170 */
2171 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2172 NAU8825_CLK_MCLK_SRC_MASK, 0xf);
2173 regmap_update_bits(regmap, NAU8825_REG_FLL1,
2174 NAU8825_ICTRL_LATCH_MASK |
2175 NAU8825_FLL_RATIO_MASK, 0x10);
2176 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2177 NAU8825_SDM_EN, NAU8825_SDM_EN);
2178 } else {
2179 /* The clock turns off intentionally for power saving
2180 * when no headset connected.
2181 */
2182 nau8825_configure_mclk_as_sysclk(regmap);
2183 dev_warn(nau8825->dev, "Disable clock for power saving when no headset connected\n");
2184 }
2185 if (nau8825->mclk_freq) {
2186 clk_disable_unprepare(nau8825->mclk);
2187 nau8825->mclk_freq = 0;
2188 }
2189
2190 break;
2191 case NAU8825_CLK_FLL_MCLK:
2192 /* Acquire the semaphore to synchronize the playback and
2193 * interrupt handler. In order to avoid the playback inter-
2194 * fered by cross talk process, the driver make the playback
2195 * preparation halted until cross talk process finish.
2196 */
2197 nau8825_sema_acquire(nau8825, 3 * HZ);
2198 /* Higher FLL reference input frequency can only set lower
2199 * gain error, such as 0000 for input reference from MCLK
2200 * 12.288Mhz.
2201 */
2202 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2203 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
2204 NAU8825_FLL_CLK_SRC_MCLK | 0);
2205 /* Release the semaphore. */
2206 nau8825_sema_release(nau8825);
2207
2208 ret = nau8825_mclk_prepare(nau8825, freq);
2209 if (ret)
2210 return ret;
2211
2212 break;
2213 case NAU8825_CLK_FLL_BLK:
2214 /* Acquire the semaphore to synchronize the playback and
2215 * interrupt handler. In order to avoid the playback inter-
2216 * fered by cross talk process, the driver make the playback
2217 * preparation halted until cross talk process finish.
2218 */
2219 nau8825_sema_acquire(nau8825, 3 * HZ);
2220 /* If FLL reference input is from low frequency source,
2221 * higher error gain can apply such as 0xf which has
2222 * the most sensitive gain error correction threshold,
2223 * Therefore, FLL has the most accurate DCO to
2224 * target frequency.
2225 */
2226 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2227 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
2228 NAU8825_FLL_CLK_SRC_BLK |
2229 (0xf << NAU8825_GAIN_ERR_SFT));
2230 /* Release the semaphore. */
2231 nau8825_sema_release(nau8825);
2232
2233 if (nau8825->mclk_freq) {
2234 clk_disable_unprepare(nau8825->mclk);
2235 nau8825->mclk_freq = 0;
2236 }
2237
2238 break;
2239 case NAU8825_CLK_FLL_FS:
2240 /* Acquire the semaphore to synchronize the playback and
2241 * interrupt handler. In order to avoid the playback inter-
2242 * fered by cross talk process, the driver make the playback
2243 * preparation halted until cross talk process finish.
2244 */
2245 nau8825_sema_acquire(nau8825, 3 * HZ);
2246 /* If FLL reference input is from low frequency source,
2247 * higher error gain can apply such as 0xf which has
2248 * the most sensitive gain error correction threshold,
2249 * Therefore, FLL has the most accurate DCO to
2250 * target frequency.
2251 */
2252 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2253 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
2254 NAU8825_FLL_CLK_SRC_FS |
2255 (0xf << NAU8825_GAIN_ERR_SFT));
2256 /* Release the semaphore. */
2257 nau8825_sema_release(nau8825);
2258
2259 if (nau8825->mclk_freq) {
2260 clk_disable_unprepare(nau8825->mclk);
2261 nau8825->mclk_freq = 0;
2262 }
2263
2264 break;
2265 default:
2266 dev_err(nau8825->dev, "Invalid clock id (%d)\n", clk_id);
2267 return -EINVAL;
2268 }
2269
2270 dev_dbg(nau8825->dev, "Sysclk is %dHz and clock id is %d\n", freq,
2271 clk_id);
2272 return 0;
2273 }
2274
2275 static int nau8825_set_sysclk(struct snd_soc_codec *codec, int clk_id,
2276 int source, unsigned int freq, int dir)
2277 {
2278 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2279
2280 return nau8825_configure_sysclk(nau8825, clk_id, freq);
2281 }
2282
2283 static int nau8825_resume_setup(struct nau8825 *nau8825)
2284 {
2285 struct regmap *regmap = nau8825->regmap;
2286
2287 /* Close clock when jack type detection at manual mode */
2288 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
2289
2290 /* Clear all interruption status */
2291 nau8825_int_status_clear_all(regmap);
2292
2293 /* Enable both insertion and ejection interruptions, and then
2294 * bypass de-bounce circuit.
2295 */
2296 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
2297 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN |
2298 NAU8825_IRQ_EJECT_EN | NAU8825_IRQ_INSERT_EN,
2299 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN);
2300 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
2301 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
2302 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
2303 NAU8825_IRQ_INSERT_DIS | NAU8825_IRQ_EJECT_DIS, 0);
2304
2305 return 0;
2306 }
2307
2308 static int nau8825_set_bias_level(struct snd_soc_codec *codec,
2309 enum snd_soc_bias_level level)
2310 {
2311 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2312 int ret;
2313
2314 switch (level) {
2315 case SND_SOC_BIAS_ON:
2316 break;
2317
2318 case SND_SOC_BIAS_PREPARE:
2319 break;
2320
2321 case SND_SOC_BIAS_STANDBY:
2322 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
2323 if (nau8825->mclk_freq) {
2324 ret = clk_prepare_enable(nau8825->mclk);
2325 if (ret) {
2326 dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
2327 return ret;
2328 }
2329 }
2330 /* Setup codec configuration after resume */
2331 nau8825_resume_setup(nau8825);
2332 }
2333 break;
2334
2335 case SND_SOC_BIAS_OFF:
2336 /* Reset the configuration of jack type for detection */
2337 /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */
2338 regmap_update_bits(nau8825->regmap, NAU8825_REG_MIC_BIAS,
2339 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0);
2340 /* ground HPL/HPR, MICGRND1/2 */
2341 regmap_update_bits(nau8825->regmap,
2342 NAU8825_REG_HSD_CTRL, 0xf, 0xf);
2343 /* Cancel and reset cross talk detection funciton */
2344 nau8825_xtalk_cancel(nau8825);
2345 /* Turn off all interruptions before system shutdown. Keep the
2346 * interruption quiet before resume setup completes.
2347 */
2348 regmap_write(nau8825->regmap,
2349 NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff);
2350 /* Disable ADC needed for interruptions at audo mode */
2351 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
2352 NAU8825_ENABLE_ADC, 0);
2353 if (nau8825->mclk_freq)
2354 clk_disable_unprepare(nau8825->mclk);
2355 break;
2356 }
2357 return 0;
2358 }
2359
2360 static int __maybe_unused nau8825_suspend(struct snd_soc_codec *codec)
2361 {
2362 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2363
2364 disable_irq(nau8825->irq);
2365 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
2366 /* Power down codec power; don't suppoet button wakeup */
2367 snd_soc_dapm_disable_pin(nau8825->dapm, "SAR");
2368 snd_soc_dapm_disable_pin(nau8825->dapm, "MICBIAS");
2369 snd_soc_dapm_sync(nau8825->dapm);
2370 regcache_cache_only(nau8825->regmap, true);
2371 regcache_mark_dirty(nau8825->regmap);
2372
2373 return 0;
2374 }
2375
2376 static int __maybe_unused nau8825_resume(struct snd_soc_codec *codec)
2377 {
2378 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2379 int ret;
2380
2381 regcache_cache_only(nau8825->regmap, false);
2382 regcache_sync(nau8825->regmap);
2383 nau8825->xtalk_protect = true;
2384 ret = nau8825_sema_acquire(nau8825, 0);
2385 if (ret < 0)
2386 nau8825->xtalk_protect = false;
2387 enable_irq(nau8825->irq);
2388
2389 return 0;
2390 }
2391
2392 static const struct snd_soc_codec_driver nau8825_codec_driver = {
2393 .probe = nau8825_codec_probe,
2394 .remove = nau8825_codec_remove,
2395 .set_sysclk = nau8825_set_sysclk,
2396 .set_pll = nau8825_set_pll,
2397 .set_bias_level = nau8825_set_bias_level,
2398 .suspend_bias_off = true,
2399 .suspend = nau8825_suspend,
2400 .resume = nau8825_resume,
2401
2402 .component_driver = {
2403 .controls = nau8825_controls,
2404 .num_controls = ARRAY_SIZE(nau8825_controls),
2405 .dapm_widgets = nau8825_dapm_widgets,
2406 .num_dapm_widgets = ARRAY_SIZE(nau8825_dapm_widgets),
2407 .dapm_routes = nau8825_dapm_routes,
2408 .num_dapm_routes = ARRAY_SIZE(nau8825_dapm_routes),
2409 },
2410 };
2411
2412 static void nau8825_reset_chip(struct regmap *regmap)
2413 {
2414 regmap_write(regmap, NAU8825_REG_RESET, 0x00);
2415 regmap_write(regmap, NAU8825_REG_RESET, 0x00);
2416 }
2417
2418 static void nau8825_print_device_properties(struct nau8825 *nau8825)
2419 {
2420 int i;
2421 struct device *dev = nau8825->dev;
2422
2423 dev_dbg(dev, "jkdet-enable: %d\n", nau8825->jkdet_enable);
2424 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8825->jkdet_pull_enable);
2425 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8825->jkdet_pull_up);
2426 dev_dbg(dev, "jkdet-polarity: %d\n", nau8825->jkdet_polarity);
2427 dev_dbg(dev, "micbias-voltage: %d\n", nau8825->micbias_voltage);
2428 dev_dbg(dev, "vref-impedance: %d\n", nau8825->vref_impedance);
2429
2430 dev_dbg(dev, "sar-threshold-num: %d\n", nau8825->sar_threshold_num);
2431 for (i = 0; i < nau8825->sar_threshold_num; i++)
2432 dev_dbg(dev, "sar-threshold[%d]=%d\n", i,
2433 nau8825->sar_threshold[i]);
2434
2435 dev_dbg(dev, "sar-hysteresis: %d\n", nau8825->sar_hysteresis);
2436 dev_dbg(dev, "sar-voltage: %d\n", nau8825->sar_voltage);
2437 dev_dbg(dev, "sar-compare-time: %d\n", nau8825->sar_compare_time);
2438 dev_dbg(dev, "sar-sampling-time: %d\n", nau8825->sar_sampling_time);
2439 dev_dbg(dev, "short-key-debounce: %d\n", nau8825->key_debounce);
2440 dev_dbg(dev, "jack-insert-debounce: %d\n",
2441 nau8825->jack_insert_debounce);
2442 dev_dbg(dev, "jack-eject-debounce: %d\n",
2443 nau8825->jack_eject_debounce);
2444 dev_dbg(dev, "crosstalk-bypass: %d\n",
2445 nau8825->xtalk_bypass);
2446 }
2447
2448 static int nau8825_read_device_properties(struct device *dev,
2449 struct nau8825 *nau8825) {
2450 int ret;
2451
2452 nau8825->jkdet_enable = device_property_read_bool(dev,
2453 "nuvoton,jkdet-enable");
2454 nau8825->jkdet_pull_enable = device_property_read_bool(dev,
2455 "nuvoton,jkdet-pull-enable");
2456 nau8825->jkdet_pull_up = device_property_read_bool(dev,
2457 "nuvoton,jkdet-pull-up");
2458 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",
2459 &nau8825->jkdet_polarity);
2460 if (ret)
2461 nau8825->jkdet_polarity = 1;
2462 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",
2463 &nau8825->micbias_voltage);
2464 if (ret)
2465 nau8825->micbias_voltage = 6;
2466 ret = device_property_read_u32(dev, "nuvoton,vref-impedance",
2467 &nau8825->vref_impedance);
2468 if (ret)
2469 nau8825->vref_impedance = 2;
2470 ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num",
2471 &nau8825->sar_threshold_num);
2472 if (ret)
2473 nau8825->sar_threshold_num = 4;
2474 ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold",
2475 nau8825->sar_threshold, nau8825->sar_threshold_num);
2476 if (ret) {
2477 nau8825->sar_threshold[0] = 0x08;
2478 nau8825->sar_threshold[1] = 0x12;
2479 nau8825->sar_threshold[2] = 0x26;
2480 nau8825->sar_threshold[3] = 0x73;
2481 }
2482 ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis",
2483 &nau8825->sar_hysteresis);
2484 if (ret)
2485 nau8825->sar_hysteresis = 0;
2486 ret = device_property_read_u32(dev, "nuvoton,sar-voltage",
2487 &nau8825->sar_voltage);
2488 if (ret)
2489 nau8825->sar_voltage = 6;
2490 ret = device_property_read_u32(dev, "nuvoton,sar-compare-time",
2491 &nau8825->sar_compare_time);
2492 if (ret)
2493 nau8825->sar_compare_time = 1;
2494 ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time",
2495 &nau8825->sar_sampling_time);
2496 if (ret)
2497 nau8825->sar_sampling_time = 1;
2498 ret = device_property_read_u32(dev, "nuvoton,short-key-debounce",
2499 &nau8825->key_debounce);
2500 if (ret)
2501 nau8825->key_debounce = 3;
2502 ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
2503 &nau8825->jack_insert_debounce);
2504 if (ret)
2505 nau8825->jack_insert_debounce = 7;
2506 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
2507 &nau8825->jack_eject_debounce);
2508 if (ret)
2509 nau8825->jack_eject_debounce = 0;
2510 nau8825->xtalk_bypass = device_property_read_bool(dev,
2511 "nuvoton,crosstalk-bypass");
2512
2513 nau8825->mclk = devm_clk_get(dev, "mclk");
2514 if (PTR_ERR(nau8825->mclk) == -EPROBE_DEFER) {
2515 return -EPROBE_DEFER;
2516 } else if (PTR_ERR(nau8825->mclk) == -ENOENT) {
2517 /* The MCLK is managed externally or not used at all */
2518 nau8825->mclk = NULL;
2519 dev_info(dev, "No 'mclk' clock found, assume MCLK is managed externally");
2520 } else if (IS_ERR(nau8825->mclk)) {
2521 return -EINVAL;
2522 }
2523
2524 return 0;
2525 }
2526
2527 static int nau8825_setup_irq(struct nau8825 *nau8825)
2528 {
2529 int ret;
2530
2531 ret = devm_request_threaded_irq(nau8825->dev, nau8825->irq, NULL,
2532 nau8825_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
2533 "nau8825", nau8825);
2534
2535 if (ret) {
2536 dev_err(nau8825->dev, "Cannot request irq %d (%d)\n",
2537 nau8825->irq, ret);
2538 return ret;
2539 }
2540
2541 return 0;
2542 }
2543
2544 static int nau8825_i2c_probe(struct i2c_client *i2c,
2545 const struct i2c_device_id *id)
2546 {
2547 struct device *dev = &i2c->dev;
2548 struct nau8825 *nau8825 = dev_get_platdata(&i2c->dev);
2549 int ret, value;
2550
2551 if (!nau8825) {
2552 nau8825 = devm_kzalloc(dev, sizeof(*nau8825), GFP_KERNEL);
2553 if (!nau8825)
2554 return -ENOMEM;
2555 ret = nau8825_read_device_properties(dev, nau8825);
2556 if (ret)
2557 return ret;
2558 }
2559
2560 i2c_set_clientdata(i2c, nau8825);
2561
2562 nau8825->regmap = devm_regmap_init_i2c(i2c, &nau8825_regmap_config);
2563 if (IS_ERR(nau8825->regmap))
2564 return PTR_ERR(nau8825->regmap);
2565 nau8825->dev = dev;
2566 nau8825->irq = i2c->irq;
2567 /* Initiate parameters, semaphore and work queue which are needed in
2568 * cross talk suppression measurment function.
2569 */
2570 nau8825->xtalk_state = NAU8825_XTALK_DONE;
2571 nau8825->xtalk_protect = false;
2572 sema_init(&nau8825->xtalk_sem, 1);
2573 INIT_WORK(&nau8825->xtalk_work, nau8825_xtalk_work);
2574
2575 nau8825_print_device_properties(nau8825);
2576
2577 nau8825_reset_chip(nau8825->regmap);
2578 ret = regmap_read(nau8825->regmap, NAU8825_REG_I2C_DEVICE_ID, &value);
2579 if (ret < 0) {
2580 dev_err(dev, "Failed to read device id from the NAU8825: %d\n",
2581 ret);
2582 return ret;
2583 }
2584 if ((value & NAU8825_SOFTWARE_ID_MASK) !=
2585 NAU8825_SOFTWARE_ID_NAU8825) {
2586 dev_err(dev, "Not a NAU8825 chip\n");
2587 return -ENODEV;
2588 }
2589
2590 nau8825_init_regs(nau8825);
2591
2592 if (i2c->irq)
2593 nau8825_setup_irq(nau8825);
2594
2595 return snd_soc_register_codec(&i2c->dev, &nau8825_codec_driver,
2596 &nau8825_dai, 1);
2597 }
2598
2599 static int nau8825_i2c_remove(struct i2c_client *client)
2600 {
2601 snd_soc_unregister_codec(&client->dev);
2602 return 0;
2603 }
2604
2605 static const struct i2c_device_id nau8825_i2c_ids[] = {
2606 { "nau8825", 0 },
2607 { }
2608 };
2609 MODULE_DEVICE_TABLE(i2c, nau8825_i2c_ids);
2610
2611 #ifdef CONFIG_OF
2612 static const struct of_device_id nau8825_of_ids[] = {
2613 { .compatible = "nuvoton,nau8825", },
2614 {}
2615 };
2616 MODULE_DEVICE_TABLE(of, nau8825_of_ids);
2617 #endif
2618
2619 #ifdef CONFIG_ACPI
2620 static const struct acpi_device_id nau8825_acpi_match[] = {
2621 { "10508825", 0 },
2622 {},
2623 };
2624 MODULE_DEVICE_TABLE(acpi, nau8825_acpi_match);
2625 #endif
2626
2627 static struct i2c_driver nau8825_driver = {
2628 .driver = {
2629 .name = "nau8825",
2630 .of_match_table = of_match_ptr(nau8825_of_ids),
2631 .acpi_match_table = ACPI_PTR(nau8825_acpi_match),
2632 },
2633 .probe = nau8825_i2c_probe,
2634 .remove = nau8825_i2c_remove,
2635 .id_table = nau8825_i2c_ids,
2636 };
2637 module_i2c_driver(nau8825_driver);
2638
2639 MODULE_DESCRIPTION("ASoC nau8825 driver");
2640 MODULE_AUTHOR("Anatol Pomozov <anatol@chromium.org>");
2641 MODULE_LICENSE("GPL");