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Merge branch 'for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
52
53
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57 static char *model[SNDRV_CARDS];
58 static int position_fix[SNDRV_CARDS];
59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int probe_only[SNDRV_CARDS];
62 static int single_cmd;
63 static int enable_msi = -1;
64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
65 static char *patch[SNDRV_CARDS];
66 #endif
67 #ifdef CONFIG_SND_HDA_INPUT_BEEP
68 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
69 CONFIG_SND_HDA_INPUT_BEEP_MODE};
70 #endif
71
72 module_param_array(index, int, NULL, 0444);
73 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
74 module_param_array(id, charp, NULL, 0444);
75 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
76 module_param_array(enable, bool, NULL, 0444);
77 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
78 module_param_array(model, charp, NULL, 0444);
79 MODULE_PARM_DESC(model, "Use the given board model.");
80 module_param_array(position_fix, int, NULL, 0444);
81 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
82 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
83 module_param_array(bdl_pos_adj, int, NULL, 0644);
84 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
85 module_param_array(probe_mask, int, NULL, 0444);
86 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
87 module_param_array(probe_only, int, NULL, 0444);
88 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
89 module_param(single_cmd, bool, 0444);
90 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
91 "(for debugging only).");
92 module_param(enable_msi, int, 0444);
93 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
94 #ifdef CONFIG_SND_HDA_PATCH_LOADER
95 module_param_array(patch, charp, NULL, 0444);
96 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
97 #endif
98 #ifdef CONFIG_SND_HDA_INPUT_BEEP
99 module_param_array(beep_mode, int, NULL, 0444);
100 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
101 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
102 #endif
103
104 #ifdef CONFIG_SND_HDA_POWER_SAVE
105 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
106 module_param(power_save, int, 0644);
107 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
108 "(in second, 0 = disable).");
109
110 /* reset the HD-audio controller in power save mode.
111 * this may give more power-saving, but will take longer time to
112 * wake up.
113 */
114 static int power_save_controller = 1;
115 module_param(power_save_controller, bool, 0644);
116 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
117 #endif
118
119 MODULE_LICENSE("GPL");
120 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
121 "{Intel, ICH6M},"
122 "{Intel, ICH7},"
123 "{Intel, ESB2},"
124 "{Intel, ICH8},"
125 "{Intel, ICH9},"
126 "{Intel, ICH10},"
127 "{Intel, PCH},"
128 "{Intel, CPT},"
129 "{Intel, PBG},"
130 "{Intel, SCH},"
131 "{ATI, SB450},"
132 "{ATI, SB600},"
133 "{ATI, RS600},"
134 "{ATI, RS690},"
135 "{ATI, RS780},"
136 "{ATI, R600},"
137 "{ATI, RV630},"
138 "{ATI, RV610},"
139 "{ATI, RV670},"
140 "{ATI, RV635},"
141 "{ATI, RV620},"
142 "{ATI, RV770},"
143 "{VIA, VT8251},"
144 "{VIA, VT8237A},"
145 "{SiS, SIS966},"
146 "{ULI, M5461}}");
147 MODULE_DESCRIPTION("Intel HDA driver");
148
149 #ifdef CONFIG_SND_VERBOSE_PRINTK
150 #define SFX /* nop */
151 #else
152 #define SFX "hda-intel: "
153 #endif
154
155 /*
156 * registers
157 */
158 #define ICH6_REG_GCAP 0x00
159 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
160 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
161 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
162 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
163 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
164 #define ICH6_REG_VMIN 0x02
165 #define ICH6_REG_VMAJ 0x03
166 #define ICH6_REG_OUTPAY 0x04
167 #define ICH6_REG_INPAY 0x06
168 #define ICH6_REG_GCTL 0x08
169 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
170 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
171 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
172 #define ICH6_REG_WAKEEN 0x0c
173 #define ICH6_REG_STATESTS 0x0e
174 #define ICH6_REG_GSTS 0x10
175 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
176 #define ICH6_REG_INTCTL 0x20
177 #define ICH6_REG_INTSTS 0x24
178 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
179 #define ICH6_REG_SYNC 0x34
180 #define ICH6_REG_CORBLBASE 0x40
181 #define ICH6_REG_CORBUBASE 0x44
182 #define ICH6_REG_CORBWP 0x48
183 #define ICH6_REG_CORBRP 0x4a
184 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
185 #define ICH6_REG_CORBCTL 0x4c
186 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
187 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
188 #define ICH6_REG_CORBSTS 0x4d
189 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
190 #define ICH6_REG_CORBSIZE 0x4e
191
192 #define ICH6_REG_RIRBLBASE 0x50
193 #define ICH6_REG_RIRBUBASE 0x54
194 #define ICH6_REG_RIRBWP 0x58
195 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
196 #define ICH6_REG_RINTCNT 0x5a
197 #define ICH6_REG_RIRBCTL 0x5c
198 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
199 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
200 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
201 #define ICH6_REG_RIRBSTS 0x5d
202 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
203 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
204 #define ICH6_REG_RIRBSIZE 0x5e
205
206 #define ICH6_REG_IC 0x60
207 #define ICH6_REG_IR 0x64
208 #define ICH6_REG_IRS 0x68
209 #define ICH6_IRS_VALID (1<<1)
210 #define ICH6_IRS_BUSY (1<<0)
211
212 #define ICH6_REG_DPLBASE 0x70
213 #define ICH6_REG_DPUBASE 0x74
214 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
215
216 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
217 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
218
219 /* stream register offsets from stream base */
220 #define ICH6_REG_SD_CTL 0x00
221 #define ICH6_REG_SD_STS 0x03
222 #define ICH6_REG_SD_LPIB 0x04
223 #define ICH6_REG_SD_CBL 0x08
224 #define ICH6_REG_SD_LVI 0x0c
225 #define ICH6_REG_SD_FIFOW 0x0e
226 #define ICH6_REG_SD_FIFOSIZE 0x10
227 #define ICH6_REG_SD_FORMAT 0x12
228 #define ICH6_REG_SD_BDLPL 0x18
229 #define ICH6_REG_SD_BDLPU 0x1c
230
231 /* PCI space */
232 #define ICH6_PCIREG_TCSEL 0x44
233
234 /*
235 * other constants
236 */
237
238 /* max number of SDs */
239 /* ICH, ATI and VIA have 4 playback and 4 capture */
240 #define ICH6_NUM_CAPTURE 4
241 #define ICH6_NUM_PLAYBACK 4
242
243 /* ULI has 6 playback and 5 capture */
244 #define ULI_NUM_CAPTURE 5
245 #define ULI_NUM_PLAYBACK 6
246
247 /* ATI HDMI has 1 playback and 0 capture */
248 #define ATIHDMI_NUM_CAPTURE 0
249 #define ATIHDMI_NUM_PLAYBACK 1
250
251 /* TERA has 4 playback and 3 capture */
252 #define TERA_NUM_CAPTURE 3
253 #define TERA_NUM_PLAYBACK 4
254
255 /* this number is statically defined for simplicity */
256 #define MAX_AZX_DEV 16
257
258 /* max number of fragments - we may use more if allocating more pages for BDL */
259 #define BDL_SIZE 4096
260 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
261 #define AZX_MAX_FRAG 32
262 /* max buffer size - no h/w limit, you can increase as you like */
263 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
264
265 /* RIRB int mask: overrun[2], response[0] */
266 #define RIRB_INT_RESPONSE 0x01
267 #define RIRB_INT_OVERRUN 0x04
268 #define RIRB_INT_MASK 0x05
269
270 /* STATESTS int mask: S3,SD2,SD1,SD0 */
271 #define AZX_MAX_CODECS 8
272 #define AZX_DEFAULT_CODECS 4
273 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
274
275 /* SD_CTL bits */
276 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
277 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
278 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
279 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
280 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
281 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
282 #define SD_CTL_STREAM_TAG_SHIFT 20
283
284 /* SD_CTL and SD_STS */
285 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
286 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
287 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
288 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
289 SD_INT_COMPLETE)
290
291 /* SD_STS */
292 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
293
294 /* INTCTL and INTSTS */
295 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
296 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
297 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
298
299 /* below are so far hardcoded - should read registers in future */
300 #define ICH6_MAX_CORB_ENTRIES 256
301 #define ICH6_MAX_RIRB_ENTRIES 256
302
303 /* position fix mode */
304 enum {
305 POS_FIX_AUTO,
306 POS_FIX_LPIB,
307 POS_FIX_POSBUF,
308 POS_FIX_VIACOMBO,
309 };
310
311 /* Defines for ATI HD Audio support in SB450 south bridge */
312 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
313 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
314
315 /* Defines for Nvidia HDA support */
316 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
317 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
318 #define NVIDIA_HDA_ISTRM_COH 0x4d
319 #define NVIDIA_HDA_OSTRM_COH 0x4c
320 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
321
322 /* Defines for Intel SCH HDA snoop control */
323 #define INTEL_SCH_HDA_DEVC 0x78
324 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
325
326 /* Define IN stream 0 FIFO size offset in VIA controller */
327 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
328 /* Define VIA HD Audio Device ID*/
329 #define VIA_HDAC_DEVICE_ID 0x3288
330
331 /* HD Audio class code */
332 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
333
334 /*
335 */
336
337 struct azx_dev {
338 struct snd_dma_buffer bdl; /* BDL buffer */
339 u32 *posbuf; /* position buffer pointer */
340
341 unsigned int bufsize; /* size of the play buffer in bytes */
342 unsigned int period_bytes; /* size of the period in bytes */
343 unsigned int frags; /* number for period in the play buffer */
344 unsigned int fifo_size; /* FIFO size */
345 unsigned long start_wallclk; /* start + minimum wallclk */
346 unsigned long period_wallclk; /* wallclk for period */
347
348 void __iomem *sd_addr; /* stream descriptor pointer */
349
350 u32 sd_int_sta_mask; /* stream int status mask */
351
352 /* pcm support */
353 struct snd_pcm_substream *substream; /* assigned substream,
354 * set in PCM open
355 */
356 unsigned int format_val; /* format value to be set in the
357 * controller and the codec
358 */
359 unsigned char stream_tag; /* assigned stream */
360 unsigned char index; /* stream index */
361 int device; /* last device number assigned to */
362
363 unsigned int opened :1;
364 unsigned int running :1;
365 unsigned int irq_pending :1;
366 /*
367 * For VIA:
368 * A flag to ensure DMA position is 0
369 * when link position is not greater than FIFO size
370 */
371 unsigned int insufficient :1;
372 };
373
374 /* CORB/RIRB */
375 struct azx_rb {
376 u32 *buf; /* CORB/RIRB buffer
377 * Each CORB entry is 4byte, RIRB is 8byte
378 */
379 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
380 /* for RIRB */
381 unsigned short rp, wp; /* read/write pointers */
382 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
383 u32 res[AZX_MAX_CODECS]; /* last read value */
384 };
385
386 struct azx {
387 struct snd_card *card;
388 struct pci_dev *pci;
389 int dev_index;
390
391 /* chip type specific */
392 int driver_type;
393 int playback_streams;
394 int playback_index_offset;
395 int capture_streams;
396 int capture_index_offset;
397 int num_streams;
398
399 /* pci resources */
400 unsigned long addr;
401 void __iomem *remap_addr;
402 int irq;
403
404 /* locks */
405 spinlock_t reg_lock;
406 struct mutex open_mutex;
407
408 /* streams (x num_streams) */
409 struct azx_dev *azx_dev;
410
411 /* PCM */
412 struct snd_pcm *pcm[HDA_MAX_PCMS];
413
414 /* HD codec */
415 unsigned short codec_mask;
416 int codec_probe_mask; /* copied from probe_mask option */
417 struct hda_bus *bus;
418 unsigned int beep_mode;
419
420 /* CORB/RIRB */
421 struct azx_rb corb;
422 struct azx_rb rirb;
423
424 /* CORB/RIRB and position buffers */
425 struct snd_dma_buffer rb;
426 struct snd_dma_buffer posbuf;
427
428 /* flags */
429 int position_fix[2]; /* for both playback/capture streams */
430 int poll_count;
431 unsigned int running :1;
432 unsigned int initialized :1;
433 unsigned int single_cmd :1;
434 unsigned int polling_mode :1;
435 unsigned int msi :1;
436 unsigned int irq_pending_warned :1;
437 unsigned int probing :1; /* codec probing phase */
438
439 /* for debugging */
440 unsigned int last_cmd[AZX_MAX_CODECS];
441
442 /* for pending irqs */
443 struct work_struct irq_pending_work;
444
445 /* reboot notifier (for mysterious hangup problem at power-down) */
446 struct notifier_block reboot_notifier;
447 };
448
449 /* driver types */
450 enum {
451 AZX_DRIVER_ICH,
452 AZX_DRIVER_PCH,
453 AZX_DRIVER_SCH,
454 AZX_DRIVER_ATI,
455 AZX_DRIVER_ATIHDMI,
456 AZX_DRIVER_VIA,
457 AZX_DRIVER_SIS,
458 AZX_DRIVER_ULI,
459 AZX_DRIVER_NVIDIA,
460 AZX_DRIVER_TERA,
461 AZX_DRIVER_CTX,
462 AZX_DRIVER_GENERIC,
463 AZX_NUM_DRIVERS, /* keep this as last entry */
464 };
465
466 static char *driver_short_names[] __devinitdata = {
467 [AZX_DRIVER_ICH] = "HDA Intel",
468 [AZX_DRIVER_PCH] = "HDA Intel PCH",
469 [AZX_DRIVER_SCH] = "HDA Intel MID",
470 [AZX_DRIVER_ATI] = "HDA ATI SB",
471 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
472 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
473 [AZX_DRIVER_SIS] = "HDA SIS966",
474 [AZX_DRIVER_ULI] = "HDA ULI M5461",
475 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
476 [AZX_DRIVER_TERA] = "HDA Teradici",
477 [AZX_DRIVER_CTX] = "HDA Creative",
478 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
479 };
480
481 /*
482 * macros for easy use
483 */
484 #define azx_writel(chip,reg,value) \
485 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
486 #define azx_readl(chip,reg) \
487 readl((chip)->remap_addr + ICH6_REG_##reg)
488 #define azx_writew(chip,reg,value) \
489 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
490 #define azx_readw(chip,reg) \
491 readw((chip)->remap_addr + ICH6_REG_##reg)
492 #define azx_writeb(chip,reg,value) \
493 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
494 #define azx_readb(chip,reg) \
495 readb((chip)->remap_addr + ICH6_REG_##reg)
496
497 #define azx_sd_writel(dev,reg,value) \
498 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
499 #define azx_sd_readl(dev,reg) \
500 readl((dev)->sd_addr + ICH6_REG_##reg)
501 #define azx_sd_writew(dev,reg,value) \
502 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
503 #define azx_sd_readw(dev,reg) \
504 readw((dev)->sd_addr + ICH6_REG_##reg)
505 #define azx_sd_writeb(dev,reg,value) \
506 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
507 #define azx_sd_readb(dev,reg) \
508 readb((dev)->sd_addr + ICH6_REG_##reg)
509
510 /* for pcm support */
511 #define get_azx_dev(substream) (substream->runtime->private_data)
512
513 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
514 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
515 /*
516 * Interface for HD codec
517 */
518
519 /*
520 * CORB / RIRB interface
521 */
522 static int azx_alloc_cmd_io(struct azx *chip)
523 {
524 int err;
525
526 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
527 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
528 snd_dma_pci_data(chip->pci),
529 PAGE_SIZE, &chip->rb);
530 if (err < 0) {
531 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
532 return err;
533 }
534 return 0;
535 }
536
537 static void azx_init_cmd_io(struct azx *chip)
538 {
539 spin_lock_irq(&chip->reg_lock);
540 /* CORB set up */
541 chip->corb.addr = chip->rb.addr;
542 chip->corb.buf = (u32 *)chip->rb.area;
543 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
544 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
545
546 /* set the corb size to 256 entries (ULI requires explicitly) */
547 azx_writeb(chip, CORBSIZE, 0x02);
548 /* set the corb write pointer to 0 */
549 azx_writew(chip, CORBWP, 0);
550 /* reset the corb hw read pointer */
551 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
552 /* enable corb dma */
553 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
554
555 /* RIRB set up */
556 chip->rirb.addr = chip->rb.addr + 2048;
557 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
558 chip->rirb.wp = chip->rirb.rp = 0;
559 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
560 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
561 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
562
563 /* set the rirb size to 256 entries (ULI requires explicitly) */
564 azx_writeb(chip, RIRBSIZE, 0x02);
565 /* reset the rirb hw write pointer */
566 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
567 /* set N=1, get RIRB response interrupt for new entry */
568 if (chip->driver_type == AZX_DRIVER_CTX)
569 azx_writew(chip, RINTCNT, 0xc0);
570 else
571 azx_writew(chip, RINTCNT, 1);
572 /* enable rirb dma and response irq */
573 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
574 spin_unlock_irq(&chip->reg_lock);
575 }
576
577 static void azx_free_cmd_io(struct azx *chip)
578 {
579 spin_lock_irq(&chip->reg_lock);
580 /* disable ringbuffer DMAs */
581 azx_writeb(chip, RIRBCTL, 0);
582 azx_writeb(chip, CORBCTL, 0);
583 spin_unlock_irq(&chip->reg_lock);
584 }
585
586 static unsigned int azx_command_addr(u32 cmd)
587 {
588 unsigned int addr = cmd >> 28;
589
590 if (addr >= AZX_MAX_CODECS) {
591 snd_BUG();
592 addr = 0;
593 }
594
595 return addr;
596 }
597
598 static unsigned int azx_response_addr(u32 res)
599 {
600 unsigned int addr = res & 0xf;
601
602 if (addr >= AZX_MAX_CODECS) {
603 snd_BUG();
604 addr = 0;
605 }
606
607 return addr;
608 }
609
610 /* send a command */
611 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
612 {
613 struct azx *chip = bus->private_data;
614 unsigned int addr = azx_command_addr(val);
615 unsigned int wp;
616
617 spin_lock_irq(&chip->reg_lock);
618
619 /* add command to corb */
620 wp = azx_readb(chip, CORBWP);
621 wp++;
622 wp %= ICH6_MAX_CORB_ENTRIES;
623
624 chip->rirb.cmds[addr]++;
625 chip->corb.buf[wp] = cpu_to_le32(val);
626 azx_writel(chip, CORBWP, wp);
627
628 spin_unlock_irq(&chip->reg_lock);
629
630 return 0;
631 }
632
633 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
634
635 /* retrieve RIRB entry - called from interrupt handler */
636 static void azx_update_rirb(struct azx *chip)
637 {
638 unsigned int rp, wp;
639 unsigned int addr;
640 u32 res, res_ex;
641
642 wp = azx_readb(chip, RIRBWP);
643 if (wp == chip->rirb.wp)
644 return;
645 chip->rirb.wp = wp;
646
647 while (chip->rirb.rp != wp) {
648 chip->rirb.rp++;
649 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
650
651 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
652 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
653 res = le32_to_cpu(chip->rirb.buf[rp]);
654 addr = azx_response_addr(res_ex);
655 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
656 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
657 else if (chip->rirb.cmds[addr]) {
658 chip->rirb.res[addr] = res;
659 smp_wmb();
660 chip->rirb.cmds[addr]--;
661 } else
662 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
663 "last cmd=%#08x\n",
664 res, res_ex,
665 chip->last_cmd[addr]);
666 }
667 }
668
669 /* receive a response */
670 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
671 unsigned int addr)
672 {
673 struct azx *chip = bus->private_data;
674 unsigned long timeout;
675 int do_poll = 0;
676
677 again:
678 timeout = jiffies + msecs_to_jiffies(1000);
679 for (;;) {
680 if (chip->polling_mode || do_poll) {
681 spin_lock_irq(&chip->reg_lock);
682 azx_update_rirb(chip);
683 spin_unlock_irq(&chip->reg_lock);
684 }
685 if (!chip->rirb.cmds[addr]) {
686 smp_rmb();
687 bus->rirb_error = 0;
688
689 if (!do_poll)
690 chip->poll_count = 0;
691 return chip->rirb.res[addr]; /* the last value */
692 }
693 if (time_after(jiffies, timeout))
694 break;
695 if (bus->needs_damn_long_delay)
696 msleep(2); /* temporary workaround */
697 else {
698 udelay(10);
699 cond_resched();
700 }
701 }
702
703 if (!chip->polling_mode && chip->poll_count < 2) {
704 snd_printdd(SFX "azx_get_response timeout, "
705 "polling the codec once: last cmd=0x%08x\n",
706 chip->last_cmd[addr]);
707 do_poll = 1;
708 chip->poll_count++;
709 goto again;
710 }
711
712
713 if (!chip->polling_mode) {
714 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
715 "switching to polling mode: last cmd=0x%08x\n",
716 chip->last_cmd[addr]);
717 chip->polling_mode = 1;
718 goto again;
719 }
720
721 if (chip->msi) {
722 snd_printk(KERN_WARNING SFX "No response from codec, "
723 "disabling MSI: last cmd=0x%08x\n",
724 chip->last_cmd[addr]);
725 free_irq(chip->irq, chip);
726 chip->irq = -1;
727 pci_disable_msi(chip->pci);
728 chip->msi = 0;
729 if (azx_acquire_irq(chip, 1) < 0) {
730 bus->rirb_error = 1;
731 return -1;
732 }
733 goto again;
734 }
735
736 if (chip->probing) {
737 /* If this critical timeout happens during the codec probing
738 * phase, this is likely an access to a non-existing codec
739 * slot. Better to return an error and reset the system.
740 */
741 return -1;
742 }
743
744 /* a fatal communication error; need either to reset or to fallback
745 * to the single_cmd mode
746 */
747 bus->rirb_error = 1;
748 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
749 bus->response_reset = 1;
750 return -1; /* give a chance to retry */
751 }
752
753 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
754 "switching to single_cmd mode: last cmd=0x%08x\n",
755 chip->last_cmd[addr]);
756 chip->single_cmd = 1;
757 bus->response_reset = 0;
758 /* release CORB/RIRB */
759 azx_free_cmd_io(chip);
760 /* disable unsolicited responses */
761 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
762 return -1;
763 }
764
765 /*
766 * Use the single immediate command instead of CORB/RIRB for simplicity
767 *
768 * Note: according to Intel, this is not preferred use. The command was
769 * intended for the BIOS only, and may get confused with unsolicited
770 * responses. So, we shouldn't use it for normal operation from the
771 * driver.
772 * I left the codes, however, for debugging/testing purposes.
773 */
774
775 /* receive a response */
776 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
777 {
778 int timeout = 50;
779
780 while (timeout--) {
781 /* check IRV busy bit */
782 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
783 /* reuse rirb.res as the response return value */
784 chip->rirb.res[addr] = azx_readl(chip, IR);
785 return 0;
786 }
787 udelay(1);
788 }
789 if (printk_ratelimit())
790 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
791 azx_readw(chip, IRS));
792 chip->rirb.res[addr] = -1;
793 return -EIO;
794 }
795
796 /* send a command */
797 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
798 {
799 struct azx *chip = bus->private_data;
800 unsigned int addr = azx_command_addr(val);
801 int timeout = 50;
802
803 bus->rirb_error = 0;
804 while (timeout--) {
805 /* check ICB busy bit */
806 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
807 /* Clear IRV valid bit */
808 azx_writew(chip, IRS, azx_readw(chip, IRS) |
809 ICH6_IRS_VALID);
810 azx_writel(chip, IC, val);
811 azx_writew(chip, IRS, azx_readw(chip, IRS) |
812 ICH6_IRS_BUSY);
813 return azx_single_wait_for_response(chip, addr);
814 }
815 udelay(1);
816 }
817 if (printk_ratelimit())
818 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
819 azx_readw(chip, IRS), val);
820 return -EIO;
821 }
822
823 /* receive a response */
824 static unsigned int azx_single_get_response(struct hda_bus *bus,
825 unsigned int addr)
826 {
827 struct azx *chip = bus->private_data;
828 return chip->rirb.res[addr];
829 }
830
831 /*
832 * The below are the main callbacks from hda_codec.
833 *
834 * They are just the skeleton to call sub-callbacks according to the
835 * current setting of chip->single_cmd.
836 */
837
838 /* send a command */
839 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
840 {
841 struct azx *chip = bus->private_data;
842
843 chip->last_cmd[azx_command_addr(val)] = val;
844 if (chip->single_cmd)
845 return azx_single_send_cmd(bus, val);
846 else
847 return azx_corb_send_cmd(bus, val);
848 }
849
850 /* get a response */
851 static unsigned int azx_get_response(struct hda_bus *bus,
852 unsigned int addr)
853 {
854 struct azx *chip = bus->private_data;
855 if (chip->single_cmd)
856 return azx_single_get_response(bus, addr);
857 else
858 return azx_rirb_get_response(bus, addr);
859 }
860
861 #ifdef CONFIG_SND_HDA_POWER_SAVE
862 static void azx_power_notify(struct hda_bus *bus);
863 #endif
864
865 /* reset codec link */
866 static int azx_reset(struct azx *chip, int full_reset)
867 {
868 int count;
869
870 if (!full_reset)
871 goto __skip;
872
873 /* clear STATESTS */
874 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
875
876 /* reset controller */
877 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
878
879 count = 50;
880 while (azx_readb(chip, GCTL) && --count)
881 msleep(1);
882
883 /* delay for >= 100us for codec PLL to settle per spec
884 * Rev 0.9 section 5.5.1
885 */
886 msleep(1);
887
888 /* Bring controller out of reset */
889 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
890
891 count = 50;
892 while (!azx_readb(chip, GCTL) && --count)
893 msleep(1);
894
895 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
896 msleep(1);
897
898 __skip:
899 /* check to see if controller is ready */
900 if (!azx_readb(chip, GCTL)) {
901 snd_printd(SFX "azx_reset: controller not ready!\n");
902 return -EBUSY;
903 }
904
905 /* Accept unsolicited responses */
906 if (!chip->single_cmd)
907 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
908 ICH6_GCTL_UNSOL);
909
910 /* detect codecs */
911 if (!chip->codec_mask) {
912 chip->codec_mask = azx_readw(chip, STATESTS);
913 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
914 }
915
916 return 0;
917 }
918
919
920 /*
921 * Lowlevel interface
922 */
923
924 /* enable interrupts */
925 static void azx_int_enable(struct azx *chip)
926 {
927 /* enable controller CIE and GIE */
928 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
929 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
930 }
931
932 /* disable interrupts */
933 static void azx_int_disable(struct azx *chip)
934 {
935 int i;
936
937 /* disable interrupts in stream descriptor */
938 for (i = 0; i < chip->num_streams; i++) {
939 struct azx_dev *azx_dev = &chip->azx_dev[i];
940 azx_sd_writeb(azx_dev, SD_CTL,
941 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
942 }
943
944 /* disable SIE for all streams */
945 azx_writeb(chip, INTCTL, 0);
946
947 /* disable controller CIE and GIE */
948 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
949 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
950 }
951
952 /* clear interrupts */
953 static void azx_int_clear(struct azx *chip)
954 {
955 int i;
956
957 /* clear stream status */
958 for (i = 0; i < chip->num_streams; i++) {
959 struct azx_dev *azx_dev = &chip->azx_dev[i];
960 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
961 }
962
963 /* clear STATESTS */
964 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
965
966 /* clear rirb status */
967 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
968
969 /* clear int status */
970 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
971 }
972
973 /* start a stream */
974 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
975 {
976 /*
977 * Before stream start, initialize parameter
978 */
979 azx_dev->insufficient = 1;
980
981 /* enable SIE */
982 azx_writel(chip, INTCTL,
983 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
984 /* set DMA start and interrupt mask */
985 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
986 SD_CTL_DMA_START | SD_INT_MASK);
987 }
988
989 /* stop DMA */
990 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
991 {
992 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
993 ~(SD_CTL_DMA_START | SD_INT_MASK));
994 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
995 }
996
997 /* stop a stream */
998 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
999 {
1000 azx_stream_clear(chip, azx_dev);
1001 /* disable SIE */
1002 azx_writel(chip, INTCTL,
1003 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1004 }
1005
1006
1007 /*
1008 * reset and start the controller registers
1009 */
1010 static void azx_init_chip(struct azx *chip, int full_reset)
1011 {
1012 if (chip->initialized)
1013 return;
1014
1015 /* reset controller */
1016 azx_reset(chip, full_reset);
1017
1018 /* initialize interrupts */
1019 azx_int_clear(chip);
1020 azx_int_enable(chip);
1021
1022 /* initialize the codec command I/O */
1023 if (!chip->single_cmd)
1024 azx_init_cmd_io(chip);
1025
1026 /* program the position buffer */
1027 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1028 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1029
1030 chip->initialized = 1;
1031 }
1032
1033 /*
1034 * initialize the PCI registers
1035 */
1036 /* update bits in a PCI register byte */
1037 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1038 unsigned char mask, unsigned char val)
1039 {
1040 unsigned char data;
1041
1042 pci_read_config_byte(pci, reg, &data);
1043 data &= ~mask;
1044 data |= (val & mask);
1045 pci_write_config_byte(pci, reg, data);
1046 }
1047
1048 static void azx_init_pci(struct azx *chip)
1049 {
1050 unsigned short snoop;
1051
1052 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1053 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1054 * Ensuring these bits are 0 clears playback static on some HD Audio
1055 * codecs
1056 */
1057 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1058
1059 switch (chip->driver_type) {
1060 case AZX_DRIVER_ATI:
1061 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1062 update_pci_byte(chip->pci,
1063 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1064 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1065 break;
1066 case AZX_DRIVER_NVIDIA:
1067 /* For NVIDIA HDA, enable snoop */
1068 update_pci_byte(chip->pci,
1069 NVIDIA_HDA_TRANSREG_ADDR,
1070 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1071 update_pci_byte(chip->pci,
1072 NVIDIA_HDA_ISTRM_COH,
1073 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1074 update_pci_byte(chip->pci,
1075 NVIDIA_HDA_OSTRM_COH,
1076 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1077 break;
1078 case AZX_DRIVER_SCH:
1079 case AZX_DRIVER_PCH:
1080 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1081 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1082 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1083 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1084 pci_read_config_word(chip->pci,
1085 INTEL_SCH_HDA_DEVC, &snoop);
1086 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1087 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1088 ? "Failed" : "OK");
1089 }
1090 break;
1091
1092 }
1093 }
1094
1095
1096 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1097
1098 /*
1099 * interrupt handler
1100 */
1101 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1102 {
1103 struct azx *chip = dev_id;
1104 struct azx_dev *azx_dev;
1105 u32 status;
1106 u8 sd_status;
1107 int i, ok;
1108
1109 spin_lock(&chip->reg_lock);
1110
1111 status = azx_readl(chip, INTSTS);
1112 if (status == 0) {
1113 spin_unlock(&chip->reg_lock);
1114 return IRQ_NONE;
1115 }
1116
1117 for (i = 0; i < chip->num_streams; i++) {
1118 azx_dev = &chip->azx_dev[i];
1119 if (status & azx_dev->sd_int_sta_mask) {
1120 sd_status = azx_sd_readb(azx_dev, SD_STS);
1121 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1122 if (!azx_dev->substream || !azx_dev->running ||
1123 !(sd_status & SD_INT_COMPLETE))
1124 continue;
1125 /* check whether this IRQ is really acceptable */
1126 ok = azx_position_ok(chip, azx_dev);
1127 if (ok == 1) {
1128 azx_dev->irq_pending = 0;
1129 spin_unlock(&chip->reg_lock);
1130 snd_pcm_period_elapsed(azx_dev->substream);
1131 spin_lock(&chip->reg_lock);
1132 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1133 /* bogus IRQ, process it later */
1134 azx_dev->irq_pending = 1;
1135 queue_work(chip->bus->workq,
1136 &chip->irq_pending_work);
1137 }
1138 }
1139 }
1140
1141 /* clear rirb int */
1142 status = azx_readb(chip, RIRBSTS);
1143 if (status & RIRB_INT_MASK) {
1144 if (status & RIRB_INT_RESPONSE) {
1145 if (chip->driver_type == AZX_DRIVER_CTX)
1146 udelay(80);
1147 azx_update_rirb(chip);
1148 }
1149 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1150 }
1151
1152 #if 0
1153 /* clear state status int */
1154 if (azx_readb(chip, STATESTS) & 0x04)
1155 azx_writeb(chip, STATESTS, 0x04);
1156 #endif
1157 spin_unlock(&chip->reg_lock);
1158
1159 return IRQ_HANDLED;
1160 }
1161
1162
1163 /*
1164 * set up a BDL entry
1165 */
1166 static int setup_bdle(struct snd_pcm_substream *substream,
1167 struct azx_dev *azx_dev, u32 **bdlp,
1168 int ofs, int size, int with_ioc)
1169 {
1170 u32 *bdl = *bdlp;
1171
1172 while (size > 0) {
1173 dma_addr_t addr;
1174 int chunk;
1175
1176 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1177 return -EINVAL;
1178
1179 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1180 /* program the address field of the BDL entry */
1181 bdl[0] = cpu_to_le32((u32)addr);
1182 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1183 /* program the size field of the BDL entry */
1184 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1185 bdl[2] = cpu_to_le32(chunk);
1186 /* program the IOC to enable interrupt
1187 * only when the whole fragment is processed
1188 */
1189 size -= chunk;
1190 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1191 bdl += 4;
1192 azx_dev->frags++;
1193 ofs += chunk;
1194 }
1195 *bdlp = bdl;
1196 return ofs;
1197 }
1198
1199 /*
1200 * set up BDL entries
1201 */
1202 static int azx_setup_periods(struct azx *chip,
1203 struct snd_pcm_substream *substream,
1204 struct azx_dev *azx_dev)
1205 {
1206 u32 *bdl;
1207 int i, ofs, periods, period_bytes;
1208 int pos_adj;
1209
1210 /* reset BDL address */
1211 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1212 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1213
1214 period_bytes = azx_dev->period_bytes;
1215 periods = azx_dev->bufsize / period_bytes;
1216
1217 /* program the initial BDL entries */
1218 bdl = (u32 *)azx_dev->bdl.area;
1219 ofs = 0;
1220 azx_dev->frags = 0;
1221 pos_adj = bdl_pos_adj[chip->dev_index];
1222 if (pos_adj > 0) {
1223 struct snd_pcm_runtime *runtime = substream->runtime;
1224 int pos_align = pos_adj;
1225 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1226 if (!pos_adj)
1227 pos_adj = pos_align;
1228 else
1229 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1230 pos_align;
1231 pos_adj = frames_to_bytes(runtime, pos_adj);
1232 if (pos_adj >= period_bytes) {
1233 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1234 bdl_pos_adj[chip->dev_index]);
1235 pos_adj = 0;
1236 } else {
1237 ofs = setup_bdle(substream, azx_dev,
1238 &bdl, ofs, pos_adj, 1);
1239 if (ofs < 0)
1240 goto error;
1241 }
1242 } else
1243 pos_adj = 0;
1244 for (i = 0; i < periods; i++) {
1245 if (i == periods - 1 && pos_adj)
1246 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1247 period_bytes - pos_adj, 0);
1248 else
1249 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1250 period_bytes, 1);
1251 if (ofs < 0)
1252 goto error;
1253 }
1254 return 0;
1255
1256 error:
1257 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1258 azx_dev->bufsize, period_bytes);
1259 return -EINVAL;
1260 }
1261
1262 /* reset stream */
1263 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1264 {
1265 unsigned char val;
1266 int timeout;
1267
1268 azx_stream_clear(chip, azx_dev);
1269
1270 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1271 SD_CTL_STREAM_RESET);
1272 udelay(3);
1273 timeout = 300;
1274 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1275 --timeout)
1276 ;
1277 val &= ~SD_CTL_STREAM_RESET;
1278 azx_sd_writeb(azx_dev, SD_CTL, val);
1279 udelay(3);
1280
1281 timeout = 300;
1282 /* waiting for hardware to report that the stream is out of reset */
1283 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1284 --timeout)
1285 ;
1286
1287 /* reset first position - may not be synced with hw at this time */
1288 *azx_dev->posbuf = 0;
1289 }
1290
1291 /*
1292 * set up the SD for streaming
1293 */
1294 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1295 {
1296 /* make sure the run bit is zero for SD */
1297 azx_stream_clear(chip, azx_dev);
1298 /* program the stream_tag */
1299 azx_sd_writel(azx_dev, SD_CTL,
1300 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1301 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1302
1303 /* program the length of samples in cyclic buffer */
1304 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1305
1306 /* program the stream format */
1307 /* this value needs to be the same as the one programmed */
1308 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1309
1310 /* program the stream LVI (last valid index) of the BDL */
1311 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1312
1313 /* program the BDL address */
1314 /* lower BDL address */
1315 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1316 /* upper BDL address */
1317 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1318
1319 /* enable the position buffer */
1320 if (chip->position_fix[0] != POS_FIX_LPIB ||
1321 chip->position_fix[1] != POS_FIX_LPIB) {
1322 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1323 azx_writel(chip, DPLBASE,
1324 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1325 }
1326
1327 /* set the interrupt enable bits in the descriptor control register */
1328 azx_sd_writel(azx_dev, SD_CTL,
1329 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1330
1331 return 0;
1332 }
1333
1334 /*
1335 * Probe the given codec address
1336 */
1337 static int probe_codec(struct azx *chip, int addr)
1338 {
1339 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1340 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1341 unsigned int res;
1342
1343 mutex_lock(&chip->bus->cmd_mutex);
1344 chip->probing = 1;
1345 azx_send_cmd(chip->bus, cmd);
1346 res = azx_get_response(chip->bus, addr);
1347 chip->probing = 0;
1348 mutex_unlock(&chip->bus->cmd_mutex);
1349 if (res == -1)
1350 return -EIO;
1351 snd_printdd(SFX "codec #%d probed OK\n", addr);
1352 return 0;
1353 }
1354
1355 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1356 struct hda_pcm *cpcm);
1357 static void azx_stop_chip(struct azx *chip);
1358
1359 static void azx_bus_reset(struct hda_bus *bus)
1360 {
1361 struct azx *chip = bus->private_data;
1362
1363 bus->in_reset = 1;
1364 azx_stop_chip(chip);
1365 azx_init_chip(chip, 1);
1366 #ifdef CONFIG_PM
1367 if (chip->initialized) {
1368 int i;
1369
1370 for (i = 0; i < HDA_MAX_PCMS; i++)
1371 snd_pcm_suspend_all(chip->pcm[i]);
1372 snd_hda_suspend(chip->bus);
1373 snd_hda_resume(chip->bus);
1374 }
1375 #endif
1376 bus->in_reset = 0;
1377 }
1378
1379 /*
1380 * Codec initialization
1381 */
1382
1383 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1384 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1385 [AZX_DRIVER_NVIDIA] = 8,
1386 [AZX_DRIVER_TERA] = 1,
1387 };
1388
1389 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1390 {
1391 struct hda_bus_template bus_temp;
1392 int c, codecs, err;
1393 int max_slots;
1394
1395 memset(&bus_temp, 0, sizeof(bus_temp));
1396 bus_temp.private_data = chip;
1397 bus_temp.modelname = model;
1398 bus_temp.pci = chip->pci;
1399 bus_temp.ops.command = azx_send_cmd;
1400 bus_temp.ops.get_response = azx_get_response;
1401 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1402 bus_temp.ops.bus_reset = azx_bus_reset;
1403 #ifdef CONFIG_SND_HDA_POWER_SAVE
1404 bus_temp.power_save = &power_save;
1405 bus_temp.ops.pm_notify = azx_power_notify;
1406 #endif
1407
1408 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1409 if (err < 0)
1410 return err;
1411
1412 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1413 chip->bus->needs_damn_long_delay = 1;
1414
1415 codecs = 0;
1416 max_slots = azx_max_codecs[chip->driver_type];
1417 if (!max_slots)
1418 max_slots = AZX_DEFAULT_CODECS;
1419
1420 /* First try to probe all given codec slots */
1421 for (c = 0; c < max_slots; c++) {
1422 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1423 if (probe_codec(chip, c) < 0) {
1424 /* Some BIOSen give you wrong codec addresses
1425 * that don't exist
1426 */
1427 snd_printk(KERN_WARNING SFX
1428 "Codec #%d probe error; "
1429 "disabling it...\n", c);
1430 chip->codec_mask &= ~(1 << c);
1431 /* More badly, accessing to a non-existing
1432 * codec often screws up the controller chip,
1433 * and disturbs the further communications.
1434 * Thus if an error occurs during probing,
1435 * better to reset the controller chip to
1436 * get back to the sanity state.
1437 */
1438 azx_stop_chip(chip);
1439 azx_init_chip(chip, 1);
1440 }
1441 }
1442 }
1443
1444 /* Then create codec instances */
1445 for (c = 0; c < max_slots; c++) {
1446 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1447 struct hda_codec *codec;
1448 err = snd_hda_codec_new(chip->bus, c, &codec);
1449 if (err < 0)
1450 continue;
1451 codec->beep_mode = chip->beep_mode;
1452 codecs++;
1453 }
1454 }
1455 if (!codecs) {
1456 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1457 return -ENXIO;
1458 }
1459 return 0;
1460 }
1461
1462 /* configure each codec instance */
1463 static int __devinit azx_codec_configure(struct azx *chip)
1464 {
1465 struct hda_codec *codec;
1466 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1467 snd_hda_codec_configure(codec);
1468 }
1469 return 0;
1470 }
1471
1472
1473 /*
1474 * PCM support
1475 */
1476
1477 /* assign a stream for the PCM */
1478 static inline struct azx_dev *
1479 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1480 {
1481 int dev, i, nums;
1482 struct azx_dev *res = NULL;
1483
1484 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1485 dev = chip->playback_index_offset;
1486 nums = chip->playback_streams;
1487 } else {
1488 dev = chip->capture_index_offset;
1489 nums = chip->capture_streams;
1490 }
1491 for (i = 0; i < nums; i++, dev++)
1492 if (!chip->azx_dev[dev].opened) {
1493 res = &chip->azx_dev[dev];
1494 if (res->device == substream->pcm->device)
1495 break;
1496 }
1497 if (res) {
1498 res->opened = 1;
1499 res->device = substream->pcm->device;
1500 }
1501 return res;
1502 }
1503
1504 /* release the assigned stream */
1505 static inline void azx_release_device(struct azx_dev *azx_dev)
1506 {
1507 azx_dev->opened = 0;
1508 }
1509
1510 static struct snd_pcm_hardware azx_pcm_hw = {
1511 .info = (SNDRV_PCM_INFO_MMAP |
1512 SNDRV_PCM_INFO_INTERLEAVED |
1513 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1514 SNDRV_PCM_INFO_MMAP_VALID |
1515 /* No full-resume yet implemented */
1516 /* SNDRV_PCM_INFO_RESUME |*/
1517 SNDRV_PCM_INFO_PAUSE |
1518 SNDRV_PCM_INFO_SYNC_START),
1519 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1520 .rates = SNDRV_PCM_RATE_48000,
1521 .rate_min = 48000,
1522 .rate_max = 48000,
1523 .channels_min = 2,
1524 .channels_max = 2,
1525 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1526 .period_bytes_min = 128,
1527 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1528 .periods_min = 2,
1529 .periods_max = AZX_MAX_FRAG,
1530 .fifo_size = 0,
1531 };
1532
1533 struct azx_pcm {
1534 struct azx *chip;
1535 struct hda_codec *codec;
1536 struct hda_pcm_stream *hinfo[2];
1537 };
1538
1539 static int azx_pcm_open(struct snd_pcm_substream *substream)
1540 {
1541 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1542 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1543 struct azx *chip = apcm->chip;
1544 struct azx_dev *azx_dev;
1545 struct snd_pcm_runtime *runtime = substream->runtime;
1546 unsigned long flags;
1547 int err;
1548
1549 mutex_lock(&chip->open_mutex);
1550 azx_dev = azx_assign_device(chip, substream);
1551 if (azx_dev == NULL) {
1552 mutex_unlock(&chip->open_mutex);
1553 return -EBUSY;
1554 }
1555 runtime->hw = azx_pcm_hw;
1556 runtime->hw.channels_min = hinfo->channels_min;
1557 runtime->hw.channels_max = hinfo->channels_max;
1558 runtime->hw.formats = hinfo->formats;
1559 runtime->hw.rates = hinfo->rates;
1560 snd_pcm_limit_hw_rates(runtime);
1561 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1562 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1563 128);
1564 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1565 128);
1566 snd_hda_power_up(apcm->codec);
1567 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1568 if (err < 0) {
1569 azx_release_device(azx_dev);
1570 snd_hda_power_down(apcm->codec);
1571 mutex_unlock(&chip->open_mutex);
1572 return err;
1573 }
1574 snd_pcm_limit_hw_rates(runtime);
1575 /* sanity check */
1576 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1577 snd_BUG_ON(!runtime->hw.channels_max) ||
1578 snd_BUG_ON(!runtime->hw.formats) ||
1579 snd_BUG_ON(!runtime->hw.rates)) {
1580 azx_release_device(azx_dev);
1581 hinfo->ops.close(hinfo, apcm->codec, substream);
1582 snd_hda_power_down(apcm->codec);
1583 mutex_unlock(&chip->open_mutex);
1584 return -EINVAL;
1585 }
1586 spin_lock_irqsave(&chip->reg_lock, flags);
1587 azx_dev->substream = substream;
1588 azx_dev->running = 0;
1589 spin_unlock_irqrestore(&chip->reg_lock, flags);
1590
1591 runtime->private_data = azx_dev;
1592 snd_pcm_set_sync(substream);
1593 mutex_unlock(&chip->open_mutex);
1594 return 0;
1595 }
1596
1597 static int azx_pcm_close(struct snd_pcm_substream *substream)
1598 {
1599 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1600 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1601 struct azx *chip = apcm->chip;
1602 struct azx_dev *azx_dev = get_azx_dev(substream);
1603 unsigned long flags;
1604
1605 mutex_lock(&chip->open_mutex);
1606 spin_lock_irqsave(&chip->reg_lock, flags);
1607 azx_dev->substream = NULL;
1608 azx_dev->running = 0;
1609 spin_unlock_irqrestore(&chip->reg_lock, flags);
1610 azx_release_device(azx_dev);
1611 hinfo->ops.close(hinfo, apcm->codec, substream);
1612 snd_hda_power_down(apcm->codec);
1613 mutex_unlock(&chip->open_mutex);
1614 return 0;
1615 }
1616
1617 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1618 struct snd_pcm_hw_params *hw_params)
1619 {
1620 struct azx_dev *azx_dev = get_azx_dev(substream);
1621
1622 azx_dev->bufsize = 0;
1623 azx_dev->period_bytes = 0;
1624 azx_dev->format_val = 0;
1625 return snd_pcm_lib_malloc_pages(substream,
1626 params_buffer_bytes(hw_params));
1627 }
1628
1629 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1630 {
1631 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1632 struct azx_dev *azx_dev = get_azx_dev(substream);
1633 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1634
1635 /* reset BDL address */
1636 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1637 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1638 azx_sd_writel(azx_dev, SD_CTL, 0);
1639 azx_dev->bufsize = 0;
1640 azx_dev->period_bytes = 0;
1641 azx_dev->format_val = 0;
1642
1643 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1644
1645 return snd_pcm_lib_free_pages(substream);
1646 }
1647
1648 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1649 {
1650 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1651 struct azx *chip = apcm->chip;
1652 struct azx_dev *azx_dev = get_azx_dev(substream);
1653 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1654 struct snd_pcm_runtime *runtime = substream->runtime;
1655 unsigned int bufsize, period_bytes, format_val, stream_tag;
1656 int err;
1657
1658 azx_stream_reset(chip, azx_dev);
1659 format_val = snd_hda_calc_stream_format(runtime->rate,
1660 runtime->channels,
1661 runtime->format,
1662 hinfo->maxbps,
1663 apcm->codec->spdif_ctls);
1664 if (!format_val) {
1665 snd_printk(KERN_ERR SFX
1666 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1667 runtime->rate, runtime->channels, runtime->format);
1668 return -EINVAL;
1669 }
1670
1671 bufsize = snd_pcm_lib_buffer_bytes(substream);
1672 period_bytes = snd_pcm_lib_period_bytes(substream);
1673
1674 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1675 bufsize, format_val);
1676
1677 if (bufsize != azx_dev->bufsize ||
1678 period_bytes != azx_dev->period_bytes ||
1679 format_val != azx_dev->format_val) {
1680 azx_dev->bufsize = bufsize;
1681 azx_dev->period_bytes = period_bytes;
1682 azx_dev->format_val = format_val;
1683 err = azx_setup_periods(chip, substream, azx_dev);
1684 if (err < 0)
1685 return err;
1686 }
1687
1688 /* wallclk has 24Mhz clock source */
1689 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1690 runtime->rate) * 1000);
1691 azx_setup_controller(chip, azx_dev);
1692 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1693 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1694 else
1695 azx_dev->fifo_size = 0;
1696
1697 stream_tag = azx_dev->stream_tag;
1698 /* CA-IBG chips need the playback stream starting from 1 */
1699 if (chip->driver_type == AZX_DRIVER_CTX &&
1700 stream_tag > chip->capture_streams)
1701 stream_tag -= chip->capture_streams;
1702 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1703 azx_dev->format_val, substream);
1704 }
1705
1706 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1707 {
1708 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1709 struct azx *chip = apcm->chip;
1710 struct azx_dev *azx_dev;
1711 struct snd_pcm_substream *s;
1712 int rstart = 0, start, nsync = 0, sbits = 0;
1713 int nwait, timeout;
1714
1715 switch (cmd) {
1716 case SNDRV_PCM_TRIGGER_START:
1717 rstart = 1;
1718 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1719 case SNDRV_PCM_TRIGGER_RESUME:
1720 start = 1;
1721 break;
1722 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1723 case SNDRV_PCM_TRIGGER_SUSPEND:
1724 case SNDRV_PCM_TRIGGER_STOP:
1725 start = 0;
1726 break;
1727 default:
1728 return -EINVAL;
1729 }
1730
1731 snd_pcm_group_for_each_entry(s, substream) {
1732 if (s->pcm->card != substream->pcm->card)
1733 continue;
1734 azx_dev = get_azx_dev(s);
1735 sbits |= 1 << azx_dev->index;
1736 nsync++;
1737 snd_pcm_trigger_done(s, substream);
1738 }
1739
1740 spin_lock(&chip->reg_lock);
1741 if (nsync > 1) {
1742 /* first, set SYNC bits of corresponding streams */
1743 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1744 }
1745 snd_pcm_group_for_each_entry(s, substream) {
1746 if (s->pcm->card != substream->pcm->card)
1747 continue;
1748 azx_dev = get_azx_dev(s);
1749 if (start) {
1750 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1751 if (!rstart)
1752 azx_dev->start_wallclk -=
1753 azx_dev->period_wallclk;
1754 azx_stream_start(chip, azx_dev);
1755 } else {
1756 azx_stream_stop(chip, azx_dev);
1757 }
1758 azx_dev->running = start;
1759 }
1760 spin_unlock(&chip->reg_lock);
1761 if (start) {
1762 if (nsync == 1)
1763 return 0;
1764 /* wait until all FIFOs get ready */
1765 for (timeout = 5000; timeout; timeout--) {
1766 nwait = 0;
1767 snd_pcm_group_for_each_entry(s, substream) {
1768 if (s->pcm->card != substream->pcm->card)
1769 continue;
1770 azx_dev = get_azx_dev(s);
1771 if (!(azx_sd_readb(azx_dev, SD_STS) &
1772 SD_STS_FIFO_READY))
1773 nwait++;
1774 }
1775 if (!nwait)
1776 break;
1777 cpu_relax();
1778 }
1779 } else {
1780 /* wait until all RUN bits are cleared */
1781 for (timeout = 5000; timeout; timeout--) {
1782 nwait = 0;
1783 snd_pcm_group_for_each_entry(s, substream) {
1784 if (s->pcm->card != substream->pcm->card)
1785 continue;
1786 azx_dev = get_azx_dev(s);
1787 if (azx_sd_readb(azx_dev, SD_CTL) &
1788 SD_CTL_DMA_START)
1789 nwait++;
1790 }
1791 if (!nwait)
1792 break;
1793 cpu_relax();
1794 }
1795 }
1796 if (nsync > 1) {
1797 spin_lock(&chip->reg_lock);
1798 /* reset SYNC bits */
1799 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1800 spin_unlock(&chip->reg_lock);
1801 }
1802 return 0;
1803 }
1804
1805 /* get the current DMA position with correction on VIA chips */
1806 static unsigned int azx_via_get_position(struct azx *chip,
1807 struct azx_dev *azx_dev)
1808 {
1809 unsigned int link_pos, mini_pos, bound_pos;
1810 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1811 unsigned int fifo_size;
1812
1813 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1814 if (azx_dev->index >= 4) {
1815 /* Playback, no problem using link position */
1816 return link_pos;
1817 }
1818
1819 /* Capture */
1820 /* For new chipset,
1821 * use mod to get the DMA position just like old chipset
1822 */
1823 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1824 mod_dma_pos %= azx_dev->period_bytes;
1825
1826 /* azx_dev->fifo_size can't get FIFO size of in stream.
1827 * Get from base address + offset.
1828 */
1829 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1830
1831 if (azx_dev->insufficient) {
1832 /* Link position never gather than FIFO size */
1833 if (link_pos <= fifo_size)
1834 return 0;
1835
1836 azx_dev->insufficient = 0;
1837 }
1838
1839 if (link_pos <= fifo_size)
1840 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1841 else
1842 mini_pos = link_pos - fifo_size;
1843
1844 /* Find nearest previous boudary */
1845 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1846 mod_link_pos = link_pos % azx_dev->period_bytes;
1847 if (mod_link_pos >= fifo_size)
1848 bound_pos = link_pos - mod_link_pos;
1849 else if (mod_dma_pos >= mod_mini_pos)
1850 bound_pos = mini_pos - mod_mini_pos;
1851 else {
1852 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1853 if (bound_pos >= azx_dev->bufsize)
1854 bound_pos = 0;
1855 }
1856
1857 /* Calculate real DMA position we want */
1858 return bound_pos + mod_dma_pos;
1859 }
1860
1861 static unsigned int azx_get_position(struct azx *chip,
1862 struct azx_dev *azx_dev)
1863 {
1864 unsigned int pos;
1865 int stream = azx_dev->substream->stream;
1866
1867 switch (chip->position_fix[stream]) {
1868 case POS_FIX_LPIB:
1869 /* read LPIB */
1870 pos = azx_sd_readl(azx_dev, SD_LPIB);
1871 break;
1872 case POS_FIX_VIACOMBO:
1873 pos = azx_via_get_position(chip, azx_dev);
1874 break;
1875 default:
1876 /* use the position buffer */
1877 pos = le32_to_cpu(*azx_dev->posbuf);
1878 }
1879
1880 if (pos >= azx_dev->bufsize)
1881 pos = 0;
1882 return pos;
1883 }
1884
1885 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1886 {
1887 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1888 struct azx *chip = apcm->chip;
1889 struct azx_dev *azx_dev = get_azx_dev(substream);
1890 return bytes_to_frames(substream->runtime,
1891 azx_get_position(chip, azx_dev));
1892 }
1893
1894 /*
1895 * Check whether the current DMA position is acceptable for updating
1896 * periods. Returns non-zero if it's OK.
1897 *
1898 * Many HD-audio controllers appear pretty inaccurate about
1899 * the update-IRQ timing. The IRQ is issued before actually the
1900 * data is processed. So, we need to process it afterwords in a
1901 * workqueue.
1902 */
1903 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1904 {
1905 u32 wallclk;
1906 unsigned int pos;
1907 int stream;
1908
1909 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
1910 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
1911 return -1; /* bogus (too early) interrupt */
1912
1913 stream = azx_dev->substream->stream;
1914 pos = azx_get_position(chip, azx_dev);
1915 if (chip->position_fix[stream] == POS_FIX_AUTO) {
1916 if (!pos) {
1917 printk(KERN_WARNING
1918 "hda-intel: Invalid position buffer, "
1919 "using LPIB read method instead.\n");
1920 chip->position_fix[stream] = POS_FIX_LPIB;
1921 pos = azx_get_position(chip, azx_dev);
1922 } else
1923 chip->position_fix[stream] = POS_FIX_POSBUF;
1924 }
1925
1926 if (WARN_ONCE(!azx_dev->period_bytes,
1927 "hda-intel: zero azx_dev->period_bytes"))
1928 return -1; /* this shouldn't happen! */
1929 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
1930 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1931 /* NG - it's below the first next period boundary */
1932 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
1933 azx_dev->start_wallclk += wallclk;
1934 return 1; /* OK, it's fine */
1935 }
1936
1937 /*
1938 * The work for pending PCM period updates.
1939 */
1940 static void azx_irq_pending_work(struct work_struct *work)
1941 {
1942 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1943 int i, pending, ok;
1944
1945 if (!chip->irq_pending_warned) {
1946 printk(KERN_WARNING
1947 "hda-intel: IRQ timing workaround is activated "
1948 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1949 chip->card->number);
1950 chip->irq_pending_warned = 1;
1951 }
1952
1953 for (;;) {
1954 pending = 0;
1955 spin_lock_irq(&chip->reg_lock);
1956 for (i = 0; i < chip->num_streams; i++) {
1957 struct azx_dev *azx_dev = &chip->azx_dev[i];
1958 if (!azx_dev->irq_pending ||
1959 !azx_dev->substream ||
1960 !azx_dev->running)
1961 continue;
1962 ok = azx_position_ok(chip, azx_dev);
1963 if (ok > 0) {
1964 azx_dev->irq_pending = 0;
1965 spin_unlock(&chip->reg_lock);
1966 snd_pcm_period_elapsed(azx_dev->substream);
1967 spin_lock(&chip->reg_lock);
1968 } else if (ok < 0) {
1969 pending = 0; /* too early */
1970 } else
1971 pending++;
1972 }
1973 spin_unlock_irq(&chip->reg_lock);
1974 if (!pending)
1975 return;
1976 msleep(1);
1977 }
1978 }
1979
1980 /* clear irq_pending flags and assure no on-going workq */
1981 static void azx_clear_irq_pending(struct azx *chip)
1982 {
1983 int i;
1984
1985 spin_lock_irq(&chip->reg_lock);
1986 for (i = 0; i < chip->num_streams; i++)
1987 chip->azx_dev[i].irq_pending = 0;
1988 spin_unlock_irq(&chip->reg_lock);
1989 }
1990
1991 static struct snd_pcm_ops azx_pcm_ops = {
1992 .open = azx_pcm_open,
1993 .close = azx_pcm_close,
1994 .ioctl = snd_pcm_lib_ioctl,
1995 .hw_params = azx_pcm_hw_params,
1996 .hw_free = azx_pcm_hw_free,
1997 .prepare = azx_pcm_prepare,
1998 .trigger = azx_pcm_trigger,
1999 .pointer = azx_pcm_pointer,
2000 .page = snd_pcm_sgbuf_ops_page,
2001 };
2002
2003 static void azx_pcm_free(struct snd_pcm *pcm)
2004 {
2005 struct azx_pcm *apcm = pcm->private_data;
2006 if (apcm) {
2007 apcm->chip->pcm[pcm->device] = NULL;
2008 kfree(apcm);
2009 }
2010 }
2011
2012 static int
2013 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2014 struct hda_pcm *cpcm)
2015 {
2016 struct azx *chip = bus->private_data;
2017 struct snd_pcm *pcm;
2018 struct azx_pcm *apcm;
2019 int pcm_dev = cpcm->device;
2020 int s, err;
2021
2022 if (pcm_dev >= HDA_MAX_PCMS) {
2023 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
2024 pcm_dev);
2025 return -EINVAL;
2026 }
2027 if (chip->pcm[pcm_dev]) {
2028 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2029 return -EBUSY;
2030 }
2031 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2032 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2033 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2034 &pcm);
2035 if (err < 0)
2036 return err;
2037 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2038 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2039 if (apcm == NULL)
2040 return -ENOMEM;
2041 apcm->chip = chip;
2042 apcm->codec = codec;
2043 pcm->private_data = apcm;
2044 pcm->private_free = azx_pcm_free;
2045 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2046 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2047 chip->pcm[pcm_dev] = pcm;
2048 cpcm->pcm = pcm;
2049 for (s = 0; s < 2; s++) {
2050 apcm->hinfo[s] = &cpcm->stream[s];
2051 if (cpcm->stream[s].substreams)
2052 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2053 }
2054 /* buffer pre-allocation */
2055 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2056 snd_dma_pci_data(chip->pci),
2057 1024 * 64, 32 * 1024 * 1024);
2058 return 0;
2059 }
2060
2061 /*
2062 * mixer creation - all stuff is implemented in hda module
2063 */
2064 static int __devinit azx_mixer_create(struct azx *chip)
2065 {
2066 return snd_hda_build_controls(chip->bus);
2067 }
2068
2069
2070 /*
2071 * initialize SD streams
2072 */
2073 static int __devinit azx_init_stream(struct azx *chip)
2074 {
2075 int i;
2076
2077 /* initialize each stream (aka device)
2078 * assign the starting bdl address to each stream (device)
2079 * and initialize
2080 */
2081 for (i = 0; i < chip->num_streams; i++) {
2082 struct azx_dev *azx_dev = &chip->azx_dev[i];
2083 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2084 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2085 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2086 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2087 azx_dev->sd_int_sta_mask = 1 << i;
2088 /* stream tag: must be non-zero and unique */
2089 azx_dev->index = i;
2090 azx_dev->stream_tag = i + 1;
2091 }
2092
2093 return 0;
2094 }
2095
2096 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2097 {
2098 if (request_irq(chip->pci->irq, azx_interrupt,
2099 chip->msi ? 0 : IRQF_SHARED,
2100 "hda_intel", chip)) {
2101 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2102 "disabling device\n", chip->pci->irq);
2103 if (do_disconnect)
2104 snd_card_disconnect(chip->card);
2105 return -1;
2106 }
2107 chip->irq = chip->pci->irq;
2108 pci_intx(chip->pci, !chip->msi);
2109 return 0;
2110 }
2111
2112
2113 static void azx_stop_chip(struct azx *chip)
2114 {
2115 if (!chip->initialized)
2116 return;
2117
2118 /* disable interrupts */
2119 azx_int_disable(chip);
2120 azx_int_clear(chip);
2121
2122 /* disable CORB/RIRB */
2123 azx_free_cmd_io(chip);
2124
2125 /* disable position buffer */
2126 azx_writel(chip, DPLBASE, 0);
2127 azx_writel(chip, DPUBASE, 0);
2128
2129 chip->initialized = 0;
2130 }
2131
2132 #ifdef CONFIG_SND_HDA_POWER_SAVE
2133 /* power-up/down the controller */
2134 static void azx_power_notify(struct hda_bus *bus)
2135 {
2136 struct azx *chip = bus->private_data;
2137 struct hda_codec *c;
2138 int power_on = 0;
2139
2140 list_for_each_entry(c, &bus->codec_list, list) {
2141 if (c->power_on) {
2142 power_on = 1;
2143 break;
2144 }
2145 }
2146 if (power_on)
2147 azx_init_chip(chip, 1);
2148 else if (chip->running && power_save_controller &&
2149 !bus->power_keep_link_on)
2150 azx_stop_chip(chip);
2151 }
2152 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2153
2154 #ifdef CONFIG_PM
2155 /*
2156 * power management
2157 */
2158
2159 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2160 {
2161 struct hda_codec *codec;
2162
2163 list_for_each_entry(codec, &bus->codec_list, list) {
2164 if (snd_hda_codec_needs_resume(codec))
2165 return 1;
2166 }
2167 return 0;
2168 }
2169
2170 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2171 {
2172 struct snd_card *card = pci_get_drvdata(pci);
2173 struct azx *chip = card->private_data;
2174 int i;
2175
2176 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2177 azx_clear_irq_pending(chip);
2178 for (i = 0; i < HDA_MAX_PCMS; i++)
2179 snd_pcm_suspend_all(chip->pcm[i]);
2180 if (chip->initialized)
2181 snd_hda_suspend(chip->bus);
2182 azx_stop_chip(chip);
2183 if (chip->irq >= 0) {
2184 free_irq(chip->irq, chip);
2185 chip->irq = -1;
2186 }
2187 if (chip->msi)
2188 pci_disable_msi(chip->pci);
2189 pci_disable_device(pci);
2190 pci_save_state(pci);
2191 pci_set_power_state(pci, pci_choose_state(pci, state));
2192 return 0;
2193 }
2194
2195 static int azx_resume(struct pci_dev *pci)
2196 {
2197 struct snd_card *card = pci_get_drvdata(pci);
2198 struct azx *chip = card->private_data;
2199
2200 pci_set_power_state(pci, PCI_D0);
2201 pci_restore_state(pci);
2202 if (pci_enable_device(pci) < 0) {
2203 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2204 "disabling device\n");
2205 snd_card_disconnect(card);
2206 return -EIO;
2207 }
2208 pci_set_master(pci);
2209 if (chip->msi)
2210 if (pci_enable_msi(pci) < 0)
2211 chip->msi = 0;
2212 if (azx_acquire_irq(chip, 1) < 0)
2213 return -EIO;
2214 azx_init_pci(chip);
2215
2216 if (snd_hda_codecs_inuse(chip->bus))
2217 azx_init_chip(chip, 1);
2218
2219 snd_hda_resume(chip->bus);
2220 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2221 return 0;
2222 }
2223 #endif /* CONFIG_PM */
2224
2225
2226 /*
2227 * reboot notifier for hang-up problem at power-down
2228 */
2229 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2230 {
2231 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2232 snd_hda_bus_reboot_notify(chip->bus);
2233 azx_stop_chip(chip);
2234 return NOTIFY_OK;
2235 }
2236
2237 static void azx_notifier_register(struct azx *chip)
2238 {
2239 chip->reboot_notifier.notifier_call = azx_halt;
2240 register_reboot_notifier(&chip->reboot_notifier);
2241 }
2242
2243 static void azx_notifier_unregister(struct azx *chip)
2244 {
2245 if (chip->reboot_notifier.notifier_call)
2246 unregister_reboot_notifier(&chip->reboot_notifier);
2247 }
2248
2249 /*
2250 * destructor
2251 */
2252 static int azx_free(struct azx *chip)
2253 {
2254 int i;
2255
2256 azx_notifier_unregister(chip);
2257
2258 if (chip->initialized) {
2259 azx_clear_irq_pending(chip);
2260 for (i = 0; i < chip->num_streams; i++)
2261 azx_stream_stop(chip, &chip->azx_dev[i]);
2262 azx_stop_chip(chip);
2263 }
2264
2265 if (chip->irq >= 0)
2266 free_irq(chip->irq, (void*)chip);
2267 if (chip->msi)
2268 pci_disable_msi(chip->pci);
2269 if (chip->remap_addr)
2270 iounmap(chip->remap_addr);
2271
2272 if (chip->azx_dev) {
2273 for (i = 0; i < chip->num_streams; i++)
2274 if (chip->azx_dev[i].bdl.area)
2275 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2276 }
2277 if (chip->rb.area)
2278 snd_dma_free_pages(&chip->rb);
2279 if (chip->posbuf.area)
2280 snd_dma_free_pages(&chip->posbuf);
2281 pci_release_regions(chip->pci);
2282 pci_disable_device(chip->pci);
2283 kfree(chip->azx_dev);
2284 kfree(chip);
2285
2286 return 0;
2287 }
2288
2289 static int azx_dev_free(struct snd_device *device)
2290 {
2291 return azx_free(device->device_data);
2292 }
2293
2294 /*
2295 * white/black-listing for position_fix
2296 */
2297 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2298 SND_PCI_QUIRK(0x1025, 0x009f, "Acer Aspire 5110", POS_FIX_LPIB),
2299 SND_PCI_QUIRK(0x1025, 0x026f, "Acer Aspire 5538", POS_FIX_LPIB),
2300 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2301 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2302 SND_PCI_QUIRK(0x1028, 0x01f6, "Dell Latitude 131L", POS_FIX_LPIB),
2303 SND_PCI_QUIRK(0x1028, 0x0470, "Dell Inspiron 1120", POS_FIX_LPIB),
2304 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2305 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2306 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2307 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2308 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2309 SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
2310 SND_PCI_QUIRK(0x1179, 0xff10, "Toshiba A100-259", POS_FIX_LPIB),
2311 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2312 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2313 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2314 SND_PCI_QUIRK(0x1565, 0x820f, "Biostar Microtech", POS_FIX_LPIB),
2315 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2316 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2317 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2318 SND_PCI_QUIRK(0x8086, 0xd601, "eMachines T5212", POS_FIX_LPIB),
2319 {}
2320 };
2321
2322 static int __devinit check_position_fix(struct azx *chip, int fix)
2323 {
2324 const struct snd_pci_quirk *q;
2325
2326 switch (fix) {
2327 case POS_FIX_LPIB:
2328 case POS_FIX_POSBUF:
2329 case POS_FIX_VIACOMBO:
2330 return fix;
2331 }
2332
2333 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2334 if (q) {
2335 printk(KERN_INFO
2336 "hda_intel: position_fix set to %d "
2337 "for device %04x:%04x\n",
2338 q->value, q->subvendor, q->subdevice);
2339 return q->value;
2340 }
2341
2342 /* Check VIA/ATI HD Audio Controller exist */
2343 switch (chip->driver_type) {
2344 case AZX_DRIVER_VIA:
2345 case AZX_DRIVER_ATI:
2346 /* Use link position directly, avoid any transfer problem. */
2347 return POS_FIX_VIACOMBO;
2348 }
2349
2350 return POS_FIX_AUTO;
2351 }
2352
2353 /*
2354 * black-lists for probe_mask
2355 */
2356 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2357 /* Thinkpad often breaks the controller communication when accessing
2358 * to the non-working (or non-existing) modem codec slot.
2359 */
2360 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2361 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2362 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2363 /* broken BIOS */
2364 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2365 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2366 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2367 /* forced codec slots */
2368 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2369 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2370 {}
2371 };
2372
2373 #define AZX_FORCE_CODEC_MASK 0x100
2374
2375 static void __devinit check_probe_mask(struct azx *chip, int dev)
2376 {
2377 const struct snd_pci_quirk *q;
2378
2379 chip->codec_probe_mask = probe_mask[dev];
2380 if (chip->codec_probe_mask == -1) {
2381 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2382 if (q) {
2383 printk(KERN_INFO
2384 "hda_intel: probe_mask set to 0x%x "
2385 "for device %04x:%04x\n",
2386 q->value, q->subvendor, q->subdevice);
2387 chip->codec_probe_mask = q->value;
2388 }
2389 }
2390
2391 /* check forced option */
2392 if (chip->codec_probe_mask != -1 &&
2393 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2394 chip->codec_mask = chip->codec_probe_mask & 0xff;
2395 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2396 chip->codec_mask);
2397 }
2398 }
2399
2400 /*
2401 * white/black-list for enable_msi
2402 */
2403 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2404 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2405 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2406 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2407 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2408 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2409 {}
2410 };
2411
2412 static void __devinit check_msi(struct azx *chip)
2413 {
2414 const struct snd_pci_quirk *q;
2415
2416 if (enable_msi >= 0) {
2417 chip->msi = !!enable_msi;
2418 return;
2419 }
2420 chip->msi = 1; /* enable MSI as default */
2421 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2422 if (q) {
2423 printk(KERN_INFO
2424 "hda_intel: msi for device %04x:%04x set to %d\n",
2425 q->subvendor, q->subdevice, q->value);
2426 chip->msi = q->value;
2427 return;
2428 }
2429
2430 /* NVidia chipsets seem to cause troubles with MSI */
2431 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
2432 printk(KERN_INFO "hda_intel: Disable MSI for Nvidia chipset\n");
2433 chip->msi = 0;
2434 }
2435 }
2436
2437
2438 /*
2439 * constructor
2440 */
2441 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2442 int dev, int driver_type,
2443 struct azx **rchip)
2444 {
2445 struct azx *chip;
2446 int i, err;
2447 unsigned short gcap;
2448 static struct snd_device_ops ops = {
2449 .dev_free = azx_dev_free,
2450 };
2451
2452 *rchip = NULL;
2453
2454 err = pci_enable_device(pci);
2455 if (err < 0)
2456 return err;
2457
2458 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2459 if (!chip) {
2460 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2461 pci_disable_device(pci);
2462 return -ENOMEM;
2463 }
2464
2465 spin_lock_init(&chip->reg_lock);
2466 mutex_init(&chip->open_mutex);
2467 chip->card = card;
2468 chip->pci = pci;
2469 chip->irq = -1;
2470 chip->driver_type = driver_type;
2471 check_msi(chip);
2472 chip->dev_index = dev;
2473 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2474
2475 chip->position_fix[0] = chip->position_fix[1] =
2476 check_position_fix(chip, position_fix[dev]);
2477 check_probe_mask(chip, dev);
2478
2479 chip->single_cmd = single_cmd;
2480
2481 if (bdl_pos_adj[dev] < 0) {
2482 switch (chip->driver_type) {
2483 case AZX_DRIVER_ICH:
2484 case AZX_DRIVER_PCH:
2485 bdl_pos_adj[dev] = 1;
2486 break;
2487 default:
2488 bdl_pos_adj[dev] = 32;
2489 break;
2490 }
2491 }
2492
2493 #if BITS_PER_LONG != 64
2494 /* Fix up base address on ULI M5461 */
2495 if (chip->driver_type == AZX_DRIVER_ULI) {
2496 u16 tmp3;
2497 pci_read_config_word(pci, 0x40, &tmp3);
2498 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2499 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2500 }
2501 #endif
2502
2503 err = pci_request_regions(pci, "ICH HD audio");
2504 if (err < 0) {
2505 kfree(chip);
2506 pci_disable_device(pci);
2507 return err;
2508 }
2509
2510 chip->addr = pci_resource_start(pci, 0);
2511 chip->remap_addr = pci_ioremap_bar(pci, 0);
2512 if (chip->remap_addr == NULL) {
2513 snd_printk(KERN_ERR SFX "ioremap error\n");
2514 err = -ENXIO;
2515 goto errout;
2516 }
2517
2518 if (chip->msi)
2519 if (pci_enable_msi(pci) < 0)
2520 chip->msi = 0;
2521
2522 if (azx_acquire_irq(chip, 0) < 0) {
2523 err = -EBUSY;
2524 goto errout;
2525 }
2526
2527 pci_set_master(pci);
2528 synchronize_irq(chip->irq);
2529
2530 gcap = azx_readw(chip, GCAP);
2531 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2532
2533 /* disable SB600 64bit support for safety */
2534 if ((chip->driver_type == AZX_DRIVER_ATI) ||
2535 (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2536 struct pci_dev *p_smbus;
2537 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2538 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2539 NULL);
2540 if (p_smbus) {
2541 if (p_smbus->revision < 0x30)
2542 gcap &= ~ICH6_GCAP_64OK;
2543 pci_dev_put(p_smbus);
2544 }
2545 }
2546
2547 /* disable 64bit DMA address for Teradici */
2548 /* it does not work with device 6549:1200 subsys e4a2:040b */
2549 if (chip->driver_type == AZX_DRIVER_TERA)
2550 gcap &= ~ICH6_GCAP_64OK;
2551
2552 /* allow 64bit DMA address if supported by H/W */
2553 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2554 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2555 else {
2556 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2557 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2558 }
2559
2560 /* read number of streams from GCAP register instead of using
2561 * hardcoded value
2562 */
2563 chip->capture_streams = (gcap >> 8) & 0x0f;
2564 chip->playback_streams = (gcap >> 12) & 0x0f;
2565 if (!chip->playback_streams && !chip->capture_streams) {
2566 /* gcap didn't give any info, switching to old method */
2567
2568 switch (chip->driver_type) {
2569 case AZX_DRIVER_ULI:
2570 chip->playback_streams = ULI_NUM_PLAYBACK;
2571 chip->capture_streams = ULI_NUM_CAPTURE;
2572 break;
2573 case AZX_DRIVER_ATIHDMI:
2574 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2575 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2576 break;
2577 case AZX_DRIVER_GENERIC:
2578 default:
2579 chip->playback_streams = ICH6_NUM_PLAYBACK;
2580 chip->capture_streams = ICH6_NUM_CAPTURE;
2581 break;
2582 }
2583 }
2584 chip->capture_index_offset = 0;
2585 chip->playback_index_offset = chip->capture_streams;
2586 chip->num_streams = chip->playback_streams + chip->capture_streams;
2587 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2588 GFP_KERNEL);
2589 if (!chip->azx_dev) {
2590 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2591 goto errout;
2592 }
2593
2594 for (i = 0; i < chip->num_streams; i++) {
2595 /* allocate memory for the BDL for each stream */
2596 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2597 snd_dma_pci_data(chip->pci),
2598 BDL_SIZE, &chip->azx_dev[i].bdl);
2599 if (err < 0) {
2600 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2601 goto errout;
2602 }
2603 }
2604 /* allocate memory for the position buffer */
2605 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2606 snd_dma_pci_data(chip->pci),
2607 chip->num_streams * 8, &chip->posbuf);
2608 if (err < 0) {
2609 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2610 goto errout;
2611 }
2612 /* allocate CORB/RIRB */
2613 err = azx_alloc_cmd_io(chip);
2614 if (err < 0)
2615 goto errout;
2616
2617 /* initialize streams */
2618 azx_init_stream(chip);
2619
2620 /* initialize chip */
2621 azx_init_pci(chip);
2622 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2623
2624 /* codec detection */
2625 if (!chip->codec_mask) {
2626 snd_printk(KERN_ERR SFX "no codecs found!\n");
2627 err = -ENODEV;
2628 goto errout;
2629 }
2630
2631 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2632 if (err <0) {
2633 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2634 goto errout;
2635 }
2636
2637 strcpy(card->driver, "HDA-Intel");
2638 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2639 sizeof(card->shortname));
2640 snprintf(card->longname, sizeof(card->longname),
2641 "%s at 0x%lx irq %i",
2642 card->shortname, chip->addr, chip->irq);
2643
2644 *rchip = chip;
2645 return 0;
2646
2647 errout:
2648 azx_free(chip);
2649 return err;
2650 }
2651
2652 static void power_down_all_codecs(struct azx *chip)
2653 {
2654 #ifdef CONFIG_SND_HDA_POWER_SAVE
2655 /* The codecs were powered up in snd_hda_codec_new().
2656 * Now all initialization done, so turn them down if possible
2657 */
2658 struct hda_codec *codec;
2659 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2660 snd_hda_power_down(codec);
2661 }
2662 #endif
2663 }
2664
2665 static int __devinit azx_probe(struct pci_dev *pci,
2666 const struct pci_device_id *pci_id)
2667 {
2668 static int dev;
2669 struct snd_card *card;
2670 struct azx *chip;
2671 int err;
2672
2673 if (dev >= SNDRV_CARDS)
2674 return -ENODEV;
2675 if (!enable[dev]) {
2676 dev++;
2677 return -ENOENT;
2678 }
2679
2680 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2681 if (err < 0) {
2682 snd_printk(KERN_ERR SFX "Error creating card!\n");
2683 return err;
2684 }
2685
2686 /* set this here since it's referred in snd_hda_load_patch() */
2687 snd_card_set_dev(card, &pci->dev);
2688
2689 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2690 if (err < 0)
2691 goto out_free;
2692 card->private_data = chip;
2693
2694 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2695 chip->beep_mode = beep_mode[dev];
2696 #endif
2697
2698 /* create codec instances */
2699 err = azx_codec_create(chip, model[dev]);
2700 if (err < 0)
2701 goto out_free;
2702 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2703 if (patch[dev]) {
2704 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2705 patch[dev]);
2706 err = snd_hda_load_patch(chip->bus, patch[dev]);
2707 if (err < 0)
2708 goto out_free;
2709 }
2710 #endif
2711 if ((probe_only[dev] & 1) == 0) {
2712 err = azx_codec_configure(chip);
2713 if (err < 0)
2714 goto out_free;
2715 }
2716
2717 /* create PCM streams */
2718 err = snd_hda_build_pcms(chip->bus);
2719 if (err < 0)
2720 goto out_free;
2721
2722 /* create mixer controls */
2723 err = azx_mixer_create(chip);
2724 if (err < 0)
2725 goto out_free;
2726
2727 err = snd_card_register(card);
2728 if (err < 0)
2729 goto out_free;
2730
2731 pci_set_drvdata(pci, card);
2732 chip->running = 1;
2733 power_down_all_codecs(chip);
2734 azx_notifier_register(chip);
2735
2736 dev++;
2737 return err;
2738 out_free:
2739 snd_card_free(card);
2740 return err;
2741 }
2742
2743 static void __devexit azx_remove(struct pci_dev *pci)
2744 {
2745 snd_card_free(pci_get_drvdata(pci));
2746 pci_set_drvdata(pci, NULL);
2747 }
2748
2749 /* PCI IDs */
2750 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2751 /* CPT */
2752 { PCI_DEVICE(0x8086, 0x1c20), .driver_data = AZX_DRIVER_PCH },
2753 /* PBG */
2754 { PCI_DEVICE(0x8086, 0x1d20), .driver_data = AZX_DRIVER_PCH },
2755 /* SCH */
2756 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2757 /* Generic Intel */
2758 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2759 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2760 .class_mask = 0xffffff,
2761 .driver_data = AZX_DRIVER_ICH },
2762 /* ATI SB 450/600 */
2763 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2764 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2765 /* ATI HDMI */
2766 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2767 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2768 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2769 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2770 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2771 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2772 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2773 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2774 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2775 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2776 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2777 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2778 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2779 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2780 /* VIA VT8251/VT8237A */
2781 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2782 /* SIS966 */
2783 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2784 /* ULI M5461 */
2785 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2786 /* NVIDIA MCP */
2787 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2788 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2789 .class_mask = 0xffffff,
2790 .driver_data = AZX_DRIVER_NVIDIA },
2791 /* Teradici */
2792 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2793 /* Creative X-Fi (CA0110-IBG) */
2794 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2795 /* the following entry conflicts with snd-ctxfi driver,
2796 * as ctxfi driver mutates from HD-audio to native mode with
2797 * a special command sequence.
2798 */
2799 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2800 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2801 .class_mask = 0xffffff,
2802 .driver_data = AZX_DRIVER_CTX },
2803 #else
2804 /* this entry seems still valid -- i.e. without emu20kx chip */
2805 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_CTX },
2806 #endif
2807 /* Vortex86MX */
2808 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2809 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2810 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2811 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2812 .class_mask = 0xffffff,
2813 .driver_data = AZX_DRIVER_GENERIC },
2814 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2815 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2816 .class_mask = 0xffffff,
2817 .driver_data = AZX_DRIVER_GENERIC },
2818 { 0, }
2819 };
2820 MODULE_DEVICE_TABLE(pci, azx_ids);
2821
2822 /* pci_driver definition */
2823 static struct pci_driver driver = {
2824 .name = "HDA Intel",
2825 .id_table = azx_ids,
2826 .probe = azx_probe,
2827 .remove = __devexit_p(azx_remove),
2828 #ifdef CONFIG_PM
2829 .suspend = azx_suspend,
2830 .resume = azx_resume,
2831 #endif
2832 };
2833
2834 static int __init alsa_card_azx_init(void)
2835 {
2836 return pci_register_driver(&driver);
2837 }
2838
2839 static void __exit alsa_card_azx_exit(void)
2840 {
2841 pci_unregister_driver(&driver);
2842 }
2843
2844 module_init(alsa_card_azx_init)
2845 module_exit(alsa_card_azx_exit)
kernel source for telekom puls (alcatel/mediatek)