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Merge branch 'bind_unbind' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh...
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/io.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/clocksource.h>
50 #include <linux/time.h>
51 #include <linux/completion.h>
52
53 #ifdef CONFIG_X86
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/set_memory.h>
57 #include <asm/cpufeature.h>
58 #endif
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <sound/hdaudio.h>
62 #include <sound/hda_i915.h>
63 #include <linux/vgaarb.h>
64 #include <linux/vga_switcheroo.h>
65 #include <linux/firmware.h>
66 #include "hda_codec.h"
67 #include "hda_controller.h"
68 #include "hda_intel.h"
69
70 #define CREATE_TRACE_POINTS
71 #include "hda_intel_trace.h"
72
73 /* position fix mode */
74 enum {
75 POS_FIX_AUTO,
76 POS_FIX_LPIB,
77 POS_FIX_POSBUF,
78 POS_FIX_VIACOMBO,
79 POS_FIX_COMBO,
80 POS_FIX_SKL,
81 };
82
83 /* Defines for ATI HD Audio support in SB450 south bridge */
84 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
85 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
86
87 /* Defines for Nvidia HDA support */
88 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
89 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
90 #define NVIDIA_HDA_ISTRM_COH 0x4d
91 #define NVIDIA_HDA_OSTRM_COH 0x4c
92 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
93
94 /* Defines for Intel SCH HDA snoop control */
95 #define INTEL_HDA_CGCTL 0x48
96 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
97 #define INTEL_SCH_HDA_DEVC 0x78
98 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
99
100 /* Define IN stream 0 FIFO size offset in VIA controller */
101 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
102 /* Define VIA HD Audio Device ID*/
103 #define VIA_HDAC_DEVICE_ID 0x3288
104
105 /* max number of SDs */
106 /* ICH, ATI and VIA have 4 playback and 4 capture */
107 #define ICH6_NUM_CAPTURE 4
108 #define ICH6_NUM_PLAYBACK 4
109
110 /* ULI has 6 playback and 5 capture */
111 #define ULI_NUM_CAPTURE 5
112 #define ULI_NUM_PLAYBACK 6
113
114 /* ATI HDMI may have up to 8 playbacks and 0 capture */
115 #define ATIHDMI_NUM_CAPTURE 0
116 #define ATIHDMI_NUM_PLAYBACK 8
117
118 /* TERA has 4 playback and 3 capture */
119 #define TERA_NUM_CAPTURE 3
120 #define TERA_NUM_PLAYBACK 4
121
122
123 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
124 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
125 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
126 static char *model[SNDRV_CARDS];
127 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
128 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
129 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
130 static int probe_only[SNDRV_CARDS];
131 static int jackpoll_ms[SNDRV_CARDS];
132 static int single_cmd = -1;
133 static int enable_msi = -1;
134 #ifdef CONFIG_SND_HDA_PATCH_LOADER
135 static char *patch[SNDRV_CARDS];
136 #endif
137 #ifdef CONFIG_SND_HDA_INPUT_BEEP
138 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
139 CONFIG_SND_HDA_INPUT_BEEP_MODE};
140 #endif
141
142 module_param_array(index, int, NULL, 0444);
143 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
144 module_param_array(id, charp, NULL, 0444);
145 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
146 module_param_array(enable, bool, NULL, 0444);
147 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
148 module_param_array(model, charp, NULL, 0444);
149 MODULE_PARM_DESC(model, "Use the given board model.");
150 module_param_array(position_fix, int, NULL, 0444);
151 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
152 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
153 module_param_array(bdl_pos_adj, int, NULL, 0644);
154 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
155 module_param_array(probe_mask, int, NULL, 0444);
156 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
157 module_param_array(probe_only, int, NULL, 0444);
158 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
159 module_param_array(jackpoll_ms, int, NULL, 0444);
160 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
161 module_param(single_cmd, bint, 0444);
162 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
163 "(for debugging only).");
164 module_param(enable_msi, bint, 0444);
165 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
166 #ifdef CONFIG_SND_HDA_PATCH_LOADER
167 module_param_array(patch, charp, NULL, 0444);
168 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
169 #endif
170 #ifdef CONFIG_SND_HDA_INPUT_BEEP
171 module_param_array(beep_mode, bool, NULL, 0444);
172 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
173 "(0=off, 1=on) (default=1).");
174 #endif
175
176 #ifdef CONFIG_PM
177 static int param_set_xint(const char *val, const struct kernel_param *kp);
178 static const struct kernel_param_ops param_ops_xint = {
179 .set = param_set_xint,
180 .get = param_get_int,
181 };
182 #define param_check_xint param_check_int
183
184 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
185 module_param(power_save, xint, 0644);
186 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
187 "(in second, 0 = disable).");
188
189 /* reset the HD-audio controller in power save mode.
190 * this may give more power-saving, but will take longer time to
191 * wake up.
192 */
193 static bool power_save_controller = 1;
194 module_param(power_save_controller, bool, 0644);
195 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
196 #else
197 #define power_save 0
198 #endif /* CONFIG_PM */
199
200 static int align_buffer_size = -1;
201 module_param(align_buffer_size, bint, 0644);
202 MODULE_PARM_DESC(align_buffer_size,
203 "Force buffer and period sizes to be multiple of 128 bytes.");
204
205 #ifdef CONFIG_X86
206 static int hda_snoop = -1;
207 module_param_named(snoop, hda_snoop, bint, 0444);
208 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
209 #else
210 #define hda_snoop true
211 #endif
212
213
214 MODULE_LICENSE("GPL");
215 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
216 "{Intel, ICH6M},"
217 "{Intel, ICH7},"
218 "{Intel, ESB2},"
219 "{Intel, ICH8},"
220 "{Intel, ICH9},"
221 "{Intel, ICH10},"
222 "{Intel, PCH},"
223 "{Intel, CPT},"
224 "{Intel, PPT},"
225 "{Intel, LPT},"
226 "{Intel, LPT_LP},"
227 "{Intel, WPT_LP},"
228 "{Intel, SPT},"
229 "{Intel, SPT_LP},"
230 "{Intel, HPT},"
231 "{Intel, PBG},"
232 "{Intel, SCH},"
233 "{ATI, SB450},"
234 "{ATI, SB600},"
235 "{ATI, RS600},"
236 "{ATI, RS690},"
237 "{ATI, RS780},"
238 "{ATI, R600},"
239 "{ATI, RV630},"
240 "{ATI, RV610},"
241 "{ATI, RV670},"
242 "{ATI, RV635},"
243 "{ATI, RV620},"
244 "{ATI, RV770},"
245 "{VIA, VT8251},"
246 "{VIA, VT8237A},"
247 "{SiS, SIS966},"
248 "{ULI, M5461}}");
249 MODULE_DESCRIPTION("Intel HDA driver");
250
251 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
252 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
253 #define SUPPORT_VGA_SWITCHEROO
254 #endif
255 #endif
256
257
258 /*
259 */
260
261 /* driver types */
262 enum {
263 AZX_DRIVER_ICH,
264 AZX_DRIVER_PCH,
265 AZX_DRIVER_SCH,
266 AZX_DRIVER_HDMI,
267 AZX_DRIVER_ATI,
268 AZX_DRIVER_ATIHDMI,
269 AZX_DRIVER_ATIHDMI_NS,
270 AZX_DRIVER_VIA,
271 AZX_DRIVER_SIS,
272 AZX_DRIVER_ULI,
273 AZX_DRIVER_NVIDIA,
274 AZX_DRIVER_TERA,
275 AZX_DRIVER_CTX,
276 AZX_DRIVER_CTHDA,
277 AZX_DRIVER_CMEDIA,
278 AZX_DRIVER_GENERIC,
279 AZX_NUM_DRIVERS, /* keep this as last entry */
280 };
281
282 #define azx_get_snoop_type(chip) \
283 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
284 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
285
286 /* quirks for old Intel chipsets */
287 #define AZX_DCAPS_INTEL_ICH \
288 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
289
290 /* quirks for Intel PCH */
291 #define AZX_DCAPS_INTEL_PCH_BASE \
292 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
293 AZX_DCAPS_SNOOP_TYPE(SCH))
294
295 /* PCH up to IVB; no runtime PM */
296 #define AZX_DCAPS_INTEL_PCH_NOPM \
297 (AZX_DCAPS_INTEL_PCH_BASE)
298
299 /* PCH for HSW/BDW; with runtime PM */
300 #define AZX_DCAPS_INTEL_PCH \
301 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
302
303 /* HSW HDMI */
304 #define AZX_DCAPS_INTEL_HASWELL \
305 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
306 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
307 AZX_DCAPS_SNOOP_TYPE(SCH))
308
309 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
310 #define AZX_DCAPS_INTEL_BROADWELL \
311 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
312 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
313 AZX_DCAPS_SNOOP_TYPE(SCH))
314
315 #define AZX_DCAPS_INTEL_BAYTRAIL \
316 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
317
318 #define AZX_DCAPS_INTEL_BRASWELL \
319 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
320
321 #define AZX_DCAPS_INTEL_SKYLAKE \
322 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
323 AZX_DCAPS_I915_POWERWELL)
324
325 #define AZX_DCAPS_INTEL_BROXTON \
326 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
327 AZX_DCAPS_I915_POWERWELL)
328
329 /* quirks for ATI SB / AMD Hudson */
330 #define AZX_DCAPS_PRESET_ATI_SB \
331 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
332 AZX_DCAPS_SNOOP_TYPE(ATI))
333
334 /* quirks for ATI/AMD HDMI */
335 #define AZX_DCAPS_PRESET_ATI_HDMI \
336 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
337 AZX_DCAPS_NO_MSI64)
338
339 /* quirks for ATI HDMI with snoop off */
340 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
341 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
342
343 /* quirks for Nvidia */
344 #define AZX_DCAPS_PRESET_NVIDIA \
345 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
346 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
347
348 #define AZX_DCAPS_PRESET_CTHDA \
349 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
350 AZX_DCAPS_NO_64BIT |\
351 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
352
353 /*
354 * vga_switcheroo support
355 */
356 #ifdef SUPPORT_VGA_SWITCHEROO
357 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
358 #else
359 #define use_vga_switcheroo(chip) 0
360 #endif
361
362 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
363 ((pci)->device == 0x0c0c) || \
364 ((pci)->device == 0x0d0c) || \
365 ((pci)->device == 0x160c))
366
367 #define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
368 #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
369 #define IS_KBL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa171)
370 #define IS_KBL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d71)
371 #define IS_KBL_H(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa2f0)
372 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
373 #define IS_BXT_T(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x1a98)
374 #define IS_GLK(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x3198)
375 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
376 #define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci) || \
377 IS_BXT_T(pci) || IS_KBL(pci) || IS_KBL_LP(pci) || \
378 IS_KBL_H(pci) || IS_GLK(pci) || IS_CFL(pci))
379
380 static char *driver_short_names[] = {
381 [AZX_DRIVER_ICH] = "HDA Intel",
382 [AZX_DRIVER_PCH] = "HDA Intel PCH",
383 [AZX_DRIVER_SCH] = "HDA Intel MID",
384 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
385 [AZX_DRIVER_ATI] = "HDA ATI SB",
386 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
387 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
388 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
389 [AZX_DRIVER_SIS] = "HDA SIS966",
390 [AZX_DRIVER_ULI] = "HDA ULI M5461",
391 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
392 [AZX_DRIVER_TERA] = "HDA Teradici",
393 [AZX_DRIVER_CTX] = "HDA Creative",
394 [AZX_DRIVER_CTHDA] = "HDA Creative",
395 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
396 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
397 };
398
399 #ifdef CONFIG_X86
400 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
401 {
402 int pages;
403
404 if (azx_snoop(chip))
405 return;
406 if (!dmab || !dmab->area || !dmab->bytes)
407 return;
408
409 #ifdef CONFIG_SND_DMA_SGBUF
410 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
411 struct snd_sg_buf *sgbuf = dmab->private_data;
412 if (chip->driver_type == AZX_DRIVER_CMEDIA)
413 return; /* deal with only CORB/RIRB buffers */
414 if (on)
415 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
416 else
417 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
418 return;
419 }
420 #endif
421
422 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
423 if (on)
424 set_memory_wc((unsigned long)dmab->area, pages);
425 else
426 set_memory_wb((unsigned long)dmab->area, pages);
427 }
428
429 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
430 bool on)
431 {
432 __mark_pages_wc(chip, buf, on);
433 }
434 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
435 struct snd_pcm_substream *substream, bool on)
436 {
437 if (azx_dev->wc_marked != on) {
438 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
439 azx_dev->wc_marked = on;
440 }
441 }
442 #else
443 /* NOP for other archs */
444 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
445 bool on)
446 {
447 }
448 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
449 struct snd_pcm_substream *substream, bool on)
450 {
451 }
452 #endif
453
454 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
455
456 /*
457 * initialize the PCI registers
458 */
459 /* update bits in a PCI register byte */
460 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
461 unsigned char mask, unsigned char val)
462 {
463 unsigned char data;
464
465 pci_read_config_byte(pci, reg, &data);
466 data &= ~mask;
467 data |= (val & mask);
468 pci_write_config_byte(pci, reg, data);
469 }
470
471 static void azx_init_pci(struct azx *chip)
472 {
473 int snoop_type = azx_get_snoop_type(chip);
474
475 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
476 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
477 * Ensuring these bits are 0 clears playback static on some HD Audio
478 * codecs.
479 * The PCI register TCSEL is defined in the Intel manuals.
480 */
481 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
482 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
483 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
484 }
485
486 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
487 * we need to enable snoop.
488 */
489 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
490 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
491 azx_snoop(chip));
492 update_pci_byte(chip->pci,
493 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
494 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
495 }
496
497 /* For NVIDIA HDA, enable snoop */
498 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
499 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
500 azx_snoop(chip));
501 update_pci_byte(chip->pci,
502 NVIDIA_HDA_TRANSREG_ADDR,
503 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
504 update_pci_byte(chip->pci,
505 NVIDIA_HDA_ISTRM_COH,
506 0x01, NVIDIA_HDA_ENABLE_COHBIT);
507 update_pci_byte(chip->pci,
508 NVIDIA_HDA_OSTRM_COH,
509 0x01, NVIDIA_HDA_ENABLE_COHBIT);
510 }
511
512 /* Enable SCH/PCH snoop if needed */
513 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
514 unsigned short snoop;
515 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
516 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
517 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
518 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
519 if (!azx_snoop(chip))
520 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
521 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
522 pci_read_config_word(chip->pci,
523 INTEL_SCH_HDA_DEVC, &snoop);
524 }
525 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
526 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
527 "Disabled" : "Enabled");
528 }
529 }
530
531 /*
532 * In BXT-P A0, HD-Audio DMA requests is later than expected,
533 * and makes an audio stream sensitive to system latencies when
534 * 24/32 bits are playing.
535 * Adjusting threshold of DMA fifo to force the DMA request
536 * sooner to improve latency tolerance at the expense of power.
537 */
538 static void bxt_reduce_dma_latency(struct azx *chip)
539 {
540 u32 val;
541
542 val = azx_readl(chip, VS_EM4L);
543 val &= (0x3 << 20);
544 azx_writel(chip, VS_EM4L, val);
545 }
546
547 /*
548 * ML_LCAP bits:
549 * bit 0: 6 MHz Supported
550 * bit 1: 12 MHz Supported
551 * bit 2: 24 MHz Supported
552 * bit 3: 48 MHz Supported
553 * bit 4: 96 MHz Supported
554 * bit 5: 192 MHz Supported
555 */
556 static int intel_get_lctl_scf(struct azx *chip)
557 {
558 struct hdac_bus *bus = azx_bus(chip);
559 static int preferred_bits[] = { 2, 3, 1, 4, 5 };
560 u32 val, t;
561 int i;
562
563 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
564
565 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
566 t = preferred_bits[i];
567 if (val & (1 << t))
568 return t;
569 }
570
571 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
572 return 0;
573 }
574
575 static int intel_ml_lctl_set_power(struct azx *chip, int state)
576 {
577 struct hdac_bus *bus = azx_bus(chip);
578 u32 val;
579 int timeout;
580
581 /*
582 * the codecs are sharing the first link setting by default
583 * If other links are enabled for stream, they need similar fix
584 */
585 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
586 val &= ~AZX_MLCTL_SPA;
587 val |= state << AZX_MLCTL_SPA_SHIFT;
588 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
589 /* wait for CPA */
590 timeout = 50;
591 while (timeout) {
592 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
593 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
594 return 0;
595 timeout--;
596 udelay(10);
597 }
598
599 return -1;
600 }
601
602 static void intel_init_lctl(struct azx *chip)
603 {
604 struct hdac_bus *bus = azx_bus(chip);
605 u32 val;
606 int ret;
607
608 /* 0. check lctl register value is correct or not */
609 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
610 /* if SCF is already set, let's use it */
611 if ((val & ML_LCTL_SCF_MASK) != 0)
612 return;
613
614 /*
615 * Before operating on SPA, CPA must match SPA.
616 * Any deviation may result in undefined behavior.
617 */
618 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
619 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
620 return;
621
622 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
623 ret = intel_ml_lctl_set_power(chip, 0);
624 udelay(100);
625 if (ret)
626 goto set_spa;
627
628 /* 2. update SCF to select a properly audio clock*/
629 val &= ~ML_LCTL_SCF_MASK;
630 val |= intel_get_lctl_scf(chip);
631 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
632
633 set_spa:
634 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
635 intel_ml_lctl_set_power(chip, 1);
636 udelay(100);
637 }
638
639 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
640 {
641 struct hdac_bus *bus = azx_bus(chip);
642 struct pci_dev *pci = chip->pci;
643 u32 val;
644
645 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
646 snd_hdac_set_codec_wakeup(bus, true);
647 if (IS_SKL_PLUS(pci)) {
648 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
649 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
650 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
651 }
652 azx_init_chip(chip, full_reset);
653 if (IS_SKL_PLUS(pci)) {
654 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
655 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
656 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
657 }
658 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
659 snd_hdac_set_codec_wakeup(bus, false);
660
661 /* reduce dma latency to avoid noise */
662 if (IS_BXT(pci))
663 bxt_reduce_dma_latency(chip);
664
665 if (bus->mlcap != NULL)
666 intel_init_lctl(chip);
667 }
668
669 /* calculate runtime delay from LPIB */
670 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
671 unsigned int pos)
672 {
673 struct snd_pcm_substream *substream = azx_dev->core.substream;
674 int stream = substream->stream;
675 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
676 int delay;
677
678 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
679 delay = pos - lpib_pos;
680 else
681 delay = lpib_pos - pos;
682 if (delay < 0) {
683 if (delay >= azx_dev->core.delay_negative_threshold)
684 delay = 0;
685 else
686 delay += azx_dev->core.bufsize;
687 }
688
689 if (delay >= azx_dev->core.period_bytes) {
690 dev_info(chip->card->dev,
691 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
692 delay, azx_dev->core.period_bytes);
693 delay = 0;
694 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
695 chip->get_delay[stream] = NULL;
696 }
697
698 return bytes_to_frames(substream->runtime, delay);
699 }
700
701 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
702
703 /* called from IRQ */
704 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
705 {
706 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
707 int ok;
708
709 ok = azx_position_ok(chip, azx_dev);
710 if (ok == 1) {
711 azx_dev->irq_pending = 0;
712 return ok;
713 } else if (ok == 0) {
714 /* bogus IRQ, process it later */
715 azx_dev->irq_pending = 1;
716 schedule_work(&hda->irq_pending_work);
717 }
718 return 0;
719 }
720
721 /* Enable/disable i915 display power for the link */
722 static int azx_intel_link_power(struct azx *chip, bool enable)
723 {
724 struct hdac_bus *bus = azx_bus(chip);
725
726 return snd_hdac_display_power(bus, enable);
727 }
728
729 /*
730 * Check whether the current DMA position is acceptable for updating
731 * periods. Returns non-zero if it's OK.
732 *
733 * Many HD-audio controllers appear pretty inaccurate about
734 * the update-IRQ timing. The IRQ is issued before actually the
735 * data is processed. So, we need to process it afterwords in a
736 * workqueue.
737 */
738 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
739 {
740 struct snd_pcm_substream *substream = azx_dev->core.substream;
741 int stream = substream->stream;
742 u32 wallclk;
743 unsigned int pos;
744
745 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
746 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
747 return -1; /* bogus (too early) interrupt */
748
749 if (chip->get_position[stream])
750 pos = chip->get_position[stream](chip, azx_dev);
751 else { /* use the position buffer as default */
752 pos = azx_get_pos_posbuf(chip, azx_dev);
753 if (!pos || pos == (u32)-1) {
754 dev_info(chip->card->dev,
755 "Invalid position buffer, using LPIB read method instead.\n");
756 chip->get_position[stream] = azx_get_pos_lpib;
757 if (chip->get_position[0] == azx_get_pos_lpib &&
758 chip->get_position[1] == azx_get_pos_lpib)
759 azx_bus(chip)->use_posbuf = false;
760 pos = azx_get_pos_lpib(chip, azx_dev);
761 chip->get_delay[stream] = NULL;
762 } else {
763 chip->get_position[stream] = azx_get_pos_posbuf;
764 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
765 chip->get_delay[stream] = azx_get_delay_from_lpib;
766 }
767 }
768
769 if (pos >= azx_dev->core.bufsize)
770 pos = 0;
771
772 if (WARN_ONCE(!azx_dev->core.period_bytes,
773 "hda-intel: zero azx_dev->period_bytes"))
774 return -1; /* this shouldn't happen! */
775 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
776 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
777 /* NG - it's below the first next period boundary */
778 return chip->bdl_pos_adj ? 0 : -1;
779 azx_dev->core.start_wallclk += wallclk;
780 return 1; /* OK, it's fine */
781 }
782
783 /*
784 * The work for pending PCM period updates.
785 */
786 static void azx_irq_pending_work(struct work_struct *work)
787 {
788 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
789 struct azx *chip = &hda->chip;
790 struct hdac_bus *bus = azx_bus(chip);
791 struct hdac_stream *s;
792 int pending, ok;
793
794 if (!hda->irq_pending_warned) {
795 dev_info(chip->card->dev,
796 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
797 chip->card->number);
798 hda->irq_pending_warned = 1;
799 }
800
801 for (;;) {
802 pending = 0;
803 spin_lock_irq(&bus->reg_lock);
804 list_for_each_entry(s, &bus->stream_list, list) {
805 struct azx_dev *azx_dev = stream_to_azx_dev(s);
806 if (!azx_dev->irq_pending ||
807 !s->substream ||
808 !s->running)
809 continue;
810 ok = azx_position_ok(chip, azx_dev);
811 if (ok > 0) {
812 azx_dev->irq_pending = 0;
813 spin_unlock(&bus->reg_lock);
814 snd_pcm_period_elapsed(s->substream);
815 spin_lock(&bus->reg_lock);
816 } else if (ok < 0) {
817 pending = 0; /* too early */
818 } else
819 pending++;
820 }
821 spin_unlock_irq(&bus->reg_lock);
822 if (!pending)
823 return;
824 msleep(1);
825 }
826 }
827
828 /* clear irq_pending flags and assure no on-going workq */
829 static void azx_clear_irq_pending(struct azx *chip)
830 {
831 struct hdac_bus *bus = azx_bus(chip);
832 struct hdac_stream *s;
833
834 spin_lock_irq(&bus->reg_lock);
835 list_for_each_entry(s, &bus->stream_list, list) {
836 struct azx_dev *azx_dev = stream_to_azx_dev(s);
837 azx_dev->irq_pending = 0;
838 }
839 spin_unlock_irq(&bus->reg_lock);
840 }
841
842 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
843 {
844 struct hdac_bus *bus = azx_bus(chip);
845
846 if (request_irq(chip->pci->irq, azx_interrupt,
847 chip->msi ? 0 : IRQF_SHARED,
848 chip->card->irq_descr, chip)) {
849 dev_err(chip->card->dev,
850 "unable to grab IRQ %d, disabling device\n",
851 chip->pci->irq);
852 if (do_disconnect)
853 snd_card_disconnect(chip->card);
854 return -1;
855 }
856 bus->irq = chip->pci->irq;
857 pci_intx(chip->pci, !chip->msi);
858 return 0;
859 }
860
861 /* get the current DMA position with correction on VIA chips */
862 static unsigned int azx_via_get_position(struct azx *chip,
863 struct azx_dev *azx_dev)
864 {
865 unsigned int link_pos, mini_pos, bound_pos;
866 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
867 unsigned int fifo_size;
868
869 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
870 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
871 /* Playback, no problem using link position */
872 return link_pos;
873 }
874
875 /* Capture */
876 /* For new chipset,
877 * use mod to get the DMA position just like old chipset
878 */
879 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
880 mod_dma_pos %= azx_dev->core.period_bytes;
881
882 /* azx_dev->fifo_size can't get FIFO size of in stream.
883 * Get from base address + offset.
884 */
885 fifo_size = readw(azx_bus(chip)->remap_addr +
886 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
887
888 if (azx_dev->insufficient) {
889 /* Link position never gather than FIFO size */
890 if (link_pos <= fifo_size)
891 return 0;
892
893 azx_dev->insufficient = 0;
894 }
895
896 if (link_pos <= fifo_size)
897 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
898 else
899 mini_pos = link_pos - fifo_size;
900
901 /* Find nearest previous boudary */
902 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
903 mod_link_pos = link_pos % azx_dev->core.period_bytes;
904 if (mod_link_pos >= fifo_size)
905 bound_pos = link_pos - mod_link_pos;
906 else if (mod_dma_pos >= mod_mini_pos)
907 bound_pos = mini_pos - mod_mini_pos;
908 else {
909 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
910 if (bound_pos >= azx_dev->core.bufsize)
911 bound_pos = 0;
912 }
913
914 /* Calculate real DMA position we want */
915 return bound_pos + mod_dma_pos;
916 }
917
918 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
919 struct azx_dev *azx_dev)
920 {
921 return _snd_hdac_chip_readl(azx_bus(chip),
922 AZX_REG_VS_SDXDPIB_XBASE +
923 (AZX_REG_VS_SDXDPIB_XINTERVAL *
924 azx_dev->core.index));
925 }
926
927 /* get the current DMA position with correction on SKL+ chips */
928 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
929 {
930 /* DPIB register gives a more accurate position for playback */
931 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
932 return azx_skl_get_dpib_pos(chip, azx_dev);
933
934 /* For capture, we need to read posbuf, but it requires a delay
935 * for the possible boundary overlap; the read of DPIB fetches the
936 * actual posbuf
937 */
938 udelay(20);
939 azx_skl_get_dpib_pos(chip, azx_dev);
940 return azx_get_pos_posbuf(chip, azx_dev);
941 }
942
943 #ifdef CONFIG_PM
944 static DEFINE_MUTEX(card_list_lock);
945 static LIST_HEAD(card_list);
946
947 static void azx_add_card_list(struct azx *chip)
948 {
949 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
950 mutex_lock(&card_list_lock);
951 list_add(&hda->list, &card_list);
952 mutex_unlock(&card_list_lock);
953 }
954
955 static void azx_del_card_list(struct azx *chip)
956 {
957 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
958 mutex_lock(&card_list_lock);
959 list_del_init(&hda->list);
960 mutex_unlock(&card_list_lock);
961 }
962
963 /* trigger power-save check at writing parameter */
964 static int param_set_xint(const char *val, const struct kernel_param *kp)
965 {
966 struct hda_intel *hda;
967 struct azx *chip;
968 int prev = power_save;
969 int ret = param_set_int(val, kp);
970
971 if (ret || prev == power_save)
972 return ret;
973
974 mutex_lock(&card_list_lock);
975 list_for_each_entry(hda, &card_list, list) {
976 chip = &hda->chip;
977 if (!hda->probe_continued || chip->disabled)
978 continue;
979 snd_hda_set_power_save(&chip->bus, power_save * 1000);
980 }
981 mutex_unlock(&card_list_lock);
982 return 0;
983 }
984 #else
985 #define azx_add_card_list(chip) /* NOP */
986 #define azx_del_card_list(chip) /* NOP */
987 #endif /* CONFIG_PM */
988
989 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
990 /*
991 * power management
992 */
993 static int azx_suspend(struct device *dev)
994 {
995 struct snd_card *card = dev_get_drvdata(dev);
996 struct azx *chip;
997 struct hda_intel *hda;
998 struct hdac_bus *bus;
999
1000 if (!card)
1001 return 0;
1002
1003 chip = card->private_data;
1004 hda = container_of(chip, struct hda_intel, chip);
1005 if (chip->disabled || hda->init_failed || !chip->running)
1006 return 0;
1007
1008 bus = azx_bus(chip);
1009 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1010 azx_clear_irq_pending(chip);
1011 azx_stop_chip(chip);
1012 azx_enter_link_reset(chip);
1013 if (bus->irq >= 0) {
1014 free_irq(bus->irq, chip);
1015 bus->irq = -1;
1016 }
1017
1018 if (chip->msi)
1019 pci_disable_msi(chip->pci);
1020 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1021 && hda->need_i915_power)
1022 snd_hdac_display_power(bus, false);
1023
1024 trace_azx_suspend(chip);
1025 return 0;
1026 }
1027
1028 static int azx_resume(struct device *dev)
1029 {
1030 struct pci_dev *pci = to_pci_dev(dev);
1031 struct snd_card *card = dev_get_drvdata(dev);
1032 struct azx *chip;
1033 struct hda_intel *hda;
1034 struct hdac_bus *bus;
1035
1036 if (!card)
1037 return 0;
1038
1039 chip = card->private_data;
1040 hda = container_of(chip, struct hda_intel, chip);
1041 bus = azx_bus(chip);
1042 if (chip->disabled || hda->init_failed || !chip->running)
1043 return 0;
1044
1045 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1046 snd_hdac_display_power(bus, true);
1047 if (hda->need_i915_power)
1048 snd_hdac_i915_set_bclk(bus);
1049 }
1050
1051 if (chip->msi)
1052 if (pci_enable_msi(pci) < 0)
1053 chip->msi = 0;
1054 if (azx_acquire_irq(chip, 1) < 0)
1055 return -EIO;
1056 azx_init_pci(chip);
1057
1058 hda_intel_init_chip(chip, true);
1059
1060 /* power down again for link-controlled chips */
1061 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1062 !hda->need_i915_power)
1063 snd_hdac_display_power(bus, false);
1064
1065 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1066
1067 trace_azx_resume(chip);
1068 return 0;
1069 }
1070 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
1071
1072 #ifdef CONFIG_PM_SLEEP
1073 /* put codec down to D3 at hibernation for Intel SKL+;
1074 * otherwise BIOS may still access the codec and screw up the driver
1075 */
1076 static int azx_freeze_noirq(struct device *dev)
1077 {
1078 struct pci_dev *pci = to_pci_dev(dev);
1079
1080 if (IS_SKL_PLUS(pci))
1081 pci_set_power_state(pci, PCI_D3hot);
1082
1083 return 0;
1084 }
1085
1086 static int azx_thaw_noirq(struct device *dev)
1087 {
1088 struct pci_dev *pci = to_pci_dev(dev);
1089
1090 if (IS_SKL_PLUS(pci))
1091 pci_set_power_state(pci, PCI_D0);
1092
1093 return 0;
1094 }
1095 #endif /* CONFIG_PM_SLEEP */
1096
1097 #ifdef CONFIG_PM
1098 static int azx_runtime_suspend(struct device *dev)
1099 {
1100 struct snd_card *card = dev_get_drvdata(dev);
1101 struct azx *chip;
1102 struct hda_intel *hda;
1103
1104 if (!card)
1105 return 0;
1106
1107 chip = card->private_data;
1108 hda = container_of(chip, struct hda_intel, chip);
1109 if (chip->disabled || hda->init_failed)
1110 return 0;
1111
1112 if (!azx_has_pm_runtime(chip))
1113 return 0;
1114
1115 /* enable controller wake up event */
1116 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1117 STATESTS_INT_MASK);
1118
1119 azx_stop_chip(chip);
1120 azx_enter_link_reset(chip);
1121 azx_clear_irq_pending(chip);
1122 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1123 && hda->need_i915_power)
1124 snd_hdac_display_power(azx_bus(chip), false);
1125
1126 trace_azx_runtime_suspend(chip);
1127 return 0;
1128 }
1129
1130 static int azx_runtime_resume(struct device *dev)
1131 {
1132 struct snd_card *card = dev_get_drvdata(dev);
1133 struct azx *chip;
1134 struct hda_intel *hda;
1135 struct hdac_bus *bus;
1136 struct hda_codec *codec;
1137 int status;
1138
1139 if (!card)
1140 return 0;
1141
1142 chip = card->private_data;
1143 hda = container_of(chip, struct hda_intel, chip);
1144 bus = azx_bus(chip);
1145 if (chip->disabled || hda->init_failed)
1146 return 0;
1147
1148 if (!azx_has_pm_runtime(chip))
1149 return 0;
1150
1151 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1152 snd_hdac_display_power(bus, true);
1153 if (hda->need_i915_power)
1154 snd_hdac_i915_set_bclk(bus);
1155 }
1156
1157 /* Read STATESTS before controller reset */
1158 status = azx_readw(chip, STATESTS);
1159
1160 azx_init_pci(chip);
1161 hda_intel_init_chip(chip, true);
1162
1163 if (status) {
1164 list_for_each_codec(codec, &chip->bus)
1165 if (status & (1 << codec->addr))
1166 schedule_delayed_work(&codec->jackpoll_work,
1167 codec->jackpoll_interval);
1168 }
1169
1170 /* disable controller Wake Up event*/
1171 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1172 ~STATESTS_INT_MASK);
1173
1174 /* power down again for link-controlled chips */
1175 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1176 !hda->need_i915_power)
1177 snd_hdac_display_power(bus, false);
1178
1179 trace_azx_runtime_resume(chip);
1180 return 0;
1181 }
1182
1183 static int azx_runtime_idle(struct device *dev)
1184 {
1185 struct snd_card *card = dev_get_drvdata(dev);
1186 struct azx *chip;
1187 struct hda_intel *hda;
1188
1189 if (!card)
1190 return 0;
1191
1192 chip = card->private_data;
1193 hda = container_of(chip, struct hda_intel, chip);
1194 if (chip->disabled || hda->init_failed)
1195 return 0;
1196
1197 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1198 azx_bus(chip)->codec_powered || !chip->running)
1199 return -EBUSY;
1200
1201 return 0;
1202 }
1203
1204 static const struct dev_pm_ops azx_pm = {
1205 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1206 #ifdef CONFIG_PM_SLEEP
1207 .freeze_noirq = azx_freeze_noirq,
1208 .thaw_noirq = azx_thaw_noirq,
1209 #endif
1210 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1211 };
1212
1213 #define AZX_PM_OPS &azx_pm
1214 #else
1215 #define AZX_PM_OPS NULL
1216 #endif /* CONFIG_PM */
1217
1218
1219 static int azx_probe_continue(struct azx *chip);
1220
1221 #ifdef SUPPORT_VGA_SWITCHEROO
1222 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1223
1224 static void azx_vs_set_state(struct pci_dev *pci,
1225 enum vga_switcheroo_state state)
1226 {
1227 struct snd_card *card = pci_get_drvdata(pci);
1228 struct azx *chip = card->private_data;
1229 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1230 bool disabled;
1231
1232 wait_for_completion(&hda->probe_wait);
1233 if (hda->init_failed)
1234 return;
1235
1236 disabled = (state == VGA_SWITCHEROO_OFF);
1237 if (chip->disabled == disabled)
1238 return;
1239
1240 if (!hda->probe_continued) {
1241 chip->disabled = disabled;
1242 if (!disabled) {
1243 dev_info(chip->card->dev,
1244 "Start delayed initialization\n");
1245 if (azx_probe_continue(chip) < 0) {
1246 dev_err(chip->card->dev, "initialization error\n");
1247 hda->init_failed = true;
1248 }
1249 }
1250 } else {
1251 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1252 disabled ? "Disabling" : "Enabling");
1253 if (disabled) {
1254 pm_runtime_put_sync_suspend(card->dev);
1255 azx_suspend(card->dev);
1256 /* when we get suspended by vga_switcheroo we end up in D3cold,
1257 * however we have no ACPI handle, so pci/acpi can't put us there,
1258 * put ourselves there */
1259 pci->current_state = PCI_D3cold;
1260 chip->disabled = true;
1261 if (snd_hda_lock_devices(&chip->bus))
1262 dev_warn(chip->card->dev,
1263 "Cannot lock devices!\n");
1264 } else {
1265 snd_hda_unlock_devices(&chip->bus);
1266 pm_runtime_get_noresume(card->dev);
1267 chip->disabled = false;
1268 azx_resume(card->dev);
1269 }
1270 }
1271 }
1272
1273 static bool azx_vs_can_switch(struct pci_dev *pci)
1274 {
1275 struct snd_card *card = pci_get_drvdata(pci);
1276 struct azx *chip = card->private_data;
1277 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1278
1279 wait_for_completion(&hda->probe_wait);
1280 if (hda->init_failed)
1281 return false;
1282 if (chip->disabled || !hda->probe_continued)
1283 return true;
1284 if (snd_hda_lock_devices(&chip->bus))
1285 return false;
1286 snd_hda_unlock_devices(&chip->bus);
1287 return true;
1288 }
1289
1290 static void init_vga_switcheroo(struct azx *chip)
1291 {
1292 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1293 struct pci_dev *p = get_bound_vga(chip->pci);
1294 if (p) {
1295 dev_info(chip->card->dev,
1296 "Handle vga_switcheroo audio client\n");
1297 hda->use_vga_switcheroo = 1;
1298 pci_dev_put(p);
1299 }
1300 }
1301
1302 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1303 .set_gpu_state = azx_vs_set_state,
1304 .can_switch = azx_vs_can_switch,
1305 };
1306
1307 static int register_vga_switcheroo(struct azx *chip)
1308 {
1309 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1310 int err;
1311
1312 if (!hda->use_vga_switcheroo)
1313 return 0;
1314 /* FIXME: currently only handling DIS controller
1315 * is there any machine with two switchable HDMI audio controllers?
1316 */
1317 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1318 VGA_SWITCHEROO_DIS);
1319 if (err < 0)
1320 return err;
1321 hda->vga_switcheroo_registered = 1;
1322
1323 /* register as an optimus hdmi audio power domain */
1324 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1325 &hda->hdmi_pm_domain);
1326 return 0;
1327 }
1328 #else
1329 #define init_vga_switcheroo(chip) /* NOP */
1330 #define register_vga_switcheroo(chip) 0
1331 #define check_hdmi_disabled(pci) false
1332 #endif /* SUPPORT_VGA_SWITCHER */
1333
1334 /*
1335 * destructor
1336 */
1337 static int azx_free(struct azx *chip)
1338 {
1339 struct pci_dev *pci = chip->pci;
1340 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1341 struct hdac_bus *bus = azx_bus(chip);
1342
1343 if (azx_has_pm_runtime(chip) && chip->running)
1344 pm_runtime_get_noresume(&pci->dev);
1345
1346 azx_del_card_list(chip);
1347
1348 hda->init_failed = 1; /* to be sure */
1349 complete_all(&hda->probe_wait);
1350
1351 if (use_vga_switcheroo(hda)) {
1352 if (chip->disabled && hda->probe_continued)
1353 snd_hda_unlock_devices(&chip->bus);
1354 if (hda->vga_switcheroo_registered) {
1355 vga_switcheroo_unregister_client(chip->pci);
1356 vga_switcheroo_fini_domain_pm_ops(chip->card->dev);
1357 }
1358 }
1359
1360 if (bus->chip_init) {
1361 azx_clear_irq_pending(chip);
1362 azx_stop_all_streams(chip);
1363 azx_stop_chip(chip);
1364 }
1365
1366 if (bus->irq >= 0)
1367 free_irq(bus->irq, (void*)chip);
1368 if (chip->msi)
1369 pci_disable_msi(chip->pci);
1370 iounmap(bus->remap_addr);
1371
1372 azx_free_stream_pages(chip);
1373 azx_free_streams(chip);
1374 snd_hdac_bus_exit(bus);
1375
1376 if (chip->region_requested)
1377 pci_release_regions(chip->pci);
1378
1379 pci_disable_device(chip->pci);
1380 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1381 release_firmware(chip->fw);
1382 #endif
1383
1384 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1385 if (hda->need_i915_power)
1386 snd_hdac_display_power(bus, false);
1387 snd_hdac_i915_exit(bus);
1388 }
1389 kfree(hda);
1390
1391 return 0;
1392 }
1393
1394 static int azx_dev_disconnect(struct snd_device *device)
1395 {
1396 struct azx *chip = device->device_data;
1397
1398 chip->bus.shutdown = 1;
1399 return 0;
1400 }
1401
1402 static int azx_dev_free(struct snd_device *device)
1403 {
1404 return azx_free(device->device_data);
1405 }
1406
1407 #ifdef SUPPORT_VGA_SWITCHEROO
1408 /*
1409 * Check of disabled HDMI controller by vga_switcheroo
1410 */
1411 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1412 {
1413 struct pci_dev *p;
1414
1415 /* check only discrete GPU */
1416 switch (pci->vendor) {
1417 case PCI_VENDOR_ID_ATI:
1418 case PCI_VENDOR_ID_AMD:
1419 case PCI_VENDOR_ID_NVIDIA:
1420 if (pci->devfn == 1) {
1421 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1422 pci->bus->number, 0);
1423 if (p) {
1424 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1425 return p;
1426 pci_dev_put(p);
1427 }
1428 }
1429 break;
1430 }
1431 return NULL;
1432 }
1433
1434 static bool check_hdmi_disabled(struct pci_dev *pci)
1435 {
1436 bool vga_inactive = false;
1437 struct pci_dev *p = get_bound_vga(pci);
1438
1439 if (p) {
1440 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1441 vga_inactive = true;
1442 pci_dev_put(p);
1443 }
1444 return vga_inactive;
1445 }
1446 #endif /* SUPPORT_VGA_SWITCHEROO */
1447
1448 /*
1449 * white/black-listing for position_fix
1450 */
1451 static struct snd_pci_quirk position_fix_list[] = {
1452 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1453 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1454 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1455 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1456 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1457 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1458 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1459 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1460 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1461 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1462 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1463 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1464 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1465 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1466 {}
1467 };
1468
1469 static int check_position_fix(struct azx *chip, int fix)
1470 {
1471 const struct snd_pci_quirk *q;
1472
1473 switch (fix) {
1474 case POS_FIX_AUTO:
1475 case POS_FIX_LPIB:
1476 case POS_FIX_POSBUF:
1477 case POS_FIX_VIACOMBO:
1478 case POS_FIX_COMBO:
1479 case POS_FIX_SKL:
1480 return fix;
1481 }
1482
1483 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1484 if (q) {
1485 dev_info(chip->card->dev,
1486 "position_fix set to %d for device %04x:%04x\n",
1487 q->value, q->subvendor, q->subdevice);
1488 return q->value;
1489 }
1490
1491 /* Check VIA/ATI HD Audio Controller exist */
1492 if (chip->driver_type == AZX_DRIVER_VIA) {
1493 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1494 return POS_FIX_VIACOMBO;
1495 }
1496 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1497 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1498 return POS_FIX_LPIB;
1499 }
1500 if (IS_SKL_PLUS(chip->pci)) {
1501 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1502 return POS_FIX_SKL;
1503 }
1504 return POS_FIX_AUTO;
1505 }
1506
1507 static void assign_position_fix(struct azx *chip, int fix)
1508 {
1509 static azx_get_pos_callback_t callbacks[] = {
1510 [POS_FIX_AUTO] = NULL,
1511 [POS_FIX_LPIB] = azx_get_pos_lpib,
1512 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1513 [POS_FIX_VIACOMBO] = azx_via_get_position,
1514 [POS_FIX_COMBO] = azx_get_pos_lpib,
1515 [POS_FIX_SKL] = azx_get_pos_skl,
1516 };
1517
1518 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1519
1520 /* combo mode uses LPIB only for playback */
1521 if (fix == POS_FIX_COMBO)
1522 chip->get_position[1] = NULL;
1523
1524 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1525 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1526 chip->get_delay[0] = chip->get_delay[1] =
1527 azx_get_delay_from_lpib;
1528 }
1529
1530 }
1531
1532 /*
1533 * black-lists for probe_mask
1534 */
1535 static struct snd_pci_quirk probe_mask_list[] = {
1536 /* Thinkpad often breaks the controller communication when accessing
1537 * to the non-working (or non-existing) modem codec slot.
1538 */
1539 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1540 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1541 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1542 /* broken BIOS */
1543 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1544 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1545 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1546 /* forced codec slots */
1547 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1548 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1549 /* WinFast VP200 H (Teradici) user reported broken communication */
1550 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1551 {}
1552 };
1553
1554 #define AZX_FORCE_CODEC_MASK 0x100
1555
1556 static void check_probe_mask(struct azx *chip, int dev)
1557 {
1558 const struct snd_pci_quirk *q;
1559
1560 chip->codec_probe_mask = probe_mask[dev];
1561 if (chip->codec_probe_mask == -1) {
1562 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1563 if (q) {
1564 dev_info(chip->card->dev,
1565 "probe_mask set to 0x%x for device %04x:%04x\n",
1566 q->value, q->subvendor, q->subdevice);
1567 chip->codec_probe_mask = q->value;
1568 }
1569 }
1570
1571 /* check forced option */
1572 if (chip->codec_probe_mask != -1 &&
1573 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1574 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1575 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1576 (int)azx_bus(chip)->codec_mask);
1577 }
1578 }
1579
1580 /*
1581 * white/black-list for enable_msi
1582 */
1583 static struct snd_pci_quirk msi_black_list[] = {
1584 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1585 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1586 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1587 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1588 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1589 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1590 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1591 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1592 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1593 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1594 {}
1595 };
1596
1597 static void check_msi(struct azx *chip)
1598 {
1599 const struct snd_pci_quirk *q;
1600
1601 if (enable_msi >= 0) {
1602 chip->msi = !!enable_msi;
1603 return;
1604 }
1605 chip->msi = 1; /* enable MSI as default */
1606 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1607 if (q) {
1608 dev_info(chip->card->dev,
1609 "msi for device %04x:%04x set to %d\n",
1610 q->subvendor, q->subdevice, q->value);
1611 chip->msi = q->value;
1612 return;
1613 }
1614
1615 /* NVidia chipsets seem to cause troubles with MSI */
1616 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1617 dev_info(chip->card->dev, "Disabling MSI\n");
1618 chip->msi = 0;
1619 }
1620 }
1621
1622 /* check the snoop mode availability */
1623 static void azx_check_snoop_available(struct azx *chip)
1624 {
1625 int snoop = hda_snoop;
1626
1627 if (snoop >= 0) {
1628 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1629 snoop ? "snoop" : "non-snoop");
1630 chip->snoop = snoop;
1631 return;
1632 }
1633
1634 snoop = true;
1635 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1636 chip->driver_type == AZX_DRIVER_VIA) {
1637 /* force to non-snoop mode for a new VIA controller
1638 * when BIOS is set
1639 */
1640 u8 val;
1641 pci_read_config_byte(chip->pci, 0x42, &val);
1642 if (!(val & 0x80) && chip->pci->revision == 0x30)
1643 snoop = false;
1644 }
1645
1646 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1647 snoop = false;
1648
1649 chip->snoop = snoop;
1650 if (!snoop)
1651 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1652 }
1653
1654 static void azx_probe_work(struct work_struct *work)
1655 {
1656 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1657 azx_probe_continue(&hda->chip);
1658 }
1659
1660 static int default_bdl_pos_adj(struct azx *chip)
1661 {
1662 /* some exceptions: Atoms seem problematic with value 1 */
1663 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1664 switch (chip->pci->device) {
1665 case 0x0f04: /* Baytrail */
1666 case 0x2284: /* Braswell */
1667 return 32;
1668 }
1669 }
1670
1671 switch (chip->driver_type) {
1672 case AZX_DRIVER_ICH:
1673 case AZX_DRIVER_PCH:
1674 return 1;
1675 default:
1676 return 32;
1677 }
1678 }
1679
1680 /*
1681 * constructor
1682 */
1683 static const struct hdac_io_ops pci_hda_io_ops;
1684 static const struct hda_controller_ops pci_hda_ops;
1685
1686 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1687 int dev, unsigned int driver_caps,
1688 struct azx **rchip)
1689 {
1690 static struct snd_device_ops ops = {
1691 .dev_disconnect = azx_dev_disconnect,
1692 .dev_free = azx_dev_free,
1693 };
1694 struct hda_intel *hda;
1695 struct azx *chip;
1696 int err;
1697
1698 *rchip = NULL;
1699
1700 err = pci_enable_device(pci);
1701 if (err < 0)
1702 return err;
1703
1704 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1705 if (!hda) {
1706 pci_disable_device(pci);
1707 return -ENOMEM;
1708 }
1709
1710 chip = &hda->chip;
1711 mutex_init(&chip->open_mutex);
1712 chip->card = card;
1713 chip->pci = pci;
1714 chip->ops = &pci_hda_ops;
1715 chip->driver_caps = driver_caps;
1716 chip->driver_type = driver_caps & 0xff;
1717 check_msi(chip);
1718 chip->dev_index = dev;
1719 chip->jackpoll_ms = jackpoll_ms;
1720 INIT_LIST_HEAD(&chip->pcm_list);
1721 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1722 INIT_LIST_HEAD(&hda->list);
1723 init_vga_switcheroo(chip);
1724 init_completion(&hda->probe_wait);
1725
1726 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1727
1728 check_probe_mask(chip, dev);
1729
1730 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1731 chip->fallback_to_single_cmd = 1;
1732 else /* explicitly set to single_cmd or not */
1733 chip->single_cmd = single_cmd;
1734
1735 azx_check_snoop_available(chip);
1736
1737 if (bdl_pos_adj[dev] < 0)
1738 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1739 else
1740 chip->bdl_pos_adj = bdl_pos_adj[dev];
1741
1742 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1743 if (err < 0) {
1744 kfree(hda);
1745 pci_disable_device(pci);
1746 return err;
1747 }
1748
1749 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1750 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1751 chip->bus.needs_damn_long_delay = 1;
1752 }
1753
1754 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1755 if (err < 0) {
1756 dev_err(card->dev, "Error creating device [card]!\n");
1757 azx_free(chip);
1758 return err;
1759 }
1760
1761 /* continue probing in work context as may trigger request module */
1762 INIT_WORK(&hda->probe_work, azx_probe_work);
1763
1764 *rchip = chip;
1765
1766 return 0;
1767 }
1768
1769 static int azx_first_init(struct azx *chip)
1770 {
1771 int dev = chip->dev_index;
1772 struct pci_dev *pci = chip->pci;
1773 struct snd_card *card = chip->card;
1774 struct hdac_bus *bus = azx_bus(chip);
1775 int err;
1776 unsigned short gcap;
1777 unsigned int dma_bits = 64;
1778
1779 #if BITS_PER_LONG != 64
1780 /* Fix up base address on ULI M5461 */
1781 if (chip->driver_type == AZX_DRIVER_ULI) {
1782 u16 tmp3;
1783 pci_read_config_word(pci, 0x40, &tmp3);
1784 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1785 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1786 }
1787 #endif
1788
1789 err = pci_request_regions(pci, "ICH HD audio");
1790 if (err < 0)
1791 return err;
1792 chip->region_requested = 1;
1793
1794 bus->addr = pci_resource_start(pci, 0);
1795 bus->remap_addr = pci_ioremap_bar(pci, 0);
1796 if (bus->remap_addr == NULL) {
1797 dev_err(card->dev, "ioremap error\n");
1798 return -ENXIO;
1799 }
1800
1801 if (IS_SKL_PLUS(pci))
1802 snd_hdac_bus_parse_capabilities(bus);
1803
1804 /*
1805 * Some Intel CPUs has always running timer (ART) feature and
1806 * controller may have Global time sync reporting capability, so
1807 * check both of these before declaring synchronized time reporting
1808 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1809 */
1810 chip->gts_present = false;
1811
1812 #ifdef CONFIG_X86
1813 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1814 chip->gts_present = true;
1815 #endif
1816
1817 if (chip->msi) {
1818 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1819 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1820 pci->no_64bit_msi = true;
1821 }
1822 if (pci_enable_msi(pci) < 0)
1823 chip->msi = 0;
1824 }
1825
1826 if (azx_acquire_irq(chip, 0) < 0)
1827 return -EBUSY;
1828
1829 pci_set_master(pci);
1830 synchronize_irq(bus->irq);
1831
1832 gcap = azx_readw(chip, GCAP);
1833 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1834
1835 /* AMD devices support 40 or 48bit DMA, take the safe one */
1836 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1837 dma_bits = 40;
1838
1839 /* disable SB600 64bit support for safety */
1840 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1841 struct pci_dev *p_smbus;
1842 dma_bits = 40;
1843 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1844 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1845 NULL);
1846 if (p_smbus) {
1847 if (p_smbus->revision < 0x30)
1848 gcap &= ~AZX_GCAP_64OK;
1849 pci_dev_put(p_smbus);
1850 }
1851 }
1852
1853 /* NVidia hardware normally only supports up to 40 bits of DMA */
1854 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1855 dma_bits = 40;
1856
1857 /* disable 64bit DMA address on some devices */
1858 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1859 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1860 gcap &= ~AZX_GCAP_64OK;
1861 }
1862
1863 /* disable buffer size rounding to 128-byte multiples if supported */
1864 if (align_buffer_size >= 0)
1865 chip->align_buffer_size = !!align_buffer_size;
1866 else {
1867 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1868 chip->align_buffer_size = 0;
1869 else
1870 chip->align_buffer_size = 1;
1871 }
1872
1873 /* allow 64bit DMA address if supported by H/W */
1874 if (!(gcap & AZX_GCAP_64OK))
1875 dma_bits = 32;
1876 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1877 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1878 } else {
1879 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1880 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1881 }
1882
1883 /* read number of streams from GCAP register instead of using
1884 * hardcoded value
1885 */
1886 chip->capture_streams = (gcap >> 8) & 0x0f;
1887 chip->playback_streams = (gcap >> 12) & 0x0f;
1888 if (!chip->playback_streams && !chip->capture_streams) {
1889 /* gcap didn't give any info, switching to old method */
1890
1891 switch (chip->driver_type) {
1892 case AZX_DRIVER_ULI:
1893 chip->playback_streams = ULI_NUM_PLAYBACK;
1894 chip->capture_streams = ULI_NUM_CAPTURE;
1895 break;
1896 case AZX_DRIVER_ATIHDMI:
1897 case AZX_DRIVER_ATIHDMI_NS:
1898 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1899 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1900 break;
1901 case AZX_DRIVER_GENERIC:
1902 default:
1903 chip->playback_streams = ICH6_NUM_PLAYBACK;
1904 chip->capture_streams = ICH6_NUM_CAPTURE;
1905 break;
1906 }
1907 }
1908 chip->capture_index_offset = 0;
1909 chip->playback_index_offset = chip->capture_streams;
1910 chip->num_streams = chip->playback_streams + chip->capture_streams;
1911
1912 /* sanity check for the SDxCTL.STRM field overflow */
1913 if (chip->num_streams > 15 &&
1914 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1915 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1916 "forcing separate stream tags", chip->num_streams);
1917 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1918 }
1919
1920 /* initialize streams */
1921 err = azx_init_streams(chip);
1922 if (err < 0)
1923 return err;
1924
1925 err = azx_alloc_stream_pages(chip);
1926 if (err < 0)
1927 return err;
1928
1929 /* initialize chip */
1930 azx_init_pci(chip);
1931
1932 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1933 snd_hdac_i915_set_bclk(bus);
1934
1935 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1936
1937 /* codec detection */
1938 if (!azx_bus(chip)->codec_mask) {
1939 dev_err(card->dev, "no codecs found!\n");
1940 return -ENODEV;
1941 }
1942
1943 strcpy(card->driver, "HDA-Intel");
1944 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1945 sizeof(card->shortname));
1946 snprintf(card->longname, sizeof(card->longname),
1947 "%s at 0x%lx irq %i",
1948 card->shortname, bus->addr, bus->irq);
1949
1950 return 0;
1951 }
1952
1953 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1954 /* callback from request_firmware_nowait() */
1955 static void azx_firmware_cb(const struct firmware *fw, void *context)
1956 {
1957 struct snd_card *card = context;
1958 struct azx *chip = card->private_data;
1959 struct pci_dev *pci = chip->pci;
1960
1961 if (!fw) {
1962 dev_err(card->dev, "Cannot load firmware, aborting\n");
1963 goto error;
1964 }
1965
1966 chip->fw = fw;
1967 if (!chip->disabled) {
1968 /* continue probing */
1969 if (azx_probe_continue(chip))
1970 goto error;
1971 }
1972 return; /* OK */
1973
1974 error:
1975 snd_card_free(card);
1976 pci_set_drvdata(pci, NULL);
1977 }
1978 #endif
1979
1980 /*
1981 * HDA controller ops.
1982 */
1983
1984 /* PCI register access. */
1985 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1986 {
1987 writel(value, addr);
1988 }
1989
1990 static u32 pci_azx_readl(u32 __iomem *addr)
1991 {
1992 return readl(addr);
1993 }
1994
1995 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1996 {
1997 writew(value, addr);
1998 }
1999
2000 static u16 pci_azx_readw(u16 __iomem *addr)
2001 {
2002 return readw(addr);
2003 }
2004
2005 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
2006 {
2007 writeb(value, addr);
2008 }
2009
2010 static u8 pci_azx_readb(u8 __iomem *addr)
2011 {
2012 return readb(addr);
2013 }
2014
2015 static int disable_msi_reset_irq(struct azx *chip)
2016 {
2017 struct hdac_bus *bus = azx_bus(chip);
2018 int err;
2019
2020 free_irq(bus->irq, chip);
2021 bus->irq = -1;
2022 pci_disable_msi(chip->pci);
2023 chip->msi = 0;
2024 err = azx_acquire_irq(chip, 1);
2025 if (err < 0)
2026 return err;
2027
2028 return 0;
2029 }
2030
2031 /* DMA page allocation helpers. */
2032 static int dma_alloc_pages(struct hdac_bus *bus,
2033 int type,
2034 size_t size,
2035 struct snd_dma_buffer *buf)
2036 {
2037 struct azx *chip = bus_to_azx(bus);
2038 int err;
2039
2040 err = snd_dma_alloc_pages(type,
2041 bus->dev,
2042 size, buf);
2043 if (err < 0)
2044 return err;
2045 mark_pages_wc(chip, buf, true);
2046 return 0;
2047 }
2048
2049 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
2050 {
2051 struct azx *chip = bus_to_azx(bus);
2052
2053 mark_pages_wc(chip, buf, false);
2054 snd_dma_free_pages(buf);
2055 }
2056
2057 static int substream_alloc_pages(struct azx *chip,
2058 struct snd_pcm_substream *substream,
2059 size_t size)
2060 {
2061 struct azx_dev *azx_dev = get_azx_dev(substream);
2062 int ret;
2063
2064 mark_runtime_wc(chip, azx_dev, substream, false);
2065 ret = snd_pcm_lib_malloc_pages(substream, size);
2066 if (ret < 0)
2067 return ret;
2068 mark_runtime_wc(chip, azx_dev, substream, true);
2069 return 0;
2070 }
2071
2072 static int substream_free_pages(struct azx *chip,
2073 struct snd_pcm_substream *substream)
2074 {
2075 struct azx_dev *azx_dev = get_azx_dev(substream);
2076 mark_runtime_wc(chip, azx_dev, substream, false);
2077 return snd_pcm_lib_free_pages(substream);
2078 }
2079
2080 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2081 struct vm_area_struct *area)
2082 {
2083 #ifdef CONFIG_X86
2084 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2085 struct azx *chip = apcm->chip;
2086 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
2087 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2088 #endif
2089 }
2090
2091 static const struct hdac_io_ops pci_hda_io_ops = {
2092 .reg_writel = pci_azx_writel,
2093 .reg_readl = pci_azx_readl,
2094 .reg_writew = pci_azx_writew,
2095 .reg_readw = pci_azx_readw,
2096 .reg_writeb = pci_azx_writeb,
2097 .reg_readb = pci_azx_readb,
2098 .dma_alloc_pages = dma_alloc_pages,
2099 .dma_free_pages = dma_free_pages,
2100 };
2101
2102 static const struct hda_controller_ops pci_hda_ops = {
2103 .disable_msi_reset_irq = disable_msi_reset_irq,
2104 .substream_alloc_pages = substream_alloc_pages,
2105 .substream_free_pages = substream_free_pages,
2106 .pcm_mmap_prepare = pcm_mmap_prepare,
2107 .position_check = azx_position_check,
2108 .link_power = azx_intel_link_power,
2109 };
2110
2111 static int azx_probe(struct pci_dev *pci,
2112 const struct pci_device_id *pci_id)
2113 {
2114 static int dev;
2115 struct snd_card *card;
2116 struct hda_intel *hda;
2117 struct azx *chip;
2118 bool schedule_probe;
2119 int err;
2120
2121 if (dev >= SNDRV_CARDS)
2122 return -ENODEV;
2123 if (!enable[dev]) {
2124 dev++;
2125 return -ENOENT;
2126 }
2127
2128 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2129 0, &card);
2130 if (err < 0) {
2131 dev_err(&pci->dev, "Error creating card!\n");
2132 return err;
2133 }
2134
2135 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2136 if (err < 0)
2137 goto out_free;
2138 card->private_data = chip;
2139 hda = container_of(chip, struct hda_intel, chip);
2140
2141 pci_set_drvdata(pci, card);
2142
2143 err = register_vga_switcheroo(chip);
2144 if (err < 0) {
2145 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2146 goto out_free;
2147 }
2148
2149 if (check_hdmi_disabled(pci)) {
2150 dev_info(card->dev, "VGA controller is disabled\n");
2151 dev_info(card->dev, "Delaying initialization\n");
2152 chip->disabled = true;
2153 }
2154
2155 schedule_probe = !chip->disabled;
2156
2157 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2158 if (patch[dev] && *patch[dev]) {
2159 dev_info(card->dev, "Applying patch firmware '%s'\n",
2160 patch[dev]);
2161 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2162 &pci->dev, GFP_KERNEL, card,
2163 azx_firmware_cb);
2164 if (err < 0)
2165 goto out_free;
2166 schedule_probe = false; /* continued in azx_firmware_cb() */
2167 }
2168 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2169
2170 #ifndef CONFIG_SND_HDA_I915
2171 if (CONTROLLER_IN_GPU(pci))
2172 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2173 #endif
2174
2175 if (schedule_probe)
2176 schedule_work(&hda->probe_work);
2177
2178 dev++;
2179 if (chip->disabled)
2180 complete_all(&hda->probe_wait);
2181 return 0;
2182
2183 out_free:
2184 snd_card_free(card);
2185 return err;
2186 }
2187
2188 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2189 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2190 [AZX_DRIVER_NVIDIA] = 8,
2191 [AZX_DRIVER_TERA] = 1,
2192 };
2193
2194 static int azx_probe_continue(struct azx *chip)
2195 {
2196 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2197 struct hdac_bus *bus = azx_bus(chip);
2198 struct pci_dev *pci = chip->pci;
2199 int dev = chip->dev_index;
2200 int err;
2201
2202 hda->probe_continued = 1;
2203
2204 /* Request display power well for the HDA controller or codec. For
2205 * Haswell/Broadwell, both the display HDA controller and codec need
2206 * this power. For other platforms, like Baytrail/Braswell, only the
2207 * display codec needs the power and it can be released after probe.
2208 */
2209 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2210 /* HSW/BDW controllers need this power */
2211 if (CONTROLLER_IN_GPU(pci))
2212 hda->need_i915_power = 1;
2213
2214 err = snd_hdac_i915_init(bus);
2215 if (err < 0) {
2216 /* if the controller is bound only with HDMI/DP
2217 * (for HSW and BDW), we need to abort the probe;
2218 * for other chips, still continue probing as other
2219 * codecs can be on the same link.
2220 */
2221 if (CONTROLLER_IN_GPU(pci)) {
2222 dev_err(chip->card->dev,
2223 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2224 goto out_free;
2225 } else
2226 goto skip_i915;
2227 }
2228
2229 err = snd_hdac_display_power(bus, true);
2230 if (err < 0) {
2231 dev_err(chip->card->dev,
2232 "Cannot turn on display power on i915\n");
2233 goto i915_power_fail;
2234 }
2235 }
2236
2237 skip_i915:
2238 err = azx_first_init(chip);
2239 if (err < 0)
2240 goto out_free;
2241
2242 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2243 chip->beep_mode = beep_mode[dev];
2244 #endif
2245
2246 /* create codec instances */
2247 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2248 if (err < 0)
2249 goto out_free;
2250
2251 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2252 if (chip->fw) {
2253 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2254 chip->fw->data);
2255 if (err < 0)
2256 goto out_free;
2257 #ifndef CONFIG_PM
2258 release_firmware(chip->fw); /* no longer needed */
2259 chip->fw = NULL;
2260 #endif
2261 }
2262 #endif
2263 if ((probe_only[dev] & 1) == 0) {
2264 err = azx_codec_configure(chip);
2265 if (err < 0)
2266 goto out_free;
2267 }
2268
2269 err = snd_card_register(chip->card);
2270 if (err < 0)
2271 goto out_free;
2272
2273 chip->running = 1;
2274 azx_add_card_list(chip);
2275 snd_hda_set_power_save(&chip->bus, power_save * 1000);
2276 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
2277 pm_runtime_put_autosuspend(&pci->dev);
2278
2279 out_free:
2280 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2281 && !hda->need_i915_power)
2282 snd_hdac_display_power(bus, false);
2283
2284 i915_power_fail:
2285 if (err < 0)
2286 hda->init_failed = 1;
2287 complete_all(&hda->probe_wait);
2288 return err;
2289 }
2290
2291 static void azx_remove(struct pci_dev *pci)
2292 {
2293 struct snd_card *card = pci_get_drvdata(pci);
2294 struct azx *chip;
2295 struct hda_intel *hda;
2296
2297 if (card) {
2298 /* cancel the pending probing work */
2299 chip = card->private_data;
2300 hda = container_of(chip, struct hda_intel, chip);
2301 /* FIXME: below is an ugly workaround.
2302 * Both device_release_driver() and driver_probe_device()
2303 * take *both* the device's and its parent's lock before
2304 * calling the remove() and probe() callbacks. The codec
2305 * probe takes the locks of both the codec itself and its
2306 * parent, i.e. the PCI controller dev. Meanwhile, when
2307 * the PCI controller is unbound, it takes its lock, too
2308 * ==> ouch, a deadlock!
2309 * As a workaround, we unlock temporarily here the controller
2310 * device during cancel_work_sync() call.
2311 */
2312 device_unlock(&pci->dev);
2313 cancel_work_sync(&hda->probe_work);
2314 device_lock(&pci->dev);
2315
2316 snd_card_free(card);
2317 }
2318 }
2319
2320 static void azx_shutdown(struct pci_dev *pci)
2321 {
2322 struct snd_card *card = pci_get_drvdata(pci);
2323 struct azx *chip;
2324
2325 if (!card)
2326 return;
2327 chip = card->private_data;
2328 if (chip && chip->running)
2329 azx_stop_chip(chip);
2330 }
2331
2332 /* PCI IDs */
2333 static const struct pci_device_id azx_ids[] = {
2334 /* CPT */
2335 { PCI_DEVICE(0x8086, 0x1c20),
2336 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2337 /* PBG */
2338 { PCI_DEVICE(0x8086, 0x1d20),
2339 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2340 /* Panther Point */
2341 { PCI_DEVICE(0x8086, 0x1e20),
2342 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2343 /* Lynx Point */
2344 { PCI_DEVICE(0x8086, 0x8c20),
2345 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2346 /* 9 Series */
2347 { PCI_DEVICE(0x8086, 0x8ca0),
2348 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2349 /* Wellsburg */
2350 { PCI_DEVICE(0x8086, 0x8d20),
2351 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2352 { PCI_DEVICE(0x8086, 0x8d21),
2353 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2354 /* Lewisburg */
2355 { PCI_DEVICE(0x8086, 0xa1f0),
2356 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2357 { PCI_DEVICE(0x8086, 0xa270),
2358 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2359 /* Lynx Point-LP */
2360 { PCI_DEVICE(0x8086, 0x9c20),
2361 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2362 /* Lynx Point-LP */
2363 { PCI_DEVICE(0x8086, 0x9c21),
2364 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2365 /* Wildcat Point-LP */
2366 { PCI_DEVICE(0x8086, 0x9ca0),
2367 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2368 /* Sunrise Point */
2369 { PCI_DEVICE(0x8086, 0xa170),
2370 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2371 /* Sunrise Point-LP */
2372 { PCI_DEVICE(0x8086, 0x9d70),
2373 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2374 /* Kabylake */
2375 { PCI_DEVICE(0x8086, 0xa171),
2376 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2377 /* Kabylake-LP */
2378 { PCI_DEVICE(0x8086, 0x9d71),
2379 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2380 /* Kabylake-H */
2381 { PCI_DEVICE(0x8086, 0xa2f0),
2382 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2383 /* Coffelake */
2384 { PCI_DEVICE(0x8086, 0xa348),
2385 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE},
2386 /* Broxton-P(Apollolake) */
2387 { PCI_DEVICE(0x8086, 0x5a98),
2388 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2389 /* Broxton-T */
2390 { PCI_DEVICE(0x8086, 0x1a98),
2391 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2392 /* Gemini-Lake */
2393 { PCI_DEVICE(0x8086, 0x3198),
2394 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2395 /* Haswell */
2396 { PCI_DEVICE(0x8086, 0x0a0c),
2397 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2398 { PCI_DEVICE(0x8086, 0x0c0c),
2399 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2400 { PCI_DEVICE(0x8086, 0x0d0c),
2401 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2402 /* Broadwell */
2403 { PCI_DEVICE(0x8086, 0x160c),
2404 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2405 /* 5 Series/3400 */
2406 { PCI_DEVICE(0x8086, 0x3b56),
2407 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2408 /* Poulsbo */
2409 { PCI_DEVICE(0x8086, 0x811b),
2410 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2411 /* Oaktrail */
2412 { PCI_DEVICE(0x8086, 0x080a),
2413 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2414 /* BayTrail */
2415 { PCI_DEVICE(0x8086, 0x0f04),
2416 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2417 /* Braswell */
2418 { PCI_DEVICE(0x8086, 0x2284),
2419 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2420 /* ICH6 */
2421 { PCI_DEVICE(0x8086, 0x2668),
2422 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2423 /* ICH7 */
2424 { PCI_DEVICE(0x8086, 0x27d8),
2425 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2426 /* ESB2 */
2427 { PCI_DEVICE(0x8086, 0x269a),
2428 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2429 /* ICH8 */
2430 { PCI_DEVICE(0x8086, 0x284b),
2431 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2432 /* ICH9 */
2433 { PCI_DEVICE(0x8086, 0x293e),
2434 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2435 /* ICH9 */
2436 { PCI_DEVICE(0x8086, 0x293f),
2437 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2438 /* ICH10 */
2439 { PCI_DEVICE(0x8086, 0x3a3e),
2440 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2441 /* ICH10 */
2442 { PCI_DEVICE(0x8086, 0x3a6e),
2443 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2444 /* Generic Intel */
2445 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2446 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2447 .class_mask = 0xffffff,
2448 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2449 /* ATI SB 450/600/700/800/900 */
2450 { PCI_DEVICE(0x1002, 0x437b),
2451 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2452 { PCI_DEVICE(0x1002, 0x4383),
2453 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2454 /* AMD Hudson */
2455 { PCI_DEVICE(0x1022, 0x780d),
2456 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2457 /* ATI HDMI */
2458 { PCI_DEVICE(0x1002, 0x0002),
2459 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2460 { PCI_DEVICE(0x1002, 0x1308),
2461 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2462 { PCI_DEVICE(0x1002, 0x157a),
2463 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2464 { PCI_DEVICE(0x1002, 0x15b3),
2465 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2466 { PCI_DEVICE(0x1002, 0x793b),
2467 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2468 { PCI_DEVICE(0x1002, 0x7919),
2469 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2470 { PCI_DEVICE(0x1002, 0x960f),
2471 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2472 { PCI_DEVICE(0x1002, 0x970f),
2473 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2474 { PCI_DEVICE(0x1002, 0x9840),
2475 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2476 { PCI_DEVICE(0x1002, 0xaa00),
2477 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2478 { PCI_DEVICE(0x1002, 0xaa08),
2479 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2480 { PCI_DEVICE(0x1002, 0xaa10),
2481 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2482 { PCI_DEVICE(0x1002, 0xaa18),
2483 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2484 { PCI_DEVICE(0x1002, 0xaa20),
2485 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2486 { PCI_DEVICE(0x1002, 0xaa28),
2487 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2488 { PCI_DEVICE(0x1002, 0xaa30),
2489 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2490 { PCI_DEVICE(0x1002, 0xaa38),
2491 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2492 { PCI_DEVICE(0x1002, 0xaa40),
2493 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2494 { PCI_DEVICE(0x1002, 0xaa48),
2495 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2496 { PCI_DEVICE(0x1002, 0xaa50),
2497 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2498 { PCI_DEVICE(0x1002, 0xaa58),
2499 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2500 { PCI_DEVICE(0x1002, 0xaa60),
2501 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2502 { PCI_DEVICE(0x1002, 0xaa68),
2503 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2504 { PCI_DEVICE(0x1002, 0xaa80),
2505 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2506 { PCI_DEVICE(0x1002, 0xaa88),
2507 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2508 { PCI_DEVICE(0x1002, 0xaa90),
2509 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2510 { PCI_DEVICE(0x1002, 0xaa98),
2511 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2512 { PCI_DEVICE(0x1002, 0x9902),
2513 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2514 { PCI_DEVICE(0x1002, 0xaaa0),
2515 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2516 { PCI_DEVICE(0x1002, 0xaaa8),
2517 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2518 { PCI_DEVICE(0x1002, 0xaab0),
2519 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2520 { PCI_DEVICE(0x1002, 0xaac0),
2521 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2522 { PCI_DEVICE(0x1002, 0xaac8),
2523 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2524 { PCI_DEVICE(0x1002, 0xaad8),
2525 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2526 { PCI_DEVICE(0x1002, 0xaae8),
2527 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2528 { PCI_DEVICE(0x1002, 0xaae0),
2529 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2530 { PCI_DEVICE(0x1002, 0xaaf0),
2531 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2532 /* VIA VT8251/VT8237A */
2533 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2534 /* VIA GFX VT7122/VX900 */
2535 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2536 /* VIA GFX VT6122/VX11 */
2537 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2538 /* SIS966 */
2539 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2540 /* ULI M5461 */
2541 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2542 /* NVIDIA MCP */
2543 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2544 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2545 .class_mask = 0xffffff,
2546 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2547 /* Teradici */
2548 { PCI_DEVICE(0x6549, 0x1200),
2549 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2550 { PCI_DEVICE(0x6549, 0x2200),
2551 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2552 /* Creative X-Fi (CA0110-IBG) */
2553 /* CTHDA chips */
2554 { PCI_DEVICE(0x1102, 0x0010),
2555 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2556 { PCI_DEVICE(0x1102, 0x0012),
2557 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2558 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2559 /* the following entry conflicts with snd-ctxfi driver,
2560 * as ctxfi driver mutates from HD-audio to native mode with
2561 * a special command sequence.
2562 */
2563 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2564 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2565 .class_mask = 0xffffff,
2566 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2567 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2568 #else
2569 /* this entry seems still valid -- i.e. without emu20kx chip */
2570 { PCI_DEVICE(0x1102, 0x0009),
2571 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2572 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2573 #endif
2574 /* CM8888 */
2575 { PCI_DEVICE(0x13f6, 0x5011),
2576 .driver_data = AZX_DRIVER_CMEDIA |
2577 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2578 /* Vortex86MX */
2579 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2580 /* VMware HDAudio */
2581 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2582 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2583 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2584 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2585 .class_mask = 0xffffff,
2586 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2587 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2588 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2589 .class_mask = 0xffffff,
2590 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2591 { 0, }
2592 };
2593 MODULE_DEVICE_TABLE(pci, azx_ids);
2594
2595 /* pci_driver definition */
2596 static struct pci_driver azx_driver = {
2597 .name = KBUILD_MODNAME,
2598 .id_table = azx_ids,
2599 .probe = azx_probe,
2600 .remove = azx_remove,
2601 .shutdown = azx_shutdown,
2602 .driver = {
2603 .pm = AZX_PM_OPS,
2604 },
2605 };
2606
2607 module_pci_driver(azx_driver);