2 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
3 * Abramo Bagnara <abramo@alsa-project.org>
5 * Routines for control of Cirrus Logic CS461x chips
8 * - Sometimes the SPDIF input DSP tasks get's unsynchronized
9 * and the SPDIF get somewhat "distorcionated", or/and left right channel
10 * are swapped. To get around this problem when it happens, mute and unmute
11 * the SPDIF input mixer controll.
12 * - On the Hercules Game Theater XP the amplifier are sometimes turned
13 * off on inadecuate moments which causes distorcions on sound.
16 * - Secondary CODEC on some soundcards
17 * - SPDIF input support for other sample rates then 48khz
18 * - Posibility to mix the SPDIF output with analog sources.
19 * - PCM channels for Center and LFE on secondary codec
21 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
22 * is default configuration), no SPDIF, no secondary codec, no
23 * multi channel PCM. But known to work.
25 * FINALLY: A credit to the developers Tom and Jordan
26 * at Cirrus for have helping me out with the DSP, however we
27 * still don't have sufficient documentation and technical
28 * references to be able to implement all fancy feutures
29 * supported by the cs46xx DSP's.
30 * Benny <benny@hostmobility.com>
32 * This program is free software; you can redistribute it and/or modify
33 * it under the terms of the GNU General Public License as published by
34 * the Free Software Foundation; either version 2 of the License, or
35 * (at your option) any later version.
37 * This program is distributed in the hope that it will be useful,
38 * but WITHOUT ANY WARRANTY; without even the implied warranty of
39 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
40 * GNU General Public License for more details.
42 * You should have received a copy of the GNU General Public License
43 * along with this program; if not, write to the Free Software
44 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
48 #include <sound/driver.h>
49 #include <linux/delay.h>
50 #include <linux/pci.h>
52 #include <linux/init.h>
53 #include <linux/interrupt.h>
54 #include <linux/slab.h>
55 #include <linux/gameport.h>
57 #include <sound/core.h>
58 #include <sound/control.h>
59 #include <sound/info.h>
60 #include <sound/pcm.h>
61 #include <sound/pcm_params.h>
62 #include <sound/cs46xx.h>
66 #include "cs46xx_lib.h"
69 static void amp_voyetra(cs46xx_t
*chip
, int change
);
71 #ifdef CONFIG_SND_CS46XX_NEW_DSP
72 static snd_pcm_ops_t snd_cs46xx_playback_rear_ops
;
73 static snd_pcm_ops_t snd_cs46xx_playback_indirect_rear_ops
;
74 static snd_pcm_ops_t snd_cs46xx_playback_clfe_ops
;
75 static snd_pcm_ops_t snd_cs46xx_playback_indirect_clfe_ops
;
76 static snd_pcm_ops_t snd_cs46xx_playback_iec958_ops
;
77 static snd_pcm_ops_t snd_cs46xx_playback_indirect_iec958_ops
;
80 static snd_pcm_ops_t snd_cs46xx_playback_ops
;
81 static snd_pcm_ops_t snd_cs46xx_playback_indirect_ops
;
82 static snd_pcm_ops_t snd_cs46xx_capture_ops
;
83 static snd_pcm_ops_t snd_cs46xx_capture_indirect_ops
;
85 static unsigned short snd_cs46xx_codec_read(cs46xx_t
*chip
,
90 unsigned short result
,tmp
;
92 snd_assert ( (codec_index
== CS46XX_PRIMARY_CODEC_INDEX
) ||
93 (codec_index
== CS46XX_SECONDARY_CODEC_INDEX
),
96 chip
->active_ctrl(chip
, 1);
98 if (codec_index
== CS46XX_SECONDARY_CODEC_INDEX
)
99 offset
= CS46XX_SECONDARY_CODEC_OFFSET
;
102 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
103 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
104 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55
105 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
106 * 5. if DCV not cleared, break and return error
107 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
110 snd_cs46xx_peekBA0(chip
, BA0_ACSDA
+ offset
);
112 tmp
= snd_cs46xx_peekBA0(chip
, BA0_ACCTL
);
113 if ((tmp
& ACCTL_VFRM
) == 0) {
114 snd_printk(KERN_WARNING
"cs46xx: ACCTL_VFRM not set 0x%x\n",tmp
);
115 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, (tmp
& (~ACCTL_ESYN
)) | ACCTL_VFRM
);
117 tmp
= snd_cs46xx_peekBA0(chip
, BA0_ACCTL
+ offset
);
118 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, tmp
| ACCTL_ESYN
| ACCTL_VFRM
);
123 * Setup the AC97 control registers on the CS461x to send the
124 * appropriate command to the AC97 to perform the read.
125 * ACCAD = Command Address Register = 46Ch
126 * ACCDA = Command Data Register = 470h
127 * ACCTL = Control Register = 460h
128 * set DCV - will clear when process completed
129 * set CRW - Read command
130 * set VFRM - valid frame enabled
131 * set ESYN - ASYNC generation enabled
132 * set RSTN - ARST# inactive, AC97 codec not reset
135 snd_cs46xx_pokeBA0(chip
, BA0_ACCAD
, reg
);
136 snd_cs46xx_pokeBA0(chip
, BA0_ACCDA
, 0);
137 if (codec_index
== CS46XX_PRIMARY_CODEC_INDEX
) {
138 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
,/* clear ACCTL_DCV */ ACCTL_CRW
|
139 ACCTL_VFRM
| ACCTL_ESYN
|
141 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, ACCTL_DCV
| ACCTL_CRW
|
142 ACCTL_VFRM
| ACCTL_ESYN
|
145 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, ACCTL_DCV
| ACCTL_TC
|
146 ACCTL_CRW
| ACCTL_VFRM
| ACCTL_ESYN
|
151 * Wait for the read to occur.
153 for (count
= 0; count
< 1000; count
++) {
155 * First, we want to wait for a short time.
159 * Now, check to see if the read has completed.
160 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
162 if (!(snd_cs46xx_peekBA0(chip
, BA0_ACCTL
) & ACCTL_DCV
))
166 snd_printk("AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg
);
172 * Wait for the valid status bit to go active.
174 for (count
= 0; count
< 100; count
++) {
176 * Read the AC97 status register.
177 * ACSTS = Status Register = 464h
178 * VSTS - Valid Status
180 if (snd_cs46xx_peekBA0(chip
, BA0_ACSTS
+ offset
) & ACSTS_VSTS
)
185 snd_printk("AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n", codec_index
, reg
);
191 * Read the data returned from the AC97 register.
192 * ACSDA = Status Data Register = 474h
195 printk("e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg
,
196 snd_cs46xx_peekBA0(chip
, BA0_ACSDA
),
197 snd_cs46xx_peekBA0(chip
, BA0_ACCAD
));
200 //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
201 result
= snd_cs46xx_peekBA0(chip
, BA0_ACSDA
+ offset
);
203 chip
->active_ctrl(chip
, -1);
207 static unsigned short snd_cs46xx_ac97_read(ac97_t
* ac97
,
210 cs46xx_t
*chip
= ac97
->private_data
;
212 int codec_index
= ac97
->num
;
214 snd_assert(codec_index
== CS46XX_PRIMARY_CODEC_INDEX
||
215 codec_index
== CS46XX_SECONDARY_CODEC_INDEX
,
218 val
= snd_cs46xx_codec_read(chip
, reg
, codec_index
);
224 static void snd_cs46xx_codec_write(cs46xx_t
*chip
,
231 snd_assert ((codec_index
== CS46XX_PRIMARY_CODEC_INDEX
) ||
232 (codec_index
== CS46XX_SECONDARY_CODEC_INDEX
),
235 chip
->active_ctrl(chip
, 1);
238 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
239 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
240 * 3. Write ACCTL = Control Register = 460h for initiating the write
241 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
242 * 5. if DCV not cleared, break and return error
246 * Setup the AC97 control registers on the CS461x to send the
247 * appropriate command to the AC97 to perform the read.
248 * ACCAD = Command Address Register = 46Ch
249 * ACCDA = Command Data Register = 470h
250 * ACCTL = Control Register = 460h
251 * set DCV - will clear when process completed
252 * reset CRW - Write command
253 * set VFRM - valid frame enabled
254 * set ESYN - ASYNC generation enabled
255 * set RSTN - ARST# inactive, AC97 codec not reset
257 snd_cs46xx_pokeBA0(chip
, BA0_ACCAD
, reg
);
258 snd_cs46xx_pokeBA0(chip
, BA0_ACCDA
, val
);
259 snd_cs46xx_peekBA0(chip
, BA0_ACCTL
);
261 if (codec_index
== CS46XX_PRIMARY_CODEC_INDEX
) {
262 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, /* clear ACCTL_DCV */ ACCTL_VFRM
|
263 ACCTL_ESYN
| ACCTL_RSTN
);
264 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, ACCTL_DCV
| ACCTL_VFRM
|
265 ACCTL_ESYN
| ACCTL_RSTN
);
267 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, ACCTL_DCV
| ACCTL_TC
|
268 ACCTL_VFRM
| ACCTL_ESYN
| ACCTL_RSTN
);
271 for (count
= 0; count
< 4000; count
++) {
273 * First, we want to wait for a short time.
277 * Now, check to see if the write has completed.
278 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
280 if (!(snd_cs46xx_peekBA0(chip
, BA0_ACCTL
) & ACCTL_DCV
)) {
284 snd_printk("AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n", codec_index
, reg
, val
);
286 chip
->active_ctrl(chip
, -1);
289 static void snd_cs46xx_ac97_write(ac97_t
*ac97
,
293 cs46xx_t
*chip
= ac97
->private_data
;
294 int codec_index
= ac97
->num
;
296 snd_assert(codec_index
== CS46XX_PRIMARY_CODEC_INDEX
||
297 codec_index
== CS46XX_SECONDARY_CODEC_INDEX
,
300 snd_cs46xx_codec_write(chip
, reg
, val
, codec_index
);
305 * Chip initialization
308 int snd_cs46xx_download(cs46xx_t
*chip
,
310 unsigned long offset
,
314 unsigned int bank
= offset
>> 16;
315 offset
= offset
& 0xffff;
317 snd_assert(!(offset
& 3) && !(len
& 3), return -EINVAL
);
318 dst
= chip
->region
.idx
[bank
+1].remap_addr
+ offset
;
321 /* writel already converts 32-bit value to right endianess */
329 #ifdef CONFIG_SND_CS46XX_NEW_DSP
331 #include "imgs/cwc4630.h"
332 #include "imgs/cwcasync.h"
333 #include "imgs/cwcsnoop.h"
334 #include "imgs/cwcbinhack.h"
335 #include "imgs/cwcdma.h"
337 int snd_cs46xx_clear_BA1(cs46xx_t
*chip
,
338 unsigned long offset
,
342 unsigned int bank
= offset
>> 16;
343 offset
= offset
& 0xffff;
345 snd_assert(!(offset
& 3) && !(len
& 3), return -EINVAL
);
346 dst
= chip
->region
.idx
[bank
+1].remap_addr
+ offset
;
349 /* writel already converts 32-bit value to right endianess */
357 #else /* old DSP image */
359 #include "cs46xx_image.h"
361 int snd_cs46xx_download_image(cs46xx_t
*chip
)
364 unsigned long offset
= 0;
366 for (idx
= 0; idx
< BA1_MEMORY_COUNT
; idx
++) {
367 if ((err
= snd_cs46xx_download(chip
,
368 &BA1Struct
.map
[offset
],
369 BA1Struct
.memory
[idx
].offset
,
370 BA1Struct
.memory
[idx
].size
)) < 0)
372 offset
+= BA1Struct
.memory
[idx
].size
>> 2;
376 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
382 static void snd_cs46xx_reset(cs46xx_t
*chip
)
387 * Write the reset bit of the SP control register.
389 snd_cs46xx_poke(chip
, BA1_SPCR
, SPCR_RSTSP
);
392 * Write the control register.
394 snd_cs46xx_poke(chip
, BA1_SPCR
, SPCR_DRQEN
);
397 * Clear the trap registers.
399 for (idx
= 0; idx
< 8; idx
++) {
400 snd_cs46xx_poke(chip
, BA1_DREG
, DREG_REGID_TRAP_SELECT
+ idx
);
401 snd_cs46xx_poke(chip
, BA1_TWPR
, 0xFFFF);
403 snd_cs46xx_poke(chip
, BA1_DREG
, 0);
406 * Set the frame timer to reflect the number of cycles per frame.
408 snd_cs46xx_poke(chip
, BA1_FRMT
, 0xadf);
411 static int cs46xx_wait_for_fifo(cs46xx_t
* chip
,int retry_timeout
)
415 * Make sure the previous FIFO write operation has completed.
417 for(i
= 0; i
< 50; i
++){
418 status
= snd_cs46xx_peekBA0(chip
, BA0_SERBST
);
420 if( !(status
& SERBST_WBSY
) )
423 mdelay(retry_timeout
);
426 if(status
& SERBST_WBSY
) {
427 snd_printk( KERN_ERR
"cs46xx: failure waiting for FIFO command to complete\n");
435 static void snd_cs46xx_clear_serial_FIFOs(cs46xx_t
*chip
)
437 int idx
, powerdown
= 0;
441 * See if the devices are powered down. If so, we must power them up first
442 * or they will not respond.
444 tmp
= snd_cs46xx_peekBA0(chip
, BA0_CLKCR1
);
445 if (!(tmp
& CLKCR1_SWCE
)) {
446 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, tmp
| CLKCR1_SWCE
);
451 * We want to clear out the serial port FIFOs so we don't end up playing
452 * whatever random garbage happens to be in them. We fill the sample FIFOS
453 * with zero (silence).
455 snd_cs46xx_pokeBA0(chip
, BA0_SERBWP
, 0);
458 * Fill all 256 sample FIFO locations.
460 for (idx
= 0; idx
< 0xFF; idx
++) {
462 * Make sure the previous FIFO write operation has completed.
464 if (cs46xx_wait_for_fifo(chip
,1)) {
465 snd_printdd ("failed waiting for FIFO at addr (%02X)\n",idx
);
468 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, tmp
);
473 * Write the serial port FIFO index.
475 snd_cs46xx_pokeBA0(chip
, BA0_SERBAD
, idx
);
477 * Tell the serial port to load the new value into the FIFO location.
479 snd_cs46xx_pokeBA0(chip
, BA0_SERBCM
, SERBCM_WRC
);
482 * Now, if we powered up the devices, then power them back down again.
483 * This is kinda ugly, but should never happen.
486 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, tmp
);
489 static void snd_cs46xx_proc_start(cs46xx_t
*chip
)
494 * Set the frame timer to reflect the number of cycles per frame.
496 snd_cs46xx_poke(chip
, BA1_FRMT
, 0xadf);
498 * Turn on the run, run at frame, and DMA enable bits in the local copy of
499 * the SP control register.
501 snd_cs46xx_poke(chip
, BA1_SPCR
, SPCR_RUN
| SPCR_RUNFR
| SPCR_DRQEN
);
503 * Wait until the run at frame bit resets itself in the SP control
506 for (cnt
= 0; cnt
< 25; cnt
++) {
508 if (!(snd_cs46xx_peek(chip
, BA1_SPCR
) & SPCR_RUNFR
))
512 if (snd_cs46xx_peek(chip
, BA1_SPCR
) & SPCR_RUNFR
)
513 snd_printk("SPCR_RUNFR never reset\n");
516 static void snd_cs46xx_proc_stop(cs46xx_t
*chip
)
519 * Turn off the run, run at frame, and DMA enable bits in the local copy of
520 * the SP control register.
522 snd_cs46xx_poke(chip
, BA1_SPCR
, 0);
526 * Sample rate routines
529 #define GOF_PER_SEC 200
531 static void snd_cs46xx_set_play_sample_rate(cs46xx_t
*chip
, unsigned int rate
)
534 unsigned int tmp1
, tmp2
;
535 unsigned int phiIncr
;
536 unsigned int correctionPerGOF
, correctionPerSec
;
539 * Compute the values used to drive the actual sample rate conversion.
540 * The following formulas are being computed, using inline assembly
541 * since we need to use 64 bit arithmetic to compute the values:
543 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
544 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
546 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
547 * GOF_PER_SEC * correctionPerGOF
551 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
552 * correctionPerGOF:correctionPerSec =
553 * dividend:remainder(ulOther / GOF_PER_SEC)
556 phiIncr
= tmp1
/ 48000;
557 tmp1
-= phiIncr
* 48000;
562 tmp1
-= tmp2
* 48000;
563 correctionPerGOF
= tmp1
/ GOF_PER_SEC
;
564 tmp1
-= correctionPerGOF
* GOF_PER_SEC
;
565 correctionPerSec
= tmp1
;
568 * Fill in the SampleRateConverter control block.
570 spin_lock_irqsave(&chip
->reg_lock
, flags
);
571 snd_cs46xx_poke(chip
, BA1_PSRC
,
572 ((correctionPerSec
<< 16) & 0xFFFF0000) | (correctionPerGOF
& 0xFFFF));
573 snd_cs46xx_poke(chip
, BA1_PPI
, phiIncr
);
574 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
577 static void snd_cs46xx_set_capture_sample_rate(cs46xx_t
*chip
, unsigned int rate
)
580 unsigned int phiIncr
, coeffIncr
, tmp1
, tmp2
;
581 unsigned int correctionPerGOF
, correctionPerSec
, initialDelay
;
582 unsigned int frameGroupLength
, cnt
;
585 * We can only decimate by up to a factor of 1/9th the hardware rate.
586 * Correct the value if an attempt is made to stray outside that limit.
588 if ((rate
* 9) < 48000)
592 * We can not capture at at rate greater than the Input Rate (48000).
593 * Return an error if an attempt is made to stray outside that limit.
599 * Compute the values used to drive the actual sample rate conversion.
600 * The following formulas are being computed, using inline assembly
601 * since we need to use 64 bit arithmetic to compute the values:
603 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
604 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
605 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
607 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
608 * GOF_PER_SEC * correctionPerGOF
609 * initialDelay = ceil((24 * Fs,in) / Fs,out)
613 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
614 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
615 * correctionPerGOF:correctionPerSec =
616 * dividend:remainder(ulOther / GOF_PER_SEC)
617 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
621 coeffIncr
= tmp1
/ 48000;
622 tmp1
-= coeffIncr
* 48000;
625 coeffIncr
+= tmp1
/ 48000;
626 coeffIncr
^= 0xFFFFFFFF;
629 phiIncr
= tmp1
/ rate
;
630 tmp1
-= phiIncr
* rate
;
636 correctionPerGOF
= tmp1
/ GOF_PER_SEC
;
637 tmp1
-= correctionPerGOF
* GOF_PER_SEC
;
638 correctionPerSec
= tmp1
;
639 initialDelay
= ((48000 * 24) + rate
- 1) / rate
;
642 * Fill in the VariDecimate control block.
644 spin_lock_irqsave(&chip
->reg_lock
, flags
);
645 snd_cs46xx_poke(chip
, BA1_CSRC
,
646 ((correctionPerSec
<< 16) & 0xFFFF0000) | (correctionPerGOF
& 0xFFFF));
647 snd_cs46xx_poke(chip
, BA1_CCI
, coeffIncr
);
648 snd_cs46xx_poke(chip
, BA1_CD
,
649 (((BA1_VARIDEC_BUF_1
+ (initialDelay
<< 2)) << 16) & 0xFFFF0000) | 0x80);
650 snd_cs46xx_poke(chip
, BA1_CPI
, phiIncr
);
651 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
654 * Figure out the frame group length for the write back task. Basically,
655 * this is just the factors of 24000 (2^6*3*5^3) that are not present in
656 * the output sample rate.
658 frameGroupLength
= 1;
659 for (cnt
= 2; cnt
<= 64; cnt
*= 2) {
660 if (((rate
/ cnt
) * cnt
) != rate
)
661 frameGroupLength
*= 2;
663 if (((rate
/ 3) * 3) != rate
) {
664 frameGroupLength
*= 3;
666 for (cnt
= 5; cnt
<= 125; cnt
*= 5) {
667 if (((rate
/ cnt
) * cnt
) != rate
)
668 frameGroupLength
*= 5;
672 * Fill in the WriteBack control block.
674 spin_lock_irqsave(&chip
->reg_lock
, flags
);
675 snd_cs46xx_poke(chip
, BA1_CFG1
, frameGroupLength
);
676 snd_cs46xx_poke(chip
, BA1_CFG2
, (0x00800000 | frameGroupLength
));
677 snd_cs46xx_poke(chip
, BA1_CCST
, 0x0000FFFF);
678 snd_cs46xx_poke(chip
, BA1_CSPB
, ((65536 * rate
) / 24000));
679 snd_cs46xx_poke(chip
, (BA1_CSPB
+ 4), 0x0000FFFF);
680 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
687 static void snd_cs46xx_pb_trans_copy(snd_pcm_substream_t
*substream
,
688 snd_pcm_indirect_t
*rec
, size_t bytes
)
690 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
691 cs46xx_pcm_t
* cpcm
= runtime
->private_data
;
692 memcpy(cpcm
->hw_buf
.area
+ rec
->hw_data
, runtime
->dma_area
+ rec
->sw_data
, bytes
);
695 static int snd_cs46xx_playback_transfer(snd_pcm_substream_t
*substream
)
697 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
698 cs46xx_pcm_t
* cpcm
= runtime
->private_data
;
699 snd_pcm_indirect_playback_transfer(substream
, &cpcm
->pcm_rec
, snd_cs46xx_pb_trans_copy
);
703 static void snd_cs46xx_cp_trans_copy(snd_pcm_substream_t
*substream
,
704 snd_pcm_indirect_t
*rec
, size_t bytes
)
706 cs46xx_t
*chip
= snd_pcm_substream_chip(substream
);
707 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
708 memcpy(runtime
->dma_area
+ rec
->sw_data
,
709 chip
->capt
.hw_buf
.area
+ rec
->hw_data
, bytes
);
712 static int snd_cs46xx_capture_transfer(snd_pcm_substream_t
*substream
)
714 cs46xx_t
*chip
= snd_pcm_substream_chip(substream
);
715 snd_pcm_indirect_capture_transfer(substream
, &chip
->capt
.pcm_rec
, snd_cs46xx_cp_trans_copy
);
719 static snd_pcm_uframes_t
snd_cs46xx_playback_direct_pointer(snd_pcm_substream_t
* substream
)
721 cs46xx_t
*chip
= snd_pcm_substream_chip(substream
);
723 cs46xx_pcm_t
*cpcm
= substream
->runtime
->private_data
;
724 snd_assert (cpcm
->pcm_channel
,return -ENXIO
);
726 #ifdef CONFIG_SND_CS46XX_NEW_DSP
727 ptr
= snd_cs46xx_peek(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
+ 2) << 2);
729 ptr
= snd_cs46xx_peek(chip
, BA1_PBA
);
731 ptr
-= cpcm
->hw_buf
.addr
;
732 return ptr
>> cpcm
->shift
;
735 static snd_pcm_uframes_t
snd_cs46xx_playback_indirect_pointer(snd_pcm_substream_t
* substream
)
737 cs46xx_t
*chip
= snd_pcm_substream_chip(substream
);
739 cs46xx_pcm_t
*cpcm
= substream
->runtime
->private_data
;
741 #ifdef CONFIG_SND_CS46XX_NEW_DSP
742 snd_assert (cpcm
->pcm_channel
,return -ENXIO
);
743 ptr
= snd_cs46xx_peek(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
+ 2) << 2);
745 ptr
= snd_cs46xx_peek(chip
, BA1_PBA
);
747 ptr
-= cpcm
->hw_buf
.addr
;
748 return snd_pcm_indirect_playback_pointer(substream
, &cpcm
->pcm_rec
, ptr
);
751 static snd_pcm_uframes_t
snd_cs46xx_capture_direct_pointer(snd_pcm_substream_t
* substream
)
753 cs46xx_t
*chip
= snd_pcm_substream_chip(substream
);
754 size_t ptr
= snd_cs46xx_peek(chip
, BA1_CBA
) - chip
->capt
.hw_buf
.addr
;
755 return ptr
>> chip
->capt
.shift
;
758 static snd_pcm_uframes_t
snd_cs46xx_capture_indirect_pointer(snd_pcm_substream_t
* substream
)
760 cs46xx_t
*chip
= snd_pcm_substream_chip(substream
);
761 size_t ptr
= snd_cs46xx_peek(chip
, BA1_CBA
) - chip
->capt
.hw_buf
.addr
;
762 return snd_pcm_indirect_capture_pointer(substream
, &chip
->capt
.pcm_rec
, ptr
);
765 static int snd_cs46xx_playback_trigger(snd_pcm_substream_t
* substream
,
768 cs46xx_t
*chip
= snd_pcm_substream_chip(substream
);
769 /*snd_pcm_runtime_t *runtime = substream->runtime;*/
772 #ifdef CONFIG_SND_CS46XX_NEW_DSP
773 cs46xx_pcm_t
*cpcm
= substream
->runtime
->private_data
;
774 if (! cpcm
->pcm_channel
) {
779 case SNDRV_PCM_TRIGGER_START
:
780 case SNDRV_PCM_TRIGGER_RESUME
:
781 #ifdef CONFIG_SND_CS46XX_NEW_DSP
782 /* magic value to unmute PCM stream playback volume */
783 snd_cs46xx_poke(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
+
784 SCBVolumeCtrl
) << 2, 0x80008000);
786 if (cpcm
->pcm_channel
->unlinked
)
787 cs46xx_dsp_pcm_link(chip
,cpcm
->pcm_channel
);
789 if (substream
->runtime
->periods
!= CS46XX_FRAGS
)
790 snd_cs46xx_playback_transfer(substream
);
792 spin_lock(&chip
->reg_lock
);
793 if (substream
->runtime
->periods
!= CS46XX_FRAGS
)
794 snd_cs46xx_playback_transfer(substream
);
796 tmp
= snd_cs46xx_peek(chip
, BA1_PCTL
);
798 snd_cs46xx_poke(chip
, BA1_PCTL
, chip
->play_ctl
| tmp
);
800 spin_unlock(&chip
->reg_lock
);
803 case SNDRV_PCM_TRIGGER_STOP
:
804 case SNDRV_PCM_TRIGGER_SUSPEND
:
805 #ifdef CONFIG_SND_CS46XX_NEW_DSP
806 /* magic mute channel */
807 snd_cs46xx_poke(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
+
808 SCBVolumeCtrl
) << 2, 0xffffffff);
810 if (!cpcm
->pcm_channel
->unlinked
)
811 cs46xx_dsp_pcm_unlink(chip
,cpcm
->pcm_channel
);
813 spin_lock(&chip
->reg_lock
);
815 tmp
= snd_cs46xx_peek(chip
, BA1_PCTL
);
817 snd_cs46xx_poke(chip
, BA1_PCTL
, tmp
);
819 spin_unlock(&chip
->reg_lock
);
830 static int snd_cs46xx_capture_trigger(snd_pcm_substream_t
* substream
,
833 cs46xx_t
*chip
= snd_pcm_substream_chip(substream
);
837 spin_lock(&chip
->reg_lock
);
839 case SNDRV_PCM_TRIGGER_START
:
840 case SNDRV_PCM_TRIGGER_RESUME
:
841 tmp
= snd_cs46xx_peek(chip
, BA1_CCTL
);
843 snd_cs46xx_poke(chip
, BA1_CCTL
, chip
->capt
.ctl
| tmp
);
845 case SNDRV_PCM_TRIGGER_STOP
:
846 case SNDRV_PCM_TRIGGER_SUSPEND
:
847 tmp
= snd_cs46xx_peek(chip
, BA1_CCTL
);
849 snd_cs46xx_poke(chip
, BA1_CCTL
, tmp
);
855 spin_unlock(&chip
->reg_lock
);
860 #ifdef CONFIG_SND_CS46XX_NEW_DSP
861 static int _cs46xx_adjust_sample_rate (cs46xx_t
*chip
, cs46xx_pcm_t
*cpcm
,
865 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
866 if ( cpcm
->pcm_channel
== NULL
) {
867 cpcm
->pcm_channel
= cs46xx_dsp_create_pcm_channel (chip
, sample_rate
,
868 cpcm
, cpcm
->hw_buf
.addr
,cpcm
->pcm_channel_id
);
869 if (cpcm
->pcm_channel
== NULL
) {
870 snd_printk(KERN_ERR
"cs46xx: failed to create virtual PCM channel\n");
873 cpcm
->pcm_channel
->sample_rate
= sample_rate
;
875 /* if sample rate is changed */
876 if ((int)cpcm
->pcm_channel
->sample_rate
!= sample_rate
) {
877 int unlinked
= cpcm
->pcm_channel
->unlinked
;
878 cs46xx_dsp_destroy_pcm_channel (chip
,cpcm
->pcm_channel
);
880 if ( (cpcm
->pcm_channel
= cs46xx_dsp_create_pcm_channel (chip
, sample_rate
, cpcm
,
882 cpcm
->pcm_channel_id
)) == NULL
) {
883 snd_printk(KERN_ERR
"cs46xx: failed to re-create virtual PCM channel\n");
887 if (!unlinked
) cs46xx_dsp_pcm_link (chip
,cpcm
->pcm_channel
);
888 cpcm
->pcm_channel
->sample_rate
= sample_rate
;
896 static int snd_cs46xx_playback_hw_params(snd_pcm_substream_t
* substream
,
897 snd_pcm_hw_params_t
* hw_params
)
899 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
902 #ifdef CONFIG_SND_CS46XX_NEW_DSP
903 cs46xx_t
*chip
= snd_pcm_substream_chip(substream
);
904 int sample_rate
= params_rate(hw_params
);
905 int period_size
= params_period_bytes(hw_params
);
907 cpcm
= runtime
->private_data
;
909 #ifdef CONFIG_SND_CS46XX_NEW_DSP
910 snd_assert (sample_rate
!= 0, return -ENXIO
);
912 down (&chip
->spos_mutex
);
914 if (_cs46xx_adjust_sample_rate (chip
,cpcm
,sample_rate
)) {
915 up (&chip
->spos_mutex
);
919 snd_assert (cpcm
->pcm_channel
!= NULL
);
920 if (!cpcm
->pcm_channel
) {
921 up (&chip
->spos_mutex
);
926 if (cs46xx_dsp_pcm_channel_set_period (chip
,cpcm
->pcm_channel
,period_size
)) {
927 up (&chip
->spos_mutex
);
931 snd_printdd ("period_size (%d), periods (%d) buffer_size(%d)\n",
932 period_size
, params_periods(hw_params
),
933 params_buffer_bytes(hw_params
));
936 if (params_periods(hw_params
) == CS46XX_FRAGS
) {
937 if (runtime
->dma_area
!= cpcm
->hw_buf
.area
)
938 snd_pcm_lib_free_pages(substream
);
939 runtime
->dma_area
= cpcm
->hw_buf
.area
;
940 runtime
->dma_addr
= cpcm
->hw_buf
.addr
;
941 runtime
->dma_bytes
= cpcm
->hw_buf
.bytes
;
944 #ifdef CONFIG_SND_CS46XX_NEW_DSP
945 if (cpcm
->pcm_channel_id
== DSP_PCM_MAIN_CHANNEL
) {
946 substream
->ops
= &snd_cs46xx_playback_ops
;
947 } else if (cpcm
->pcm_channel_id
== DSP_PCM_REAR_CHANNEL
) {
948 substream
->ops
= &snd_cs46xx_playback_rear_ops
;
949 } else if (cpcm
->pcm_channel_id
== DSP_PCM_CENTER_LFE_CHANNEL
) {
950 substream
->ops
= &snd_cs46xx_playback_clfe_ops
;
951 } else if (cpcm
->pcm_channel_id
== DSP_IEC958_CHANNEL
) {
952 substream
->ops
= &snd_cs46xx_playback_iec958_ops
;
957 substream
->ops
= &snd_cs46xx_playback_ops
;
961 if (runtime
->dma_area
== cpcm
->hw_buf
.area
) {
962 runtime
->dma_area
= NULL
;
963 runtime
->dma_addr
= 0;
964 runtime
->dma_bytes
= 0;
966 if ((err
= snd_pcm_lib_malloc_pages(substream
, params_buffer_bytes(hw_params
))) < 0) {
967 #ifdef CONFIG_SND_CS46XX_NEW_DSP
968 up (&chip
->spos_mutex
);
973 #ifdef CONFIG_SND_CS46XX_NEW_DSP
974 if (cpcm
->pcm_channel_id
== DSP_PCM_MAIN_CHANNEL
) {
975 substream
->ops
= &snd_cs46xx_playback_indirect_ops
;
976 } else if (cpcm
->pcm_channel_id
== DSP_PCM_REAR_CHANNEL
) {
977 substream
->ops
= &snd_cs46xx_playback_indirect_rear_ops
;
978 } else if (cpcm
->pcm_channel_id
== DSP_PCM_CENTER_LFE_CHANNEL
) {
979 substream
->ops
= &snd_cs46xx_playback_indirect_clfe_ops
;
980 } else if (cpcm
->pcm_channel_id
== DSP_IEC958_CHANNEL
) {
981 substream
->ops
= &snd_cs46xx_playback_indirect_iec958_ops
;
986 substream
->ops
= &snd_cs46xx_playback_indirect_ops
;
991 #ifdef CONFIG_SND_CS46XX_NEW_DSP
992 up (&chip
->spos_mutex
);
998 static int snd_cs46xx_playback_hw_free(snd_pcm_substream_t
* substream
)
1000 /*cs46xx_t *chip = snd_pcm_substream_chip(substream);*/
1001 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
1004 cpcm
= runtime
->private_data
;
1006 /* if play_back open fails, then this function
1007 is called and cpcm can actually be NULL here */
1008 if (!cpcm
) return -ENXIO
;
1010 if (runtime
->dma_area
!= cpcm
->hw_buf
.area
)
1011 snd_pcm_lib_free_pages(substream
);
1013 runtime
->dma_area
= NULL
;
1014 runtime
->dma_addr
= 0;
1015 runtime
->dma_bytes
= 0;
1020 static int snd_cs46xx_playback_prepare(snd_pcm_substream_t
* substream
)
1024 cs46xx_t
*chip
= snd_pcm_substream_chip(substream
);
1025 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
1028 cpcm
= runtime
->private_data
;
1030 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1031 snd_assert (cpcm
->pcm_channel
!= NULL
, return -ENXIO
);
1033 pfie
= snd_cs46xx_peek(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
+ 1) << 2 );
1034 pfie
&= ~0x0000f03f;
1037 pfie
= snd_cs46xx_peek(chip
, BA1_PFIE
);
1038 pfie
&= ~0x0000f03f;
1042 /* if to convert from stereo to mono */
1043 if (runtime
->channels
== 1) {
1047 /* if to convert from 8 bit to 16 bit */
1048 if (snd_pcm_format_width(runtime
->format
) == 8) {
1052 /* if to convert to unsigned */
1053 if (snd_pcm_format_unsigned(runtime
->format
))
1056 /* Never convert byte order when sample stream is 8 bit */
1057 if (snd_pcm_format_width(runtime
->format
) != 8) {
1058 /* convert from big endian to little endian */
1059 if (snd_pcm_format_big_endian(runtime
->format
))
1063 memset(&cpcm
->pcm_rec
, 0, sizeof(cpcm
->pcm_rec
));
1064 cpcm
->pcm_rec
.sw_buffer_size
= snd_pcm_lib_buffer_bytes(substream
);
1065 cpcm
->pcm_rec
.hw_buffer_size
= runtime
->period_size
* CS46XX_FRAGS
<< cpcm
->shift
;
1067 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1069 tmp
= snd_cs46xx_peek(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
) << 2);
1071 tmp
|= (4 << cpcm
->shift
) - 1;
1072 /* playback transaction count register */
1073 snd_cs46xx_poke(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
) << 2, tmp
);
1075 /* playback format && interrupt enable */
1076 snd_cs46xx_poke(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
+ 1) << 2, pfie
| cpcm
->pcm_channel
->pcm_slot
);
1078 snd_cs46xx_poke(chip
, BA1_PBA
, cpcm
->hw_buf
.addr
);
1079 tmp
= snd_cs46xx_peek(chip
, BA1_PDTC
);
1081 tmp
|= (4 << cpcm
->shift
) - 1;
1082 snd_cs46xx_poke(chip
, BA1_PDTC
, tmp
);
1083 snd_cs46xx_poke(chip
, BA1_PFIE
, pfie
);
1084 snd_cs46xx_set_play_sample_rate(chip
, runtime
->rate
);
1090 static int snd_cs46xx_capture_hw_params(snd_pcm_substream_t
* substream
,
1091 snd_pcm_hw_params_t
* hw_params
)
1093 cs46xx_t
*chip
= snd_pcm_substream_chip(substream
);
1094 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
1097 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1098 cs46xx_dsp_pcm_ostream_set_period (chip
, params_period_bytes(hw_params
));
1100 if (runtime
->periods
== CS46XX_FRAGS
) {
1101 if (runtime
->dma_area
!= chip
->capt
.hw_buf
.area
)
1102 snd_pcm_lib_free_pages(substream
);
1103 runtime
->dma_area
= chip
->capt
.hw_buf
.area
;
1104 runtime
->dma_addr
= chip
->capt
.hw_buf
.addr
;
1105 runtime
->dma_bytes
= chip
->capt
.hw_buf
.bytes
;
1106 substream
->ops
= &snd_cs46xx_capture_ops
;
1108 if (runtime
->dma_area
== chip
->capt
.hw_buf
.area
) {
1109 runtime
->dma_area
= NULL
;
1110 runtime
->dma_addr
= 0;
1111 runtime
->dma_bytes
= 0;
1113 if ((err
= snd_pcm_lib_malloc_pages(substream
, params_buffer_bytes(hw_params
))) < 0)
1115 substream
->ops
= &snd_cs46xx_capture_indirect_ops
;
1121 static int snd_cs46xx_capture_hw_free(snd_pcm_substream_t
* substream
)
1123 cs46xx_t
*chip
= snd_pcm_substream_chip(substream
);
1124 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
1126 if (runtime
->dma_area
!= chip
->capt
.hw_buf
.area
)
1127 snd_pcm_lib_free_pages(substream
);
1128 runtime
->dma_area
= NULL
;
1129 runtime
->dma_addr
= 0;
1130 runtime
->dma_bytes
= 0;
1135 static int snd_cs46xx_capture_prepare(snd_pcm_substream_t
* substream
)
1137 cs46xx_t
*chip
= snd_pcm_substream_chip(substream
);
1138 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
1140 snd_cs46xx_poke(chip
, BA1_CBA
, chip
->capt
.hw_buf
.addr
);
1141 chip
->capt
.shift
= 2;
1142 memset(&chip
->capt
.pcm_rec
, 0, sizeof(chip
->capt
.pcm_rec
));
1143 chip
->capt
.pcm_rec
.sw_buffer_size
= snd_pcm_lib_buffer_bytes(substream
);
1144 chip
->capt
.pcm_rec
.hw_buffer_size
= runtime
->period_size
* CS46XX_FRAGS
<< 2;
1145 snd_cs46xx_set_capture_sample_rate(chip
, runtime
->rate
);
1150 static irqreturn_t
snd_cs46xx_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
1152 cs46xx_t
*chip
= dev_id
;
1154 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1155 dsp_spos_instance_t
* ins
= chip
->dsp_spos_instance
;
1158 cs46xx_pcm_t
*cpcm
= NULL
;
1162 * Read the Interrupt Status Register to clear the interrupt
1164 status1
= snd_cs46xx_peekBA0(chip
, BA0_HISR
);
1165 if ((status1
& 0x7fffffff) == 0) {
1166 snd_cs46xx_pokeBA0(chip
, BA0_HICR
, HICR_CHGM
| HICR_IEV
);
1170 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1171 status2
= snd_cs46xx_peekBA0(chip
, BA0_HSR0
);
1173 for (i
= 0; i
< DSP_MAX_PCM_CHANNELS
; ++i
) {
1175 if ( status1
& (1 << i
) ) {
1176 if (i
== CS46XX_DSP_CAPTURE_CHANNEL
) {
1177 if (chip
->capt
.substream
)
1178 snd_pcm_period_elapsed(chip
->capt
.substream
);
1180 if (ins
->pcm_channels
[i
].active
&&
1181 ins
->pcm_channels
[i
].private_data
&&
1182 !ins
->pcm_channels
[i
].unlinked
) {
1183 cpcm
= ins
->pcm_channels
[i
].private_data
;
1184 snd_pcm_period_elapsed(cpcm
->substream
);
1189 if ( status2
& (1 << (i
- 16))) {
1190 if (ins
->pcm_channels
[i
].active
&&
1191 ins
->pcm_channels
[i
].private_data
&&
1192 !ins
->pcm_channels
[i
].unlinked
) {
1193 cpcm
= ins
->pcm_channels
[i
].private_data
;
1194 snd_pcm_period_elapsed(cpcm
->substream
);
1202 if ((status1
& HISR_VC0
) && chip
->playback_pcm
) {
1203 if (chip
->playback_pcm
->substream
)
1204 snd_pcm_period_elapsed(chip
->playback_pcm
->substream
);
1206 if ((status1
& HISR_VC1
) && chip
->pcm
) {
1207 if (chip
->capt
.substream
)
1208 snd_pcm_period_elapsed(chip
->capt
.substream
);
1212 if ((status1
& HISR_MIDI
) && chip
->rmidi
) {
1215 spin_lock(&chip
->reg_lock
);
1216 while ((snd_cs46xx_peekBA0(chip
, BA0_MIDSR
) & MIDSR_RBE
) == 0) {
1217 c
= snd_cs46xx_peekBA0(chip
, BA0_MIDRP
);
1218 if ((chip
->midcr
& MIDCR_RIE
) == 0)
1220 snd_rawmidi_receive(chip
->midi_input
, &c
, 1);
1222 while ((snd_cs46xx_peekBA0(chip
, BA0_MIDSR
) & MIDSR_TBF
) == 0) {
1223 if ((chip
->midcr
& MIDCR_TIE
) == 0)
1225 if (snd_rawmidi_transmit(chip
->midi_output
, &c
, 1) != 1) {
1226 chip
->midcr
&= ~MIDCR_TIE
;
1227 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
1230 snd_cs46xx_pokeBA0(chip
, BA0_MIDWP
, c
);
1232 spin_unlock(&chip
->reg_lock
);
1235 * EOI to the PCI part....reenables interrupts
1237 snd_cs46xx_pokeBA0(chip
, BA0_HICR
, HICR_CHGM
| HICR_IEV
);
1242 static snd_pcm_hardware_t snd_cs46xx_playback
=
1244 .info
= (SNDRV_PCM_INFO_MMAP
|
1245 SNDRV_PCM_INFO_INTERLEAVED
|
1246 SNDRV_PCM_INFO_BLOCK_TRANSFER
|
1247 SNDRV_PCM_INFO_RESUME
),
1248 .formats
= (SNDRV_PCM_FMTBIT_S8
| SNDRV_PCM_FMTBIT_U8
|
1249 SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_S16_BE
|
1250 SNDRV_PCM_FMTBIT_U16_LE
| SNDRV_PCM_FMTBIT_U16_BE
),
1251 .rates
= SNDRV_PCM_RATE_CONTINUOUS
| SNDRV_PCM_RATE_8000_48000
,
1256 .buffer_bytes_max
= (256 * 1024),
1257 .period_bytes_min
= CS46XX_MIN_PERIOD_SIZE
,
1258 .period_bytes_max
= CS46XX_MAX_PERIOD_SIZE
,
1259 .periods_min
= CS46XX_FRAGS
,
1260 .periods_max
= 1024,
1264 static snd_pcm_hardware_t snd_cs46xx_capture
=
1266 .info
= (SNDRV_PCM_INFO_MMAP
|
1267 SNDRV_PCM_INFO_INTERLEAVED
|
1268 SNDRV_PCM_INFO_BLOCK_TRANSFER
|
1269 SNDRV_PCM_INFO_RESUME
),
1270 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1271 .rates
= SNDRV_PCM_RATE_CONTINUOUS
| SNDRV_PCM_RATE_8000_48000
,
1276 .buffer_bytes_max
= (256 * 1024),
1277 .period_bytes_min
= CS46XX_MIN_PERIOD_SIZE
,
1278 .period_bytes_max
= CS46XX_MAX_PERIOD_SIZE
,
1279 .periods_min
= CS46XX_FRAGS
,
1280 .periods_max
= 1024,
1284 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1286 static unsigned int period_sizes
[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1288 static snd_pcm_hw_constraint_list_t hw_constraints_period_sizes
= {
1289 .count
= ARRAY_SIZE(period_sizes
),
1290 .list
= period_sizes
,
1296 static void snd_cs46xx_pcm_free_substream(snd_pcm_runtime_t
*runtime
)
1298 kfree(runtime
->private_data
);
1301 static int _cs46xx_playback_open_channel (snd_pcm_substream_t
* substream
,int pcm_channel_id
)
1303 cs46xx_t
*chip
= snd_pcm_substream_chip(substream
);
1304 cs46xx_pcm_t
* cpcm
;
1305 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
1307 cpcm
= kcalloc(1, sizeof(*cpcm
), GFP_KERNEL
);
1310 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, snd_dma_pci_data(chip
->pci
),
1311 PAGE_SIZE
, &cpcm
->hw_buf
) < 0) {
1316 runtime
->hw
= snd_cs46xx_playback
;
1317 runtime
->private_data
= cpcm
;
1318 runtime
->private_free
= snd_cs46xx_pcm_free_substream
;
1320 cpcm
->substream
= substream
;
1321 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1322 down (&chip
->spos_mutex
);
1323 cpcm
->pcm_channel
= NULL
;
1324 cpcm
->pcm_channel_id
= pcm_channel_id
;
1327 snd_pcm_hw_constraint_list(runtime
, 0,
1328 SNDRV_PCM_HW_PARAM_PERIOD_BYTES
,
1329 &hw_constraints_period_sizes
);
1331 up (&chip
->spos_mutex
);
1333 chip
->playback_pcm
= cpcm
; /* HACK */
1336 if (chip
->accept_valid
)
1337 substream
->runtime
->hw
.info
|= SNDRV_PCM_INFO_MMAP_VALID
;
1338 chip
->active_ctrl(chip
, 1);
1343 static int snd_cs46xx_playback_open(snd_pcm_substream_t
* substream
)
1345 snd_printdd("open front channel\n");
1346 return _cs46xx_playback_open_channel(substream
,DSP_PCM_MAIN_CHANNEL
);
1349 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1350 static int snd_cs46xx_playback_open_rear(snd_pcm_substream_t
* substream
)
1352 snd_printdd("open rear channel\n");
1354 return _cs46xx_playback_open_channel(substream
,DSP_PCM_REAR_CHANNEL
);
1357 static int snd_cs46xx_playback_open_clfe(snd_pcm_substream_t
* substream
)
1359 snd_printdd("open center - LFE channel\n");
1361 return _cs46xx_playback_open_channel(substream
,DSP_PCM_CENTER_LFE_CHANNEL
);
1364 static int snd_cs46xx_playback_open_iec958(snd_pcm_substream_t
* substream
)
1366 cs46xx_t
*chip
= snd_pcm_substream_chip(substream
);
1368 snd_printdd("open raw iec958 channel\n");
1370 down (&chip
->spos_mutex
);
1371 cs46xx_iec958_pre_open (chip
);
1372 up (&chip
->spos_mutex
);
1374 return _cs46xx_playback_open_channel(substream
,DSP_IEC958_CHANNEL
);
1377 static int snd_cs46xx_playback_close(snd_pcm_substream_t
* substream
);
1379 static int snd_cs46xx_playback_close_iec958(snd_pcm_substream_t
* substream
)
1382 cs46xx_t
*chip
= snd_pcm_substream_chip(substream
);
1384 snd_printdd("close raw iec958 channel\n");
1386 err
= snd_cs46xx_playback_close(substream
);
1388 down (&chip
->spos_mutex
);
1389 cs46xx_iec958_post_close (chip
);
1390 up (&chip
->spos_mutex
);
1396 static int snd_cs46xx_capture_open(snd_pcm_substream_t
* substream
)
1398 cs46xx_t
*chip
= snd_pcm_substream_chip(substream
);
1400 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, snd_dma_pci_data(chip
->pci
),
1401 PAGE_SIZE
, &chip
->capt
.hw_buf
) < 0)
1403 chip
->capt
.substream
= substream
;
1404 substream
->runtime
->hw
= snd_cs46xx_capture
;
1406 if (chip
->accept_valid
)
1407 substream
->runtime
->hw
.info
|= SNDRV_PCM_INFO_MMAP_VALID
;
1409 chip
->active_ctrl(chip
, 1);
1411 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1412 snd_pcm_hw_constraint_list(substream
->runtime
, 0,
1413 SNDRV_PCM_HW_PARAM_PERIOD_BYTES
,
1414 &hw_constraints_period_sizes
);
1419 static int snd_cs46xx_playback_close(snd_pcm_substream_t
* substream
)
1421 cs46xx_t
*chip
= snd_pcm_substream_chip(substream
);
1422 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
1423 cs46xx_pcm_t
* cpcm
;
1425 cpcm
= runtime
->private_data
;
1427 /* when playback_open fails, then cpcm can be NULL */
1428 if (!cpcm
) return -ENXIO
;
1430 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1431 down (&chip
->spos_mutex
);
1432 if (cpcm
->pcm_channel
) {
1433 cs46xx_dsp_destroy_pcm_channel(chip
,cpcm
->pcm_channel
);
1434 cpcm
->pcm_channel
= NULL
;
1436 up (&chip
->spos_mutex
);
1438 chip
->playback_pcm
= NULL
;
1441 cpcm
->substream
= NULL
;
1442 snd_dma_free_pages(&cpcm
->hw_buf
);
1443 chip
->active_ctrl(chip
, -1);
1448 static int snd_cs46xx_capture_close(snd_pcm_substream_t
* substream
)
1450 cs46xx_t
*chip
= snd_pcm_substream_chip(substream
);
1452 chip
->capt
.substream
= NULL
;
1453 snd_dma_free_pages(&chip
->capt
.hw_buf
);
1454 chip
->active_ctrl(chip
, -1);
1459 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1460 static snd_pcm_ops_t snd_cs46xx_playback_rear_ops
= {
1461 .open
= snd_cs46xx_playback_open_rear
,
1462 .close
= snd_cs46xx_playback_close
,
1463 .ioctl
= snd_pcm_lib_ioctl
,
1464 .hw_params
= snd_cs46xx_playback_hw_params
,
1465 .hw_free
= snd_cs46xx_playback_hw_free
,
1466 .prepare
= snd_cs46xx_playback_prepare
,
1467 .trigger
= snd_cs46xx_playback_trigger
,
1468 .pointer
= snd_cs46xx_playback_direct_pointer
,
1471 static snd_pcm_ops_t snd_cs46xx_playback_indirect_rear_ops
= {
1472 .open
= snd_cs46xx_playback_open_rear
,
1473 .close
= snd_cs46xx_playback_close
,
1474 .ioctl
= snd_pcm_lib_ioctl
,
1475 .hw_params
= snd_cs46xx_playback_hw_params
,
1476 .hw_free
= snd_cs46xx_playback_hw_free
,
1477 .prepare
= snd_cs46xx_playback_prepare
,
1478 .trigger
= snd_cs46xx_playback_trigger
,
1479 .pointer
= snd_cs46xx_playback_indirect_pointer
,
1480 .ack
= snd_cs46xx_playback_transfer
,
1483 static snd_pcm_ops_t snd_cs46xx_playback_clfe_ops
= {
1484 .open
= snd_cs46xx_playback_open_clfe
,
1485 .close
= snd_cs46xx_playback_close
,
1486 .ioctl
= snd_pcm_lib_ioctl
,
1487 .hw_params
= snd_cs46xx_playback_hw_params
,
1488 .hw_free
= snd_cs46xx_playback_hw_free
,
1489 .prepare
= snd_cs46xx_playback_prepare
,
1490 .trigger
= snd_cs46xx_playback_trigger
,
1491 .pointer
= snd_cs46xx_playback_direct_pointer
,
1494 static snd_pcm_ops_t snd_cs46xx_playback_indirect_clfe_ops
= {
1495 .open
= snd_cs46xx_playback_open_clfe
,
1496 .close
= snd_cs46xx_playback_close
,
1497 .ioctl
= snd_pcm_lib_ioctl
,
1498 .hw_params
= snd_cs46xx_playback_hw_params
,
1499 .hw_free
= snd_cs46xx_playback_hw_free
,
1500 .prepare
= snd_cs46xx_playback_prepare
,
1501 .trigger
= snd_cs46xx_playback_trigger
,
1502 .pointer
= snd_cs46xx_playback_indirect_pointer
,
1503 .ack
= snd_cs46xx_playback_transfer
,
1506 static snd_pcm_ops_t snd_cs46xx_playback_iec958_ops
= {
1507 .open
= snd_cs46xx_playback_open_iec958
,
1508 .close
= snd_cs46xx_playback_close_iec958
,
1509 .ioctl
= snd_pcm_lib_ioctl
,
1510 .hw_params
= snd_cs46xx_playback_hw_params
,
1511 .hw_free
= snd_cs46xx_playback_hw_free
,
1512 .prepare
= snd_cs46xx_playback_prepare
,
1513 .trigger
= snd_cs46xx_playback_trigger
,
1514 .pointer
= snd_cs46xx_playback_direct_pointer
,
1517 static snd_pcm_ops_t snd_cs46xx_playback_indirect_iec958_ops
= {
1518 .open
= snd_cs46xx_playback_open_iec958
,
1519 .close
= snd_cs46xx_playback_close_iec958
,
1520 .ioctl
= snd_pcm_lib_ioctl
,
1521 .hw_params
= snd_cs46xx_playback_hw_params
,
1522 .hw_free
= snd_cs46xx_playback_hw_free
,
1523 .prepare
= snd_cs46xx_playback_prepare
,
1524 .trigger
= snd_cs46xx_playback_trigger
,
1525 .pointer
= snd_cs46xx_playback_indirect_pointer
,
1526 .ack
= snd_cs46xx_playback_transfer
,
1531 static snd_pcm_ops_t snd_cs46xx_playback_ops
= {
1532 .open
= snd_cs46xx_playback_open
,
1533 .close
= snd_cs46xx_playback_close
,
1534 .ioctl
= snd_pcm_lib_ioctl
,
1535 .hw_params
= snd_cs46xx_playback_hw_params
,
1536 .hw_free
= snd_cs46xx_playback_hw_free
,
1537 .prepare
= snd_cs46xx_playback_prepare
,
1538 .trigger
= snd_cs46xx_playback_trigger
,
1539 .pointer
= snd_cs46xx_playback_direct_pointer
,
1542 static snd_pcm_ops_t snd_cs46xx_playback_indirect_ops
= {
1543 .open
= snd_cs46xx_playback_open
,
1544 .close
= snd_cs46xx_playback_close
,
1545 .ioctl
= snd_pcm_lib_ioctl
,
1546 .hw_params
= snd_cs46xx_playback_hw_params
,
1547 .hw_free
= snd_cs46xx_playback_hw_free
,
1548 .prepare
= snd_cs46xx_playback_prepare
,
1549 .trigger
= snd_cs46xx_playback_trigger
,
1550 .pointer
= snd_cs46xx_playback_indirect_pointer
,
1551 .ack
= snd_cs46xx_playback_transfer
,
1554 static snd_pcm_ops_t snd_cs46xx_capture_ops
= {
1555 .open
= snd_cs46xx_capture_open
,
1556 .close
= snd_cs46xx_capture_close
,
1557 .ioctl
= snd_pcm_lib_ioctl
,
1558 .hw_params
= snd_cs46xx_capture_hw_params
,
1559 .hw_free
= snd_cs46xx_capture_hw_free
,
1560 .prepare
= snd_cs46xx_capture_prepare
,
1561 .trigger
= snd_cs46xx_capture_trigger
,
1562 .pointer
= snd_cs46xx_capture_direct_pointer
,
1565 static snd_pcm_ops_t snd_cs46xx_capture_indirect_ops
= {
1566 .open
= snd_cs46xx_capture_open
,
1567 .close
= snd_cs46xx_capture_close
,
1568 .ioctl
= snd_pcm_lib_ioctl
,
1569 .hw_params
= snd_cs46xx_capture_hw_params
,
1570 .hw_free
= snd_cs46xx_capture_hw_free
,
1571 .prepare
= snd_cs46xx_capture_prepare
,
1572 .trigger
= snd_cs46xx_capture_trigger
,
1573 .pointer
= snd_cs46xx_capture_indirect_pointer
,
1574 .ack
= snd_cs46xx_capture_transfer
,
1577 static void snd_cs46xx_pcm_free(snd_pcm_t
*pcm
)
1579 cs46xx_t
*chip
= pcm
->private_data
;
1581 snd_pcm_lib_preallocate_free_for_all(pcm
);
1584 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1585 static void snd_cs46xx_pcm_rear_free(snd_pcm_t
*pcm
)
1587 cs46xx_t
*chip
= pcm
->private_data
;
1588 chip
->pcm_rear
= NULL
;
1589 snd_pcm_lib_preallocate_free_for_all(pcm
);
1592 static void snd_cs46xx_pcm_center_lfe_free(snd_pcm_t
*pcm
)
1594 cs46xx_t
*chip
= pcm
->private_data
;
1595 chip
->pcm_center_lfe
= NULL
;
1596 snd_pcm_lib_preallocate_free_for_all(pcm
);
1599 static void snd_cs46xx_pcm_iec958_free(snd_pcm_t
*pcm
)
1601 cs46xx_t
*chip
= pcm
->private_data
;
1602 chip
->pcm_iec958
= NULL
;
1603 snd_pcm_lib_preallocate_free_for_all(pcm
);
1606 #define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1)
1608 #define MAX_PLAYBACK_CHANNELS 1
1611 int __devinit
snd_cs46xx_pcm(cs46xx_t
*chip
, int device
, snd_pcm_t
** rpcm
)
1618 if ((err
= snd_pcm_new(chip
->card
, "CS46xx", device
, MAX_PLAYBACK_CHANNELS
, 1, &pcm
)) < 0)
1621 pcm
->private_data
= chip
;
1622 pcm
->private_free
= snd_cs46xx_pcm_free
;
1624 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_cs46xx_playback_ops
);
1625 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_CAPTURE
, &snd_cs46xx_capture_ops
);
1628 pcm
->info_flags
= 0;
1629 strcpy(pcm
->name
, "CS46xx");
1632 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1633 snd_dma_pci_data(chip
->pci
), 64*1024, 256*1024);
1642 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1643 int __devinit
snd_cs46xx_pcm_rear(cs46xx_t
*chip
, int device
, snd_pcm_t
** rpcm
)
1651 if ((err
= snd_pcm_new(chip
->card
, "CS46xx - Rear", device
, MAX_PLAYBACK_CHANNELS
, 0, &pcm
)) < 0)
1654 pcm
->private_data
= chip
;
1655 pcm
->private_free
= snd_cs46xx_pcm_rear_free
;
1657 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_cs46xx_playback_rear_ops
);
1660 pcm
->info_flags
= 0;
1661 strcpy(pcm
->name
, "CS46xx - Rear");
1662 chip
->pcm_rear
= pcm
;
1664 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1665 snd_dma_pci_data(chip
->pci
), 64*1024, 256*1024);
1673 int __devinit
snd_cs46xx_pcm_center_lfe(cs46xx_t
*chip
, int device
, snd_pcm_t
** rpcm
)
1681 if ((err
= snd_pcm_new(chip
->card
, "CS46xx - Center LFE", device
, MAX_PLAYBACK_CHANNELS
, 0, &pcm
)) < 0)
1684 pcm
->private_data
= chip
;
1685 pcm
->private_free
= snd_cs46xx_pcm_center_lfe_free
;
1687 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_cs46xx_playback_clfe_ops
);
1690 pcm
->info_flags
= 0;
1691 strcpy(pcm
->name
, "CS46xx - Center LFE");
1692 chip
->pcm_center_lfe
= pcm
;
1694 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1695 snd_dma_pci_data(chip
->pci
), 64*1024, 256*1024);
1703 int __devinit
snd_cs46xx_pcm_iec958(cs46xx_t
*chip
, int device
, snd_pcm_t
** rpcm
)
1711 if ((err
= snd_pcm_new(chip
->card
, "CS46xx - IEC958", device
, 1, 0, &pcm
)) < 0)
1714 pcm
->private_data
= chip
;
1715 pcm
->private_free
= snd_cs46xx_pcm_iec958_free
;
1717 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_cs46xx_playback_iec958_ops
);
1720 pcm
->info_flags
= 0;
1721 strcpy(pcm
->name
, "CS46xx - IEC958");
1722 chip
->pcm_rear
= pcm
;
1724 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1725 snd_dma_pci_data(chip
->pci
), 64*1024, 256*1024);
1737 static void snd_cs46xx_mixer_free_ac97_bus(ac97_bus_t
*bus
)
1739 cs46xx_t
*chip
= bus
->private_data
;
1741 chip
->ac97_bus
= NULL
;
1744 static void snd_cs46xx_mixer_free_ac97(ac97_t
*ac97
)
1746 cs46xx_t
*chip
= ac97
->private_data
;
1748 snd_assert ((ac97
== chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
]) ||
1749 (ac97
== chip
->ac97
[CS46XX_SECONDARY_CODEC_INDEX
]),
1752 if (ac97
== chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
]) {
1753 chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
] = NULL
;
1754 chip
->eapd_switch
= NULL
;
1757 chip
->ac97
[CS46XX_SECONDARY_CODEC_INDEX
] = NULL
;
1760 static int snd_cs46xx_vol_info(snd_kcontrol_t
*kcontrol
,
1761 snd_ctl_elem_info_t
*uinfo
)
1763 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_INTEGER
;
1765 uinfo
->value
.integer
.min
= 0;
1766 uinfo
->value
.integer
.max
= 0x7fff;
1770 static int snd_cs46xx_vol_get(snd_kcontrol_t
* kcontrol
, snd_ctl_elem_value_t
* ucontrol
)
1772 cs46xx_t
*chip
= snd_kcontrol_chip(kcontrol
);
1773 int reg
= kcontrol
->private_value
;
1774 unsigned int val
= snd_cs46xx_peek(chip
, reg
);
1775 ucontrol
->value
.integer
.value
[0] = 0xffff - (val
>> 16);
1776 ucontrol
->value
.integer
.value
[1] = 0xffff - (val
& 0xffff);
1780 static int snd_cs46xx_vol_put(snd_kcontrol_t
* kcontrol
, snd_ctl_elem_value_t
* ucontrol
)
1782 cs46xx_t
*chip
= snd_kcontrol_chip(kcontrol
);
1783 int reg
= kcontrol
->private_value
;
1784 unsigned int val
= ((0xffff - ucontrol
->value
.integer
.value
[0]) << 16 |
1785 (0xffff - ucontrol
->value
.integer
.value
[1]));
1786 unsigned int old
= snd_cs46xx_peek(chip
, reg
);
1787 int change
= (old
!= val
);
1790 snd_cs46xx_poke(chip
, reg
, val
);
1796 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1798 static int snd_cs46xx_vol_dac_get(snd_kcontrol_t
* kcontrol
, snd_ctl_elem_value_t
* ucontrol
)
1800 cs46xx_t
*chip
= snd_kcontrol_chip(kcontrol
);
1802 ucontrol
->value
.integer
.value
[0] = chip
->dsp_spos_instance
->dac_volume_left
;
1803 ucontrol
->value
.integer
.value
[1] = chip
->dsp_spos_instance
->dac_volume_right
;
1808 static int snd_cs46xx_vol_dac_put(snd_kcontrol_t
* kcontrol
, snd_ctl_elem_value_t
* ucontrol
)
1810 cs46xx_t
*chip
= snd_kcontrol_chip(kcontrol
);
1813 if (chip
->dsp_spos_instance
->dac_volume_right
!= ucontrol
->value
.integer
.value
[0] ||
1814 chip
->dsp_spos_instance
->dac_volume_left
!= ucontrol
->value
.integer
.value
[1]) {
1815 cs46xx_dsp_set_dac_volume(chip
,
1816 ucontrol
->value
.integer
.value
[0],
1817 ucontrol
->value
.integer
.value
[1]);
1825 static int snd_cs46xx_vol_iec958_get(snd_kcontrol_t
* kcontrol
, snd_ctl_elem_value_t
* ucontrol
)
1827 cs46xx_t
*chip
= snd_kcontrol_chip(kcontrol
);
1829 ucontrol
->value
.integer
.value
[0] = chip
->dsp_spos_instance
->spdif_input_volume_left
;
1830 ucontrol
->value
.integer
.value
[1] = chip
->dsp_spos_instance
->spdif_input_volume_right
;
1834 static int snd_cs46xx_vol_iec958_put(snd_kcontrol_t
* kcontrol
, snd_ctl_elem_value_t
* ucontrol
)
1836 cs46xx_t
*chip
= snd_kcontrol_chip(kcontrol
);
1839 if (chip
->dsp_spos_instance
->spdif_input_volume_left
!= ucontrol
->value
.integer
.value
[0] ||
1840 chip
->dsp_spos_instance
->spdif_input_volume_right
!= ucontrol
->value
.integer
.value
[1]) {
1841 cs46xx_dsp_set_iec958_volume (chip
,
1842 ucontrol
->value
.integer
.value
[0],
1843 ucontrol
->value
.integer
.value
[1]);
1851 static int snd_mixer_boolean_info(snd_kcontrol_t
*kcontrol
,
1852 snd_ctl_elem_info_t
*uinfo
)
1854 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BOOLEAN
;
1856 uinfo
->value
.integer
.min
= 0;
1857 uinfo
->value
.integer
.max
= 1;
1861 static int snd_cs46xx_iec958_get(snd_kcontrol_t
*kcontrol
,
1862 snd_ctl_elem_value_t
*ucontrol
)
1864 cs46xx_t
*chip
= snd_kcontrol_chip(kcontrol
);
1865 int reg
= kcontrol
->private_value
;
1867 if (reg
== CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT
)
1868 ucontrol
->value
.integer
.value
[0] = (chip
->dsp_spos_instance
->spdif_status_out
& DSP_SPDIF_STATUS_OUTPUT_ENABLED
);
1870 ucontrol
->value
.integer
.value
[0] = chip
->dsp_spos_instance
->spdif_status_in
;
1875 static int snd_cs46xx_iec958_put(snd_kcontrol_t
*kcontrol
,
1876 snd_ctl_elem_value_t
*ucontrol
)
1878 cs46xx_t
*chip
= snd_kcontrol_chip(kcontrol
);
1881 switch (kcontrol
->private_value
) {
1882 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT
:
1883 down (&chip
->spos_mutex
);
1884 change
= (chip
->dsp_spos_instance
->spdif_status_out
& DSP_SPDIF_STATUS_OUTPUT_ENABLED
);
1885 if (ucontrol
->value
.integer
.value
[0] && !change
)
1886 cs46xx_dsp_enable_spdif_out(chip
);
1887 else if (change
&& !ucontrol
->value
.integer
.value
[0])
1888 cs46xx_dsp_disable_spdif_out(chip
);
1890 res
= (change
!= (chip
->dsp_spos_instance
->spdif_status_out
& DSP_SPDIF_STATUS_OUTPUT_ENABLED
));
1891 up (&chip
->spos_mutex
);
1893 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT
:
1894 change
= chip
->dsp_spos_instance
->spdif_status_in
;
1895 if (ucontrol
->value
.integer
.value
[0] && !change
) {
1896 cs46xx_dsp_enable_spdif_in(chip
);
1897 /* restore volume */
1899 else if (change
&& !ucontrol
->value
.integer
.value
[0])
1900 cs46xx_dsp_disable_spdif_in(chip
);
1902 res
= (change
!= chip
->dsp_spos_instance
->spdif_status_in
);
1906 snd_assert(0, (void)0);
1912 static int snd_cs46xx_adc_capture_get(snd_kcontrol_t
*kcontrol
,
1913 snd_ctl_elem_value_t
*ucontrol
)
1915 cs46xx_t
*chip
= snd_kcontrol_chip(kcontrol
);
1916 dsp_spos_instance_t
* ins
= chip
->dsp_spos_instance
;
1918 if (ins
->adc_input
!= NULL
)
1919 ucontrol
->value
.integer
.value
[0] = 1;
1921 ucontrol
->value
.integer
.value
[0] = 0;
1926 static int snd_cs46xx_adc_capture_put(snd_kcontrol_t
*kcontrol
,
1927 snd_ctl_elem_value_t
*ucontrol
)
1929 cs46xx_t
*chip
= snd_kcontrol_chip(kcontrol
);
1930 dsp_spos_instance_t
* ins
= chip
->dsp_spos_instance
;
1933 if (ucontrol
->value
.integer
.value
[0] && !ins
->adc_input
) {
1934 cs46xx_dsp_enable_adc_capture(chip
);
1936 } else if (!ucontrol
->value
.integer
.value
[0] && ins
->adc_input
) {
1937 cs46xx_dsp_disable_adc_capture(chip
);
1943 static int snd_cs46xx_pcm_capture_get(snd_kcontrol_t
*kcontrol
,
1944 snd_ctl_elem_value_t
*ucontrol
)
1946 cs46xx_t
*chip
= snd_kcontrol_chip(kcontrol
);
1947 dsp_spos_instance_t
* ins
= chip
->dsp_spos_instance
;
1949 if (ins
->pcm_input
!= NULL
)
1950 ucontrol
->value
.integer
.value
[0] = 1;
1952 ucontrol
->value
.integer
.value
[0] = 0;
1958 static int snd_cs46xx_pcm_capture_put(snd_kcontrol_t
*kcontrol
,
1959 snd_ctl_elem_value_t
*ucontrol
)
1961 cs46xx_t
*chip
= snd_kcontrol_chip(kcontrol
);
1962 dsp_spos_instance_t
* ins
= chip
->dsp_spos_instance
;
1965 if (ucontrol
->value
.integer
.value
[0] && !ins
->pcm_input
) {
1966 cs46xx_dsp_enable_pcm_capture(chip
);
1968 } else if (!ucontrol
->value
.integer
.value
[0] && ins
->pcm_input
) {
1969 cs46xx_dsp_disable_pcm_capture(chip
);
1976 static int snd_herc_spdif_select_get(snd_kcontrol_t
*kcontrol
,
1977 snd_ctl_elem_value_t
*ucontrol
)
1979 cs46xx_t
*chip
= snd_kcontrol_chip(kcontrol
);
1981 int val1
= snd_cs46xx_peekBA0(chip
, BA0_EGPIODR
);
1983 if (val1
& EGPIODR_GPOE0
)
1984 ucontrol
->value
.integer
.value
[0] = 1;
1986 ucontrol
->value
.integer
.value
[0] = 0;
1992 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
1994 static int snd_herc_spdif_select_put(snd_kcontrol_t
*kcontrol
,
1995 snd_ctl_elem_value_t
*ucontrol
)
1997 cs46xx_t
*chip
= snd_kcontrol_chip(kcontrol
);
1998 int val1
= snd_cs46xx_peekBA0(chip
, BA0_EGPIODR
);
1999 int val2
= snd_cs46xx_peekBA0(chip
, BA0_EGPIOPTR
);
2001 if (ucontrol
->value
.integer
.value
[0]) {
2002 /* optical is default */
2003 snd_cs46xx_pokeBA0(chip
, BA0_EGPIODR
,
2004 EGPIODR_GPOE0
| val1
); /* enable EGPIO0 output */
2005 snd_cs46xx_pokeBA0(chip
, BA0_EGPIOPTR
,
2006 EGPIOPTR_GPPT0
| val2
); /* open-drain on output */
2009 snd_cs46xx_pokeBA0(chip
, BA0_EGPIODR
, val1
& ~EGPIODR_GPOE0
); /* disable */
2010 snd_cs46xx_pokeBA0(chip
, BA0_EGPIOPTR
, val2
& ~EGPIOPTR_GPPT0
); /* disable */
2013 /* checking diff from the EGPIO direction register
2015 return (val1
!= (int)snd_cs46xx_peekBA0(chip
, BA0_EGPIODR
));
2019 static int snd_cs46xx_spdif_info(snd_kcontrol_t
*kcontrol
, snd_ctl_elem_info_t
* uinfo
)
2021 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
2026 static int snd_cs46xx_spdif_default_get(snd_kcontrol_t
* kcontrol
,
2027 snd_ctl_elem_value_t
* ucontrol
)
2029 cs46xx_t
*chip
= snd_kcontrol_chip(kcontrol
);
2030 dsp_spos_instance_t
* ins
= chip
->dsp_spos_instance
;
2032 down (&chip
->spos_mutex
);
2033 ucontrol
->value
.iec958
.status
[0] = _wrap_all_bits((ins
->spdif_csuv_default
>> 24) & 0xff);
2034 ucontrol
->value
.iec958
.status
[1] = _wrap_all_bits((ins
->spdif_csuv_default
>> 16) & 0xff);
2035 ucontrol
->value
.iec958
.status
[2] = 0;
2036 ucontrol
->value
.iec958
.status
[3] = _wrap_all_bits((ins
->spdif_csuv_default
) & 0xff);
2037 up (&chip
->spos_mutex
);
2042 static int snd_cs46xx_spdif_default_put(snd_kcontrol_t
* kcontrol
,
2043 snd_ctl_elem_value_t
* ucontrol
)
2045 cs46xx_t
* chip
= snd_kcontrol_chip(kcontrol
);
2046 dsp_spos_instance_t
* ins
= chip
->dsp_spos_instance
;
2050 down (&chip
->spos_mutex
);
2051 val
= ((unsigned int)_wrap_all_bits(ucontrol
->value
.iec958
.status
[0]) << 24) |
2052 ((unsigned int)_wrap_all_bits(ucontrol
->value
.iec958
.status
[2]) << 16) |
2053 ((unsigned int)_wrap_all_bits(ucontrol
->value
.iec958
.status
[3])) |
2054 /* left and right validity bit */
2055 (1 << 13) | (1 << 12);
2058 change
= (unsigned int)ins
->spdif_csuv_default
!= val
;
2059 ins
->spdif_csuv_default
= val
;
2061 if ( !(ins
->spdif_status_out
& DSP_SPDIF_STATUS_PLAYBACK_OPEN
) )
2062 cs46xx_poke_via_dsp (chip
,SP_SPDOUT_CSUV
,val
);
2064 up (&chip
->spos_mutex
);
2069 static int snd_cs46xx_spdif_mask_get(snd_kcontrol_t
* kcontrol
,
2070 snd_ctl_elem_value_t
* ucontrol
)
2072 ucontrol
->value
.iec958
.status
[0] = 0xff;
2073 ucontrol
->value
.iec958
.status
[1] = 0xff;
2074 ucontrol
->value
.iec958
.status
[2] = 0x00;
2075 ucontrol
->value
.iec958
.status
[3] = 0xff;
2079 static int snd_cs46xx_spdif_stream_get(snd_kcontrol_t
* kcontrol
,
2080 snd_ctl_elem_value_t
* ucontrol
)
2082 cs46xx_t
*chip
= snd_kcontrol_chip(kcontrol
);
2083 dsp_spos_instance_t
* ins
= chip
->dsp_spos_instance
;
2085 down (&chip
->spos_mutex
);
2086 ucontrol
->value
.iec958
.status
[0] = _wrap_all_bits((ins
->spdif_csuv_stream
>> 24) & 0xff);
2087 ucontrol
->value
.iec958
.status
[1] = _wrap_all_bits((ins
->spdif_csuv_stream
>> 16) & 0xff);
2088 ucontrol
->value
.iec958
.status
[2] = 0;
2089 ucontrol
->value
.iec958
.status
[3] = _wrap_all_bits((ins
->spdif_csuv_stream
) & 0xff);
2090 up (&chip
->spos_mutex
);
2095 static int snd_cs46xx_spdif_stream_put(snd_kcontrol_t
* kcontrol
,
2096 snd_ctl_elem_value_t
* ucontrol
)
2098 cs46xx_t
* chip
= snd_kcontrol_chip(kcontrol
);
2099 dsp_spos_instance_t
* ins
= chip
->dsp_spos_instance
;
2103 down (&chip
->spos_mutex
);
2104 val
= ((unsigned int)_wrap_all_bits(ucontrol
->value
.iec958
.status
[0]) << 24) |
2105 ((unsigned int)_wrap_all_bits(ucontrol
->value
.iec958
.status
[1]) << 16) |
2106 ((unsigned int)_wrap_all_bits(ucontrol
->value
.iec958
.status
[3])) |
2107 /* left and right validity bit */
2108 (1 << 13) | (1 << 12);
2111 change
= ins
->spdif_csuv_stream
!= val
;
2112 ins
->spdif_csuv_stream
= val
;
2114 if ( ins
->spdif_status_out
& DSP_SPDIF_STATUS_PLAYBACK_OPEN
)
2115 cs46xx_poke_via_dsp (chip
,SP_SPDOUT_CSUV
,val
);
2117 up (&chip
->spos_mutex
);
2122 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2125 #ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
2126 static int snd_cs46xx_egpio_select_info(snd_kcontrol_t
*kcontrol
,
2127 snd_ctl_elem_info_t
*uinfo
)
2129 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_INTEGER
;
2131 uinfo
->value
.integer
.min
= 0;
2132 uinfo
->value
.integer
.max
= 8;
2136 static int snd_cs46xx_egpio_select_get(snd_kcontrol_t
*kcontrol
,
2137 snd_ctl_elem_value_t
*ucontrol
)
2139 cs46xx_t
*chip
= snd_kcontrol_chip(kcontrol
);
2140 ucontrol
->value
.integer
.value
[0] = chip
->current_gpio
;
2145 static int snd_cs46xx_egpio_select_put(snd_kcontrol_t
*kcontrol
,
2146 snd_ctl_elem_value_t
*ucontrol
)
2148 cs46xx_t
*chip
= snd_kcontrol_chip(kcontrol
);
2149 int change
= (chip
->current_gpio
!= ucontrol
->value
.integer
.value
[0]);
2150 chip
->current_gpio
= ucontrol
->value
.integer
.value
[0];
2156 static int snd_cs46xx_egpio_get(snd_kcontrol_t
*kcontrol
,
2157 snd_ctl_elem_value_t
*ucontrol
)
2159 cs46xx_t
*chip
= snd_kcontrol_chip(kcontrol
);
2160 int reg
= kcontrol
->private_value
;
2162 snd_printdd ("put: reg = %04x, gpio %02x\n",reg
,chip
->current_gpio
);
2163 ucontrol
->value
.integer
.value
[0] =
2164 (snd_cs46xx_peekBA0(chip
, reg
) & (1 << chip
->current_gpio
)) ? 1 : 0;
2169 static int snd_cs46xx_egpio_put(snd_kcontrol_t
*kcontrol
,
2170 snd_ctl_elem_value_t
*ucontrol
)
2172 cs46xx_t
*chip
= snd_kcontrol_chip(kcontrol
);
2173 int reg
= kcontrol
->private_value
;
2174 int val
= snd_cs46xx_peekBA0(chip
, reg
);
2176 snd_printdd ("put: reg = %04x, gpio %02x\n",reg
,chip
->current_gpio
);
2178 if (ucontrol
->value
.integer
.value
[0])
2179 val
|= (1 << chip
->current_gpio
);
2181 val
&= ~(1 << chip
->current_gpio
);
2183 snd_cs46xx_pokeBA0(chip
, reg
,val
);
2184 snd_printdd ("put: val %08x oldval %08x\n",val
,oldval
);
2186 return (oldval
!= val
);
2188 #endif /* CONFIG_SND_CS46XX_DEBUG_GPIO */
2190 static snd_kcontrol_new_t snd_cs46xx_controls
[] __devinitdata
= {
2192 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2193 .name
= "DAC Volume",
2194 .info
= snd_cs46xx_vol_info
,
2195 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2196 .get
= snd_cs46xx_vol_get
,
2197 .put
= snd_cs46xx_vol_put
,
2198 .private_value
= BA1_PVOL
,
2200 .get
= snd_cs46xx_vol_dac_get
,
2201 .put
= snd_cs46xx_vol_dac_put
,
2206 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2207 .name
= "ADC Volume",
2208 .info
= snd_cs46xx_vol_info
,
2209 .get
= snd_cs46xx_vol_get
,
2210 .put
= snd_cs46xx_vol_put
,
2211 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2212 .private_value
= BA1_CVOL
,
2214 .private_value
= (VARIDECIMATE_SCB_ADDR
+ 0xE) << 2,
2217 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2219 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2220 .name
= "ADC Capture Switch",
2221 .info
= snd_mixer_boolean_info
,
2222 .get
= snd_cs46xx_adc_capture_get
,
2223 .put
= snd_cs46xx_adc_capture_put
2226 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2227 .name
= "DAC Capture Switch",
2228 .info
= snd_mixer_boolean_info
,
2229 .get
= snd_cs46xx_pcm_capture_get
,
2230 .put
= snd_cs46xx_pcm_capture_put
2233 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2234 .name
= "IEC958 Output Switch",
2235 .info
= snd_mixer_boolean_info
,
2236 .get
= snd_cs46xx_iec958_get
,
2237 .put
= snd_cs46xx_iec958_put
,
2238 .private_value
= CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT
,
2241 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2242 .name
= "IEC958 Input Switch",
2243 .info
= snd_mixer_boolean_info
,
2244 .get
= snd_cs46xx_iec958_get
,
2245 .put
= snd_cs46xx_iec958_put
,
2246 .private_value
= CS46XX_MIXER_SPDIF_INPUT_ELEMENT
,
2249 /* Input IEC958 volume does not work for the moment. (Benny) */
2251 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2252 .name
= "IEC958 Input Volume",
2253 .info
= snd_cs46xx_vol_info
,
2254 .get
= snd_cs46xx_vol_iec958_get
,
2255 .put
= snd_cs46xx_vol_iec958_put
,
2256 .private_value
= (ASYNCRX_SCB_ADDR
+ 0xE) << 2,
2260 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2261 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,DEFAULT
),
2262 .info
= snd_cs46xx_spdif_info
,
2263 .get
= snd_cs46xx_spdif_default_get
,
2264 .put
= snd_cs46xx_spdif_default_put
,
2267 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2268 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,MASK
),
2269 .info
= snd_cs46xx_spdif_info
,
2270 .get
= snd_cs46xx_spdif_mask_get
,
2271 .access
= SNDRV_CTL_ELEM_ACCESS_READ
2274 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2275 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,PCM_STREAM
),
2276 .info
= snd_cs46xx_spdif_info
,
2277 .get
= snd_cs46xx_spdif_stream_get
,
2278 .put
= snd_cs46xx_spdif_stream_put
2282 #ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
2284 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2285 .name
= "EGPIO select",
2286 .info
= snd_cs46xx_egpio_select_info
,
2287 .get
= snd_cs46xx_egpio_select_get
,
2288 .put
= snd_cs46xx_egpio_select_put
,
2292 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2293 .name
= "EGPIO Input/Output",
2294 .info
= snd_mixer_boolean_info
,
2295 .get
= snd_cs46xx_egpio_get
,
2296 .put
= snd_cs46xx_egpio_put
,
2297 .private_value
= BA0_EGPIODR
,
2300 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2301 .name
= "EGPIO CMOS/Open drain",
2302 .info
= snd_mixer_boolean_info
,
2303 .get
= snd_cs46xx_egpio_get
,
2304 .put
= snd_cs46xx_egpio_put
,
2305 .private_value
= BA0_EGPIOPTR
,
2308 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2309 .name
= "EGPIO On/Off",
2310 .info
= snd_mixer_boolean_info
,
2311 .get
= snd_cs46xx_egpio_get
,
2312 .put
= snd_cs46xx_egpio_put
,
2313 .private_value
= BA0_EGPIOSR
,
2318 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2319 /* set primary cs4294 codec into Extended Audio Mode */
2320 static int snd_cs46xx_front_dup_get(snd_kcontrol_t
*kcontrol
,
2321 snd_ctl_elem_value_t
*ucontrol
)
2323 cs46xx_t
*chip
= snd_kcontrol_chip(kcontrol
);
2325 val
= snd_ac97_read(chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
], AC97_CSR_ACMODE
);
2326 ucontrol
->value
.integer
.value
[0] = (val
& 0x200) ? 0 : 1;
2330 static int snd_cs46xx_front_dup_put(snd_kcontrol_t
*kcontrol
,
2331 snd_ctl_elem_value_t
*ucontrol
)
2333 cs46xx_t
*chip
= snd_kcontrol_chip(kcontrol
);
2334 return snd_ac97_update_bits(chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
],
2335 AC97_CSR_ACMODE
, 0x200,
2336 ucontrol
->value
.integer
.value
[0] ? 0 : 0x200);
2339 static snd_kcontrol_new_t snd_cs46xx_front_dup_ctl
= {
2340 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2341 .name
= "Duplicate Front",
2342 .info
= snd_mixer_boolean_info
,
2343 .get
= snd_cs46xx_front_dup_get
,
2344 .put
= snd_cs46xx_front_dup_put
,
2348 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2349 /* Only available on the Hercules Game Theater XP soundcard */
2350 static snd_kcontrol_new_t snd_hercules_controls
[] __devinitdata
= {
2352 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2353 .name
= "Optical/Coaxial SPDIF Input Switch",
2354 .info
= snd_mixer_boolean_info
,
2355 .get
= snd_herc_spdif_select_get
,
2356 .put
= snd_herc_spdif_select_put
,
2361 static void snd_cs46xx_codec_reset (ac97_t
* ac97
)
2363 unsigned long end_time
;
2366 /* reset to defaults */
2367 snd_ac97_write(ac97
, AC97_RESET
, 0);
2369 /* set the desired CODEC mode */
2370 if (ac97
->num
== CS46XX_PRIMARY_CODEC_INDEX
) {
2371 snd_printdd("cs46xx: CODOEC1 mode %04x\n",0x0);
2372 snd_cs46xx_ac97_write(ac97
,AC97_CSR_ACMODE
,0x0);
2373 } else if (ac97
->num
== CS46XX_SECONDARY_CODEC_INDEX
) {
2374 snd_printdd("cs46xx: CODOEC2 mode %04x\n",0x3);
2375 snd_cs46xx_ac97_write(ac97
,AC97_CSR_ACMODE
,0x3);
2377 snd_assert(0); /* should never happen ... */
2382 /* it's necessary to wait awhile until registers are accessible after RESET */
2383 /* because the PCM or MASTER volume registers can be modified, */
2384 /* the REC_GAIN register is used for tests */
2385 end_time
= jiffies
+ HZ
;
2387 unsigned short ext_mid
;
2389 /* use preliminary reads to settle the communication */
2390 snd_ac97_read(ac97
, AC97_RESET
);
2391 snd_ac97_read(ac97
, AC97_VENDOR_ID1
);
2392 snd_ac97_read(ac97
, AC97_VENDOR_ID2
);
2394 ext_mid
= snd_ac97_read(ac97
, AC97_EXTENDED_MID
);
2395 if (ext_mid
!= 0xffff && (ext_mid
& 1) != 0)
2398 /* test if we can write to the record gain volume register */
2399 snd_ac97_write_cache(ac97
, AC97_REC_GAIN
, 0x8a05);
2400 if ((err
= snd_ac97_read(ac97
, AC97_REC_GAIN
)) == 0x8a05)
2404 } while (time_after_eq(end_time
, jiffies
));
2406 snd_printk("CS46xx secondary codec dont respond!\n");
2410 static int __devinit
cs46xx_detect_codec(cs46xx_t
*chip
, int codec
)
2413 ac97_template_t ac97
;
2415 memset(&ac97
, 0, sizeof(ac97
));
2416 ac97
.private_data
= chip
;
2417 ac97
.private_free
= snd_cs46xx_mixer_free_ac97
;
2419 if (chip
->amplifier_ctrl
== amp_voyetra
)
2420 ac97
.scaps
= AC97_SCAP_INV_EAPD
;
2422 if (codec
== CS46XX_SECONDARY_CODEC_INDEX
) {
2423 snd_cs46xx_codec_write(chip
, AC97_RESET
, 0, codec
);
2425 if (snd_cs46xx_codec_read(chip
, AC97_RESET
, codec
) & 0x8000) {
2426 snd_printdd("snd_cs46xx: seconadry codec not present\n");
2431 snd_cs46xx_codec_write(chip
, AC97_MASTER
, 0x8000, codec
);
2432 for (idx
= 0; idx
< 100; ++idx
) {
2433 if (snd_cs46xx_codec_read(chip
, AC97_MASTER
, codec
) == 0x8000) {
2434 err
= snd_ac97_mixer(chip
->ac97_bus
, &ac97
, &chip
->ac97
[codec
]);
2439 snd_printdd("snd_cs46xx: codec %d detection timeout\n", codec
);
2443 int __devinit
snd_cs46xx_mixer(cs46xx_t
*chip
, int spdif_device
)
2445 snd_card_t
*card
= chip
->card
;
2446 snd_ctl_elem_id_t id
;
2449 static ac97_bus_ops_t ops
= {
2450 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2451 .reset
= snd_cs46xx_codec_reset
,
2453 .write
= snd_cs46xx_ac97_write
,
2454 .read
= snd_cs46xx_ac97_read
,
2457 /* detect primary codec */
2458 chip
->nr_ac97_codecs
= 0;
2459 snd_printdd("snd_cs46xx: detecting primary codec\n");
2460 if ((err
= snd_ac97_bus(card
, 0, &ops
, chip
, &chip
->ac97_bus
)) < 0)
2462 chip
->ac97_bus
->private_free
= snd_cs46xx_mixer_free_ac97_bus
;
2464 if (cs46xx_detect_codec(chip
, CS46XX_PRIMARY_CODEC_INDEX
) < 0)
2466 chip
->nr_ac97_codecs
= 1;
2468 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2469 snd_printdd("snd_cs46xx: detecting seconadry codec\n");
2470 /* try detect a secondary codec */
2471 if (! cs46xx_detect_codec(chip
, CS46XX_SECONDARY_CODEC_INDEX
))
2472 chip
->nr_ac97_codecs
= 2;
2473 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2475 /* add cs4630 mixer controls */
2476 for (idx
= 0; idx
< ARRAY_SIZE(snd_cs46xx_controls
); idx
++) {
2477 snd_kcontrol_t
*kctl
;
2478 kctl
= snd_ctl_new1(&snd_cs46xx_controls
[idx
], chip
);
2479 if (kctl
&& kctl
->id
.iface
== SNDRV_CTL_ELEM_IFACE_PCM
)
2480 kctl
->id
.device
= spdif_device
;
2481 if ((err
= snd_ctl_add(card
, kctl
)) < 0)
2485 /* get EAPD mixer switch (for voyetra hack) */
2486 memset(&id
, 0, sizeof(id
));
2487 id
.iface
= SNDRV_CTL_ELEM_IFACE_MIXER
;
2488 strcpy(id
.name
, "External Amplifier");
2489 chip
->eapd_switch
= snd_ctl_find_id(chip
->card
, &id
);
2491 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2492 if (chip
->nr_ac97_codecs
== 1) {
2493 unsigned int id2
= chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
]->id
& 0xffff;
2494 if (id2
== 0x592b || id2
== 0x592d) {
2495 err
= snd_ctl_add(card
, snd_ctl_new1(&snd_cs46xx_front_dup_ctl
, chip
));
2498 snd_ac97_write_cache(chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
],
2499 AC97_CSR_ACMODE
, 0x200);
2502 /* do soundcard specific mixer setup */
2503 if (chip
->mixer_init
) {
2504 snd_printdd ("calling chip->mixer_init(chip);\n");
2505 chip
->mixer_init(chip
);
2509 /* turn on amplifier */
2510 chip
->amplifier_ctrl(chip
, 1);
2519 static void snd_cs46xx_midi_reset(cs46xx_t
*chip
)
2521 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, MIDCR_MRST
);
2523 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2526 static int snd_cs46xx_midi_input_open(snd_rawmidi_substream_t
* substream
)
2528 cs46xx_t
*chip
= substream
->rmidi
->private_data
;
2530 chip
->active_ctrl(chip
, 1);
2531 spin_lock_irq(&chip
->reg_lock
);
2532 chip
->uartm
|= CS46XX_MODE_INPUT
;
2533 chip
->midcr
|= MIDCR_RXE
;
2534 chip
->midi_input
= substream
;
2535 if (!(chip
->uartm
& CS46XX_MODE_OUTPUT
)) {
2536 snd_cs46xx_midi_reset(chip
);
2538 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2540 spin_unlock_irq(&chip
->reg_lock
);
2544 static int snd_cs46xx_midi_input_close(snd_rawmidi_substream_t
* substream
)
2546 cs46xx_t
*chip
= substream
->rmidi
->private_data
;
2548 spin_lock_irq(&chip
->reg_lock
);
2549 chip
->midcr
&= ~(MIDCR_RXE
| MIDCR_RIE
);
2550 chip
->midi_input
= NULL
;
2551 if (!(chip
->uartm
& CS46XX_MODE_OUTPUT
)) {
2552 snd_cs46xx_midi_reset(chip
);
2554 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2556 chip
->uartm
&= ~CS46XX_MODE_INPUT
;
2557 spin_unlock_irq(&chip
->reg_lock
);
2558 chip
->active_ctrl(chip
, -1);
2562 static int snd_cs46xx_midi_output_open(snd_rawmidi_substream_t
* substream
)
2564 cs46xx_t
*chip
= substream
->rmidi
->private_data
;
2566 chip
->active_ctrl(chip
, 1);
2568 spin_lock_irq(&chip
->reg_lock
);
2569 chip
->uartm
|= CS46XX_MODE_OUTPUT
;
2570 chip
->midcr
|= MIDCR_TXE
;
2571 chip
->midi_output
= substream
;
2572 if (!(chip
->uartm
& CS46XX_MODE_INPUT
)) {
2573 snd_cs46xx_midi_reset(chip
);
2575 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2577 spin_unlock_irq(&chip
->reg_lock
);
2581 static int snd_cs46xx_midi_output_close(snd_rawmidi_substream_t
* substream
)
2583 cs46xx_t
*chip
= substream
->rmidi
->private_data
;
2585 spin_lock_irq(&chip
->reg_lock
);
2586 chip
->midcr
&= ~(MIDCR_TXE
| MIDCR_TIE
);
2587 chip
->midi_output
= NULL
;
2588 if (!(chip
->uartm
& CS46XX_MODE_INPUT
)) {
2589 snd_cs46xx_midi_reset(chip
);
2591 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2593 chip
->uartm
&= ~CS46XX_MODE_OUTPUT
;
2594 spin_unlock_irq(&chip
->reg_lock
);
2595 chip
->active_ctrl(chip
, -1);
2599 static void snd_cs46xx_midi_input_trigger(snd_rawmidi_substream_t
* substream
, int up
)
2601 unsigned long flags
;
2602 cs46xx_t
*chip
= substream
->rmidi
->private_data
;
2604 spin_lock_irqsave(&chip
->reg_lock
, flags
);
2606 if ((chip
->midcr
& MIDCR_RIE
) == 0) {
2607 chip
->midcr
|= MIDCR_RIE
;
2608 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2611 if (chip
->midcr
& MIDCR_RIE
) {
2612 chip
->midcr
&= ~MIDCR_RIE
;
2613 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2616 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
2619 static void snd_cs46xx_midi_output_trigger(snd_rawmidi_substream_t
* substream
, int up
)
2621 unsigned long flags
;
2622 cs46xx_t
*chip
= substream
->rmidi
->private_data
;
2625 spin_lock_irqsave(&chip
->reg_lock
, flags
);
2627 if ((chip
->midcr
& MIDCR_TIE
) == 0) {
2628 chip
->midcr
|= MIDCR_TIE
;
2629 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2630 while ((chip
->midcr
& MIDCR_TIE
) &&
2631 (snd_cs46xx_peekBA0(chip
, BA0_MIDSR
) & MIDSR_TBF
) == 0) {
2632 if (snd_rawmidi_transmit(substream
, &byte
, 1) != 1) {
2633 chip
->midcr
&= ~MIDCR_TIE
;
2635 snd_cs46xx_pokeBA0(chip
, BA0_MIDWP
, byte
);
2638 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2641 if (chip
->midcr
& MIDCR_TIE
) {
2642 chip
->midcr
&= ~MIDCR_TIE
;
2643 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2646 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
2649 static snd_rawmidi_ops_t snd_cs46xx_midi_output
=
2651 .open
= snd_cs46xx_midi_output_open
,
2652 .close
= snd_cs46xx_midi_output_close
,
2653 .trigger
= snd_cs46xx_midi_output_trigger
,
2656 static snd_rawmidi_ops_t snd_cs46xx_midi_input
=
2658 .open
= snd_cs46xx_midi_input_open
,
2659 .close
= snd_cs46xx_midi_input_close
,
2660 .trigger
= snd_cs46xx_midi_input_trigger
,
2663 int __devinit
snd_cs46xx_midi(cs46xx_t
*chip
, int device
, snd_rawmidi_t
**rrawmidi
)
2665 snd_rawmidi_t
*rmidi
;
2670 if ((err
= snd_rawmidi_new(chip
->card
, "CS46XX", device
, 1, 1, &rmidi
)) < 0)
2672 strcpy(rmidi
->name
, "CS46XX");
2673 snd_rawmidi_set_ops(rmidi
, SNDRV_RAWMIDI_STREAM_OUTPUT
, &snd_cs46xx_midi_output
);
2674 snd_rawmidi_set_ops(rmidi
, SNDRV_RAWMIDI_STREAM_INPUT
, &snd_cs46xx_midi_input
);
2675 rmidi
->info_flags
|= SNDRV_RAWMIDI_INFO_OUTPUT
| SNDRV_RAWMIDI_INFO_INPUT
| SNDRV_RAWMIDI_INFO_DUPLEX
;
2676 rmidi
->private_data
= chip
;
2677 chip
->rmidi
= rmidi
;
2685 * gameport interface
2688 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
2690 static void snd_cs46xx_gameport_trigger(struct gameport
*gameport
)
2692 cs46xx_t
*chip
= gameport_get_port_data(gameport
);
2694 snd_assert(chip
, return);
2695 snd_cs46xx_pokeBA0(chip
, BA0_JSPT
, 0xFF); //outb(gameport->io, 0xFF);
2698 static unsigned char snd_cs46xx_gameport_read(struct gameport
*gameport
)
2700 cs46xx_t
*chip
= gameport_get_port_data(gameport
);
2702 snd_assert(chip
, return 0);
2703 return snd_cs46xx_peekBA0(chip
, BA0_JSPT
); //inb(gameport->io);
2706 static int snd_cs46xx_gameport_cooked_read(struct gameport
*gameport
, int *axes
, int *buttons
)
2708 cs46xx_t
*chip
= gameport_get_port_data(gameport
);
2709 unsigned js1
, js2
, jst
;
2711 snd_assert(chip
, return 0);
2713 js1
= snd_cs46xx_peekBA0(chip
, BA0_JSC1
);
2714 js2
= snd_cs46xx_peekBA0(chip
, BA0_JSC2
);
2715 jst
= snd_cs46xx_peekBA0(chip
, BA0_JSPT
);
2717 *buttons
= (~jst
>> 4) & 0x0F;
2719 axes
[0] = ((js1
& JSC1_Y1V_MASK
) >> JSC1_Y1V_SHIFT
) & 0xFFFF;
2720 axes
[1] = ((js1
& JSC1_X1V_MASK
) >> JSC1_X1V_SHIFT
) & 0xFFFF;
2721 axes
[2] = ((js2
& JSC2_Y2V_MASK
) >> JSC2_Y2V_SHIFT
) & 0xFFFF;
2722 axes
[3] = ((js2
& JSC2_X2V_MASK
) >> JSC2_X2V_SHIFT
) & 0xFFFF;
2724 for(jst
=0;jst
<4;++jst
)
2725 if(axes
[jst
]==0xFFFF) axes
[jst
] = -1;
2729 static int snd_cs46xx_gameport_open(struct gameport
*gameport
, int mode
)
2732 case GAMEPORT_MODE_COOKED
:
2734 case GAMEPORT_MODE_RAW
:
2742 int __devinit
snd_cs46xx_gameport(cs46xx_t
*chip
)
2744 struct gameport
*gp
;
2746 chip
->gameport
= gp
= gameport_allocate_port();
2748 printk(KERN_ERR
"cs46xx: cannot allocate memory for gameport\n");
2752 gameport_set_name(gp
, "CS46xx Gameport");
2753 gameport_set_phys(gp
, "pci%s/gameport0", pci_name(chip
->pci
));
2754 gameport_set_dev_parent(gp
, &chip
->pci
->dev
);
2755 gameport_set_port_data(gp
, chip
);
2757 gp
->open
= snd_cs46xx_gameport_open
;
2758 gp
->read
= snd_cs46xx_gameport_read
;
2759 gp
->trigger
= snd_cs46xx_gameport_trigger
;
2760 gp
->cooked_read
= snd_cs46xx_gameport_cooked_read
;
2762 snd_cs46xx_pokeBA0(chip
, BA0_JSIO
, 0xFF); // ?
2763 snd_cs46xx_pokeBA0(chip
, BA0_JSCTL
, JSCTL_SP_MEDIUM_SLOW
);
2765 gameport_register_port(gp
);
2770 static inline void snd_cs46xx_remove_gameport(cs46xx_t
*chip
)
2772 if (chip
->gameport
) {
2773 gameport_unregister_port(chip
->gameport
);
2774 chip
->gameport
= NULL
;
2778 int __devinit
snd_cs46xx_gameport(cs46xx_t
*chip
) { return -ENOSYS
; }
2779 static inline void snd_cs46xx_remove_gameport(cs46xx_t
*chip
) { }
2780 #endif /* CONFIG_GAMEPORT */
2786 static long snd_cs46xx_io_read(snd_info_entry_t
*entry
, void *file_private_data
,
2787 struct file
*file
, char __user
*buf
,
2788 unsigned long count
, unsigned long pos
)
2791 snd_cs46xx_region_t
*region
= (snd_cs46xx_region_t
*)entry
->private_data
;
2794 if (pos
+ (size_t)size
> region
->size
)
2795 size
= region
->size
- pos
;
2797 if (copy_to_user_fromio(buf
, region
->remap_addr
+ pos
, size
))
2803 static struct snd_info_entry_ops snd_cs46xx_proc_io_ops
= {
2804 .read
= snd_cs46xx_io_read
,
2807 static int __devinit
snd_cs46xx_proc_init(snd_card_t
* card
, cs46xx_t
*chip
)
2809 snd_info_entry_t
*entry
;
2812 for (idx
= 0; idx
< 5; idx
++) {
2813 snd_cs46xx_region_t
*region
= &chip
->region
.idx
[idx
];
2814 if (! snd_card_proc_new(card
, region
->name
, &entry
)) {
2815 entry
->content
= SNDRV_INFO_CONTENT_DATA
;
2816 entry
->private_data
= chip
;
2817 entry
->c
.ops
= &snd_cs46xx_proc_io_ops
;
2818 entry
->size
= region
->size
;
2819 entry
->mode
= S_IFREG
| S_IRUSR
;
2822 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2823 cs46xx_dsp_proc_init(card
, chip
);
2828 static int snd_cs46xx_proc_done(cs46xx_t
*chip
)
2830 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2831 cs46xx_dsp_proc_done(chip
);
2839 static void snd_cs46xx_hw_stop(cs46xx_t
*chip
)
2843 tmp
= snd_cs46xx_peek(chip
, BA1_PFIE
);
2846 snd_cs46xx_poke(chip
, BA1_PFIE
, tmp
); /* playback interrupt disable */
2848 tmp
= snd_cs46xx_peek(chip
, BA1_CIE
);
2851 snd_cs46xx_poke(chip
, BA1_CIE
, tmp
); /* capture interrupt disable */
2854 * Stop playback DMA.
2856 tmp
= snd_cs46xx_peek(chip
, BA1_PCTL
);
2857 snd_cs46xx_poke(chip
, BA1_PCTL
, tmp
& 0x0000ffff);
2862 tmp
= snd_cs46xx_peek(chip
, BA1_CCTL
);
2863 snd_cs46xx_poke(chip
, BA1_CCTL
, tmp
& 0xffff0000);
2866 * Reset the processor.
2868 snd_cs46xx_reset(chip
);
2870 snd_cs46xx_proc_stop(chip
);
2873 * Power down the PLL.
2875 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, 0);
2878 * Turn off the Processor by turning off the software clock enable flag in
2879 * the clock control register.
2881 tmp
= snd_cs46xx_peekBA0(chip
, BA0_CLKCR1
) & ~CLKCR1_SWCE
;
2882 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, tmp
);
2886 static int snd_cs46xx_free(cs46xx_t
*chip
)
2890 snd_assert(chip
!= NULL
, return -EINVAL
);
2892 if (chip
->active_ctrl
)
2893 chip
->active_ctrl(chip
, 1);
2895 snd_cs46xx_remove_gameport(chip
);
2897 if (chip
->amplifier_ctrl
)
2898 chip
->amplifier_ctrl(chip
, -chip
->amplifier
); /* force to off */
2900 snd_cs46xx_proc_done(chip
);
2902 if (chip
->region
.idx
[0].resource
)
2903 snd_cs46xx_hw_stop(chip
);
2905 for (idx
= 0; idx
< 5; idx
++) {
2906 snd_cs46xx_region_t
*region
= &chip
->region
.idx
[idx
];
2907 if (region
->remap_addr
)
2908 iounmap(region
->remap_addr
);
2909 if (region
->resource
) {
2910 release_resource(region
->resource
);
2911 kfree_nocheck(region
->resource
);
2915 free_irq(chip
->irq
, (void *)chip
);
2917 if (chip
->active_ctrl
)
2918 chip
->active_ctrl(chip
, -chip
->amplifier
);
2920 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2921 if (chip
->dsp_spos_instance
) {
2922 cs46xx_dsp_spos_destroy(chip
);
2923 chip
->dsp_spos_instance
= NULL
;
2927 pci_disable_device(chip
->pci
);
2932 static int snd_cs46xx_dev_free(snd_device_t
*device
)
2934 cs46xx_t
*chip
= device
->device_data
;
2935 return snd_cs46xx_free(chip
);
2941 static int snd_cs46xx_chip_init(cs46xx_t
*chip
)
2946 * First, blast the clock control register to zero so that the PLL starts
2947 * out in a known state, and blast the master serial port control register
2948 * to zero so that the serial ports also start out in a known state.
2950 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, 0);
2951 snd_cs46xx_pokeBA0(chip
, BA0_SERMC1
, 0);
2954 * If we are in AC97 mode, then we must set the part to a host controlled
2955 * AC-link. Otherwise, we won't be able to bring up the link.
2957 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2958 snd_cs46xx_pokeBA0(chip
, BA0_SERACC
, SERACC_HSP
| SERACC_CHIP_TYPE_2_0
|
2959 SERACC_TWO_CODECS
); /* 2.00 dual codecs */
2960 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
2962 snd_cs46xx_pokeBA0(chip
, BA0_SERACC
, SERACC_HSP
| SERACC_CHIP_TYPE_1_03
); /* 1.03 codec */
2966 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
2967 * spec) and then drive it high. This is done for non AC97 modes since
2968 * there might be logic external to the CS461x that uses the ARST# line
2971 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, 0);
2972 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2973 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL2
, 0);
2976 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, ACCTL_RSTN
);
2977 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2978 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL2
, ACCTL_RSTN
);
2982 * The first thing we do here is to enable sync generation. As soon
2983 * as we start receiving bit clock, we'll start producing the SYNC
2986 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, ACCTL_ESYN
| ACCTL_RSTN
);
2987 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2988 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL2
, ACCTL_ESYN
| ACCTL_RSTN
);
2992 * Now wait for a short while to allow the AC97 part to start
2993 * generating bit clock (so we don't try to start the PLL without an
2999 * Set the serial port timing configuration, so that
3000 * the clock control circuit gets its clock from the correct place.
3002 snd_cs46xx_pokeBA0(chip
, BA0_SERMC1
, SERMC1_PTC_AC97
);
3005 * Write the selected clock control setup to the hardware. Do not turn on
3006 * SWCE yet (if requested), so that the devices clocked by the output of
3007 * PLL are not clocked until the PLL is stable.
3009 snd_cs46xx_pokeBA0(chip
, BA0_PLLCC
, PLLCC_LPF_1050_2780_KHZ
| PLLCC_CDR_73_104_MHZ
);
3010 snd_cs46xx_pokeBA0(chip
, BA0_PLLM
, 0x3a);
3011 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR2
, CLKCR2_PDIVS_8
);
3016 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, CLKCR1_PLLP
);
3019 * Wait until the PLL has stabilized.
3024 * Turn on clocking of the core so that we can setup the serial ports.
3026 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, CLKCR1_PLLP
| CLKCR1_SWCE
);
3029 * Enable FIFO Host Bypass
3031 snd_cs46xx_pokeBA0(chip
, BA0_SERBCF
, SERBCF_HBP
);
3034 * Fill the serial port FIFOs with silence.
3036 snd_cs46xx_clear_serial_FIFOs(chip
);
3039 * Set the serial port FIFO pointer to the first sample in the FIFO.
3041 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3044 * Write the serial port configuration to the part. The master
3045 * enable bit is not set until all other values have been written.
3047 snd_cs46xx_pokeBA0(chip
, BA0_SERC1
, SERC1_SO1F_AC97
| SERC1_SO1EN
);
3048 snd_cs46xx_pokeBA0(chip
, BA0_SERC2
, SERC2_SI1F_AC97
| SERC1_SO1EN
);
3049 snd_cs46xx_pokeBA0(chip
, BA0_SERMC1
, SERMC1_PTC_AC97
| SERMC1_MSPE
);
3052 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3053 snd_cs46xx_pokeBA0(chip
, BA0_SERC7
, SERC7_ASDI2EN
);
3054 snd_cs46xx_pokeBA0(chip
, BA0_SERC3
, 0);
3055 snd_cs46xx_pokeBA0(chip
, BA0_SERC4
, 0);
3056 snd_cs46xx_pokeBA0(chip
, BA0_SERC5
, 0);
3057 snd_cs46xx_pokeBA0(chip
, BA0_SERC6
, 1);
3064 * Wait for the codec ready signal from the AC97 codec.
3067 while (timeout
-- > 0) {
3069 * Read the AC97 status register to see if we've seen a CODEC READY
3070 * signal from the AC97 codec.
3072 if (snd_cs46xx_peekBA0(chip
, BA0_ACSTS
) & ACSTS_CRDY
)
3078 snd_printk("create - never read codec ready from AC'97\n");
3079 snd_printk("it is not probably bug, try to use CS4236 driver\n");
3082 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3085 for (count
= 0; count
< 150; count
++) {
3086 /* First, we want to wait for a short time. */
3089 if (snd_cs46xx_peekBA0(chip
, BA0_ACSTS2
) & ACSTS_CRDY
)
3094 * Make sure CODEC is READY.
3096 if (!(snd_cs46xx_peekBA0(chip
, BA0_ACSTS2
) & ACSTS_CRDY
))
3097 snd_printdd("cs46xx: never read card ready from secondary AC'97\n");
3102 * Assert the vaid frame signal so that we can start sending commands
3103 * to the AC97 codec.
3105 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, ACCTL_VFRM
| ACCTL_ESYN
| ACCTL_RSTN
);
3106 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3107 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL2
, ACCTL_VFRM
| ACCTL_ESYN
| ACCTL_RSTN
);
3112 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
3113 * the codec is pumping ADC data across the AC-link.
3116 while (timeout
-- > 0) {
3118 * Read the input slot valid register and see if input slots 3 and
3121 if ((snd_cs46xx_peekBA0(chip
, BA0_ACISV
) & (ACISV_ISV3
| ACISV_ISV4
)) == (ACISV_ISV3
| ACISV_ISV4
))
3126 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3127 snd_printk("create - never read ISV3 & ISV4 from AC'97\n");
3130 /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3131 Reloading the driver may help, if there's other soundcards
3132 with the same problem I would like to know. (Benny) */
3134 snd_printk("ERROR: snd-cs46xx: never read ISV3 & ISV4 from AC'97\n");
3135 snd_printk(" Try reloading the ALSA driver, if you find something\n");
3136 snd_printk(" broken or not working on your soundcard upon\n");
3137 snd_printk(" this message please report to alsa-devel@lists.sourceforge.net\n");
3144 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
3145 * commense the transfer of digital audio data to the AC97 codec.
3148 snd_cs46xx_pokeBA0(chip
, BA0_ACOSV
, ACOSV_SLV3
| ACOSV_SLV4
);
3152 * Power down the DAC and ADC. We will power them up (if) when we need
3155 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3158 * Turn off the Processor by turning off the software clock enable flag in
3159 * the clock control register.
3161 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3162 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3168 * start and load DSP
3170 int __devinit
snd_cs46xx_start_dsp(cs46xx_t
*chip
)
3174 * Reset the processor.
3176 snd_cs46xx_reset(chip
);
3178 * Download the image to the processor.
3180 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3182 if (cs46xx_dsp_load_module(chip
, &cwcemb80_module
) < 0) {
3183 snd_printk(KERN_ERR
"image download error\n");
3188 if (cs46xx_dsp_load_module(chip
, &cwc4630_module
) < 0) {
3189 snd_printk(KERN_ERR
"image download error [cwc4630]\n");
3193 if (cs46xx_dsp_load_module(chip
, &cwcasync_module
) < 0) {
3194 snd_printk(KERN_ERR
"image download error [cwcasync]\n");
3198 if (cs46xx_dsp_load_module(chip
, &cwcsnoop_module
) < 0) {
3199 snd_printk(KERN_ERR
"image download error [cwcsnoop]\n");
3203 if (cs46xx_dsp_load_module(chip
, &cwcbinhack_module
) < 0) {
3204 snd_printk(KERN_ERR
"image download error [cwcbinhack]\n");
3208 if (cs46xx_dsp_load_module(chip
, &cwcdma_module
) < 0) {
3209 snd_printk(KERN_ERR
"image download error [cwcdma]\n");
3213 if (cs46xx_dsp_scb_and_task_init(chip
) < 0)
3217 if (snd_cs46xx_download_image(chip
) < 0) {
3218 snd_printk("image download error\n");
3223 * Stop playback DMA.
3225 tmp
= snd_cs46xx_peek(chip
, BA1_PCTL
);
3226 chip
->play_ctl
= tmp
& 0xffff0000;
3227 snd_cs46xx_poke(chip
, BA1_PCTL
, tmp
& 0x0000ffff);
3233 tmp
= snd_cs46xx_peek(chip
, BA1_CCTL
);
3234 chip
->capt
.ctl
= tmp
& 0x0000ffff;
3235 snd_cs46xx_poke(chip
, BA1_CCTL
, tmp
& 0xffff0000);
3239 snd_cs46xx_set_play_sample_rate(chip
, 8000);
3240 snd_cs46xx_set_capture_sample_rate(chip
, 8000);
3242 snd_cs46xx_proc_start(chip
);
3245 * Enable interrupts on the part.
3247 snd_cs46xx_pokeBA0(chip
, BA0_HICR
, HICR_IEV
| HICR_CHGM
);
3249 tmp
= snd_cs46xx_peek(chip
, BA1_PFIE
);
3251 snd_cs46xx_poke(chip
, BA1_PFIE
, tmp
); /* playback interrupt enable */
3253 tmp
= snd_cs46xx_peek(chip
, BA1_CIE
);
3256 snd_cs46xx_poke(chip
, BA1_CIE
, tmp
); /* capture interrupt enable */
3258 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3259 /* set the attenuation to 0dB */
3260 snd_cs46xx_poke(chip
, BA1_PVOL
, 0x80008000);
3261 snd_cs46xx_poke(chip
, BA1_CVOL
, 0x80008000);
3269 * AMP control - null AMP
3272 static void amp_none(cs46xx_t
*chip
, int change
)
3276 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3277 static int voyetra_setup_eapd_slot(cs46xx_t
*chip
)
3280 u32 idx
, valid_slots
,tmp
,powerdown
= 0;
3281 u16 modem_power
,pin_config
,logic_type
;
3283 snd_printdd ("cs46xx: cs46xx_setup_eapd_slot()+\n");
3286 * See if the devices are powered down. If so, we must power them up first
3287 * or they will not respond.
3289 tmp
= snd_cs46xx_peekBA0(chip
, BA0_CLKCR1
);
3291 if (!(tmp
& CLKCR1_SWCE
)) {
3292 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, tmp
| CLKCR1_SWCE
);
3297 * Clear PRA. The Bonzo chip will be used for GPIO not for modem
3300 if(chip
->nr_ac97_codecs
!= 2) {
3301 snd_printk (KERN_ERR
"cs46xx: cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3305 modem_power
= snd_cs46xx_codec_read (chip
,
3306 AC97_EXTENDED_MSTATUS
,
3307 CS46XX_SECONDARY_CODEC_INDEX
);
3308 modem_power
&=0xFEFF;
3310 snd_cs46xx_codec_write(chip
,
3311 AC97_EXTENDED_MSTATUS
, modem_power
,
3312 CS46XX_SECONDARY_CODEC_INDEX
);
3315 * Set GPIO pin's 7 and 8 so that they are configured for output.
3317 pin_config
= snd_cs46xx_codec_read (chip
,
3319 CS46XX_SECONDARY_CODEC_INDEX
);
3322 snd_cs46xx_codec_write(chip
,
3323 AC97_GPIO_CFG
, pin_config
,
3324 CS46XX_SECONDARY_CODEC_INDEX
);
3327 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3330 logic_type
= snd_cs46xx_codec_read(chip
, AC97_GPIO_POLARITY
,
3331 CS46XX_SECONDARY_CODEC_INDEX
);
3334 snd_cs46xx_codec_write (chip
, AC97_GPIO_POLARITY
, logic_type
,
3335 CS46XX_SECONDARY_CODEC_INDEX
);
3337 valid_slots
= snd_cs46xx_peekBA0(chip
, BA0_ACOSV
);
3338 valid_slots
|= 0x200;
3339 snd_cs46xx_pokeBA0(chip
, BA0_ACOSV
, valid_slots
);
3341 if ( cs46xx_wait_for_fifo(chip
,1) ) {
3342 snd_printdd("FIFO is busy\n");
3348 * Fill slots 12 with the correct value for the GPIO pins.
3350 for(idx
= 0x90; idx
<= 0x9F; idx
++) {
3352 * Initialize the fifo so that bits 7 and 8 are on.
3354 * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3355 * the left. 0x1800 corresponds to bits 7 and 8.
3357 snd_cs46xx_pokeBA0(chip
, BA0_SERBWP
, 0x1800);
3360 * Wait for command to complete
3362 if ( cs46xx_wait_for_fifo(chip
,200) ) {
3363 snd_printdd("failed waiting for FIFO at addr (%02X)\n",idx
);
3369 * Write the serial port FIFO index.
3371 snd_cs46xx_pokeBA0(chip
, BA0_SERBAD
, idx
);
3374 * Tell the serial port to load the new value into the FIFO location.
3376 snd_cs46xx_pokeBA0(chip
, BA0_SERBCM
, SERBCM_WRC
);
3379 /* wait for last command to complete */
3380 cs46xx_wait_for_fifo(chip
,200);
3383 * Now, if we powered up the devices, then power them back down again.
3384 * This is kinda ugly, but should never happen.
3387 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, tmp
);
3397 static void amp_voyetra(cs46xx_t
*chip
, int change
)
3399 /* Manage the EAPD bit on the Crystal 4297
3400 and the Analog AD1885 */
3402 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3403 int old
= chip
->amplifier
;
3407 chip
->amplifier
+= change
;
3408 oval
= snd_cs46xx_codec_read(chip
, AC97_POWERDOWN
,
3409 CS46XX_PRIMARY_CODEC_INDEX
);
3411 if (chip
->amplifier
) {
3412 /* Turn the EAPD amp on */
3415 /* Turn the EAPD amp off */
3419 snd_cs46xx_codec_write(chip
, AC97_POWERDOWN
, val
,
3420 CS46XX_PRIMARY_CODEC_INDEX
);
3421 if (chip
->eapd_switch
)
3422 snd_ctl_notify(chip
->card
, SNDRV_CTL_EVENT_MASK_VALUE
,
3423 &chip
->eapd_switch
->id
);
3426 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3427 if (chip
->amplifier
&& !old
) {
3428 voyetra_setup_eapd_slot(chip
);
3433 static void hercules_init(cs46xx_t
*chip
)
3435 /* default: AMP off, and SPDIF input optical */
3436 snd_cs46xx_pokeBA0(chip
, BA0_EGPIODR
, EGPIODR_GPOE0
);
3437 snd_cs46xx_pokeBA0(chip
, BA0_EGPIOPTR
, EGPIODR_GPOE0
);
3442 * Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3444 static void amp_hercules(cs46xx_t
*chip
, int change
)
3446 int old
= chip
->amplifier
;
3447 int val1
= snd_cs46xx_peekBA0(chip
, BA0_EGPIODR
);
3448 int val2
= snd_cs46xx_peekBA0(chip
, BA0_EGPIOPTR
);
3450 chip
->amplifier
+= change
;
3451 if (chip
->amplifier
&& !old
) {
3452 snd_printdd ("Hercules amplifier ON\n");
3454 snd_cs46xx_pokeBA0(chip
, BA0_EGPIODR
,
3455 EGPIODR_GPOE2
| val1
); /* enable EGPIO2 output */
3456 snd_cs46xx_pokeBA0(chip
, BA0_EGPIOPTR
,
3457 EGPIOPTR_GPPT2
| val2
); /* open-drain on output */
3458 } else if (old
&& !chip
->amplifier
) {
3459 snd_printdd ("Hercules amplifier OFF\n");
3460 snd_cs46xx_pokeBA0(chip
, BA0_EGPIODR
, val1
& ~EGPIODR_GPOE2
); /* disable */
3461 snd_cs46xx_pokeBA0(chip
, BA0_EGPIOPTR
, val2
& ~EGPIOPTR_GPPT2
); /* disable */
3465 static void voyetra_mixer_init (cs46xx_t
*chip
)
3467 snd_printdd ("initializing Voyetra mixer\n");
3469 /* Enable SPDIF out */
3470 snd_cs46xx_pokeBA0(chip
, BA0_EGPIODR
, EGPIODR_GPOE0
);
3471 snd_cs46xx_pokeBA0(chip
, BA0_EGPIOPTR
, EGPIODR_GPOE0
);
3474 static void hercules_mixer_init (cs46xx_t
*chip
)
3476 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3479 snd_card_t
*card
= chip
->card
;
3482 /* set EGPIO to default */
3483 hercules_init(chip
);
3485 snd_printdd ("initializing Hercules mixer\n");
3487 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3488 for (idx
= 0 ; idx
< ARRAY_SIZE(snd_hercules_controls
); idx
++) {
3489 snd_kcontrol_t
*kctl
;
3491 kctl
= snd_ctl_new1(&snd_hercules_controls
[idx
], chip
);
3492 if ((err
= snd_ctl_add(card
, kctl
)) < 0) {
3493 printk (KERN_ERR
"cs46xx: failed to initialize Hercules mixer (%d)\n",err
);
3506 static void amp_voyetra_4294(cs46xx_t
*chip
, int change
)
3508 chip
->amplifier
+= change
;
3510 if (chip
->amplifier
) {
3511 /* Switch the GPIO pins 7 and 8 to open drain */
3512 snd_cs46xx_codec_write(chip
, 0x4C,
3513 snd_cs46xx_codec_read(chip
, 0x4C) & 0xFE7F);
3514 snd_cs46xx_codec_write(chip
, 0x4E,
3515 snd_cs46xx_codec_read(chip
, 0x4E) | 0x0180);
3516 /* Now wake the AMP (this might be backwards) */
3517 snd_cs46xx_codec_write(chip
, 0x54,
3518 snd_cs46xx_codec_read(chip
, 0x54) & ~0x0180);
3520 snd_cs46xx_codec_write(chip
, 0x54,
3521 snd_cs46xx_codec_read(chip
, 0x54) | 0x0180);
3530 #ifndef PCI_VENDOR_ID_INTEL
3531 #define PCI_VENDOR_ID_INTEL 0x8086
3532 #endif /* PCI_VENDOR_ID_INTEL */
3534 #ifndef PCI_DEVICE_ID_INTEL_82371AB_3
3535 #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
3536 #endif /* PCI_DEVICE_ID_INTEL_82371AB_3 */
3539 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3540 * whenever we need to beat on the chip.
3542 * The original idea and code for this hack comes from David Kaiser at
3543 * Linuxcare. Perhaps one day Crystal will document their chips well
3544 * enough to make them useful.
3547 static void clkrun_hack(cs46xx_t
*chip
, int change
)
3551 if (chip
->acpi_dev
== NULL
)
3554 chip
->amplifier
+= change
;
3556 /* Read ACPI port */
3557 nval
= control
= inw(chip
->acpi_port
+ 0x10);
3559 /* Flip CLKRUN off while running */
3560 if (! chip
->amplifier
)
3564 if (nval
!= control
)
3565 outw(nval
, chip
->acpi_port
+ 0x10);
3570 * detect intel piix4
3572 static void clkrun_init(cs46xx_t
*chip
)
3576 chip
->acpi_dev
= pci_find_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB_3
, NULL
);
3577 if (chip
->acpi_dev
== NULL
)
3578 return; /* Not a thinkpad thats for sure */
3580 /* Find the control port */
3581 pci_read_config_byte(chip
->acpi_dev
, 0x41, &pp
);
3582 chip
->acpi_port
= pp
<< 8;
3595 void (*init
)(cs46xx_t
*);
3596 void (*amp
)(cs46xx_t
*, int);
3597 void (*active
)(cs46xx_t
*, int);
3598 void (*mixer_init
)(cs46xx_t
*);
3601 static struct cs_card_type __devinitdata cards
[] = {
3605 .name
= "Genius Soundmaker 128 value",
3606 /* nothing special */
3613 .mixer_init
= voyetra_mixer_init
,
3618 .name
= "Mitac MI6020/21",
3624 .name
= "Hercules Game Theatre XP",
3625 .amp
= amp_hercules
,
3626 .mixer_init
= hercules_mixer_init
,
3631 .name
= "Hercules Game Theatre XP",
3632 .amp
= amp_hercules
,
3633 .mixer_init
= hercules_mixer_init
,
3638 .name
= "Hercules Game Theatre XP",
3639 .amp
= amp_hercules
,
3640 .mixer_init
= hercules_mixer_init
,
3646 .name
= "Hercules Game Theatre XP",
3647 .amp
= amp_hercules
,
3648 .mixer_init
= hercules_mixer_init
,
3653 .name
= "Hercules Game Theatre XP",
3654 .amp
= amp_hercules
,
3655 .mixer_init
= hercules_mixer_init
,
3660 .name
= "Hercules Game Theatre XP",
3661 .amp
= amp_hercules
,
3662 .mixer_init
= hercules_mixer_init
,
3668 .name
= "Terratec SiXPack 5.1",
3670 /* Not sure if the 570 needs the clkrun hack */
3672 .vendor
= PCI_VENDOR_ID_IBM
,
3674 .name
= "Thinkpad 570",
3675 .init
= clkrun_init
,
3676 .active
= clkrun_hack
,
3679 .vendor
= PCI_VENDOR_ID_IBM
,
3681 .name
= "Thinkpad 600X/A20/T20",
3682 .init
= clkrun_init
,
3683 .active
= clkrun_hack
,
3686 .vendor
= PCI_VENDOR_ID_IBM
,
3688 .name
= "Thinkpad 600E (unsupported)",
3698 static int snd_cs46xx_suspend(snd_card_t
*card
, pm_message_t state
)
3700 cs46xx_t
*chip
= card
->pm_private_data
;
3703 snd_pcm_suspend_all(chip
->pcm
);
3704 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3705 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3707 snd_ac97_suspend(chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
]);
3708 if (chip
->ac97
[CS46XX_SECONDARY_CODEC_INDEX
])
3709 snd_ac97_suspend(chip
->ac97
[CS46XX_SECONDARY_CODEC_INDEX
]);
3711 amp_saved
= chip
->amplifier
;
3713 chip
->amplifier_ctrl(chip
, -chip
->amplifier
);
3714 snd_cs46xx_hw_stop(chip
);
3715 /* disable CLKRUN */
3716 chip
->active_ctrl(chip
, -chip
->amplifier
);
3717 chip
->amplifier
= amp_saved
; /* restore the status */
3718 pci_disable_device(chip
->pci
);
3722 static int snd_cs46xx_resume(snd_card_t
*card
)
3724 cs46xx_t
*chip
= card
->pm_private_data
;
3727 pci_enable_device(chip
->pci
);
3728 pci_set_master(chip
->pci
);
3729 amp_saved
= chip
->amplifier
;
3730 chip
->amplifier
= 0;
3731 chip
->active_ctrl(chip
, 1); /* force to on */
3733 snd_cs46xx_chip_init(chip
);
3736 snd_cs46xx_codec_write(chip
, BA0_AC97_GENERAL_PURPOSE
,
3737 chip
->ac97_general_purpose
);
3738 snd_cs46xx_codec_write(chip
, AC97_POWER_CONTROL
,
3739 chip
->ac97_powerdown
);
3741 snd_cs46xx_codec_write(chip
, BA0_AC97_POWERDOWN
,
3742 chip
->ac97_powerdown
);
3746 snd_ac97_resume(chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
]);
3747 if (chip
->ac97
[CS46XX_SECONDARY_CODEC_INDEX
])
3748 snd_ac97_resume(chip
->ac97
[CS46XX_SECONDARY_CODEC_INDEX
]);
3751 chip
->amplifier_ctrl(chip
, 1); /* turn amp on */
3753 chip
->active_ctrl(chip
, -1); /* disable CLKRUN */
3754 chip
->amplifier
= amp_saved
;
3757 #endif /* CONFIG_PM */
3763 int __devinit
snd_cs46xx_create(snd_card_t
* card
,
3764 struct pci_dev
* pci
,
3765 int external_amp
, int thinkpad
,
3770 snd_cs46xx_region_t
*region
;
3771 struct cs_card_type
*cp
;
3772 u16 ss_card
, ss_vendor
;
3773 static snd_device_ops_t ops
= {
3774 .dev_free
= snd_cs46xx_dev_free
,
3779 /* enable PCI device */
3780 if ((err
= pci_enable_device(pci
)) < 0)
3783 chip
= kcalloc(1, sizeof(*chip
), GFP_KERNEL
);
3785 pci_disable_device(pci
);
3788 spin_lock_init(&chip
->reg_lock
);
3789 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3790 init_MUTEX(&chip
->spos_mutex
);
3795 chip
->ba0_addr
= pci_resource_start(pci
, 0);
3796 chip
->ba1_addr
= pci_resource_start(pci
, 1);
3797 if (chip
->ba0_addr
== 0 || chip
->ba0_addr
== (unsigned long)~0 ||
3798 chip
->ba1_addr
== 0 || chip
->ba1_addr
== (unsigned long)~0) {
3799 snd_printk("wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n", chip
->ba0_addr
, chip
->ba1_addr
);
3800 snd_cs46xx_free(chip
);
3804 region
= &chip
->region
.name
.ba0
;
3805 strcpy(region
->name
, "CS46xx_BA0");
3806 region
->base
= chip
->ba0_addr
;
3807 region
->size
= CS46XX_BA0_SIZE
;
3809 region
= &chip
->region
.name
.data0
;
3810 strcpy(region
->name
, "CS46xx_BA1_data0");
3811 region
->base
= chip
->ba1_addr
+ BA1_SP_DMEM0
;
3812 region
->size
= CS46XX_BA1_DATA0_SIZE
;
3814 region
= &chip
->region
.name
.data1
;
3815 strcpy(region
->name
, "CS46xx_BA1_data1");
3816 region
->base
= chip
->ba1_addr
+ BA1_SP_DMEM1
;
3817 region
->size
= CS46XX_BA1_DATA1_SIZE
;
3819 region
= &chip
->region
.name
.pmem
;
3820 strcpy(region
->name
, "CS46xx_BA1_pmem");
3821 region
->base
= chip
->ba1_addr
+ BA1_SP_PMEM
;
3822 region
->size
= CS46XX_BA1_PRG_SIZE
;
3824 region
= &chip
->region
.name
.reg
;
3825 strcpy(region
->name
, "CS46xx_BA1_reg");
3826 region
->base
= chip
->ba1_addr
+ BA1_SP_REG
;
3827 region
->size
= CS46XX_BA1_REG_SIZE
;
3829 /* set up amp and clkrun hack */
3830 pci_read_config_word(pci
, PCI_SUBSYSTEM_VENDOR_ID
, &ss_vendor
);
3831 pci_read_config_word(pci
, PCI_SUBSYSTEM_ID
, &ss_card
);
3833 for (cp
= &cards
[0]; cp
->name
; cp
++) {
3834 if (cp
->vendor
== ss_vendor
&& cp
->id
== ss_card
) {
3835 snd_printdd ("hack for %s enabled\n", cp
->name
);
3837 chip
->amplifier_ctrl
= cp
->amp
;
3838 chip
->active_ctrl
= cp
->active
;
3839 chip
->mixer_init
= cp
->mixer_init
;
3848 snd_printk("Crystal EAPD support forced on.\n");
3849 chip
->amplifier_ctrl
= amp_voyetra
;
3853 snd_printk("Activating CLKRUN hack for Thinkpad.\n");
3854 chip
->active_ctrl
= clkrun_hack
;
3858 if (chip
->amplifier_ctrl
== NULL
)
3859 chip
->amplifier_ctrl
= amp_none
;
3860 if (chip
->active_ctrl
== NULL
)
3861 chip
->active_ctrl
= amp_none
;
3863 chip
->active_ctrl(chip
, 1); /* enable CLKRUN */
3865 pci_set_master(pci
);
3867 for (idx
= 0; idx
< 5; idx
++) {
3868 region
= &chip
->region
.idx
[idx
];
3869 if ((region
->resource
= request_mem_region(region
->base
, region
->size
, region
->name
)) == NULL
) {
3870 snd_printk("unable to request memory region 0x%lx-0x%lx\n", region
->base
, region
->base
+ region
->size
- 1);
3871 snd_cs46xx_free(chip
);
3874 region
->remap_addr
= ioremap_nocache(region
->base
, region
->size
);
3875 if (region
->remap_addr
== NULL
) {
3876 snd_printk("%s ioremap problem\n", region
->name
);
3877 snd_cs46xx_free(chip
);
3882 if (request_irq(pci
->irq
, snd_cs46xx_interrupt
, SA_INTERRUPT
|SA_SHIRQ
, "CS46XX", (void *) chip
)) {
3883 snd_printk("unable to grab IRQ %d\n", pci
->irq
);
3884 snd_cs46xx_free(chip
);
3887 chip
->irq
= pci
->irq
;
3889 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3890 chip
->dsp_spos_instance
= cs46xx_dsp_spos_create(chip
);
3891 if (chip
->dsp_spos_instance
== NULL
) {
3892 snd_cs46xx_free(chip
);
3897 err
= snd_cs46xx_chip_init(chip
);
3899 snd_cs46xx_free(chip
);
3903 if ((err
= snd_device_new(card
, SNDRV_DEV_LOWLEVEL
, chip
, &ops
)) < 0) {
3904 snd_cs46xx_free(chip
);
3908 snd_cs46xx_proc_init(card
, chip
);
3910 snd_card_set_pm_callback(card
, snd_cs46xx_suspend
, snd_cs46xx_resume
, chip
);
3912 chip
->active_ctrl(chip
, -1); /* disable CLKRUN */
3914 snd_card_set_dev(card
, &pci
->dev
);