import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / vcodec / val_types_private.h
1 /**
2 * @file
3 * val_types_private.h
4 *
5 * @par Project:
6 * Video
7 *
8 * @par Description:
9 * Video Abstraction Layer Type Definitions for internal use
10 *
11 * @par Author:
12 * Jackal Chen (mtk02532)
13 *
14 * @par $Revision: #1 $
15 * @par $Modtime:$
16 * @par $Log:$
17 *
18 */
19
20 #ifndef _VAL_TYPES_PRIVATE_H_
21 #define _VAL_TYPES_PRIVATE_H_
22
23 #include "val_types_public.h"
24
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28
29 //#define __EARLY_PORTING__
30
31 #define OALMEM_STATUS_NUM 16
32
33 /**
34 * @par Enumeration
35 * VAL_HW_COMPLETE_T
36 * @par Description
37 * This is polling or interrupt for waiting for HW done
38 */
39 typedef enum _VAL_HW_COMPLETE_T
40 {
41 VAL_POLLING_MODE = 0, ///< polling
42 VAL_INTERRUPT_MODE, ///< interrupt
43 VAL_MODE_MAX = 0xFFFFFFFF ///< Max result
44 }
45 VAL_HW_COMPLETE_T;
46
47
48 /**
49 * @par Enumeration
50 * VAL_CODEC_TYPE_T
51 * @par Description
52 * This is the item in VAL_OBJECT_T for open driver type and
53 * in VAL_CLOCK_T for clock setting and
54 * in VAL_ISR_T for irq line setting
55 */
56 typedef enum _VAL_CODEC_TYPE_T
57 {
58 VAL_CODEC_TYPE_NONE = 0, ///< None
59 VAL_CODEC_TYPE_MP4_ENC, ///< MP4 encoder
60 VAL_CODEC_TYPE_MP4_DEC, ///< MP4 decoder
61 VAL_CODEC_TYPE_H263_ENC, ///< H.263 encoder
62 VAL_CODEC_TYPE_H263_DEC, ///< H.263 decoder
63 VAL_CODEC_TYPE_H264_ENC, ///< H.264 encoder
64 VAL_CODEC_TYPE_H264_DEC, ///< H.264 decoder
65 VAL_CODEC_TYPE_SORENSON_SPARK_DEC, ///< Sorenson Spark decoder
66 VAL_CODEC_TYPE_VC1_SP_DEC, ///< VC-1 simple profile decoder
67 VAL_CODEC_TYPE_RV9_DEC, ///< RV9 decoder
68 VAL_CODEC_TYPE_MP1_MP2_DEC, ///< MPEG1/2 decoder
69 VAL_CODEC_TYPE_XVID_DEC, ///< Xvid decoder
70 VAL_CODEC_TYPE_DIVX4_DIVX5_DEC, ///< Divx4/5 decoder
71 VAL_CODEC_TYPE_VC1_MP_WMV9_DEC, ///< VC-1 main profile (WMV9) decoder
72 VAL_CODEC_TYPE_RV8_DEC, ///< RV8 decoder
73 VAL_CODEC_TYPE_WMV7_DEC, ///< WMV7 decoder
74 VAL_CODEC_TYPE_WMV8_DEC, ///< WMV8 decoder
75 VAL_CODEC_TYPE_AVS_DEC, ///< AVS decoder
76 VAL_CODEC_TYPE_DIVX_3_11_DEC, ///< Divx3.11 decoder
77 VAL_CODEC_TYPE_H264_DEC_MAIN, ///< H.264 main profile decoder (due to different packet) == 20
78 VAL_CODEC_TYPE_MAX = 0xFFFFFFFF ///< Max driver type
79 } VAL_CODEC_TYPE_T;
80
81
82 typedef enum _VAL_CACHE_TYPE_T
83 {
84
85 VAL_CACHE_TYPE_CACHABLE = 0,
86 VAL_CACHE_TYPE_NONCACHABLE,
87 VAL_CACHE_TYPE_MAX = 0xFFFFFFFF
88
89 } VAL_CACHE_TYPE_T;
90
91
92 /**
93 * @par Structure
94 * VAL_INTMEM_T
95 * @par Description
96 * This is a parameter for eVideoIntMemUsed()
97 */
98 typedef struct _VAL_INTMEM_T
99 {
100 VAL_VOID_T *pvHandle; ///< [IN] The video codec driver handle
101 VAL_UINT32_T u4HandleSize; ///< [IN] The size of video codec driver handle
102 VAL_UINT32_T u4MemSize; ///< [OUT] The size of internal memory
103 VAL_VOID_T *pvMemVa; ///< [OUT] The internal memory start virtual address
104 VAL_VOID_T *pvMemPa; ///< [OUT] The internal memory start physical address
105 VAL_VOID_T *pvReserved; ///< [IN/OUT] The reserved parameter
106 VAL_UINT32_T u4ReservedSize; ///< [IN] The size of reserved parameter structure
107 } VAL_INTMEM_T;
108
109
110 /**
111 * @par Structure
112 * VAL_EVENT_T
113 * @par Description
114 * This is a parameter for eVideoWaitEvent() and eVideoSetEvent()
115 */
116 typedef struct _VAL_EVENT_T
117 {
118 VAL_VOID_T *pvHandle; ///< [IN] The video codec driver handle
119 VAL_UINT32_T u4HandleSize; ///< [IN] The size of video codec driver handle
120 VAL_VOID_T *pvWaitQueue; ///< [IN] The waitqueue discription
121 VAL_VOID_T *pvEvent; ///< [IN] The event discription
122 VAL_UINT32_T u4TimeoutMs; ///< [IN] The timeout ms
123 VAL_VOID_T *pvReserved; ///< [IN/OUT] The reserved parameter
124 VAL_UINT32_T u4ReservedSize; ///< [IN] The size of reserved parameter structure
125 } VAL_EVENT_T;
126
127
128 /**
129 * @par Structure
130 * VAL_MUTEX_T
131 * @par Description
132 * This is a parameter for eVideoWaitMutex() and eVideoReleaseMutex()
133 */
134 typedef struct _VAL_MUTEX_T
135 {
136 VAL_VOID_T *pvHandle; ///< [IN] The video codec driver handle
137 VAL_UINT32_T u4HandleSize; ///< [IN] The size of video codec driver handle
138 VAL_VOID_T *pvMutex; ///< [IN] The Mutex discriptor
139 VAL_UINT32_T u4TimeoutMs; ///< [IN] The timeout ms
140 VAL_VOID_T *pvReserved; ///< [IN/OUT] The reserved parameter
141 VAL_UINT32_T u4ReservedSize; ///< [IN] The size of reserved parameter structure
142 } VAL_MUTEX_T;
143
144
145 /**
146 * @par Structure
147 * VAL_POWER_T
148 * @par Description
149 * This is a parameter for eVideoHwPowerCtrl()
150 */
151 typedef struct _VAL_POWER_T
152 {
153 VAL_VOID_T *pvHandle; ///< [IN] The video codec driver handle
154 VAL_UINT32_T u4HandleSize; ///< [IN] The size of video codec driver handle
155 VAL_DRIVER_TYPE_T eDriverType; ///< [IN] The driver type
156 VAL_BOOL_T fgEnable; ///< [IN] Enable or not.
157 VAL_VOID_T *pvReserved; ///< [IN/OUT] The reserved parameter
158 VAL_UINT32_T u4ReservedSize; ///< [IN] The size of reserved parameter structure
159 //VAL_UINT32_T u4L2CUser; ///< [OUT] The number of power user right now
160 } VAL_POWER_T;
161
162
163 /**
164 * @par Structure
165 * VAL_MMAP_T
166 * @par Description
167 * This is a parameter for eVideoMMAP() and eVideoUNMAP()
168 */
169 typedef struct _VAL_MMAP_T
170 {
171 VAL_VOID_T *pvHandle; ///< [IN] The video codec driver handle
172 VAL_UINT32_T u4HandleSize; ///< [IN] The size of video codec driver handle
173 VAL_VOID_T *pvMemPa; ///< [IN] The physical memory address
174 VAL_UINT32_T u4MemSize; ///< [IN] The memory size
175 VAL_VOID_T *pvMemVa; ///< [IN] The mapped virtual memory address
176 VAL_VOID_T *pvReserved; ///< [IN/OUT] The reserved parameter
177 VAL_UINT32_T u4ReservedSize; ///< [IN] The size of reserved parameter structure
178 } VAL_MMAP_T;
179
180
181 typedef struct
182 {
183 VAL_UINT32_T u4ReadAddr; /// [IN] memory source address in VA
184 VAL_UINT32_T u4ReadData; /// [OUT] memory data
185 } VAL_VCODEC_OAL_MEM_STAUTS_T;
186
187
188 typedef struct
189 {
190 VAL_UINT32_T u4HWIsCompleted; ///< [IN/OUT] HW is Completed or not, set by driver & clear by codec (0: not completed or still in lock status; 1: HW is completed or in unlock status)
191 VAL_UINT32_T u4HWIsTimeout; ///< [OUT] HW is Timeout or not, set by driver & clear by codec (0: not in timeout status; 1: HW is in timeout status)
192 VAL_UINT32_T u4NumOfRegister; ///< [IN] Number of HW register need to store;
193 VAL_VCODEC_OAL_MEM_STAUTS_T *pHWStatus; ///< [OUT] HW status based on input address.
194 } VAL_VCODEC_OAL_HW_REGISTER_T;
195
196
197 typedef struct
198 {
199 VAL_VCODEC_OAL_HW_REGISTER_T *Oal_HW_reg;
200 VAL_UINT32_T *Oal_HW_mem_reg;
201 VAL_UINT32_T *kva_Oal_HW_mem_reg;
202 VAL_UINT32_T pa_Oal_HW_mem_reg;
203 VAL_ULONG_T ObjId;
204 VAL_EVENT_T IsrEvent;
205 VAL_UINT32_T slotindex;
206 VAL_UINT32_T u4VCodecThreadNum;
207 VAL_UINT32_T u4VCodecThreadID[VCODEC_THREAD_MAX_NUM];
208 VAL_HANDLE_T pvHandle; // physical address of the owner handle
209 VAL_UINT32_T u4NumOfRegister;
210 VAL_VCODEC_OAL_MEM_STAUTS_T oalmem_status[OALMEM_STATUS_NUM]; // MAX 16 items could be read; //kernel space access register
211 VAL_UINT32_T kva_u4HWIsCompleted;
212 VAL_UINT32_T kva_u4HWIsTimeout;
213 VAL_UINT32_T tid1;
214 VAL_UINT32_T tid2;
215
216 // record VA, PA
217 VAL_UINT32_T *va1;
218 VAL_UINT32_T *va2;
219 VAL_UINT32_T *va3;
220 VAL_UINT32_T pa1;
221 VAL_UINT32_T pa2;
222 VAL_UINT32_T pa3;
223
224 } VAL_VCODEC_OAL_HW_CONTEXT_T;
225
226
227 typedef struct
228 {
229 int CPUid; // [in]
230 int Loading; // [out]
231 } VAL_VCODEC_CORE_LOADING_T;
232
233 typedef void (*ena)(int);
234 typedef void (*disa)(int);
235 typedef void (*ena_timeout)(int, int);
236 typedef int (*user_reg)(int, int);
237 typedef void (*user_unreg)(int);
238 typedef void (*user_enable)(int);
239 typedef void (*user_disable)(int);
240 typedef void (*user_enable_timeout)(int, int);
241
242 typedef struct _VAL_INIT_HANDLE
243 {
244 int i4DriverType;
245 int i4VENCLivePhoto;
246 } VAL_INIT_HANDLE;
247 #ifdef __cplusplus
248 }
249 #endif
250
251 #endif // #ifndef _VAL_TYPES_PRIVATE_H_