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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / pci.h
1 /*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 #include <linux/pci_regs.h> /* The pci register defines */
21
22 /*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41 #ifdef __KERNEL__
42
43 #include <linux/mod_devicetable.h>
44
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <asm/atomic.h>
53 #include <linux/device.h>
54 #include <linux/io.h>
55
56 /* Include the ID list */
57 #include <linux/pci_ids.h>
58
59 /* pci_slot represents a physical slot */
60 struct pci_slot {
61 struct pci_bus *bus; /* The bus this slot is on */
62 struct list_head list; /* node in list of slots on this bus */
63 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
64 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
65 struct kobject kobj;
66 };
67
68 static inline const char *pci_slot_name(const struct pci_slot *slot)
69 {
70 return kobject_name(&slot->kobj);
71 }
72
73 /* File state for mmap()s on /proc/bus/pci/X/Y */
74 enum pci_mmap_state {
75 pci_mmap_io,
76 pci_mmap_mem
77 };
78
79 /* This defines the direction arg to the DMA mapping routines. */
80 #define PCI_DMA_BIDIRECTIONAL 0
81 #define PCI_DMA_TODEVICE 1
82 #define PCI_DMA_FROMDEVICE 2
83 #define PCI_DMA_NONE 3
84
85 #define DEVICE_COUNT_RESOURCE 12
86
87 typedef int __bitwise pci_power_t;
88
89 #define PCI_D0 ((pci_power_t __force) 0)
90 #define PCI_D1 ((pci_power_t __force) 1)
91 #define PCI_D2 ((pci_power_t __force) 2)
92 #define PCI_D3hot ((pci_power_t __force) 3)
93 #define PCI_D3cold ((pci_power_t __force) 4)
94 #define PCI_UNKNOWN ((pci_power_t __force) 5)
95 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
96
97 /** The pci_channel state describes connectivity between the CPU and
98 * the pci device. If some PCI bus between here and the pci device
99 * has crashed or locked up, this info is reflected here.
100 */
101 typedef unsigned int __bitwise pci_channel_state_t;
102
103 enum pci_channel_state {
104 /* I/O channel is in normal state */
105 pci_channel_io_normal = (__force pci_channel_state_t) 1,
106
107 /* I/O to channel is blocked */
108 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
109
110 /* PCI card is dead */
111 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
112 };
113
114 typedef unsigned int __bitwise pcie_reset_state_t;
115
116 enum pcie_reset_state {
117 /* Reset is NOT asserted (Use to deassert reset) */
118 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
119
120 /* Use #PERST to reset PCI-E device */
121 pcie_warm_reset = (__force pcie_reset_state_t) 2,
122
123 /* Use PCI-E Hot Reset to reset device */
124 pcie_hot_reset = (__force pcie_reset_state_t) 3
125 };
126
127 typedef unsigned short __bitwise pci_dev_flags_t;
128 enum pci_dev_flags {
129 /* INTX_DISABLE in PCI_COMMAND register disables MSI
130 * generation too.
131 */
132 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
133 /* Device configuration is irrevocably lost if disabled into D3 */
134 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
135 };
136
137 typedef unsigned short __bitwise pci_bus_flags_t;
138 enum pci_bus_flags {
139 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
140 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
141 };
142
143 struct pci_cap_saved_state {
144 struct hlist_node next;
145 char cap_nr;
146 u32 data[0];
147 };
148
149 struct pcie_link_state;
150 struct pci_vpd;
151
152 /*
153 * The pci_dev structure is used to describe PCI devices.
154 */
155 struct pci_dev {
156 struct list_head bus_list; /* node in per-bus list */
157 struct pci_bus *bus; /* bus this device is on */
158 struct pci_bus *subordinate; /* bus this device bridges to */
159
160 void *sysdata; /* hook for sys-specific extension */
161 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
162 struct pci_slot *slot; /* Physical slot this device is in */
163
164 unsigned int devfn; /* encoded device & function index */
165 unsigned short vendor;
166 unsigned short device;
167 unsigned short subsystem_vendor;
168 unsigned short subsystem_device;
169 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
170 u8 revision; /* PCI revision, low byte of class word */
171 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
172 u8 pcie_type; /* PCI-E device/port type */
173 u8 rom_base_reg; /* which config register controls the ROM */
174 u8 pin; /* which interrupt pin this device uses */
175
176 struct pci_driver *driver; /* which driver has allocated this device */
177 u64 dma_mask; /* Mask of the bits of bus address this
178 device implements. Normally this is
179 0xffffffff. You only need to change
180 this if your device has broken DMA
181 or supports 64-bit transfers. */
182
183 struct device_dma_parameters dma_parms;
184
185 pci_power_t current_state; /* Current operating state. In ACPI-speak,
186 this is D0-D3, D0 being fully functional,
187 and D3 being off. */
188 int pm_cap; /* PM capability offset in the
189 configuration space */
190 unsigned int pme_support:5; /* Bitmask of states from which PME#
191 can be generated */
192 unsigned int d1_support:1; /* Low power state D1 is supported */
193 unsigned int d2_support:1; /* Low power state D2 is supported */
194 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
195
196 #ifdef CONFIG_PCIEASPM
197 struct pcie_link_state *link_state; /* ASPM link state. */
198 #endif
199
200 pci_channel_state_t error_state; /* current connectivity state */
201 struct device dev; /* Generic device interface */
202
203 int cfg_size; /* Size of configuration space */
204
205 /*
206 * Instead of touching interrupt line and base address registers
207 * directly, use the values stored here. They might be different!
208 */
209 unsigned int irq;
210 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
211
212 /* These fields are used by common fixups */
213 unsigned int transparent:1; /* Transparent PCI bridge */
214 unsigned int multifunction:1;/* Part of multi-function device */
215 /* keep track of device state */
216 unsigned int is_added:1;
217 unsigned int is_busmaster:1; /* device is busmaster */
218 unsigned int no_msi:1; /* device may not use msi */
219 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
220 unsigned int broken_parity_status:1; /* Device generates false positive parity */
221 unsigned int msi_enabled:1;
222 unsigned int msix_enabled:1;
223 unsigned int ari_enabled:1; /* ARI forwarding */
224 unsigned int is_managed:1;
225 unsigned int is_pcie:1;
226 pci_dev_flags_t dev_flags;
227 atomic_t enable_cnt; /* pci_enable_device has been called */
228
229 u32 saved_config_space[16]; /* config space saved at suspend time */
230 struct hlist_head saved_cap_space;
231 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
232 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
233 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
234 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
235 #ifdef CONFIG_PCI_MSI
236 struct list_head msi_list;
237 #endif
238 struct pci_vpd *vpd;
239 };
240
241 extern struct pci_dev *alloc_pci_dev(void);
242
243 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
244 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
245 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
246
247 static inline int pci_channel_offline(struct pci_dev *pdev)
248 {
249 return (pdev->error_state != pci_channel_io_normal);
250 }
251
252 static inline struct pci_cap_saved_state *pci_find_saved_cap(
253 struct pci_dev *pci_dev, char cap)
254 {
255 struct pci_cap_saved_state *tmp;
256 struct hlist_node *pos;
257
258 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
259 if (tmp->cap_nr == cap)
260 return tmp;
261 }
262 return NULL;
263 }
264
265 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
266 struct pci_cap_saved_state *new_cap)
267 {
268 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
269 }
270
271 /*
272 * For PCI devices, the region numbers are assigned this way:
273 *
274 * 0-5 standard PCI regions
275 * 6 expansion ROM
276 * 7-10 bridges: address space assigned to buses behind the bridge
277 */
278
279 #define PCI_ROM_RESOURCE 6
280 #define PCI_BRIDGE_RESOURCES 7
281 #define PCI_NUM_RESOURCES 11
282
283 #ifndef PCI_BUS_NUM_RESOURCES
284 #define PCI_BUS_NUM_RESOURCES 16
285 #endif
286
287 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
288
289 struct pci_bus {
290 struct list_head node; /* node in list of buses */
291 struct pci_bus *parent; /* parent bus this bridge is on */
292 struct list_head children; /* list of child buses */
293 struct list_head devices; /* list of devices on this bus */
294 struct pci_dev *self; /* bridge device as seen by parent */
295 struct list_head slots; /* list of slots on this bus */
296 struct resource *resource[PCI_BUS_NUM_RESOURCES];
297 /* address space routed to this bus */
298
299 struct pci_ops *ops; /* configuration access functions */
300 void *sysdata; /* hook for sys-specific extension */
301 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
302
303 unsigned char number; /* bus number */
304 unsigned char primary; /* number of primary bridge */
305 unsigned char secondary; /* number of secondary bridge */
306 unsigned char subordinate; /* max number of subordinate buses */
307
308 char name[48];
309
310 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
311 pci_bus_flags_t bus_flags; /* Inherited by child busses */
312 struct device *bridge;
313 struct device dev;
314 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
315 struct bin_attribute *legacy_mem; /* legacy mem */
316 unsigned int is_added:1;
317 };
318
319 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
320 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
321
322 /*
323 * Error values that may be returned by PCI functions.
324 */
325 #define PCIBIOS_SUCCESSFUL 0x00
326 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
327 #define PCIBIOS_BAD_VENDOR_ID 0x83
328 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
329 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
330 #define PCIBIOS_SET_FAILED 0x88
331 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
332
333 /* Low-level architecture-dependent routines */
334
335 struct pci_ops {
336 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
337 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
338 };
339
340 /*
341 * ACPI needs to be able to access PCI config space before we've done a
342 * PCI bus scan and created pci_bus structures.
343 */
344 extern int raw_pci_read(unsigned int domain, unsigned int bus,
345 unsigned int devfn, int reg, int len, u32 *val);
346 extern int raw_pci_write(unsigned int domain, unsigned int bus,
347 unsigned int devfn, int reg, int len, u32 val);
348
349 struct pci_bus_region {
350 resource_size_t start;
351 resource_size_t end;
352 };
353
354 struct pci_dynids {
355 spinlock_t lock; /* protects list, index */
356 struct list_head list; /* for IDs added at runtime */
357 };
358
359 /* ---------------------------------------------------------------- */
360 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
361 * a set of callbacks in struct pci_error_handlers, then that device driver
362 * will be notified of PCI bus errors, and will be driven to recovery
363 * when an error occurs.
364 */
365
366 typedef unsigned int __bitwise pci_ers_result_t;
367
368 enum pci_ers_result {
369 /* no result/none/not supported in device driver */
370 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
371
372 /* Device driver can recover without slot reset */
373 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
374
375 /* Device driver wants slot to be reset. */
376 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
377
378 /* Device has completely failed, is unrecoverable */
379 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
380
381 /* Device driver is fully recovered and operational */
382 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
383 };
384
385 /* PCI bus error event callbacks */
386 struct pci_error_handlers {
387 /* PCI bus error detected on this device */
388 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
389 enum pci_channel_state error);
390
391 /* MMIO has been re-enabled, but not DMA */
392 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
393
394 /* PCI Express link has been reset */
395 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
396
397 /* PCI slot has been reset */
398 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
399
400 /* Device driver may resume normal operations */
401 void (*resume)(struct pci_dev *dev);
402 };
403
404 /* ---------------------------------------------------------------- */
405
406 struct module;
407 struct pci_driver {
408 struct list_head node;
409 char *name;
410 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
411 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
412 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
413 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
414 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
415 int (*resume_early) (struct pci_dev *dev);
416 int (*resume) (struct pci_dev *dev); /* Device woken up */
417 void (*shutdown) (struct pci_dev *dev);
418 struct pm_ext_ops *pm;
419 struct pci_error_handlers *err_handler;
420 struct device_driver driver;
421 struct pci_dynids dynids;
422 };
423
424 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
425
426 /**
427 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
428 * @_table: device table name
429 *
430 * This macro is used to create a struct pci_device_id array (a device table)
431 * in a generic manner.
432 */
433 #define DEFINE_PCI_DEVICE_TABLE(_table) \
434 const struct pci_device_id _table[] __devinitconst
435
436 /**
437 * PCI_DEVICE - macro used to describe a specific pci device
438 * @vend: the 16 bit PCI Vendor ID
439 * @dev: the 16 bit PCI Device ID
440 *
441 * This macro is used to create a struct pci_device_id that matches a
442 * specific device. The subvendor and subdevice fields will be set to
443 * PCI_ANY_ID.
444 */
445 #define PCI_DEVICE(vend,dev) \
446 .vendor = (vend), .device = (dev), \
447 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
448
449 /**
450 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
451 * @dev_class: the class, subclass, prog-if triple for this device
452 * @dev_class_mask: the class mask for this device
453 *
454 * This macro is used to create a struct pci_device_id that matches a
455 * specific PCI class. The vendor, device, subvendor, and subdevice
456 * fields will be set to PCI_ANY_ID.
457 */
458 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
459 .class = (dev_class), .class_mask = (dev_class_mask), \
460 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
461 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
462
463 /**
464 * PCI_VDEVICE - macro used to describe a specific pci device in short form
465 * @vendor: the vendor name
466 * @device: the 16 bit PCI Device ID
467 *
468 * This macro is used to create a struct pci_device_id that matches a
469 * specific PCI device. The subvendor, and subdevice fields will be set
470 * to PCI_ANY_ID. The macro allows the next field to follow as the device
471 * private data.
472 */
473
474 #define PCI_VDEVICE(vendor, device) \
475 PCI_VENDOR_ID_##vendor, (device), \
476 PCI_ANY_ID, PCI_ANY_ID, 0, 0
477
478 /* these external functions are only available when PCI support is enabled */
479 #ifdef CONFIG_PCI
480
481 extern struct bus_type pci_bus_type;
482
483 /* Do NOT directly access these two variables, unless you are arch specific pci
484 * code, or pci core code. */
485 extern struct list_head pci_root_buses; /* list of all known PCI buses */
486 /* Some device drivers need know if pci is initiated */
487 extern int no_pci_devices(void);
488
489 void pcibios_fixup_bus(struct pci_bus *);
490 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
491 char *pcibios_setup(char *str);
492
493 /* Used only when drivers/pci/setup.c is used */
494 void pcibios_align_resource(void *, struct resource *, resource_size_t,
495 resource_size_t);
496 void pcibios_update_irq(struct pci_dev *, int irq);
497
498 /* Generic PCI functions used internally */
499
500 extern struct pci_bus *pci_find_bus(int domain, int busnr);
501 void pci_bus_add_devices(struct pci_bus *bus);
502 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
503 struct pci_ops *ops, void *sysdata);
504 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
505 void *sysdata)
506 {
507 struct pci_bus *root_bus;
508 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
509 if (root_bus)
510 pci_bus_add_devices(root_bus);
511 return root_bus;
512 }
513 struct pci_bus *pci_create_bus(struct device *parent, int bus,
514 struct pci_ops *ops, void *sysdata);
515 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
516 int busnr);
517 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
518 const char *name,
519 struct hotplug_slot *hotplug);
520 void pci_destroy_slot(struct pci_slot *slot);
521 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
522 int pci_scan_slot(struct pci_bus *bus, int devfn);
523 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
524 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
525 unsigned int pci_scan_child_bus(struct pci_bus *bus);
526 int __must_check pci_bus_add_device(struct pci_dev *dev);
527 void pci_read_bridge_bases(struct pci_bus *child);
528 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
529 struct resource *res);
530 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
531 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
532 extern void pci_dev_put(struct pci_dev *dev);
533 extern void pci_remove_bus(struct pci_bus *b);
534 extern void pci_remove_bus_device(struct pci_dev *dev);
535 extern void pci_stop_bus_device(struct pci_dev *dev);
536 void pci_setup_cardbus(struct pci_bus *bus);
537 extern void pci_sort_breadthfirst(void);
538
539 /* Generic PCI functions exported to card drivers */
540
541 #ifdef CONFIG_PCI_LEGACY
542 struct pci_dev __deprecated *pci_find_device(unsigned int vendor,
543 unsigned int device,
544 struct pci_dev *from);
545 struct pci_dev __deprecated *pci_find_slot(unsigned int bus,
546 unsigned int devfn);
547 #endif /* CONFIG_PCI_LEGACY */
548
549 enum pci_lost_interrupt_reason {
550 PCI_LOST_IRQ_NO_INFORMATION = 0,
551 PCI_LOST_IRQ_DISABLE_MSI,
552 PCI_LOST_IRQ_DISABLE_MSIX,
553 PCI_LOST_IRQ_DISABLE_ACPI,
554 };
555 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
556 int pci_find_capability(struct pci_dev *dev, int cap);
557 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
558 int pci_find_ext_capability(struct pci_dev *dev, int cap);
559 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
560 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
561 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
562
563 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
564 struct pci_dev *from);
565 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
566 unsigned int ss_vendor, unsigned int ss_device,
567 struct pci_dev *from);
568 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
569 struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn);
570 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
571 int pci_dev_present(const struct pci_device_id *ids);
572
573 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
574 int where, u8 *val);
575 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
576 int where, u16 *val);
577 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
578 int where, u32 *val);
579 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
580 int where, u8 val);
581 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
582 int where, u16 val);
583 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
584 int where, u32 val);
585
586 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
587 {
588 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
589 }
590 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
591 {
592 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
593 }
594 static inline int pci_read_config_dword(struct pci_dev *dev, int where,
595 u32 *val)
596 {
597 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
598 }
599 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
600 {
601 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
602 }
603 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
604 {
605 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
606 }
607 static inline int pci_write_config_dword(struct pci_dev *dev, int where,
608 u32 val)
609 {
610 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
611 }
612
613 int __must_check pci_enable_device(struct pci_dev *dev);
614 int __must_check pci_enable_device_io(struct pci_dev *dev);
615 int __must_check pci_enable_device_mem(struct pci_dev *dev);
616 int __must_check pci_reenable_device(struct pci_dev *);
617 int __must_check pcim_enable_device(struct pci_dev *pdev);
618 void pcim_pin_device(struct pci_dev *pdev);
619
620 static inline int pci_is_managed(struct pci_dev *pdev)
621 {
622 return pdev->is_managed;
623 }
624
625 void pci_disable_device(struct pci_dev *dev);
626 void pci_set_master(struct pci_dev *dev);
627 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
628 #define HAVE_PCI_SET_MWI
629 int __must_check pci_set_mwi(struct pci_dev *dev);
630 int pci_try_set_mwi(struct pci_dev *dev);
631 void pci_clear_mwi(struct pci_dev *dev);
632 void pci_intx(struct pci_dev *dev, int enable);
633 void pci_msi_off(struct pci_dev *dev);
634 int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
635 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
636 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
637 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
638 int pcix_get_max_mmrbc(struct pci_dev *dev);
639 int pcix_get_mmrbc(struct pci_dev *dev);
640 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
641 int pcie_get_readrq(struct pci_dev *dev);
642 int pcie_set_readrq(struct pci_dev *dev, int rq);
643 int pci_reset_function(struct pci_dev *dev);
644 int pci_execute_reset_function(struct pci_dev *dev);
645 void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
646 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
647 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
648
649 /* ROM control related routines */
650 int pci_enable_rom(struct pci_dev *pdev);
651 void pci_disable_rom(struct pci_dev *pdev);
652 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
653 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
654 size_t pci_get_rom_size(void __iomem *rom, size_t size);
655
656 /* Power management related routines */
657 int pci_save_state(struct pci_dev *dev);
658 int pci_restore_state(struct pci_dev *dev);
659 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
660 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
661 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
662 void pci_pme_active(struct pci_dev *dev, bool enable);
663 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable);
664 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
665 pci_power_t pci_target_state(struct pci_dev *dev);
666 int pci_prepare_to_sleep(struct pci_dev *dev);
667 int pci_back_from_sleep(struct pci_dev *dev);
668
669 /* Functions for PCI Hotplug drivers to use */
670 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
671
672 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
673 void pci_bus_assign_resources(struct pci_bus *bus);
674 void pci_bus_size_bridges(struct pci_bus *bus);
675 int pci_claim_resource(struct pci_dev *, int);
676 void pci_assign_unassigned_resources(void);
677 void pdev_enable_device(struct pci_dev *);
678 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
679 int pci_enable_resources(struct pci_dev *, int mask);
680 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
681 int (*)(struct pci_dev *, u8, u8));
682 #define HAVE_PCI_REQ_REGIONS 2
683 int __must_check pci_request_regions(struct pci_dev *, const char *);
684 void pci_release_regions(struct pci_dev *);
685 int __must_check pci_request_region(struct pci_dev *, int, const char *);
686 void pci_release_region(struct pci_dev *, int);
687 int pci_request_selected_regions(struct pci_dev *, int, const char *);
688 void pci_release_selected_regions(struct pci_dev *, int);
689
690 /* drivers/pci/bus.c */
691 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
692 struct resource *res, resource_size_t size,
693 resource_size_t align, resource_size_t min,
694 unsigned int type_mask,
695 void (*alignf)(void *, struct resource *,
696 resource_size_t, resource_size_t),
697 void *alignf_data);
698 void pci_enable_bridges(struct pci_bus *bus);
699
700 /* Proper probing supporting hot-pluggable devices */
701 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
702 const char *mod_name);
703
704 /*
705 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
706 */
707 #define pci_register_driver(driver) \
708 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
709
710 void pci_unregister_driver(struct pci_driver *dev);
711 void pci_remove_behind_bridge(struct pci_dev *dev);
712 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
713 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
714 struct pci_dev *dev);
715 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
716 int pass);
717
718 void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *),
719 void *userdata);
720 int pci_cfg_space_size_ext(struct pci_dev *dev);
721 int pci_cfg_space_size(struct pci_dev *dev);
722 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
723
724 /* kmem_cache style wrapper around pci_alloc_consistent() */
725
726 #include <linux/dmapool.h>
727
728 #define pci_pool dma_pool
729 #define pci_pool_create(name, pdev, size, align, allocation) \
730 dma_pool_create(name, &pdev->dev, size, align, allocation)
731 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
732 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
733 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
734
735 enum pci_dma_burst_strategy {
736 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
737 strategy_parameter is N/A */
738 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
739 byte boundaries */
740 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
741 strategy_parameter byte boundaries */
742 };
743
744 struct msix_entry {
745 u32 vector; /* kernel uses to write allocated vector */
746 u16 entry; /* driver uses to specify entry, OS writes */
747 };
748
749
750 #ifndef CONFIG_PCI_MSI
751 static inline int pci_enable_msi(struct pci_dev *dev)
752 {
753 return -1;
754 }
755
756 static inline void pci_msi_shutdown(struct pci_dev *dev)
757 { }
758 static inline void pci_disable_msi(struct pci_dev *dev)
759 { }
760
761 static inline int pci_enable_msix(struct pci_dev *dev,
762 struct msix_entry *entries, int nvec)
763 {
764 return -1;
765 }
766
767 static inline void pci_msix_shutdown(struct pci_dev *dev)
768 { }
769 static inline void pci_disable_msix(struct pci_dev *dev)
770 { }
771
772 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
773 { }
774
775 static inline void pci_restore_msi_state(struct pci_dev *dev)
776 { }
777 #else
778 extern int pci_enable_msi(struct pci_dev *dev);
779 extern void pci_msi_shutdown(struct pci_dev *dev);
780 extern void pci_disable_msi(struct pci_dev *dev);
781 extern int pci_enable_msix(struct pci_dev *dev,
782 struct msix_entry *entries, int nvec);
783 extern void pci_msix_shutdown(struct pci_dev *dev);
784 extern void pci_disable_msix(struct pci_dev *dev);
785 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
786 extern void pci_restore_msi_state(struct pci_dev *dev);
787 #endif
788
789 #ifdef CONFIG_HT_IRQ
790 /* The functions a driver should call */
791 int ht_create_irq(struct pci_dev *dev, int idx);
792 void ht_destroy_irq(unsigned int irq);
793 #endif /* CONFIG_HT_IRQ */
794
795 extern void pci_block_user_cfg_access(struct pci_dev *dev);
796 extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
797
798 /*
799 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
800 * a PCI domain is defined to be a set of PCI busses which share
801 * configuration space.
802 */
803 #ifdef CONFIG_PCI_DOMAINS
804 extern int pci_domains_supported;
805 #else
806 enum { pci_domains_supported = 0 };
807 static inline int pci_domain_nr(struct pci_bus *bus)
808 {
809 return 0;
810 }
811
812 static inline int pci_proc_domain(struct pci_bus *bus)
813 {
814 return 0;
815 }
816 #endif /* CONFIG_PCI_DOMAINS */
817
818 #else /* CONFIG_PCI is not enabled */
819
820 /*
821 * If the system does not have PCI, clearly these return errors. Define
822 * these as simple inline functions to avoid hair in drivers.
823 */
824
825 #define _PCI_NOP(o, s, t) \
826 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
827 int where, t val) \
828 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
829
830 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
831 _PCI_NOP(o, word, u16 x) \
832 _PCI_NOP(o, dword, u32 x)
833 _PCI_NOP_ALL(read, *)
834 _PCI_NOP_ALL(write,)
835
836 static inline struct pci_dev *pci_find_device(unsigned int vendor,
837 unsigned int device,
838 struct pci_dev *from)
839 {
840 return NULL;
841 }
842
843 static inline struct pci_dev *pci_find_slot(unsigned int bus,
844 unsigned int devfn)
845 {
846 return NULL;
847 }
848
849 static inline struct pci_dev *pci_get_device(unsigned int vendor,
850 unsigned int device,
851 struct pci_dev *from)
852 {
853 return NULL;
854 }
855
856 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
857 unsigned int device,
858 unsigned int ss_vendor,
859 unsigned int ss_device,
860 struct pci_dev *from)
861 {
862 return NULL;
863 }
864
865 static inline struct pci_dev *pci_get_class(unsigned int class,
866 struct pci_dev *from)
867 {
868 return NULL;
869 }
870
871 #define pci_dev_present(ids) (0)
872 #define no_pci_devices() (1)
873 #define pci_dev_put(dev) do { } while (0)
874
875 static inline void pci_set_master(struct pci_dev *dev)
876 { }
877
878 static inline int pci_enable_device(struct pci_dev *dev)
879 {
880 return -EIO;
881 }
882
883 static inline void pci_disable_device(struct pci_dev *dev)
884 { }
885
886 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
887 {
888 return -EIO;
889 }
890
891 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
892 {
893 return -EIO;
894 }
895
896 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
897 unsigned int size)
898 {
899 return -EIO;
900 }
901
902 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
903 unsigned long mask)
904 {
905 return -EIO;
906 }
907
908 static inline int pci_assign_resource(struct pci_dev *dev, int i)
909 {
910 return -EBUSY;
911 }
912
913 static inline int __pci_register_driver(struct pci_driver *drv,
914 struct module *owner)
915 {
916 return 0;
917 }
918
919 static inline int pci_register_driver(struct pci_driver *drv)
920 {
921 return 0;
922 }
923
924 static inline void pci_unregister_driver(struct pci_driver *drv)
925 { }
926
927 static inline int pci_find_capability(struct pci_dev *dev, int cap)
928 {
929 return 0;
930 }
931
932 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
933 int cap)
934 {
935 return 0;
936 }
937
938 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
939 {
940 return 0;
941 }
942
943 /* Power management related routines */
944 static inline int pci_save_state(struct pci_dev *dev)
945 {
946 return 0;
947 }
948
949 static inline int pci_restore_state(struct pci_dev *dev)
950 {
951 return 0;
952 }
953
954 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
955 {
956 return 0;
957 }
958
959 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
960 pm_message_t state)
961 {
962 return PCI_D0;
963 }
964
965 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
966 int enable)
967 {
968 return 0;
969 }
970
971 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
972 {
973 return -EIO;
974 }
975
976 static inline void pci_release_regions(struct pci_dev *dev)
977 { }
978
979 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
980
981 static inline void pci_block_user_cfg_access(struct pci_dev *dev)
982 { }
983
984 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
985 { }
986
987 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
988 { return NULL; }
989
990 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
991 unsigned int devfn)
992 { return NULL; }
993
994 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
995 unsigned int devfn)
996 { return NULL; }
997
998 #endif /* CONFIG_PCI */
999
1000 /* Include architecture-dependent settings and functions */
1001
1002 #include <asm/pci.h>
1003
1004 /* these helpers provide future and backwards compatibility
1005 * for accessing popular PCI BAR info */
1006 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1007 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1008 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1009 #define pci_resource_len(dev,bar) \
1010 ((pci_resource_start((dev), (bar)) == 0 && \
1011 pci_resource_end((dev), (bar)) == \
1012 pci_resource_start((dev), (bar))) ? 0 : \
1013 \
1014 (pci_resource_end((dev), (bar)) - \
1015 pci_resource_start((dev), (bar)) + 1))
1016
1017 /* Similar to the helpers above, these manipulate per-pci_dev
1018 * driver-specific data. They are really just a wrapper around
1019 * the generic device structure functions of these calls.
1020 */
1021 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1022 {
1023 return dev_get_drvdata(&pdev->dev);
1024 }
1025
1026 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1027 {
1028 dev_set_drvdata(&pdev->dev, data);
1029 }
1030
1031 /* If you want to know what to call your pci_dev, ask this function.
1032 * Again, it's a wrapper around the generic device.
1033 */
1034 static inline const char *pci_name(struct pci_dev *pdev)
1035 {
1036 return dev_name(&pdev->dev);
1037 }
1038
1039
1040 /* Some archs don't want to expose struct resource to userland as-is
1041 * in sysfs and /proc
1042 */
1043 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1044 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1045 const struct resource *rsrc, resource_size_t *start,
1046 resource_size_t *end)
1047 {
1048 *start = rsrc->start;
1049 *end = rsrc->end;
1050 }
1051 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1052
1053
1054 /*
1055 * The world is not perfect and supplies us with broken PCI devices.
1056 * For at least a part of these bugs we need a work-around, so both
1057 * generic (drivers/pci/quirks.c) and per-architecture code can define
1058 * fixup hooks to be called for particular buggy devices.
1059 */
1060
1061 struct pci_fixup {
1062 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1063 void (*hook)(struct pci_dev *dev);
1064 };
1065
1066 enum pci_fixup_pass {
1067 pci_fixup_early, /* Before probing BARs */
1068 pci_fixup_header, /* After reading configuration header */
1069 pci_fixup_final, /* Final phase of device fixups */
1070 pci_fixup_enable, /* pci_enable_device() time */
1071 pci_fixup_resume, /* pci_device_resume() */
1072 pci_fixup_suspend, /* pci_device_suspend */
1073 pci_fixup_resume_early, /* pci_device_resume_early() */
1074 };
1075
1076 /* Anonymous variables would be nice... */
1077 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1078 static const struct pci_fixup __pci_fixup_##name __used \
1079 __attribute__((__section__(#section))) = { vendor, device, hook };
1080 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1081 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1082 vendor##device##hook, vendor, device, hook)
1083 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1084 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1085 vendor##device##hook, vendor, device, hook)
1086 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1087 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1088 vendor##device##hook, vendor, device, hook)
1089 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1090 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1091 vendor##device##hook, vendor, device, hook)
1092 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1093 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1094 resume##vendor##device##hook, vendor, device, hook)
1095 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1096 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1097 resume_early##vendor##device##hook, vendor, device, hook)
1098 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1099 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1100 suspend##vendor##device##hook, vendor, device, hook)
1101
1102
1103 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1104
1105 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1106 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1107 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1108 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
1109 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
1110 const char *name);
1111 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
1112
1113 extern int pci_pci_problems;
1114 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1115 #define PCIPCI_TRITON 2
1116 #define PCIPCI_NATOMA 4
1117 #define PCIPCI_VIAETBF 8
1118 #define PCIPCI_VSFX 16
1119 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1120 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1121
1122 extern unsigned long pci_cardbus_io_size;
1123 extern unsigned long pci_cardbus_mem_size;
1124
1125 int pcibios_add_platform_entries(struct pci_dev *dev);
1126 void pcibios_disable_device(struct pci_dev *dev);
1127 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1128 enum pcie_reset_state state);
1129
1130 #ifdef CONFIG_PCI_MMCONFIG
1131 extern void __init pci_mmcfg_early_init(void);
1132 extern void __init pci_mmcfg_late_init(void);
1133 #else
1134 static inline void pci_mmcfg_early_init(void) { }
1135 static inline void pci_mmcfg_late_init(void) { }
1136 #endif
1137
1138 #ifdef CONFIG_HAS_IOMEM
1139 static inline void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
1140 {
1141 /*
1142 * Make sure the BAR is actually a memory resource, not an IO resource
1143 */
1144 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1145 WARN_ON(1);
1146 return NULL;
1147 }
1148 return ioremap_nocache(pci_resource_start(pdev, bar),
1149 pci_resource_len(pdev, bar));
1150 }
1151 #endif
1152
1153 #endif /* __KERNEL__ */
1154 #endif /* LINUX_PCI_H */
kernel source for telekom puls (alcatel/mediatek)