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atomic: use <linux/atomic.h>
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / pci.h
1 /*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 #include <linux/pci_regs.h> /* The pci register defines */
21
22 /*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41 #ifdef __KERNEL__
42
43 #include <linux/mod_devicetable.h>
44
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <linux/atomic.h>
53 #include <linux/device.h>
54 #include <linux/io.h>
55 #include <linux/irqreturn.h>
56
57 /* Include the ID list */
58 #include <linux/pci_ids.h>
59
60 /* pci_slot represents a physical slot */
61 struct pci_slot {
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
66 struct kobject kobj;
67 };
68
69 static inline const char *pci_slot_name(const struct pci_slot *slot)
70 {
71 return kobject_name(&slot->kobj);
72 }
73
74 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 enum pci_mmap_state {
76 pci_mmap_io,
77 pci_mmap_mem
78 };
79
80 /* This defines the direction arg to the DMA mapping routines. */
81 #define PCI_DMA_BIDIRECTIONAL 0
82 #define PCI_DMA_TODEVICE 1
83 #define PCI_DMA_FROMDEVICE 2
84 #define PCI_DMA_NONE 3
85
86 /*
87 * For PCI devices, the region numbers are assigned this way:
88 */
89 enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = 5,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
97 /* device specific resources */
98 #ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101 #endif
102
103 /* resources assigned to buses behind the bridge */
104 #define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110 /* total resources associated with a PCI device */
111 PCI_NUM_RESOURCES,
112
113 /* preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE
115 };
116
117 typedef int __bitwise pci_power_t;
118
119 #define PCI_D0 ((pci_power_t __force) 0)
120 #define PCI_D1 ((pci_power_t __force) 1)
121 #define PCI_D2 ((pci_power_t __force) 2)
122 #define PCI_D3hot ((pci_power_t __force) 3)
123 #define PCI_D3cold ((pci_power_t __force) 4)
124 #define PCI_UNKNOWN ((pci_power_t __force) 5)
125 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
126
127 /* Remember to update this when the list above changes! */
128 extern const char *pci_power_names[];
129
130 static inline const char *pci_power_name(pci_power_t state)
131 {
132 return pci_power_names[1 + (int) state];
133 }
134
135 #define PCI_PM_D2_DELAY 200
136 #define PCI_PM_D3_WAIT 10
137 #define PCI_PM_BUS_WAIT 50
138
139 /** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
142 */
143 typedef unsigned int __bitwise pci_channel_state_t;
144
145 enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
148
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
151
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
154 };
155
156 typedef unsigned int __bitwise pcie_reset_state_t;
157
158 enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
161
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
164
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
167 };
168
169 typedef unsigned short __bitwise pci_dev_flags_t;
170 enum pci_dev_flags {
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
172 * generation too.
173 */
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
177 };
178
179 enum pci_irq_reroute_variant {
180 INTEL_IRQ_REROUTE_VARIANT = 1,
181 MAX_IRQ_REROUTE_VARIANTS = 3
182 };
183
184 typedef unsigned short __bitwise pci_bus_flags_t;
185 enum pci_bus_flags {
186 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
187 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
188 };
189
190 /* Based on the PCI Hotplug Spec, but some values are made up by us */
191 enum pci_bus_speed {
192 PCI_SPEED_33MHz = 0x00,
193 PCI_SPEED_66MHz = 0x01,
194 PCI_SPEED_66MHz_PCIX = 0x02,
195 PCI_SPEED_100MHz_PCIX = 0x03,
196 PCI_SPEED_133MHz_PCIX = 0x04,
197 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
198 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
199 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
200 PCI_SPEED_66MHz_PCIX_266 = 0x09,
201 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
202 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
203 AGP_UNKNOWN = 0x0c,
204 AGP_1X = 0x0d,
205 AGP_2X = 0x0e,
206 AGP_4X = 0x0f,
207 AGP_8X = 0x10,
208 PCI_SPEED_66MHz_PCIX_533 = 0x11,
209 PCI_SPEED_100MHz_PCIX_533 = 0x12,
210 PCI_SPEED_133MHz_PCIX_533 = 0x13,
211 PCIE_SPEED_2_5GT = 0x14,
212 PCIE_SPEED_5_0GT = 0x15,
213 PCIE_SPEED_8_0GT = 0x16,
214 PCI_SPEED_UNKNOWN = 0xff,
215 };
216
217 struct pci_cap_saved_data {
218 char cap_nr;
219 unsigned int size;
220 u32 data[0];
221 };
222
223 struct pci_cap_saved_state {
224 struct hlist_node next;
225 struct pci_cap_saved_data cap;
226 };
227
228 struct pcie_link_state;
229 struct pci_vpd;
230 struct pci_sriov;
231 struct pci_ats;
232
233 /*
234 * The pci_dev structure is used to describe PCI devices.
235 */
236 struct pci_dev {
237 struct list_head bus_list; /* node in per-bus list */
238 struct pci_bus *bus; /* bus this device is on */
239 struct pci_bus *subordinate; /* bus this device bridges to */
240
241 void *sysdata; /* hook for sys-specific extension */
242 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
243 struct pci_slot *slot; /* Physical slot this device is in */
244
245 unsigned int devfn; /* encoded device & function index */
246 unsigned short vendor;
247 unsigned short device;
248 unsigned short subsystem_vendor;
249 unsigned short subsystem_device;
250 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
251 u8 revision; /* PCI revision, low byte of class word */
252 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
253 u8 pcie_cap; /* PCI-E capability offset */
254 u8 pcie_type; /* PCI-E device/port type */
255 u8 rom_base_reg; /* which config register controls the ROM */
256 u8 pin; /* which interrupt pin this device uses */
257
258 struct pci_driver *driver; /* which driver has allocated this device */
259 u64 dma_mask; /* Mask of the bits of bus address this
260 device implements. Normally this is
261 0xffffffff. You only need to change
262 this if your device has broken DMA
263 or supports 64-bit transfers. */
264
265 struct device_dma_parameters dma_parms;
266
267 pci_power_t current_state; /* Current operating state. In ACPI-speak,
268 this is D0-D3, D0 being fully functional,
269 and D3 being off. */
270 int pm_cap; /* PM capability offset in the
271 configuration space */
272 unsigned int pme_support:5; /* Bitmask of states from which PME#
273 can be generated */
274 unsigned int pme_interrupt:1;
275 unsigned int d1_support:1; /* Low power state D1 is supported */
276 unsigned int d2_support:1; /* Low power state D2 is supported */
277 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
278 unsigned int mmio_always_on:1; /* disallow turning off io/mem
279 decoding during bar sizing */
280 unsigned int wakeup_prepared:1;
281 unsigned int d3_delay; /* D3->D0 transition time in ms */
282
283 #ifdef CONFIG_PCIEASPM
284 struct pcie_link_state *link_state; /* ASPM link state. */
285 #endif
286
287 pci_channel_state_t error_state; /* current connectivity state */
288 struct device dev; /* Generic device interface */
289
290 int cfg_size; /* Size of configuration space */
291
292 /*
293 * Instead of touching interrupt line and base address registers
294 * directly, use the values stored here. They might be different!
295 */
296 unsigned int irq;
297 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
298 resource_size_t fw_addr[DEVICE_COUNT_RESOURCE]; /* FW-assigned addr */
299
300 /* These fields are used by common fixups */
301 unsigned int transparent:1; /* Transparent PCI bridge */
302 unsigned int multifunction:1;/* Part of multi-function device */
303 /* keep track of device state */
304 unsigned int is_added:1;
305 unsigned int is_busmaster:1; /* device is busmaster */
306 unsigned int no_msi:1; /* device may not use msi */
307 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
308 unsigned int broken_parity_status:1; /* Device generates false positive parity */
309 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
310 unsigned int msi_enabled:1;
311 unsigned int msix_enabled:1;
312 unsigned int ari_enabled:1; /* ARI forwarding */
313 unsigned int is_managed:1;
314 unsigned int is_pcie:1; /* Obsolete. Will be removed.
315 Use pci_is_pcie() instead */
316 unsigned int needs_freset:1; /* Dev requires fundamental reset */
317 unsigned int state_saved:1;
318 unsigned int is_physfn:1;
319 unsigned int is_virtfn:1;
320 unsigned int reset_fn:1;
321 unsigned int is_hotplug_bridge:1;
322 unsigned int __aer_firmware_first_valid:1;
323 unsigned int __aer_firmware_first:1;
324 pci_dev_flags_t dev_flags;
325 atomic_t enable_cnt; /* pci_enable_device has been called */
326
327 u32 saved_config_space[16]; /* config space saved at suspend time */
328 struct hlist_head saved_cap_space;
329 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
330 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
331 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
332 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
333 #ifdef CONFIG_PCI_MSI
334 struct list_head msi_list;
335 #endif
336 struct pci_vpd *vpd;
337 #ifdef CONFIG_PCI_IOV
338 union {
339 struct pci_sriov *sriov; /* SR-IOV capability related */
340 struct pci_dev *physfn; /* the PF this VF is associated with */
341 };
342 struct pci_ats *ats; /* Address Translation Service */
343 #endif
344 };
345
346 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
347 {
348 #ifdef CONFIG_PCI_IOV
349 if (dev->is_virtfn)
350 dev = dev->physfn;
351 #endif
352
353 return dev;
354 }
355
356 extern struct pci_dev *alloc_pci_dev(void);
357
358 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
359 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
360 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
361
362 static inline int pci_channel_offline(struct pci_dev *pdev)
363 {
364 return (pdev->error_state != pci_channel_io_normal);
365 }
366
367 static inline struct pci_cap_saved_state *pci_find_saved_cap(
368 struct pci_dev *pci_dev, char cap)
369 {
370 struct pci_cap_saved_state *tmp;
371 struct hlist_node *pos;
372
373 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
374 if (tmp->cap.cap_nr == cap)
375 return tmp;
376 }
377 return NULL;
378 }
379
380 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
381 struct pci_cap_saved_state *new_cap)
382 {
383 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
384 }
385
386 /*
387 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
388 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
389 * buses below host bridges or subtractive decode bridges) go in the list.
390 * Use pci_bus_for_each_resource() to iterate through all the resources.
391 */
392
393 /*
394 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
395 * and there's no way to program the bridge with the details of the window.
396 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
397 * decode bit set, because they are explicit and can be programmed with _SRS.
398 */
399 #define PCI_SUBTRACTIVE_DECODE 0x1
400
401 struct pci_bus_resource {
402 struct list_head list;
403 struct resource *res;
404 unsigned int flags;
405 };
406
407 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
408
409 struct pci_bus {
410 struct list_head node; /* node in list of buses */
411 struct pci_bus *parent; /* parent bus this bridge is on */
412 struct list_head children; /* list of child buses */
413 struct list_head devices; /* list of devices on this bus */
414 struct pci_dev *self; /* bridge device as seen by parent */
415 struct list_head slots; /* list of slots on this bus */
416 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
417 struct list_head resources; /* address space routed to this bus */
418
419 struct pci_ops *ops; /* configuration access functions */
420 void *sysdata; /* hook for sys-specific extension */
421 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
422
423 unsigned char number; /* bus number */
424 unsigned char primary; /* number of primary bridge */
425 unsigned char secondary; /* number of secondary bridge */
426 unsigned char subordinate; /* max number of subordinate buses */
427 unsigned char max_bus_speed; /* enum pci_bus_speed */
428 unsigned char cur_bus_speed; /* enum pci_bus_speed */
429
430 char name[48];
431
432 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
433 pci_bus_flags_t bus_flags; /* Inherited by child busses */
434 struct device *bridge;
435 struct device dev;
436 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
437 struct bin_attribute *legacy_mem; /* legacy mem */
438 unsigned int is_added:1;
439 };
440
441 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
442 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
443
444 /*
445 * Returns true if the pci bus is root (behind host-pci bridge),
446 * false otherwise
447 */
448 static inline bool pci_is_root_bus(struct pci_bus *pbus)
449 {
450 return !(pbus->parent);
451 }
452
453 #ifdef CONFIG_PCI_MSI
454 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
455 {
456 return pci_dev->msi_enabled || pci_dev->msix_enabled;
457 }
458 #else
459 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
460 #endif
461
462 /*
463 * Error values that may be returned by PCI functions.
464 */
465 #define PCIBIOS_SUCCESSFUL 0x00
466 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
467 #define PCIBIOS_BAD_VENDOR_ID 0x83
468 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
469 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
470 #define PCIBIOS_SET_FAILED 0x88
471 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
472
473 /* Low-level architecture-dependent routines */
474
475 struct pci_ops {
476 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
477 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
478 };
479
480 /*
481 * ACPI needs to be able to access PCI config space before we've done a
482 * PCI bus scan and created pci_bus structures.
483 */
484 extern int raw_pci_read(unsigned int domain, unsigned int bus,
485 unsigned int devfn, int reg, int len, u32 *val);
486 extern int raw_pci_write(unsigned int domain, unsigned int bus,
487 unsigned int devfn, int reg, int len, u32 val);
488
489 struct pci_bus_region {
490 resource_size_t start;
491 resource_size_t end;
492 };
493
494 struct pci_dynids {
495 spinlock_t lock; /* protects list, index */
496 struct list_head list; /* for IDs added at runtime */
497 };
498
499 /* ---------------------------------------------------------------- */
500 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
501 * a set of callbacks in struct pci_error_handlers, then that device driver
502 * will be notified of PCI bus errors, and will be driven to recovery
503 * when an error occurs.
504 */
505
506 typedef unsigned int __bitwise pci_ers_result_t;
507
508 enum pci_ers_result {
509 /* no result/none/not supported in device driver */
510 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
511
512 /* Device driver can recover without slot reset */
513 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
514
515 /* Device driver wants slot to be reset. */
516 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
517
518 /* Device has completely failed, is unrecoverable */
519 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
520
521 /* Device driver is fully recovered and operational */
522 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
523 };
524
525 /* PCI bus error event callbacks */
526 struct pci_error_handlers {
527 /* PCI bus error detected on this device */
528 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
529 enum pci_channel_state error);
530
531 /* MMIO has been re-enabled, but not DMA */
532 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
533
534 /* PCI Express link has been reset */
535 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
536
537 /* PCI slot has been reset */
538 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
539
540 /* Device driver may resume normal operations */
541 void (*resume)(struct pci_dev *dev);
542 };
543
544 /* ---------------------------------------------------------------- */
545
546 struct module;
547 struct pci_driver {
548 struct list_head node;
549 const char *name;
550 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
551 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
552 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
553 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
554 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
555 int (*resume_early) (struct pci_dev *dev);
556 int (*resume) (struct pci_dev *dev); /* Device woken up */
557 void (*shutdown) (struct pci_dev *dev);
558 struct pci_error_handlers *err_handler;
559 struct device_driver driver;
560 struct pci_dynids dynids;
561 };
562
563 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
564
565 /**
566 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
567 * @_table: device table name
568 *
569 * This macro is used to create a struct pci_device_id array (a device table)
570 * in a generic manner.
571 */
572 #define DEFINE_PCI_DEVICE_TABLE(_table) \
573 const struct pci_device_id _table[] __devinitconst
574
575 /**
576 * PCI_DEVICE - macro used to describe a specific pci device
577 * @vend: the 16 bit PCI Vendor ID
578 * @dev: the 16 bit PCI Device ID
579 *
580 * This macro is used to create a struct pci_device_id that matches a
581 * specific device. The subvendor and subdevice fields will be set to
582 * PCI_ANY_ID.
583 */
584 #define PCI_DEVICE(vend,dev) \
585 .vendor = (vend), .device = (dev), \
586 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
587
588 /**
589 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
590 * @dev_class: the class, subclass, prog-if triple for this device
591 * @dev_class_mask: the class mask for this device
592 *
593 * This macro is used to create a struct pci_device_id that matches a
594 * specific PCI class. The vendor, device, subvendor, and subdevice
595 * fields will be set to PCI_ANY_ID.
596 */
597 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
598 .class = (dev_class), .class_mask = (dev_class_mask), \
599 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
600 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
601
602 /**
603 * PCI_VDEVICE - macro used to describe a specific pci device in short form
604 * @vendor: the vendor name
605 * @device: the 16 bit PCI Device ID
606 *
607 * This macro is used to create a struct pci_device_id that matches a
608 * specific PCI device. The subvendor, and subdevice fields will be set
609 * to PCI_ANY_ID. The macro allows the next field to follow as the device
610 * private data.
611 */
612
613 #define PCI_VDEVICE(vendor, device) \
614 PCI_VENDOR_ID_##vendor, (device), \
615 PCI_ANY_ID, PCI_ANY_ID, 0, 0
616
617 /* these external functions are only available when PCI support is enabled */
618 #ifdef CONFIG_PCI
619
620 extern struct bus_type pci_bus_type;
621
622 /* Do NOT directly access these two variables, unless you are arch specific pci
623 * code, or pci core code. */
624 extern struct list_head pci_root_buses; /* list of all known PCI buses */
625 /* Some device drivers need know if pci is initiated */
626 extern int no_pci_devices(void);
627
628 void pcibios_fixup_bus(struct pci_bus *);
629 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
630 char *pcibios_setup(char *str);
631
632 /* Used only when drivers/pci/setup.c is used */
633 resource_size_t pcibios_align_resource(void *, const struct resource *,
634 resource_size_t,
635 resource_size_t);
636 void pcibios_update_irq(struct pci_dev *, int irq);
637
638 /* Weak but can be overriden by arch */
639 void pci_fixup_cardbus(struct pci_bus *);
640
641 /* Generic PCI functions used internally */
642
643 void pcibios_scan_specific_bus(int busn);
644 extern struct pci_bus *pci_find_bus(int domain, int busnr);
645 void pci_bus_add_devices(const struct pci_bus *bus);
646 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
647 struct pci_ops *ops, void *sysdata);
648 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
649 void *sysdata)
650 {
651 struct pci_bus *root_bus;
652 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
653 if (root_bus)
654 pci_bus_add_devices(root_bus);
655 return root_bus;
656 }
657 struct pci_bus *pci_create_bus(struct device *parent, int bus,
658 struct pci_ops *ops, void *sysdata);
659 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
660 int busnr);
661 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
662 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
663 const char *name,
664 struct hotplug_slot *hotplug);
665 void pci_destroy_slot(struct pci_slot *slot);
666 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
667 int pci_scan_slot(struct pci_bus *bus, int devfn);
668 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
669 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
670 unsigned int pci_scan_child_bus(struct pci_bus *bus);
671 int __must_check pci_bus_add_device(struct pci_dev *dev);
672 void pci_read_bridge_bases(struct pci_bus *child);
673 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
674 struct resource *res);
675 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
676 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
677 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
678 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
679 extern void pci_dev_put(struct pci_dev *dev);
680 extern void pci_remove_bus(struct pci_bus *b);
681 extern void pci_remove_bus_device(struct pci_dev *dev);
682 extern void pci_stop_bus_device(struct pci_dev *dev);
683 void pci_setup_cardbus(struct pci_bus *bus);
684 extern void pci_sort_breadthfirst(void);
685 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
686 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
687 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
688
689 /* Generic PCI functions exported to card drivers */
690
691 enum pci_lost_interrupt_reason {
692 PCI_LOST_IRQ_NO_INFORMATION = 0,
693 PCI_LOST_IRQ_DISABLE_MSI,
694 PCI_LOST_IRQ_DISABLE_MSIX,
695 PCI_LOST_IRQ_DISABLE_ACPI,
696 };
697 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
698 int pci_find_capability(struct pci_dev *dev, int cap);
699 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
700 int pci_find_ext_capability(struct pci_dev *dev, int cap);
701 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
702 int cap);
703 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
704 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
705 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
706
707 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
708 struct pci_dev *from);
709 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
710 unsigned int ss_vendor, unsigned int ss_device,
711 struct pci_dev *from);
712 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
713 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
714 unsigned int devfn);
715 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
716 unsigned int devfn)
717 {
718 return pci_get_domain_bus_and_slot(0, bus, devfn);
719 }
720 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
721 int pci_dev_present(const struct pci_device_id *ids);
722
723 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
724 int where, u8 *val);
725 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
726 int where, u16 *val);
727 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
728 int where, u32 *val);
729 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
730 int where, u8 val);
731 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
732 int where, u16 val);
733 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
734 int where, u32 val);
735 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
736
737 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
738 {
739 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
740 }
741 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
742 {
743 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
744 }
745 static inline int pci_read_config_dword(struct pci_dev *dev, int where,
746 u32 *val)
747 {
748 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
749 }
750 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
751 {
752 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
753 }
754 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
755 {
756 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
757 }
758 static inline int pci_write_config_dword(struct pci_dev *dev, int where,
759 u32 val)
760 {
761 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
762 }
763
764 int __must_check pci_enable_device(struct pci_dev *dev);
765 int __must_check pci_enable_device_io(struct pci_dev *dev);
766 int __must_check pci_enable_device_mem(struct pci_dev *dev);
767 int __must_check pci_reenable_device(struct pci_dev *);
768 int __must_check pcim_enable_device(struct pci_dev *pdev);
769 void pcim_pin_device(struct pci_dev *pdev);
770
771 static inline int pci_is_enabled(struct pci_dev *pdev)
772 {
773 return (atomic_read(&pdev->enable_cnt) > 0);
774 }
775
776 static inline int pci_is_managed(struct pci_dev *pdev)
777 {
778 return pdev->is_managed;
779 }
780
781 void pci_disable_device(struct pci_dev *dev);
782 void pci_set_master(struct pci_dev *dev);
783 void pci_clear_master(struct pci_dev *dev);
784 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
785 int pci_set_cacheline_size(struct pci_dev *dev);
786 #define HAVE_PCI_SET_MWI
787 int __must_check pci_set_mwi(struct pci_dev *dev);
788 int pci_try_set_mwi(struct pci_dev *dev);
789 void pci_clear_mwi(struct pci_dev *dev);
790 void pci_intx(struct pci_dev *dev, int enable);
791 void pci_msi_off(struct pci_dev *dev);
792 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
793 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
794 int pcix_get_max_mmrbc(struct pci_dev *dev);
795 int pcix_get_mmrbc(struct pci_dev *dev);
796 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
797 int pcie_get_readrq(struct pci_dev *dev);
798 int pcie_set_readrq(struct pci_dev *dev, int rq);
799 int __pci_reset_function(struct pci_dev *dev);
800 int pci_reset_function(struct pci_dev *dev);
801 void pci_update_resource(struct pci_dev *dev, int resno);
802 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
803 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
804
805 /* ROM control related routines */
806 int pci_enable_rom(struct pci_dev *pdev);
807 void pci_disable_rom(struct pci_dev *pdev);
808 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
809 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
810 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
811
812 /* Power management related routines */
813 int pci_save_state(struct pci_dev *dev);
814 void pci_restore_state(struct pci_dev *dev);
815 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
816 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
817 int pci_load_and_free_saved_state(struct pci_dev *dev,
818 struct pci_saved_state **state);
819 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
820 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
821 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
822 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
823 void pci_pme_active(struct pci_dev *dev, bool enable);
824 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
825 bool runtime, bool enable);
826 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
827 pci_power_t pci_target_state(struct pci_dev *dev);
828 int pci_prepare_to_sleep(struct pci_dev *dev);
829 int pci_back_from_sleep(struct pci_dev *dev);
830 bool pci_dev_run_wake(struct pci_dev *dev);
831 bool pci_check_pme_status(struct pci_dev *dev);
832 void pci_pme_wakeup_bus(struct pci_bus *bus);
833
834 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
835 bool enable)
836 {
837 return __pci_enable_wake(dev, state, false, enable);
838 }
839
840 #define PCI_EXP_IDO_REQUEST (1<<0)
841 #define PCI_EXP_IDO_COMPLETION (1<<1)
842 void pci_enable_ido(struct pci_dev *dev, unsigned long type);
843 void pci_disable_ido(struct pci_dev *dev, unsigned long type);
844
845 enum pci_obff_signal_type {
846 PCI_EXP_OBFF_SIGNAL_L0,
847 PCI_EXP_OBFF_SIGNAL_ALWAYS,
848 };
849 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
850 void pci_disable_obff(struct pci_dev *dev);
851
852 bool pci_ltr_supported(struct pci_dev *dev);
853 int pci_enable_ltr(struct pci_dev *dev);
854 void pci_disable_ltr(struct pci_dev *dev);
855 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
856
857 /* For use by arch with custom probe code */
858 void set_pcie_port_type(struct pci_dev *pdev);
859 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
860
861 /* Functions for PCI Hotplug drivers to use */
862 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
863 #ifdef CONFIG_HOTPLUG
864 unsigned int pci_rescan_bus(struct pci_bus *bus);
865 #endif
866
867 /* Vital product data routines */
868 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
869 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
870 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
871
872 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
873 void pci_bus_assign_resources(const struct pci_bus *bus);
874 void pci_bus_size_bridges(struct pci_bus *bus);
875 int pci_claim_resource(struct pci_dev *, int);
876 void pci_assign_unassigned_resources(void);
877 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
878 void pdev_enable_device(struct pci_dev *);
879 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
880 int pci_enable_resources(struct pci_dev *, int mask);
881 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
882 int (*)(struct pci_dev *, u8, u8));
883 #define HAVE_PCI_REQ_REGIONS 2
884 int __must_check pci_request_regions(struct pci_dev *, const char *);
885 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
886 void pci_release_regions(struct pci_dev *);
887 int __must_check pci_request_region(struct pci_dev *, int, const char *);
888 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
889 void pci_release_region(struct pci_dev *, int);
890 int pci_request_selected_regions(struct pci_dev *, int, const char *);
891 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
892 void pci_release_selected_regions(struct pci_dev *, int);
893
894 /* drivers/pci/bus.c */
895 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
896 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
897 void pci_bus_remove_resources(struct pci_bus *bus);
898
899 #define pci_bus_for_each_resource(bus, res, i) \
900 for (i = 0; \
901 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
902 i++)
903
904 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
905 struct resource *res, resource_size_t size,
906 resource_size_t align, resource_size_t min,
907 unsigned int type_mask,
908 resource_size_t (*alignf)(void *,
909 const struct resource *,
910 resource_size_t,
911 resource_size_t),
912 void *alignf_data);
913 void pci_enable_bridges(struct pci_bus *bus);
914
915 /* Proper probing supporting hot-pluggable devices */
916 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
917 const char *mod_name);
918
919 /*
920 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
921 */
922 #define pci_register_driver(driver) \
923 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
924
925 void pci_unregister_driver(struct pci_driver *dev);
926 void pci_remove_behind_bridge(struct pci_dev *dev);
927 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
928 int pci_add_dynid(struct pci_driver *drv,
929 unsigned int vendor, unsigned int device,
930 unsigned int subvendor, unsigned int subdevice,
931 unsigned int class, unsigned int class_mask,
932 unsigned long driver_data);
933 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
934 struct pci_dev *dev);
935 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
936 int pass);
937
938 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
939 void *userdata);
940 int pci_cfg_space_size_ext(struct pci_dev *dev);
941 int pci_cfg_space_size(struct pci_dev *dev);
942 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
943
944 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
945 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
946
947 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
948 unsigned int command_bits, u32 flags);
949 /* kmem_cache style wrapper around pci_alloc_consistent() */
950
951 #include <linux/pci-dma.h>
952 #include <linux/dmapool.h>
953
954 #define pci_pool dma_pool
955 #define pci_pool_create(name, pdev, size, align, allocation) \
956 dma_pool_create(name, &pdev->dev, size, align, allocation)
957 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
958 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
959 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
960
961 enum pci_dma_burst_strategy {
962 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
963 strategy_parameter is N/A */
964 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
965 byte boundaries */
966 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
967 strategy_parameter byte boundaries */
968 };
969
970 struct msix_entry {
971 u32 vector; /* kernel uses to write allocated vector */
972 u16 entry; /* driver uses to specify entry, OS writes */
973 };
974
975
976 #ifndef CONFIG_PCI_MSI
977 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
978 {
979 return -1;
980 }
981
982 static inline void pci_msi_shutdown(struct pci_dev *dev)
983 { }
984 static inline void pci_disable_msi(struct pci_dev *dev)
985 { }
986
987 static inline int pci_msix_table_size(struct pci_dev *dev)
988 {
989 return 0;
990 }
991 static inline int pci_enable_msix(struct pci_dev *dev,
992 struct msix_entry *entries, int nvec)
993 {
994 return -1;
995 }
996
997 static inline void pci_msix_shutdown(struct pci_dev *dev)
998 { }
999 static inline void pci_disable_msix(struct pci_dev *dev)
1000 { }
1001
1002 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1003 { }
1004
1005 static inline void pci_restore_msi_state(struct pci_dev *dev)
1006 { }
1007 static inline int pci_msi_enabled(void)
1008 {
1009 return 0;
1010 }
1011 #else
1012 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
1013 extern void pci_msi_shutdown(struct pci_dev *dev);
1014 extern void pci_disable_msi(struct pci_dev *dev);
1015 extern int pci_msix_table_size(struct pci_dev *dev);
1016 extern int pci_enable_msix(struct pci_dev *dev,
1017 struct msix_entry *entries, int nvec);
1018 extern void pci_msix_shutdown(struct pci_dev *dev);
1019 extern void pci_disable_msix(struct pci_dev *dev);
1020 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1021 extern void pci_restore_msi_state(struct pci_dev *dev);
1022 extern int pci_msi_enabled(void);
1023 #endif
1024
1025 #ifdef CONFIG_PCIEPORTBUS
1026 extern bool pcie_ports_disabled;
1027 extern bool pcie_ports_auto;
1028 #else
1029 #define pcie_ports_disabled true
1030 #define pcie_ports_auto false
1031 #endif
1032
1033 #ifndef CONFIG_PCIEASPM
1034 static inline int pcie_aspm_enabled(void) { return 0; }
1035 static inline bool pcie_aspm_support_enabled(void) { return false; }
1036 #else
1037 extern int pcie_aspm_enabled(void);
1038 extern bool pcie_aspm_support_enabled(void);
1039 #endif
1040
1041 #ifdef CONFIG_PCIEAER
1042 void pci_no_aer(void);
1043 bool pci_aer_available(void);
1044 #else
1045 static inline void pci_no_aer(void) { }
1046 static inline bool pci_aer_available(void) { return false; }
1047 #endif
1048
1049 #ifndef CONFIG_PCIE_ECRC
1050 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1051 {
1052 return;
1053 }
1054 static inline void pcie_ecrc_get_policy(char *str) {};
1055 #else
1056 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1057 extern void pcie_ecrc_get_policy(char *str);
1058 #endif
1059
1060 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1061
1062 #ifdef CONFIG_HT_IRQ
1063 /* The functions a driver should call */
1064 int ht_create_irq(struct pci_dev *dev, int idx);
1065 void ht_destroy_irq(unsigned int irq);
1066 #endif /* CONFIG_HT_IRQ */
1067
1068 extern void pci_block_user_cfg_access(struct pci_dev *dev);
1069 extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
1070
1071 /*
1072 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1073 * a PCI domain is defined to be a set of PCI busses which share
1074 * configuration space.
1075 */
1076 #ifdef CONFIG_PCI_DOMAINS
1077 extern int pci_domains_supported;
1078 #else
1079 enum { pci_domains_supported = 0 };
1080 static inline int pci_domain_nr(struct pci_bus *bus)
1081 {
1082 return 0;
1083 }
1084
1085 static inline int pci_proc_domain(struct pci_bus *bus)
1086 {
1087 return 0;
1088 }
1089 #endif /* CONFIG_PCI_DOMAINS */
1090
1091 /* some architectures require additional setup to direct VGA traffic */
1092 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1093 unsigned int command_bits, u32 flags);
1094 extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1095
1096 #else /* CONFIG_PCI is not enabled */
1097
1098 /*
1099 * If the system does not have PCI, clearly these return errors. Define
1100 * these as simple inline functions to avoid hair in drivers.
1101 */
1102
1103 #define _PCI_NOP(o, s, t) \
1104 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1105 int where, t val) \
1106 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1107
1108 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1109 _PCI_NOP(o, word, u16 x) \
1110 _PCI_NOP(o, dword, u32 x)
1111 _PCI_NOP_ALL(read, *)
1112 _PCI_NOP_ALL(write,)
1113
1114 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1115 unsigned int device,
1116 struct pci_dev *from)
1117 {
1118 return NULL;
1119 }
1120
1121 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1122 unsigned int device,
1123 unsigned int ss_vendor,
1124 unsigned int ss_device,
1125 struct pci_dev *from)
1126 {
1127 return NULL;
1128 }
1129
1130 static inline struct pci_dev *pci_get_class(unsigned int class,
1131 struct pci_dev *from)
1132 {
1133 return NULL;
1134 }
1135
1136 #define pci_dev_present(ids) (0)
1137 #define no_pci_devices() (1)
1138 #define pci_dev_put(dev) do { } while (0)
1139
1140 static inline void pci_set_master(struct pci_dev *dev)
1141 { }
1142
1143 static inline int pci_enable_device(struct pci_dev *dev)
1144 {
1145 return -EIO;
1146 }
1147
1148 static inline void pci_disable_device(struct pci_dev *dev)
1149 { }
1150
1151 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1152 {
1153 return -EIO;
1154 }
1155
1156 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1157 {
1158 return -EIO;
1159 }
1160
1161 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1162 unsigned int size)
1163 {
1164 return -EIO;
1165 }
1166
1167 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1168 unsigned long mask)
1169 {
1170 return -EIO;
1171 }
1172
1173 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1174 {
1175 return -EBUSY;
1176 }
1177
1178 static inline int __pci_register_driver(struct pci_driver *drv,
1179 struct module *owner)
1180 {
1181 return 0;
1182 }
1183
1184 static inline int pci_register_driver(struct pci_driver *drv)
1185 {
1186 return 0;
1187 }
1188
1189 static inline void pci_unregister_driver(struct pci_driver *drv)
1190 { }
1191
1192 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1193 {
1194 return 0;
1195 }
1196
1197 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1198 int cap)
1199 {
1200 return 0;
1201 }
1202
1203 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1204 {
1205 return 0;
1206 }
1207
1208 /* Power management related routines */
1209 static inline int pci_save_state(struct pci_dev *dev)
1210 {
1211 return 0;
1212 }
1213
1214 static inline void pci_restore_state(struct pci_dev *dev)
1215 { }
1216
1217 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1218 {
1219 return 0;
1220 }
1221
1222 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1223 {
1224 return 0;
1225 }
1226
1227 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1228 pm_message_t state)
1229 {
1230 return PCI_D0;
1231 }
1232
1233 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1234 int enable)
1235 {
1236 return 0;
1237 }
1238
1239 static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1240 {
1241 }
1242
1243 static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1244 {
1245 }
1246
1247 static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1248 {
1249 return 0;
1250 }
1251
1252 static inline void pci_disable_obff(struct pci_dev *dev)
1253 {
1254 }
1255
1256 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1257 {
1258 return -EIO;
1259 }
1260
1261 static inline void pci_release_regions(struct pci_dev *dev)
1262 { }
1263
1264 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1265
1266 static inline void pci_block_user_cfg_access(struct pci_dev *dev)
1267 { }
1268
1269 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
1270 { }
1271
1272 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1273 { return NULL; }
1274
1275 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1276 unsigned int devfn)
1277 { return NULL; }
1278
1279 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1280 unsigned int devfn)
1281 { return NULL; }
1282
1283 static inline int pci_domain_nr(struct pci_bus *bus)
1284 { return 0; }
1285
1286 #define dev_is_pci(d) (false)
1287 #define dev_is_pf(d) (false)
1288 #define dev_num_vf(d) (0)
1289 #endif /* CONFIG_PCI */
1290
1291 /* Include architecture-dependent settings and functions */
1292
1293 #include <asm/pci.h>
1294
1295 #ifndef PCIBIOS_MAX_MEM_32
1296 #define PCIBIOS_MAX_MEM_32 (-1)
1297 #endif
1298
1299 /* these helpers provide future and backwards compatibility
1300 * for accessing popular PCI BAR info */
1301 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1302 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1303 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1304 #define pci_resource_len(dev,bar) \
1305 ((pci_resource_start((dev), (bar)) == 0 && \
1306 pci_resource_end((dev), (bar)) == \
1307 pci_resource_start((dev), (bar))) ? 0 : \
1308 \
1309 (pci_resource_end((dev), (bar)) - \
1310 pci_resource_start((dev), (bar)) + 1))
1311
1312 /* Similar to the helpers above, these manipulate per-pci_dev
1313 * driver-specific data. They are really just a wrapper around
1314 * the generic device structure functions of these calls.
1315 */
1316 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1317 {
1318 return dev_get_drvdata(&pdev->dev);
1319 }
1320
1321 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1322 {
1323 dev_set_drvdata(&pdev->dev, data);
1324 }
1325
1326 /* If you want to know what to call your pci_dev, ask this function.
1327 * Again, it's a wrapper around the generic device.
1328 */
1329 static inline const char *pci_name(const struct pci_dev *pdev)
1330 {
1331 return dev_name(&pdev->dev);
1332 }
1333
1334
1335 /* Some archs don't want to expose struct resource to userland as-is
1336 * in sysfs and /proc
1337 */
1338 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1339 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1340 const struct resource *rsrc, resource_size_t *start,
1341 resource_size_t *end)
1342 {
1343 *start = rsrc->start;
1344 *end = rsrc->end;
1345 }
1346 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1347
1348
1349 /*
1350 * The world is not perfect and supplies us with broken PCI devices.
1351 * For at least a part of these bugs we need a work-around, so both
1352 * generic (drivers/pci/quirks.c) and per-architecture code can define
1353 * fixup hooks to be called for particular buggy devices.
1354 */
1355
1356 struct pci_fixup {
1357 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1358 void (*hook)(struct pci_dev *dev);
1359 };
1360
1361 enum pci_fixup_pass {
1362 pci_fixup_early, /* Before probing BARs */
1363 pci_fixup_header, /* After reading configuration header */
1364 pci_fixup_final, /* Final phase of device fixups */
1365 pci_fixup_enable, /* pci_enable_device() time */
1366 pci_fixup_resume, /* pci_device_resume() */
1367 pci_fixup_suspend, /* pci_device_suspend */
1368 pci_fixup_resume_early, /* pci_device_resume_early() */
1369 };
1370
1371 /* Anonymous variables would be nice... */
1372 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1373 static const struct pci_fixup __pci_fixup_##name __used \
1374 __attribute__((__section__(#section))) = { vendor, device, hook };
1375 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1376 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1377 vendor##device##hook, vendor, device, hook)
1378 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1379 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1380 vendor##device##hook, vendor, device, hook)
1381 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1382 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1383 vendor##device##hook, vendor, device, hook)
1384 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1385 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1386 vendor##device##hook, vendor, device, hook)
1387 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1388 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1389 resume##vendor##device##hook, vendor, device, hook)
1390 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1391 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1392 resume_early##vendor##device##hook, vendor, device, hook)
1393 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1394 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1395 suspend##vendor##device##hook, vendor, device, hook)
1396
1397 #ifdef CONFIG_PCI_QUIRKS
1398 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1399 #else
1400 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1401 struct pci_dev *dev) {}
1402 #endif
1403
1404 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1405 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1406 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1407 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
1408 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
1409 const char *name);
1410 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
1411
1412 extern int pci_pci_problems;
1413 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1414 #define PCIPCI_TRITON 2
1415 #define PCIPCI_NATOMA 4
1416 #define PCIPCI_VIAETBF 8
1417 #define PCIPCI_VSFX 16
1418 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1419 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1420
1421 extern unsigned long pci_cardbus_io_size;
1422 extern unsigned long pci_cardbus_mem_size;
1423 extern u8 __devinitdata pci_dfl_cache_line_size;
1424 extern u8 pci_cache_line_size;
1425
1426 extern unsigned long pci_hotplug_io_size;
1427 extern unsigned long pci_hotplug_mem_size;
1428
1429 int pcibios_add_platform_entries(struct pci_dev *dev);
1430 void pcibios_disable_device(struct pci_dev *dev);
1431 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1432 enum pcie_reset_state state);
1433
1434 #ifdef CONFIG_PCI_MMCONFIG
1435 extern void __init pci_mmcfg_early_init(void);
1436 extern void __init pci_mmcfg_late_init(void);
1437 #else
1438 static inline void pci_mmcfg_early_init(void) { }
1439 static inline void pci_mmcfg_late_init(void) { }
1440 #endif
1441
1442 int pci_ext_cfg_avail(struct pci_dev *dev);
1443
1444 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1445
1446 #ifdef CONFIG_PCI_IOV
1447 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1448 extern void pci_disable_sriov(struct pci_dev *dev);
1449 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1450 extern int pci_num_vf(struct pci_dev *dev);
1451 #else
1452 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1453 {
1454 return -ENODEV;
1455 }
1456 static inline void pci_disable_sriov(struct pci_dev *dev)
1457 {
1458 }
1459 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1460 {
1461 return IRQ_NONE;
1462 }
1463 static inline int pci_num_vf(struct pci_dev *dev)
1464 {
1465 return 0;
1466 }
1467 #endif
1468
1469 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1470 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1471 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1472 #endif
1473
1474 /**
1475 * pci_pcie_cap - get the saved PCIe capability offset
1476 * @dev: PCI device
1477 *
1478 * PCIe capability offset is calculated at PCI device initialization
1479 * time and saved in the data structure. This function returns saved
1480 * PCIe capability offset. Using this instead of pci_find_capability()
1481 * reduces unnecessary search in the PCI configuration space. If you
1482 * need to calculate PCIe capability offset from raw device for some
1483 * reasons, please use pci_find_capability() instead.
1484 */
1485 static inline int pci_pcie_cap(struct pci_dev *dev)
1486 {
1487 return dev->pcie_cap;
1488 }
1489
1490 /**
1491 * pci_is_pcie - check if the PCI device is PCI Express capable
1492 * @dev: PCI device
1493 *
1494 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1495 */
1496 static inline bool pci_is_pcie(struct pci_dev *dev)
1497 {
1498 return !!pci_pcie_cap(dev);
1499 }
1500
1501 void pci_request_acs(void);
1502
1503
1504 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1505 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1506
1507 /* Large Resource Data Type Tag Item Names */
1508 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1509 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1510 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1511
1512 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1513 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1514 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1515
1516 /* Small Resource Data Type Tag Item Names */
1517 #define PCI_VPD_STIN_END 0x78 /* End */
1518
1519 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1520
1521 #define PCI_VPD_SRDT_TIN_MASK 0x78
1522 #define PCI_VPD_SRDT_LEN_MASK 0x07
1523
1524 #define PCI_VPD_LRDT_TAG_SIZE 3
1525 #define PCI_VPD_SRDT_TAG_SIZE 1
1526
1527 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1528
1529 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1530 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1531 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1532 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1533
1534 /**
1535 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1536 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1537 *
1538 * Returns the extracted Large Resource Data Type length.
1539 */
1540 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1541 {
1542 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1543 }
1544
1545 /**
1546 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1547 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1548 *
1549 * Returns the extracted Small Resource Data Type length.
1550 */
1551 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1552 {
1553 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1554 }
1555
1556 /**
1557 * pci_vpd_info_field_size - Extracts the information field length
1558 * @lrdt: Pointer to the beginning of an information field header
1559 *
1560 * Returns the extracted information field length.
1561 */
1562 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1563 {
1564 return info_field[2];
1565 }
1566
1567 /**
1568 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1569 * @buf: Pointer to buffered vpd data
1570 * @off: The offset into the buffer at which to begin the search
1571 * @len: The length of the vpd buffer
1572 * @rdt: The Resource Data Type to search for
1573 *
1574 * Returns the index where the Resource Data Type was found or
1575 * -ENOENT otherwise.
1576 */
1577 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1578
1579 /**
1580 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1581 * @buf: Pointer to buffered vpd data
1582 * @off: The offset into the buffer at which to begin the search
1583 * @len: The length of the buffer area, relative to off, in which to search
1584 * @kw: The keyword to search for
1585 *
1586 * Returns the index where the information field keyword was found or
1587 * -ENOENT otherwise.
1588 */
1589 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1590 unsigned int len, const char *kw);
1591
1592 /* PCI <-> OF binding helpers */
1593 #ifdef CONFIG_OF
1594 struct device_node;
1595 extern void pci_set_of_node(struct pci_dev *dev);
1596 extern void pci_release_of_node(struct pci_dev *dev);
1597 extern void pci_set_bus_of_node(struct pci_bus *bus);
1598 extern void pci_release_bus_of_node(struct pci_bus *bus);
1599
1600 /* Arch may override this (weak) */
1601 extern struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus);
1602
1603 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1604 {
1605 return pdev ? pdev->dev.of_node : NULL;
1606 }
1607
1608 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1609 {
1610 return bus ? bus->dev.of_node : NULL;
1611 }
1612
1613 #else /* CONFIG_OF */
1614 static inline void pci_set_of_node(struct pci_dev *dev) { }
1615 static inline void pci_release_of_node(struct pci_dev *dev) { }
1616 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1617 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1618 #endif /* CONFIG_OF */
1619
1620 /**
1621 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1622 * @pdev: the PCI device
1623 *
1624 * if the device is PCIE, return NULL
1625 * if the device isn't connected to a PCIe bridge (that is its parent is a
1626 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1627 * parent
1628 */
1629 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1630
1631 #endif /* __KERNEL__ */
1632 #endif /* LINUX_PCI_H */
kernel source for telekom puls (alcatel/mediatek)