2 * Definitions for the NVM Express interface
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 #include <linux/types.h>
25 __u64 cap
; /* Controller Capabilities */
26 __u32 vs
; /* Version */
27 __u32 intms
; /* Interrupt Mask Set */
28 __u32 intmc
; /* Interrupt Mask Clear */
29 __u32 cc
; /* Controller Configuration */
30 __u32 rsvd1
; /* Reserved */
31 __u32 csts
; /* Controller Status */
32 __u32 rsvd2
; /* Reserved */
33 __u32 aqa
; /* Admin Queue Attributes */
34 __u64 asq
; /* Admin SQ Base Address */
35 __u64 acq
; /* Admin CQ Base Address */
38 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
39 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
40 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
41 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
44 NVME_CC_ENABLE
= 1 << 0,
45 NVME_CC_CSS_NVM
= 0 << 4,
46 NVME_CC_MPS_SHIFT
= 7,
47 NVME_CC_ARB_RR
= 0 << 11,
48 NVME_CC_ARB_WRRU
= 1 << 11,
49 NVME_CC_ARB_VS
= 7 << 11,
50 NVME_CC_SHN_NONE
= 0 << 14,
51 NVME_CC_SHN_NORMAL
= 1 << 14,
52 NVME_CC_SHN_ABRUPT
= 2 << 14,
53 NVME_CC_IOSQES
= 6 << 16,
54 NVME_CC_IOCQES
= 4 << 20,
55 NVME_CSTS_RDY
= 1 << 0,
56 NVME_CSTS_CFS
= 1 << 1,
57 NVME_CSTS_SHST_NORMAL
= 0 << 2,
58 NVME_CSTS_SHST_OCCUR
= 1 << 2,
59 NVME_CSTS_SHST_CMPLT
= 2 << 2,
62 struct nvme_id_power_state
{
63 __le16 max_power
; /* centiwatts */
65 __le32 entry_lat
; /* microseconds */
66 __le32 exit_lat
; /* microseconds */
74 #define NVME_VS(major, minor) (major << 16 | minor)
106 struct nvme_id_power_state psd
[32];
111 NVME_CTRL_ONCS_COMPARE
= 1 << 0,
112 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE
= 1 << 1,
113 NVME_CTRL_ONCS_DSM
= 1 << 2,
133 struct nvme_lbaf lbaf
[16];
139 NVME_NS_FEAT_THIN
= 1 << 0,
140 NVME_LBAF_RP_BEST
= 0,
141 NVME_LBAF_RP_BETTER
= 1,
142 NVME_LBAF_RP_GOOD
= 2,
143 NVME_LBAF_RP_DEGRADED
= 3,
146 struct nvme_smart_log
{
147 __u8 critical_warning
;
153 __u8 data_units_read
[16];
154 __u8 data_units_written
[16];
156 __u8 host_writes
[16];
157 __u8 ctrl_busy_time
[16];
158 __u8 power_cycles
[16];
159 __u8 power_on_hours
[16];
160 __u8 unsafe_shutdowns
[16];
161 __u8 media_errors
[16];
162 __u8 num_err_log_entries
[16];
167 NVME_SMART_CRIT_SPARE
= 1 << 0,
168 NVME_SMART_CRIT_TEMPERATURE
= 1 << 1,
169 NVME_SMART_CRIT_RELIABILITY
= 1 << 2,
170 NVME_SMART_CRIT_MEDIA
= 1 << 3,
171 NVME_SMART_CRIT_VOLATILE_MEMORY
= 1 << 4,
174 struct nvme_lba_range_type
{
185 NVME_LBART_TYPE_FS
= 0x01,
186 NVME_LBART_TYPE_RAID
= 0x02,
187 NVME_LBART_TYPE_CACHE
= 0x03,
188 NVME_LBART_TYPE_SWAP
= 0x04,
190 NVME_LBART_ATTRIB_TEMP
= 1 << 0,
191 NVME_LBART_ATTRIB_HIDE
= 1 << 1,
197 nvme_cmd_flush
= 0x00,
198 nvme_cmd_write
= 0x01,
199 nvme_cmd_read
= 0x02,
200 nvme_cmd_write_uncor
= 0x04,
201 nvme_cmd_compare
= 0x05,
205 struct nvme_common_command
{
217 struct nvme_rw_command
{
236 NVME_RW_LR
= 1 << 15,
237 NVME_RW_FUA
= 1 << 14,
238 NVME_RW_DSM_FREQ_UNSPEC
= 0,
239 NVME_RW_DSM_FREQ_TYPICAL
= 1,
240 NVME_RW_DSM_FREQ_RARE
= 2,
241 NVME_RW_DSM_FREQ_READS
= 3,
242 NVME_RW_DSM_FREQ_WRITES
= 4,
243 NVME_RW_DSM_FREQ_RW
= 5,
244 NVME_RW_DSM_FREQ_ONCE
= 6,
245 NVME_RW_DSM_FREQ_PREFETCH
= 7,
246 NVME_RW_DSM_FREQ_TEMP
= 8,
247 NVME_RW_DSM_LATENCY_NONE
= 0 << 4,
248 NVME_RW_DSM_LATENCY_IDLE
= 1 << 4,
249 NVME_RW_DSM_LATENCY_NORM
= 2 << 4,
250 NVME_RW_DSM_LATENCY_LOW
= 3 << 4,
251 NVME_RW_DSM_SEQ_REQ
= 1 << 6,
252 NVME_RW_DSM_COMPRESSED
= 1 << 7,
255 struct nvme_dsm_cmd
{
269 NVME_DSMGMT_IDR
= 1 << 0,
270 NVME_DSMGMT_IDW
= 1 << 1,
271 NVME_DSMGMT_AD
= 1 << 2,
274 struct nvme_dsm_range
{
282 enum nvme_admin_opcode
{
283 nvme_admin_delete_sq
= 0x00,
284 nvme_admin_create_sq
= 0x01,
285 nvme_admin_get_log_page
= 0x02,
286 nvme_admin_delete_cq
= 0x04,
287 nvme_admin_create_cq
= 0x05,
288 nvme_admin_identify
= 0x06,
289 nvme_admin_abort_cmd
= 0x08,
290 nvme_admin_set_features
= 0x09,
291 nvme_admin_get_features
= 0x0a,
292 nvme_admin_async_event
= 0x0c,
293 nvme_admin_activate_fw
= 0x10,
294 nvme_admin_download_fw
= 0x11,
295 nvme_admin_format_nvm
= 0x80,
296 nvme_admin_security_send
= 0x81,
297 nvme_admin_security_recv
= 0x82,
301 NVME_QUEUE_PHYS_CONTIG
= (1 << 0),
302 NVME_CQ_IRQ_ENABLED
= (1 << 1),
303 NVME_SQ_PRIO_URGENT
= (0 << 1),
304 NVME_SQ_PRIO_HIGH
= (1 << 1),
305 NVME_SQ_PRIO_MEDIUM
= (2 << 1),
306 NVME_SQ_PRIO_LOW
= (3 << 1),
307 NVME_FEAT_ARBITRATION
= 0x01,
308 NVME_FEAT_POWER_MGMT
= 0x02,
309 NVME_FEAT_LBA_RANGE
= 0x03,
310 NVME_FEAT_TEMP_THRESH
= 0x04,
311 NVME_FEAT_ERR_RECOVERY
= 0x05,
312 NVME_FEAT_VOLATILE_WC
= 0x06,
313 NVME_FEAT_NUM_QUEUES
= 0x07,
314 NVME_FEAT_IRQ_COALESCE
= 0x08,
315 NVME_FEAT_IRQ_CONFIG
= 0x09,
316 NVME_FEAT_WRITE_ATOMIC
= 0x0a,
317 NVME_FEAT_ASYNC_EVENT
= 0x0b,
318 NVME_FEAT_SW_PROGRESS
= 0x0c,
321 struct nvme_identify
{
333 struct nvme_features
{
346 struct nvme_create_cq
{
360 struct nvme_create_sq
{
374 struct nvme_delete_queue
{
384 struct nvme_download_firmware
{
396 struct nvme_format_cmd
{
406 struct nvme_command
{
408 struct nvme_common_command common
;
409 struct nvme_rw_command rw
;
410 struct nvme_identify identify
;
411 struct nvme_features features
;
412 struct nvme_create_cq create_cq
;
413 struct nvme_create_sq create_sq
;
414 struct nvme_delete_queue delete_queue
;
415 struct nvme_download_firmware dlfw
;
416 struct nvme_format_cmd format
;
417 struct nvme_dsm_cmd dsm
;
422 NVME_SC_SUCCESS
= 0x0,
423 NVME_SC_INVALID_OPCODE
= 0x1,
424 NVME_SC_INVALID_FIELD
= 0x2,
425 NVME_SC_CMDID_CONFLICT
= 0x3,
426 NVME_SC_DATA_XFER_ERROR
= 0x4,
427 NVME_SC_POWER_LOSS
= 0x5,
428 NVME_SC_INTERNAL
= 0x6,
429 NVME_SC_ABORT_REQ
= 0x7,
430 NVME_SC_ABORT_QUEUE
= 0x8,
431 NVME_SC_FUSED_FAIL
= 0x9,
432 NVME_SC_FUSED_MISSING
= 0xa,
433 NVME_SC_INVALID_NS
= 0xb,
434 NVME_SC_CMD_SEQ_ERROR
= 0xc,
435 NVME_SC_LBA_RANGE
= 0x80,
436 NVME_SC_CAP_EXCEEDED
= 0x81,
437 NVME_SC_NS_NOT_READY
= 0x82,
438 NVME_SC_CQ_INVALID
= 0x100,
439 NVME_SC_QID_INVALID
= 0x101,
440 NVME_SC_QUEUE_SIZE
= 0x102,
441 NVME_SC_ABORT_LIMIT
= 0x103,
442 NVME_SC_ABORT_MISSING
= 0x104,
443 NVME_SC_ASYNC_LIMIT
= 0x105,
444 NVME_SC_FIRMWARE_SLOT
= 0x106,
445 NVME_SC_FIRMWARE_IMAGE
= 0x107,
446 NVME_SC_INVALID_VECTOR
= 0x108,
447 NVME_SC_INVALID_LOG_PAGE
= 0x109,
448 NVME_SC_INVALID_FORMAT
= 0x10a,
449 NVME_SC_BAD_ATTRIBUTES
= 0x180,
450 NVME_SC_WRITE_FAULT
= 0x280,
451 NVME_SC_READ_ERROR
= 0x281,
452 NVME_SC_GUARD_CHECK
= 0x282,
453 NVME_SC_APPTAG_CHECK
= 0x283,
454 NVME_SC_REFTAG_CHECK
= 0x284,
455 NVME_SC_COMPARE_FAILED
= 0x285,
456 NVME_SC_ACCESS_DENIED
= 0x286,
459 struct nvme_completion
{
460 __le32 result
; /* Used by admin commands to return data */
462 __le16 sq_head
; /* how much of this queue may be reclaimed */
463 __le16 sq_id
; /* submission queue that generated this entry */
464 __u16 command_id
; /* of the command which completed */
465 __le16 status
; /* did the command fail, and if so, why? */
468 struct nvme_user_io
{
483 struct nvme_admin_cmd
{
504 #define NVME_IOCTL_ID _IO('N', 0x40)
505 #define NVME_IOCTL_ADMIN_CMD _IOWR('N', 0x41, struct nvme_admin_cmd)
506 #define NVME_IOCTL_SUBMIT_IO _IOW('N', 0x42, struct nvme_user_io)
509 #include <linux/pci.h>
511 #define NVME_IO_TIMEOUT (5 * HZ)
514 * Represents an NVM Express device. Each nvme_dev is a PCI function.
517 struct list_head node
;
518 struct nvme_queue
**queues
;
520 struct pci_dev
*pci_dev
;
521 struct dma_pool
*prp_page_pool
;
522 struct dma_pool
*prp_small_pool
;
527 struct msix_entry
*entry
;
528 struct nvme_bar __iomem
*bar
;
529 struct list_head namespaces
;
532 char firmware_rev
[8];
538 * An NVM Express namespace is equivalent to a SCSI LUN
541 struct list_head list
;
543 struct nvme_dev
*dev
;
544 struct request_queue
*queue
;
545 struct gendisk
*disk
;
552 * The nvme_iod describes the data in an I/O, including the list of PRP
553 * entries. You can't see it in this data structure because C doesn't let
554 * me express that. Use nvme_alloc_iod to ensure there's enough space
555 * allocated to store the PRP list.
558 void *private; /* For the use of the submitter of the I/O */
559 int npages
; /* In the PRP list. 0 means small pool in use */
560 int offset
; /* Of PRP list */
561 int nents
; /* Used in scatterlist */
562 int length
; /* Of data, in bytes */
563 dma_addr_t first_dma
;
564 struct scatterlist sg
[0];
568 #endif /* _LINUX_NVME_H */