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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / mlx4 / device.h
1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX4_DEVICE_H
34 #define MLX4_DEVICE_H
35
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
39 #include <linux/cpu_rmap.h>
40
41 #include <linux/atomic.h>
42
43 #include <linux/clocksource.h>
44
45 #define MAX_MSIX_P_PORT 17
46 #define MAX_MSIX 64
47 #define MSIX_LEGACY_SZ 4
48 #define MIN_MSIX_P_PORT 5
49
50 enum {
51 MLX4_FLAG_MSI_X = 1 << 0,
52 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
53 MLX4_FLAG_MASTER = 1 << 2,
54 MLX4_FLAG_SLAVE = 1 << 3,
55 MLX4_FLAG_SRIOV = 1 << 4,
56 };
57
58 enum {
59 MLX4_PORT_CAP_IS_SM = 1 << 1,
60 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
61 };
62
63 enum {
64 MLX4_MAX_PORTS = 2,
65 MLX4_MAX_PORT_PKEYS = 128
66 };
67
68 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
69 * These qkeys must not be allowed for general use. This is a 64k range,
70 * and to test for violation, we use the mask (protect against future chg).
71 */
72 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
73 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
74
75 enum {
76 MLX4_BOARD_ID_LEN = 64
77 };
78
79 enum {
80 MLX4_MAX_NUM_PF = 16,
81 MLX4_MAX_NUM_VF = 64,
82 MLX4_MFUNC_MAX = 80,
83 MLX4_MAX_EQ_NUM = 1024,
84 MLX4_MFUNC_EQ_NUM = 4,
85 MLX4_MFUNC_MAX_EQES = 8,
86 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
87 };
88
89 /* Driver supports 3 diffrent device methods to manage traffic steering:
90 * -device managed - High level API for ib and eth flow steering. FW is
91 * managing flow steering tables.
92 * - B0 steering mode - Common low level API for ib and (if supported) eth.
93 * - A0 steering mode - Limited low level API for eth. In case of IB,
94 * B0 mode is in use.
95 */
96 enum {
97 MLX4_STEERING_MODE_A0,
98 MLX4_STEERING_MODE_B0,
99 MLX4_STEERING_MODE_DEVICE_MANAGED
100 };
101
102 static inline const char *mlx4_steering_mode_str(int steering_mode)
103 {
104 switch (steering_mode) {
105 case MLX4_STEERING_MODE_A0:
106 return "A0 steering";
107
108 case MLX4_STEERING_MODE_B0:
109 return "B0 steering";
110
111 case MLX4_STEERING_MODE_DEVICE_MANAGED:
112 return "Device managed flow steering";
113
114 default:
115 return "Unrecognize steering mode";
116 }
117 }
118
119 enum {
120 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
121 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
122 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
123 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
124 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
125 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
126 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
127 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
128 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
129 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
130 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
131 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
132 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
133 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
134 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
135 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
136 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
137 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
138 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
139 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
140 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
141 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
142 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
143 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
144 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
145 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
146 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
147 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
148 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
149 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
150 };
151
152 enum {
153 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
154 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
155 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
156 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
157 MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN = 1LL << 4,
158 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
159 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
160 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7
161 };
162
163 enum {
164 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
165 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1
166 };
167
168 enum {
169 MLX4_USER_DEV_CAP_64B_CQE = 1L << 0
170 };
171
172 enum {
173 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0
174 };
175
176
177 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
178
179 enum {
180 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
181 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
182 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
183 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
184 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
185 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
186 };
187
188 enum mlx4_event {
189 MLX4_EVENT_TYPE_COMP = 0x00,
190 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
191 MLX4_EVENT_TYPE_COMM_EST = 0x02,
192 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
193 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
194 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
195 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
196 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
197 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
198 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
199 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
200 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
201 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
202 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
203 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
204 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
205 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
206 MLX4_EVENT_TYPE_CMD = 0x0a,
207 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
208 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
209 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
210 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
211 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
212 MLX4_EVENT_TYPE_NONE = 0xff,
213 };
214
215 enum {
216 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
217 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
218 };
219
220 enum {
221 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
222 };
223
224 enum slave_port_state {
225 SLAVE_PORT_DOWN = 0,
226 SLAVE_PENDING_UP,
227 SLAVE_PORT_UP,
228 };
229
230 enum slave_port_gen_event {
231 SLAVE_PORT_GEN_EVENT_DOWN = 0,
232 SLAVE_PORT_GEN_EVENT_UP,
233 SLAVE_PORT_GEN_EVENT_NONE,
234 };
235
236 enum slave_port_state_event {
237 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
238 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
239 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
240 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
241 };
242
243 enum {
244 MLX4_PERM_LOCAL_READ = 1 << 10,
245 MLX4_PERM_LOCAL_WRITE = 1 << 11,
246 MLX4_PERM_REMOTE_READ = 1 << 12,
247 MLX4_PERM_REMOTE_WRITE = 1 << 13,
248 MLX4_PERM_ATOMIC = 1 << 14,
249 MLX4_PERM_BIND_MW = 1 << 15,
250 };
251
252 enum {
253 MLX4_OPCODE_NOP = 0x00,
254 MLX4_OPCODE_SEND_INVAL = 0x01,
255 MLX4_OPCODE_RDMA_WRITE = 0x08,
256 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
257 MLX4_OPCODE_SEND = 0x0a,
258 MLX4_OPCODE_SEND_IMM = 0x0b,
259 MLX4_OPCODE_LSO = 0x0e,
260 MLX4_OPCODE_RDMA_READ = 0x10,
261 MLX4_OPCODE_ATOMIC_CS = 0x11,
262 MLX4_OPCODE_ATOMIC_FA = 0x12,
263 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
264 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
265 MLX4_OPCODE_BIND_MW = 0x18,
266 MLX4_OPCODE_FMR = 0x19,
267 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
268 MLX4_OPCODE_CONFIG_CMD = 0x1f,
269
270 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
271 MLX4_RECV_OPCODE_SEND = 0x01,
272 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
273 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
274
275 MLX4_CQE_OPCODE_ERROR = 0x1e,
276 MLX4_CQE_OPCODE_RESIZE = 0x16,
277 };
278
279 enum {
280 MLX4_STAT_RATE_OFFSET = 5
281 };
282
283 enum mlx4_protocol {
284 MLX4_PROT_IB_IPV6 = 0,
285 MLX4_PROT_ETH,
286 MLX4_PROT_IB_IPV4,
287 MLX4_PROT_FCOE
288 };
289
290 enum {
291 MLX4_MTT_FLAG_PRESENT = 1
292 };
293
294 enum mlx4_qp_region {
295 MLX4_QP_REGION_FW = 0,
296 MLX4_QP_REGION_ETH_ADDR,
297 MLX4_QP_REGION_FC_ADDR,
298 MLX4_QP_REGION_FC_EXCH,
299 MLX4_NUM_QP_REGION
300 };
301
302 enum mlx4_port_type {
303 MLX4_PORT_TYPE_NONE = 0,
304 MLX4_PORT_TYPE_IB = 1,
305 MLX4_PORT_TYPE_ETH = 2,
306 MLX4_PORT_TYPE_AUTO = 3
307 };
308
309 enum mlx4_special_vlan_idx {
310 MLX4_NO_VLAN_IDX = 0,
311 MLX4_VLAN_MISS_IDX,
312 MLX4_VLAN_REGULAR
313 };
314
315 enum mlx4_steer_type {
316 MLX4_MC_STEER = 0,
317 MLX4_UC_STEER,
318 MLX4_NUM_STEERS
319 };
320
321 enum {
322 MLX4_NUM_FEXCH = 64 * 1024,
323 };
324
325 enum {
326 MLX4_MAX_FAST_REG_PAGES = 511,
327 };
328
329 enum {
330 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
331 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
332 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
333 };
334
335 /* Port mgmt change event handling */
336 enum {
337 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
338 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
339 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
340 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
341 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
342 };
343
344 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
345 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
346
347 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
348 {
349 return (major << 32) | (minor << 16) | subminor;
350 }
351
352 struct mlx4_phys_caps {
353 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
354 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
355 u32 num_phys_eqs;
356 u32 base_sqpn;
357 u32 base_proxy_sqpn;
358 u32 base_tunnel_sqpn;
359 };
360
361 struct mlx4_caps {
362 u64 fw_ver;
363 u32 function;
364 int num_ports;
365 int vl_cap[MLX4_MAX_PORTS + 1];
366 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
367 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
368 u64 def_mac[MLX4_MAX_PORTS + 1];
369 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
370 int gid_table_len[MLX4_MAX_PORTS + 1];
371 int pkey_table_len[MLX4_MAX_PORTS + 1];
372 int trans_type[MLX4_MAX_PORTS + 1];
373 int vendor_oui[MLX4_MAX_PORTS + 1];
374 int wavelength[MLX4_MAX_PORTS + 1];
375 u64 trans_code[MLX4_MAX_PORTS + 1];
376 int local_ca_ack_delay;
377 int num_uars;
378 u32 uar_page_size;
379 int bf_reg_size;
380 int bf_regs_per_page;
381 int max_sq_sg;
382 int max_rq_sg;
383 int num_qps;
384 int max_wqes;
385 int max_sq_desc_sz;
386 int max_rq_desc_sz;
387 int max_qp_init_rdma;
388 int max_qp_dest_rdma;
389 u32 *qp0_proxy;
390 u32 *qp1_proxy;
391 u32 *qp0_tunnel;
392 u32 *qp1_tunnel;
393 int num_srqs;
394 int max_srq_wqes;
395 int max_srq_sge;
396 int reserved_srqs;
397 int num_cqs;
398 int max_cqes;
399 int reserved_cqs;
400 int num_eqs;
401 int reserved_eqs;
402 int num_comp_vectors;
403 int comp_pool;
404 int num_mpts;
405 int max_fmr_maps;
406 int num_mtts;
407 int fmr_reserved_mtts;
408 int reserved_mtts;
409 int reserved_mrws;
410 int reserved_uars;
411 int num_mgms;
412 int num_amgms;
413 int reserved_mcgs;
414 int num_qp_per_mgm;
415 int steering_mode;
416 int fs_log_max_ucast_qp_range_size;
417 int num_pds;
418 int reserved_pds;
419 int max_xrcds;
420 int reserved_xrcds;
421 int mtt_entry_sz;
422 u32 max_msg_sz;
423 u32 page_size_cap;
424 u64 flags;
425 u64 flags2;
426 u32 bmme_flags;
427 u32 reserved_lkey;
428 u16 stat_rate_support;
429 u8 port_width_cap[MLX4_MAX_PORTS + 1];
430 int max_gso_sz;
431 int max_rss_tbl_sz;
432 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
433 int reserved_qps;
434 int reserved_qps_base[MLX4_NUM_QP_REGION];
435 int log_num_macs;
436 int log_num_vlans;
437 int log_num_prios;
438 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
439 u8 supported_type[MLX4_MAX_PORTS + 1];
440 u8 suggested_type[MLX4_MAX_PORTS + 1];
441 u8 default_sense[MLX4_MAX_PORTS + 1];
442 u32 port_mask[MLX4_MAX_PORTS + 1];
443 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
444 u32 max_counters;
445 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
446 u16 sqp_demux;
447 u32 eqe_size;
448 u32 cqe_size;
449 u8 eqe_factor;
450 u32 userspace_caps; /* userspace must be aware of these */
451 u32 function_caps; /* VFs must be aware of these */
452 u16 hca_core_clock;
453 };
454
455 struct mlx4_buf_list {
456 void *buf;
457 dma_addr_t map;
458 };
459
460 struct mlx4_buf {
461 struct mlx4_buf_list direct;
462 struct mlx4_buf_list *page_list;
463 int nbufs;
464 int npages;
465 int page_shift;
466 };
467
468 struct mlx4_mtt {
469 u32 offset;
470 int order;
471 int page_shift;
472 };
473
474 enum {
475 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
476 };
477
478 struct mlx4_db_pgdir {
479 struct list_head list;
480 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
481 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
482 unsigned long *bits[2];
483 __be32 *db_page;
484 dma_addr_t db_dma;
485 };
486
487 struct mlx4_ib_user_db_page;
488
489 struct mlx4_db {
490 __be32 *db;
491 union {
492 struct mlx4_db_pgdir *pgdir;
493 struct mlx4_ib_user_db_page *user_page;
494 } u;
495 dma_addr_t dma;
496 int index;
497 int order;
498 };
499
500 struct mlx4_hwq_resources {
501 struct mlx4_db db;
502 struct mlx4_mtt mtt;
503 struct mlx4_buf buf;
504 };
505
506 struct mlx4_mr {
507 struct mlx4_mtt mtt;
508 u64 iova;
509 u64 size;
510 u32 key;
511 u32 pd;
512 u32 access;
513 int enabled;
514 };
515
516 enum mlx4_mw_type {
517 MLX4_MW_TYPE_1 = 1,
518 MLX4_MW_TYPE_2 = 2,
519 };
520
521 struct mlx4_mw {
522 u32 key;
523 u32 pd;
524 enum mlx4_mw_type type;
525 int enabled;
526 };
527
528 struct mlx4_fmr {
529 struct mlx4_mr mr;
530 struct mlx4_mpt_entry *mpt;
531 __be64 *mtts;
532 dma_addr_t dma_handle;
533 int max_pages;
534 int max_maps;
535 int maps;
536 u8 page_shift;
537 };
538
539 struct mlx4_uar {
540 unsigned long pfn;
541 int index;
542 struct list_head bf_list;
543 unsigned free_bf_bmap;
544 void __iomem *map;
545 void __iomem *bf_map;
546 };
547
548 struct mlx4_bf {
549 unsigned long offset;
550 int buf_size;
551 struct mlx4_uar *uar;
552 void __iomem *reg;
553 };
554
555 struct mlx4_cq {
556 void (*comp) (struct mlx4_cq *);
557 void (*event) (struct mlx4_cq *, enum mlx4_event);
558
559 struct mlx4_uar *uar;
560
561 u32 cons_index;
562
563 __be32 *set_ci_db;
564 __be32 *arm_db;
565 int arm_sn;
566
567 int cqn;
568 unsigned vector;
569
570 atomic_t refcount;
571 struct completion free;
572 };
573
574 struct mlx4_qp {
575 void (*event) (struct mlx4_qp *, enum mlx4_event);
576
577 int qpn;
578
579 atomic_t refcount;
580 struct completion free;
581 };
582
583 struct mlx4_srq {
584 void (*event) (struct mlx4_srq *, enum mlx4_event);
585
586 int srqn;
587 int max;
588 int max_gs;
589 int wqe_shift;
590
591 atomic_t refcount;
592 struct completion free;
593 };
594
595 struct mlx4_av {
596 __be32 port_pd;
597 u8 reserved1;
598 u8 g_slid;
599 __be16 dlid;
600 u8 reserved2;
601 u8 gid_index;
602 u8 stat_rate;
603 u8 hop_limit;
604 __be32 sl_tclass_flowlabel;
605 u8 dgid[16];
606 };
607
608 struct mlx4_eth_av {
609 __be32 port_pd;
610 u8 reserved1;
611 u8 smac_idx;
612 u16 reserved2;
613 u8 reserved3;
614 u8 gid_index;
615 u8 stat_rate;
616 u8 hop_limit;
617 __be32 sl_tclass_flowlabel;
618 u8 dgid[16];
619 u32 reserved4[2];
620 __be16 vlan;
621 u8 mac[6];
622 };
623
624 union mlx4_ext_av {
625 struct mlx4_av ib;
626 struct mlx4_eth_av eth;
627 };
628
629 struct mlx4_counter {
630 u8 reserved1[3];
631 u8 counter_mode;
632 __be32 num_ifc;
633 u32 reserved2[2];
634 __be64 rx_frames;
635 __be64 rx_bytes;
636 __be64 tx_frames;
637 __be64 tx_bytes;
638 };
639
640 struct mlx4_dev {
641 struct pci_dev *pdev;
642 unsigned long flags;
643 unsigned long num_slaves;
644 struct mlx4_caps caps;
645 struct mlx4_phys_caps phys_caps;
646 struct radix_tree_root qp_table_tree;
647 u8 rev_id;
648 char board_id[MLX4_BOARD_ID_LEN];
649 int num_vfs;
650 int oper_log_mgm_entry_size;
651 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
652 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
653 };
654
655 struct mlx4_eqe {
656 u8 reserved1;
657 u8 type;
658 u8 reserved2;
659 u8 subtype;
660 union {
661 u32 raw[6];
662 struct {
663 __be32 cqn;
664 } __packed comp;
665 struct {
666 u16 reserved1;
667 __be16 token;
668 u32 reserved2;
669 u8 reserved3[3];
670 u8 status;
671 __be64 out_param;
672 } __packed cmd;
673 struct {
674 __be32 qpn;
675 } __packed qp;
676 struct {
677 __be32 srqn;
678 } __packed srq;
679 struct {
680 __be32 cqn;
681 u32 reserved1;
682 u8 reserved2[3];
683 u8 syndrome;
684 } __packed cq_err;
685 struct {
686 u32 reserved1[2];
687 __be32 port;
688 } __packed port_change;
689 struct {
690 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
691 u32 reserved;
692 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
693 } __packed comm_channel_arm;
694 struct {
695 u8 port;
696 u8 reserved[3];
697 __be64 mac;
698 } __packed mac_update;
699 struct {
700 __be32 slave_id;
701 } __packed flr_event;
702 struct {
703 __be16 current_temperature;
704 __be16 warning_threshold;
705 } __packed warming;
706 struct {
707 u8 reserved[3];
708 u8 port;
709 union {
710 struct {
711 __be16 mstr_sm_lid;
712 __be16 port_lid;
713 __be32 changed_attr;
714 u8 reserved[3];
715 u8 mstr_sm_sl;
716 __be64 gid_prefix;
717 } __packed port_info;
718 struct {
719 __be32 block_ptr;
720 __be32 tbl_entries_mask;
721 } __packed tbl_change_info;
722 } params;
723 } __packed port_mgmt_change;
724 } event;
725 u8 slave_id;
726 u8 reserved3[2];
727 u8 owner;
728 } __packed;
729
730 struct mlx4_init_port_param {
731 int set_guid0;
732 int set_node_guid;
733 int set_si_guid;
734 u16 mtu;
735 int port_width_cap;
736 u16 vl_cap;
737 u16 max_gid;
738 u16 max_pkey;
739 u64 guid0;
740 u64 node_guid;
741 u64 si_guid;
742 };
743
744 #define mlx4_foreach_port(port, dev, type) \
745 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
746 if ((type) == (dev)->caps.port_mask[(port)])
747
748 #define mlx4_foreach_non_ib_transport_port(port, dev) \
749 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
750 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
751
752 #define mlx4_foreach_ib_transport_port(port, dev) \
753 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
754 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
755 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
756
757 #define MLX4_INVALID_SLAVE_ID 0xFF
758
759 void handle_port_mgmt_change_event(struct work_struct *work);
760
761 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
762 {
763 return dev->caps.function;
764 }
765
766 static inline int mlx4_is_master(struct mlx4_dev *dev)
767 {
768 return dev->flags & MLX4_FLAG_MASTER;
769 }
770
771 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
772 {
773 return (qpn < dev->phys_caps.base_sqpn + 8 +
774 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev));
775 }
776
777 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
778 {
779 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
780
781 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
782 return 1;
783
784 return 0;
785 }
786
787 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
788 {
789 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
790 }
791
792 static inline int mlx4_is_slave(struct mlx4_dev *dev)
793 {
794 return dev->flags & MLX4_FLAG_SLAVE;
795 }
796
797 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
798 struct mlx4_buf *buf);
799 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
800 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
801 {
802 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
803 return buf->direct.buf + offset;
804 else
805 return buf->page_list[offset >> PAGE_SHIFT].buf +
806 (offset & (PAGE_SIZE - 1));
807 }
808
809 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
810 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
811 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
812 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
813
814 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
815 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
816 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf);
817 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
818
819 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
820 struct mlx4_mtt *mtt);
821 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
822 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
823
824 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
825 int npages, int page_shift, struct mlx4_mr *mr);
826 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
827 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
828 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
829 struct mlx4_mw *mw);
830 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
831 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
832 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
833 int start_index, int npages, u64 *page_list);
834 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
835 struct mlx4_buf *buf);
836
837 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
838 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
839
840 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
841 int size, int max_direct);
842 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
843 int size);
844
845 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
846 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
847 unsigned vector, int collapsed, int timestamp_en);
848 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
849
850 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
851 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
852
853 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
854 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
855
856 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
857 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
858 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
859 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
860 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
861
862 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
863 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
864
865 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
866 int block_mcast_loopback, enum mlx4_protocol prot);
867 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
868 enum mlx4_protocol prot);
869 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
870 u8 port, int block_mcast_loopback,
871 enum mlx4_protocol protocol, u64 *reg_id);
872 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
873 enum mlx4_protocol protocol, u64 reg_id);
874
875 enum {
876 MLX4_DOMAIN_UVERBS = 0x1000,
877 MLX4_DOMAIN_ETHTOOL = 0x2000,
878 MLX4_DOMAIN_RFS = 0x3000,
879 MLX4_DOMAIN_NIC = 0x5000,
880 };
881
882 enum mlx4_net_trans_rule_id {
883 MLX4_NET_TRANS_RULE_ID_ETH = 0,
884 MLX4_NET_TRANS_RULE_ID_IB,
885 MLX4_NET_TRANS_RULE_ID_IPV6,
886 MLX4_NET_TRANS_RULE_ID_IPV4,
887 MLX4_NET_TRANS_RULE_ID_TCP,
888 MLX4_NET_TRANS_RULE_ID_UDP,
889 MLX4_NET_TRANS_RULE_NUM, /* should be last */
890 };
891
892 extern const u16 __sw_id_hw[];
893
894 static inline int map_hw_to_sw_id(u16 header_id)
895 {
896
897 int i;
898 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
899 if (header_id == __sw_id_hw[i])
900 return i;
901 }
902 return -EINVAL;
903 }
904
905 enum mlx4_net_trans_promisc_mode {
906 MLX4_FS_REGULAR = 1,
907 MLX4_FS_ALL_DEFAULT,
908 MLX4_FS_MC_DEFAULT,
909 MLX4_FS_UC_SNIFFER,
910 MLX4_FS_MC_SNIFFER,
911 MLX4_FS_MODE_NUM, /* should be last */
912 };
913
914 struct mlx4_spec_eth {
915 u8 dst_mac[6];
916 u8 dst_mac_msk[6];
917 u8 src_mac[6];
918 u8 src_mac_msk[6];
919 u8 ether_type_enable;
920 __be16 ether_type;
921 __be16 vlan_id_msk;
922 __be16 vlan_id;
923 };
924
925 struct mlx4_spec_tcp_udp {
926 __be16 dst_port;
927 __be16 dst_port_msk;
928 __be16 src_port;
929 __be16 src_port_msk;
930 };
931
932 struct mlx4_spec_ipv4 {
933 __be32 dst_ip;
934 __be32 dst_ip_msk;
935 __be32 src_ip;
936 __be32 src_ip_msk;
937 };
938
939 struct mlx4_spec_ib {
940 __be32 l3_qpn;
941 __be32 qpn_msk;
942 u8 dst_gid[16];
943 u8 dst_gid_msk[16];
944 };
945
946 struct mlx4_spec_list {
947 struct list_head list;
948 enum mlx4_net_trans_rule_id id;
949 union {
950 struct mlx4_spec_eth eth;
951 struct mlx4_spec_ib ib;
952 struct mlx4_spec_ipv4 ipv4;
953 struct mlx4_spec_tcp_udp tcp_udp;
954 };
955 };
956
957 enum mlx4_net_trans_hw_rule_queue {
958 MLX4_NET_TRANS_Q_FIFO,
959 MLX4_NET_TRANS_Q_LIFO,
960 };
961
962 struct mlx4_net_trans_rule {
963 struct list_head list;
964 enum mlx4_net_trans_hw_rule_queue queue_mode;
965 bool exclusive;
966 bool allow_loopback;
967 enum mlx4_net_trans_promisc_mode promisc_mode;
968 u8 port;
969 u16 priority;
970 u32 qpn;
971 };
972
973 struct mlx4_net_trans_rule_hw_ctrl {
974 __be16 prio;
975 u8 type;
976 u8 flags;
977 u8 rsvd1;
978 u8 funcid;
979 u8 vep;
980 u8 port;
981 __be32 qpn;
982 __be32 rsvd2;
983 };
984
985 struct mlx4_net_trans_rule_hw_ib {
986 u8 size;
987 u8 rsvd1;
988 __be16 id;
989 u32 rsvd2;
990 __be32 l3_qpn;
991 __be32 qpn_mask;
992 u8 dst_gid[16];
993 u8 dst_gid_msk[16];
994 } __packed;
995
996 struct mlx4_net_trans_rule_hw_eth {
997 u8 size;
998 u8 rsvd;
999 __be16 id;
1000 u8 rsvd1[6];
1001 u8 dst_mac[6];
1002 u16 rsvd2;
1003 u8 dst_mac_msk[6];
1004 u16 rsvd3;
1005 u8 src_mac[6];
1006 u16 rsvd4;
1007 u8 src_mac_msk[6];
1008 u8 rsvd5;
1009 u8 ether_type_enable;
1010 __be16 ether_type;
1011 __be16 vlan_tag_msk;
1012 __be16 vlan_tag;
1013 } __packed;
1014
1015 struct mlx4_net_trans_rule_hw_tcp_udp {
1016 u8 size;
1017 u8 rsvd;
1018 __be16 id;
1019 __be16 rsvd1[3];
1020 __be16 dst_port;
1021 __be16 rsvd2;
1022 __be16 dst_port_msk;
1023 __be16 rsvd3;
1024 __be16 src_port;
1025 __be16 rsvd4;
1026 __be16 src_port_msk;
1027 } __packed;
1028
1029 struct mlx4_net_trans_rule_hw_ipv4 {
1030 u8 size;
1031 u8 rsvd;
1032 __be16 id;
1033 __be32 rsvd1;
1034 __be32 dst_ip;
1035 __be32 dst_ip_msk;
1036 __be32 src_ip;
1037 __be32 src_ip_msk;
1038 } __packed;
1039
1040 struct _rule_hw {
1041 union {
1042 struct {
1043 u8 size;
1044 u8 rsvd;
1045 __be16 id;
1046 };
1047 struct mlx4_net_trans_rule_hw_eth eth;
1048 struct mlx4_net_trans_rule_hw_ib ib;
1049 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1050 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1051 };
1052 };
1053
1054 /* translating DMFS verbs sniffer rule to the FW API would need two reg IDs */
1055 struct mlx4_flow_handle {
1056 u64 reg_id[2];
1057 };
1058
1059 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1060 enum mlx4_net_trans_promisc_mode mode);
1061 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1062 enum mlx4_net_trans_promisc_mode mode);
1063 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1064 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1065 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1066 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1067 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1068
1069 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1070 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1071 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1072 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1073 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
1074 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1075 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1076 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1077 u8 promisc);
1078 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
1079 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
1080 u8 *pg, u16 *ratelimit);
1081 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1082 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1083 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
1084
1085 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1086 int npages, u64 iova, u32 *lkey, u32 *rkey);
1087 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1088 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1089 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1090 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1091 u32 *lkey, u32 *rkey);
1092 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1093 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1094 int mlx4_test_interrupts(struct mlx4_dev *dev);
1095 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1096 int *vector);
1097 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1098
1099 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1100 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1101
1102 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1103 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1104
1105 int mlx4_flow_attach(struct mlx4_dev *dev,
1106 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1107 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1108 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1109 enum mlx4_net_trans_promisc_mode flow_type);
1110 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1111 enum mlx4_net_trans_rule_id id);
1112 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1113
1114 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1115 int i, int val);
1116
1117 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1118
1119 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1120 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1121 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1122 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1123 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1124 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1125 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1126
1127 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1128 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1129
1130 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1131
1132 #endif /* MLX4_DEVICE_H */
kernel source for telekom puls (alcatel/mediatek)