Merge branch 'for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / mfd / mc13783.h
1 /*
2 * Copyright 2009-2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9 #ifndef __LINUX_MFD_MC13783_H
10 #define __LINUX_MFD_MC13783_H
11
12 #include <linux/mfd/mc13xxx.h>
13
14 struct mc13783;
15
16 struct mc13xxx *mc13783_to_mc13xxx(struct mc13783 *mc13783);
17
18 static inline void mc13783_lock(struct mc13783 *mc13783)
19 {
20 mc13xxx_lock(mc13783_to_mc13xxx(mc13783));
21 }
22
23 static inline void mc13783_unlock(struct mc13783 *mc13783)
24 {
25 mc13xxx_unlock(mc13783_to_mc13xxx(mc13783));
26 }
27
28 static inline int mc13783_reg_read(struct mc13783 *mc13783,
29 unsigned int offset, u32 *val)
30 {
31 return mc13xxx_reg_read(mc13783_to_mc13xxx(mc13783), offset, val);
32 }
33
34 static inline int mc13783_reg_write(struct mc13783 *mc13783,
35 unsigned int offset, u32 val)
36 {
37 return mc13xxx_reg_write(mc13783_to_mc13xxx(mc13783), offset, val);
38 }
39
40 static inline int mc13783_reg_rmw(struct mc13783 *mc13783,
41 unsigned int offset, u32 mask, u32 val)
42 {
43 return mc13xxx_reg_rmw(mc13783_to_mc13xxx(mc13783), offset, mask, val);
44 }
45
46 static inline int mc13783_get_flags(struct mc13783 *mc13783)
47 {
48 return mc13xxx_get_flags(mc13783_to_mc13xxx(mc13783));
49 }
50
51 static inline int mc13783_irq_request(struct mc13783 *mc13783, int irq,
52 irq_handler_t handler, const char *name, void *dev)
53 {
54 return mc13xxx_irq_request(mc13783_to_mc13xxx(mc13783), irq,
55 handler, name, dev);
56 }
57
58 static inline int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq,
59 irq_handler_t handler, const char *name, void *dev)
60 {
61 return mc13xxx_irq_request_nounmask(mc13783_to_mc13xxx(mc13783), irq,
62 handler, name, dev);
63 }
64
65 static inline int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev)
66 {
67 return mc13xxx_irq_free(mc13783_to_mc13xxx(mc13783), irq, dev);
68 }
69
70 static inline int mc13783_irq_mask(struct mc13783 *mc13783, int irq)
71 {
72 return mc13xxx_irq_mask(mc13783_to_mc13xxx(mc13783), irq);
73 }
74
75 static inline int mc13783_irq_unmask(struct mc13783 *mc13783, int irq)
76 {
77 return mc13xxx_irq_unmask(mc13783_to_mc13xxx(mc13783), irq);
78 }
79 static inline int mc13783_irq_status(struct mc13783 *mc13783, int irq,
80 int *enabled, int *pending)
81 {
82 return mc13xxx_irq_status(mc13783_to_mc13xxx(mc13783),
83 irq, enabled, pending);
84 }
85
86 static inline int mc13783_irq_ack(struct mc13783 *mc13783, int irq)
87 {
88 return mc13xxx_irq_ack(mc13783_to_mc13xxx(mc13783), irq);
89 }
90
91 #define MC13783_ADC0 43
92 #define MC13783_ADC0_ADREFEN (1 << 10)
93 #define MC13783_ADC0_ADREFMODE (1 << 11)
94 #define MC13783_ADC0_TSMOD0 (1 << 12)
95 #define MC13783_ADC0_TSMOD1 (1 << 13)
96 #define MC13783_ADC0_TSMOD2 (1 << 14)
97 #define MC13783_ADC0_ADINC1 (1 << 16)
98 #define MC13783_ADC0_ADINC2 (1 << 17)
99
100 #define MC13783_ADC0_TSMOD_MASK (MC13783_ADC0_TSMOD0 | \
101 MC13783_ADC0_TSMOD1 | \
102 MC13783_ADC0_TSMOD2)
103
104 #define mc13783_regulator_init_data mc13xxx_regulator_init_data
105 #define mc13783_regulator_platform_data mc13xxx_regulator_platform_data
106 #define mc13783_led_platform_data mc13xxx_led_platform_data
107 #define mc13783_leds_platform_data mc13xxx_leds_platform_data
108
109 #define mc13783_platform_data mc13xxx_platform_data
110 #define MC13783_USE_TOUCHSCREEN MC13XXX_USE_TOUCHSCREEN
111 #define MC13783_USE_CODEC MC13XXX_USE_CODEC
112 #define MC13783_USE_ADC MC13XXX_USE_ADC
113 #define MC13783_USE_RTC MC13XXX_USE_RTC
114 #define MC13783_USE_REGULATOR MC13XXX_USE_REGULATOR
115 #define MC13783_USE_LED MC13XXX_USE_LED
116
117 #define MC13783_ADC_MODE_TS 1
118 #define MC13783_ADC_MODE_SINGLE_CHAN 2
119 #define MC13783_ADC_MODE_MULT_CHAN 3
120
121 int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
122 unsigned int channel, unsigned int *sample);
123
124
125 #define MC13783_SW_SW1A 0
126 #define MC13783_SW_SW1B 1
127 #define MC13783_SW_SW2A 2
128 #define MC13783_SW_SW2B 3
129 #define MC13783_SW_SW3 4
130 #define MC13783_SW_PLL 5
131 #define MC13783_REGU_VAUDIO 6
132 #define MC13783_REGU_VIOHI 7
133 #define MC13783_REGU_VIOLO 8
134 #define MC13783_REGU_VDIG 9
135 #define MC13783_REGU_VGEN 10
136 #define MC13783_REGU_VRFDIG 11
137 #define MC13783_REGU_VRFREF 12
138 #define MC13783_REGU_VRFCP 13
139 #define MC13783_REGU_VSIM 14
140 #define MC13783_REGU_VESIM 15
141 #define MC13783_REGU_VCAM 16
142 #define MC13783_REGU_VRFBG 17
143 #define MC13783_REGU_VVIB 18
144 #define MC13783_REGU_VRF1 19
145 #define MC13783_REGU_VRF2 20
146 #define MC13783_REGU_VMMC1 21
147 #define MC13783_REGU_VMMC2 22
148 #define MC13783_REGU_GPO1 23
149 #define MC13783_REGU_GPO2 24
150 #define MC13783_REGU_GPO3 25
151 #define MC13783_REGU_GPO4 26
152 #define MC13783_REGU_V1 27
153 #define MC13783_REGU_V2 28
154 #define MC13783_REGU_V3 29
155 #define MC13783_REGU_V4 30
156 #define MC13783_REGU_PWGT1SPI 31
157 #define MC13783_REGU_PWGT2SPI 32
158
159 #define MC13783_IRQ_ADCDONE MC13XXX_IRQ_ADCDONE
160 #define MC13783_IRQ_ADCBISDONE MC13XXX_IRQ_ADCBISDONE
161 #define MC13783_IRQ_TS MC13XXX_IRQ_TS
162 #define MC13783_IRQ_WHIGH 3
163 #define MC13783_IRQ_WLOW 4
164 #define MC13783_IRQ_CHGDET MC13XXX_IRQ_CHGDET
165 #define MC13783_IRQ_CHGOV 7
166 #define MC13783_IRQ_CHGREV MC13XXX_IRQ_CHGREV
167 #define MC13783_IRQ_CHGSHORT MC13XXX_IRQ_CHGSHORT
168 #define MC13783_IRQ_CCCV MC13XXX_IRQ_CCCV
169 #define MC13783_IRQ_CHGCURR MC13XXX_IRQ_CHGCURR
170 #define MC13783_IRQ_BPON MC13XXX_IRQ_BPON
171 #define MC13783_IRQ_LOBATL MC13XXX_IRQ_LOBATL
172 #define MC13783_IRQ_LOBATH MC13XXX_IRQ_LOBATH
173 #define MC13783_IRQ_UDP 15
174 #define MC13783_IRQ_USB 16
175 #define MC13783_IRQ_ID 19
176 #define MC13783_IRQ_SE1 21
177 #define MC13783_IRQ_CKDET 22
178 #define MC13783_IRQ_UDM 23
179 #define MC13783_IRQ_1HZ MC13XXX_IRQ_1HZ
180 #define MC13783_IRQ_TODA MC13XXX_IRQ_TODA
181 #define MC13783_IRQ_ONOFD1 27
182 #define MC13783_IRQ_ONOFD2 28
183 #define MC13783_IRQ_ONOFD3 29
184 #define MC13783_IRQ_SYSRST MC13XXX_IRQ_SYSRST
185 #define MC13783_IRQ_RTCRST MC13XXX_IRQ_RTCRST
186 #define MC13783_IRQ_PC MC13XXX_IRQ_PC
187 #define MC13783_IRQ_WARM MC13XXX_IRQ_WARM
188 #define MC13783_IRQ_MEMHLD MC13XXX_IRQ_MEMHLD
189 #define MC13783_IRQ_PWRRDY 35
190 #define MC13783_IRQ_THWARNL MC13XXX_IRQ_THWARNL
191 #define MC13783_IRQ_THWARNH MC13XXX_IRQ_THWARNH
192 #define MC13783_IRQ_CLK MC13XXX_IRQ_CLK
193 #define MC13783_IRQ_SEMAF 39
194 #define MC13783_IRQ_MC2B 41
195 #define MC13783_IRQ_HSDET 42
196 #define MC13783_IRQ_HSL 43
197 #define MC13783_IRQ_ALSPTH 44
198 #define MC13783_IRQ_AHSSHORT 45
199 #define MC13783_NUM_IRQ MC13XXX_NUM_IRQ
200
201 #endif /* ifndef __LINUX_MFD_MC13783_H */