include/linux/dmaengine.h

   1 /*
   2  * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc., 59
  16  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called COPYING.
  20  */
  21 #ifndef DMAENGINE_H
  22 #define DMAENGINE_H
  23
  24 #include <linux/device.h>
  25 #include <linux/uio.h>
  26 #include <linux/kref.h>
  27 #include <linux/completion.h>
  28 #include <linux/rcupdate.h>
  29 #include <linux/dma-mapping.h>
  30
  31 /**
  32  * enum dma_state - resource PNP/power management state
  33  * @DMA_RESOURCE_SUSPEND: DMA device going into low power state
  34  * @DMA_RESOURCE_RESUME: DMA device returning to full power
  35  * @DMA_RESOURCE_AVAILABLE: DMA device available to the system
  36  * @DMA_RESOURCE_REMOVED: DMA device removed from the system
  37  */
  38 enum dma_state {
  39         DMA_RESOURCE_SUSPEND,
  40         DMA_RESOURCE_RESUME,
  41         DMA_RESOURCE_AVAILABLE,
  42         DMA_RESOURCE_REMOVED,
  43 };
  44
  45 /**
  46  * enum dma_state_client - state of the channel in the client
  47  * @DMA_ACK: client would like to use, or was using this channel
  48  * @DMA_DUP: client has already seen this channel, or is not using this channel
  49  * @DMA_NAK: client does not want to see any more channels
  50  */
  51 enum dma_state_client {
  52         DMA_ACK,
  53         DMA_DUP,
  54         DMA_NAK,
  55 };
  56
  57 /**
  58  * typedef dma_cookie_t - an opaque DMA cookie
  59  *
  60  * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
  61  */
  62 typedef s32 dma_cookie_t;
  63
  64 #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
  65
  66 /**
  67  * enum dma_status - DMA transaction status
  68  * @DMA_SUCCESS: transaction completed successfully
  69  * @DMA_IN_PROGRESS: transaction not yet processed
  70  * @DMA_ERROR: transaction failed
  71  */
  72 enum dma_status {
  73         DMA_SUCCESS,
  74         DMA_IN_PROGRESS,
  75         DMA_ERROR,
  76 };
  77
  78 /**
  79  * enum dma_transaction_type - DMA transaction types/indexes
  80  */
  81 enum dma_transaction_type {
  82         DMA_MEMCPY,
  83         DMA_XOR,
  84         DMA_PQ_XOR,
  85         DMA_DUAL_XOR,
  86         DMA_PQ_UPDATE,
  87         DMA_ZERO_SUM,
  88         DMA_PQ_ZERO_SUM,
  89         DMA_MEMSET,
  90         DMA_MEMCPY_CRC32C,
  91         DMA_INTERRUPT,
  92 };
  93
  94 /* last transaction type for creation of the capabilities mask */
  95 #define DMA_TX_TYPE_END (DMA_INTERRUPT + 1)
  96
  97 /**
  98  * enum dma_ctrl_flags - DMA flags to augment operation preparation,
  99  *      control completion, and communicate status.
 100  * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
 101  *      this transaction
 102  * @DMA_CTRL_ACK - the descriptor cannot be reused until the client
 103  *      acknowledges receipt, i.e. has has a chance to establish any
 104  *      dependency chains
 105  */
 106 enum dma_ctrl_flags {
 107         DMA_PREP_INTERRUPT = (1 << 0),
 108         DMA_CTRL_ACK = (1 << 1),
 109 };
 110
 111 /**
 112  * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
 113  * See linux/cpumask.h
 114  */
 115 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
 116
 117 /**
 118  * struct dma_chan_percpu - the per-CPU part of struct dma_chan
 119  * @refcount: local_t used for open-coded "bigref" counting
 120  * @memcpy_count: transaction counter
 121  * @bytes_transferred: byte counter
 122  */
 123
 124 struct dma_chan_percpu {
 125         local_t refcount;
 126         /* stats */
 127         unsigned long memcpy_count;
 128         unsigned long bytes_transferred;
 129 };
 130
 131 /**
 132  * struct dma_chan - devices supply DMA channels, clients use them
 133  * @device: ptr to the dma device who supplies this channel, always !%NULL
 134  * @cookie: last cookie value returned to client
 135  * @chan_id: channel ID for sysfs
 136  * @class_dev: class device for sysfs
 137  * @refcount: kref, used in "bigref" slow-mode
 138  * @slow_ref: indicates that the DMA channel is free
 139  * @rcu: the DMA channel's RCU head
 140  * @device_node: used to add this to the device chan list
 141  * @local: per-cpu pointer to a struct dma_chan_percpu
 142  * @client-count: how many clients are using this channel
 143  */
 144 struct dma_chan {
 145         struct dma_device *device;
 146         dma_cookie_t cookie;
 147
 148         /* sysfs */
 149         int chan_id;
 150         struct device dev;
 151
 152         struct kref refcount;
 153         int slow_ref;
 154         struct rcu_head rcu;
 155
 156         struct list_head device_node;
 157         struct dma_chan_percpu *local;
 158         int client_count;
 159 };
 160
 161 #define to_dma_chan(p) container_of(p, struct dma_chan, dev)
 162
 163 void dma_chan_cleanup(struct kref *kref);
 164
 165 static inline void dma_chan_get(struct dma_chan *chan)
 166 {
 167         if (unlikely(chan->slow_ref))
 168                 kref_get(&chan->refcount);
 169         else {
 170                 local_inc(&(per_cpu_ptr(chan->local, get_cpu())->refcount));
 171                 put_cpu();
 172         }
 173 }
 174
 175 static inline void dma_chan_put(struct dma_chan *chan)
 176 {
 177         if (unlikely(chan->slow_ref))
 178                 kref_put(&chan->refcount, dma_chan_cleanup);
 179         else {
 180                 local_dec(&(per_cpu_ptr(chan->local, get_cpu())->refcount));
 181                 put_cpu();
 182         }
 183 }
 184
 185 /*
 186  * typedef dma_event_callback - function pointer to a DMA event callback
 187  * For each channel added to the system this routine is called for each client.
 188  * If the client would like to use the channel it returns '1' to signal (ack)
 189  * the dmaengine core to take out a reference on the channel and its
 190  * corresponding device.  A client must not 'ack' an available channel more
 191  * than once.  When a channel is removed all clients are notified.  If a client
 192  * is using the channel it must 'ack' the removal.  A client must not 'ack' a
 193  * removed channel more than once.
 194  * @client - 'this' pointer for the client context
 195  * @chan - channel to be acted upon
 196  * @state - available or removed
 197  */
 198 struct dma_client;
 199 typedef enum dma_state_client (*dma_event_callback) (struct dma_client *client,
 200                 struct dma_chan *chan, enum dma_state state);
 201
 202 /**
 203  * struct dma_client - info on the entity making use of DMA services
 204  * @event_callback: func ptr to call when something happens
 205  * @cap_mask: only return channels that satisfy the requested capabilities
 206  *  a value of zero corresponds to any capability
 207  * @global_node: list_head for global dma_client_list
 208  */
 209 struct dma_client {
 210         dma_event_callback      event_callback;
 211         dma_cap_mask_t          cap_mask;
 212         struct list_head        global_node;
 213 };
 214
 215 typedef void (*dma_async_tx_callback)(void *dma_async_param);
 216 /**
 217  * struct dma_async_tx_descriptor - async transaction descriptor
 218  * ---dma generic offload fields---
 219  * @cookie: tracking cookie for this transaction, set to -EBUSY if
 220  *      this tx is sitting on a dependency list
 221  * @flags: flags to augment operation preparation, control completion, and
 222  *      communicate status
 223  * @phys: physical address of the descriptor
 224  * @tx_list: driver common field for operations that require multiple
 225  *      descriptors
 226  * @chan: target channel for this operation
 227  * @tx_submit: set the prepared descriptor(s) to be executed by the engine
 228  * @callback: routine to call after this operation is complete
 229  * @callback_param: general parameter to pass to the callback routine
 230  * ---async_tx api specific fields---
 231  * @next: at completion submit this descriptor
 232  * @parent: pointer to the next level up in the dependency chain
 233  * @lock: protect the parent and next pointers
 234  */
 235 struct dma_async_tx_descriptor {
 236         dma_cookie_t cookie;
 237         enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
 238         dma_addr_t phys;
 239         struct list_head tx_list;
 240         struct dma_chan *chan;
 241         dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
 242         dma_async_tx_callback callback;
 243         void *callback_param;
 244         struct dma_async_tx_descriptor *next;
 245         struct dma_async_tx_descriptor *parent;
 246         spinlock_t lock;
 247 };
 248
 249 /**
 250  * struct dma_device - info on the entity supplying DMA services
 251  * @chancnt: how many DMA channels are supported
 252  * @channels: the list of struct dma_chan
 253  * @global_node: list_head for global dma_device_list
 254  * @cap_mask: one or more dma_capability flags
 255  * @max_xor: maximum number of xor sources, 0 if no capability
 256  * @refcount: reference count
 257  * @done: IO completion struct
 258  * @dev_id: unique device ID
 259  * @dev: struct device reference for dma mapping api
 260  * @device_alloc_chan_resources: allocate resources and return the
 261  *      number of allocated descriptors
 262  * @device_free_chan_resources: release DMA channel's resources
 263  * @device_prep_dma_memcpy: prepares a memcpy operation
 264  * @device_prep_dma_xor: prepares a xor operation
 265  * @device_prep_dma_zero_sum: prepares a zero_sum operation
 266  * @device_prep_dma_memset: prepares a memset operation
 267  * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
 268  * @device_issue_pending: push pending transactions to hardware
 269  */
 270 struct dma_device {
 271
 272         unsigned int chancnt;
 273         struct list_head channels;
 274         struct list_head global_node;
 275         dma_cap_mask_t  cap_mask;
 276         int max_xor;
 277
 278         struct kref refcount;
 279         struct completion done;
 280
 281         int dev_id;
 282         struct device *dev;
 283
 284         int (*device_alloc_chan_resources)(struct dma_chan *chan,
 285                         struct dma_client *client);
 286         void (*device_free_chan_resources)(struct dma_chan *chan);
 287
 288         struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
 289                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 290                 size_t len, unsigned long flags);
 291         struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
 292                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
 293                 unsigned int src_cnt, size_t len, unsigned long flags);
 294         struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)(
 295                 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
 296                 size_t len, u32 *result, unsigned long flags);
 297         struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
 298                 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
 299                 unsigned long flags);
 300         struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
 301                 struct dma_chan *chan, unsigned long flags);
 302
 303         enum dma_status (*device_is_tx_complete)(struct dma_chan *chan,
 304                         dma_cookie_t cookie, dma_cookie_t *last,
 305                         dma_cookie_t *used);
 306         void (*device_issue_pending)(struct dma_chan *chan);
 307 };
 308
 309 /* --- public DMA engine API --- */
 310
 311 void dma_async_client_register(struct dma_client *client);
 312 void dma_async_client_unregister(struct dma_client *client);
 313 void dma_async_client_chan_request(struct dma_client *client);
 314 dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
 315         void *dest, void *src, size_t len);
 316 dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
 317         struct page *page, unsigned int offset, void *kdata, size_t len);
 318 dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
 319         struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
 320         unsigned int src_off, size_t len);
 321 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
 322         struct dma_chan *chan);
 323
 324 static inline void
 325 async_tx_ack(struct dma_async_tx_descriptor *tx)
 326 {
 327         tx->flags |= DMA_CTRL_ACK;
 328 }
 329
 330 static inline int
 331 async_tx_test_ack(struct dma_async_tx_descriptor *tx)
 332 {
 333         return tx->flags & DMA_CTRL_ACK;
 334 }
 335
 336 #define first_dma_cap(mask) __first_dma_cap(&(mask))
 337 static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
 338 {
 339         return min_t(int, DMA_TX_TYPE_END,
 340                 find_first_bit(srcp->bits, DMA_TX_TYPE_END));
 341 }
 342
 343 #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
 344 static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
 345 {
 346         return min_t(int, DMA_TX_TYPE_END,
 347                 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
 348 }
 349
 350 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
 351 static inline void
 352 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
 353 {
 354         set_bit(tx_type, dstp->bits);
 355 }
 356
 357 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
 358 static inline int
 359 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
 360 {
 361         return test_bit(tx_type, srcp->bits);
 362 }
 363
 364 #define for_each_dma_cap_mask(cap, mask) \
 365         for ((cap) = first_dma_cap(mask);       \
 366                 (cap) < DMA_TX_TYPE_END;        \
 367                 (cap) = next_dma_cap((cap), (mask)))
 368
 369 /**
 370  * dma_async_issue_pending - flush pending transactions to HW
 371  * @chan: target DMA channel
 372  *
 373  * This allows drivers to push copies to HW in batches,
 374  * reducing MMIO writes where possible.
 375  */
 376 static inline void dma_async_issue_pending(struct dma_chan *chan)
 377 {
 378         chan->device->device_issue_pending(chan);
 379 }
 380
 381 #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
 382
 383 /**
 384  * dma_async_is_tx_complete - poll for transaction completion
 385  * @chan: DMA channel
 386  * @cookie: transaction identifier to check status of
 387  * @last: returns last completed cookie, can be NULL
 388  * @used: returns last issued cookie, can be NULL
 389  *
 390  * If @last and @used are passed in, upon return they reflect the driver
 391  * internal state and can be used with dma_async_is_complete() to check
 392  * the status of multiple cookies without re-checking hardware state.
 393  */
 394 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
 395         dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
 396 {
 397         return chan->device->device_is_tx_complete(chan, cookie, last, used);
 398 }
 399
 400 #define dma_async_memcpy_complete(chan, cookie, last, used)\
 401         dma_async_is_tx_complete(chan, cookie, last, used)
 402
 403 /**
 404  * dma_async_is_complete - test a cookie against chan state
 405  * @cookie: transaction identifier to test status of
 406  * @last_complete: last know completed transaction
 407  * @last_used: last cookie value handed out
 408  *
 409  * dma_async_is_complete() is used in dma_async_memcpy_complete()
 410  * the test logic is separated for lightweight testing of multiple cookies
 411  */
 412 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
 413                         dma_cookie_t last_complete, dma_cookie_t last_used)
 414 {
 415         if (last_complete <= last_used) {
 416                 if ((cookie <= last_complete) || (cookie > last_used))
 417                         return DMA_SUCCESS;
 418         } else {
 419                 if ((cookie <= last_complete) && (cookie > last_used))
 420                         return DMA_SUCCESS;
 421         }
 422         return DMA_IN_PROGRESS;
 423 }
 424
 425 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
 426
 427 /* --- DMA device --- */
 428
 429 int dma_async_device_register(struct dma_device *device);
 430 void dma_async_device_unregister(struct dma_device *device);
 431
 432 /* --- Helper iov-locking functions --- */
 433
 434 struct dma_page_list {
 435         char __user *base_address;
 436         int nr_pages;
 437         struct page **pages;
 438 };
 439
 440 struct dma_pinned_list {
 441         int nr_iovecs;
 442         struct dma_page_list page_list[0];
 443 };
 444
 445 struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
 446 void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
 447
 448 dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
 449         struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
 450 dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
 451         struct dma_pinned_list *pinned_list, struct page *page,
 452         unsigned int offset, size_t len);
 453
 454 #endif /* DMAENGINE_H */