Merge branch 'topic/hda' into for-linus
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / dmaengine.h
1 /*
2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
21 #ifndef DMAENGINE_H
22 #define DMAENGINE_H
23
24 #include <linux/device.h>
25 #include <linux/uio.h>
26 #include <linux/dma-mapping.h>
27
28 /**
29 * typedef dma_cookie_t - an opaque DMA cookie
30 *
31 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
32 */
33 typedef s32 dma_cookie_t;
34 #define DMA_MIN_COOKIE 1
35 #define DMA_MAX_COOKIE INT_MAX
36
37 #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
38
39 /**
40 * enum dma_status - DMA transaction status
41 * @DMA_SUCCESS: transaction completed successfully
42 * @DMA_IN_PROGRESS: transaction not yet processed
43 * @DMA_PAUSED: transaction is paused
44 * @DMA_ERROR: transaction failed
45 */
46 enum dma_status {
47 DMA_SUCCESS,
48 DMA_IN_PROGRESS,
49 DMA_PAUSED,
50 DMA_ERROR,
51 };
52
53 /**
54 * enum dma_transaction_type - DMA transaction types/indexes
55 *
56 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
57 * automatically set as dma devices are registered.
58 */
59 enum dma_transaction_type {
60 DMA_MEMCPY,
61 DMA_XOR,
62 DMA_PQ,
63 DMA_XOR_VAL,
64 DMA_PQ_VAL,
65 DMA_MEMSET,
66 DMA_INTERRUPT,
67 DMA_SG,
68 DMA_PRIVATE,
69 DMA_ASYNC_TX,
70 DMA_SLAVE,
71 DMA_CYCLIC,
72 };
73
74 /* last transaction type for creation of the capabilities mask */
75 #define DMA_TX_TYPE_END (DMA_CYCLIC + 1)
76
77
78 /**
79 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
80 * control completion, and communicate status.
81 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
82 * this transaction
83 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
84 * acknowledges receipt, i.e. has has a chance to establish any dependency
85 * chains
86 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
87 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
88 * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single
89 * (if not set, do the source dma-unmapping as page)
90 * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single
91 * (if not set, do the destination dma-unmapping as page)
92 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
93 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
94 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
95 * sources that were the result of a previous operation, in the case of a PQ
96 * operation it continues the calculation with new sources
97 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
98 * on the result of this operation
99 */
100 enum dma_ctrl_flags {
101 DMA_PREP_INTERRUPT = (1 << 0),
102 DMA_CTRL_ACK = (1 << 1),
103 DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
104 DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
105 DMA_COMPL_SRC_UNMAP_SINGLE = (1 << 4),
106 DMA_COMPL_DEST_UNMAP_SINGLE = (1 << 5),
107 DMA_PREP_PQ_DISABLE_P = (1 << 6),
108 DMA_PREP_PQ_DISABLE_Q = (1 << 7),
109 DMA_PREP_CONTINUE = (1 << 8),
110 DMA_PREP_FENCE = (1 << 9),
111 };
112
113 /**
114 * enum dma_ctrl_cmd - DMA operations that can optionally be exercised
115 * on a running channel.
116 * @DMA_TERMINATE_ALL: terminate all ongoing transfers
117 * @DMA_PAUSE: pause ongoing transfers
118 * @DMA_RESUME: resume paused transfer
119 * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers
120 * that need to runtime reconfigure the slave channels (as opposed to passing
121 * configuration data in statically from the platform). An additional
122 * argument of struct dma_slave_config must be passed in with this
123 * command.
124 * @FSLDMA_EXTERNAL_START: this command will put the Freescale DMA controller
125 * into external start mode.
126 */
127 enum dma_ctrl_cmd {
128 DMA_TERMINATE_ALL,
129 DMA_PAUSE,
130 DMA_RESUME,
131 DMA_SLAVE_CONFIG,
132 FSLDMA_EXTERNAL_START,
133 };
134
135 /**
136 * enum sum_check_bits - bit position of pq_check_flags
137 */
138 enum sum_check_bits {
139 SUM_CHECK_P = 0,
140 SUM_CHECK_Q = 1,
141 };
142
143 /**
144 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
145 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
146 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
147 */
148 enum sum_check_flags {
149 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
150 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
151 };
152
153
154 /**
155 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
156 * See linux/cpumask.h
157 */
158 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
159
160 /**
161 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
162 * @memcpy_count: transaction counter
163 * @bytes_transferred: byte counter
164 */
165
166 struct dma_chan_percpu {
167 /* stats */
168 unsigned long memcpy_count;
169 unsigned long bytes_transferred;
170 };
171
172 /**
173 * struct dma_chan - devices supply DMA channels, clients use them
174 * @device: ptr to the dma device who supplies this channel, always !%NULL
175 * @cookie: last cookie value returned to client
176 * @chan_id: channel ID for sysfs
177 * @dev: class device for sysfs
178 * @device_node: used to add this to the device chan list
179 * @local: per-cpu pointer to a struct dma_chan_percpu
180 * @client-count: how many clients are using this channel
181 * @table_count: number of appearances in the mem-to-mem allocation table
182 * @private: private data for certain client-channel associations
183 */
184 struct dma_chan {
185 struct dma_device *device;
186 dma_cookie_t cookie;
187
188 /* sysfs */
189 int chan_id;
190 struct dma_chan_dev *dev;
191
192 struct list_head device_node;
193 struct dma_chan_percpu __percpu *local;
194 int client_count;
195 int table_count;
196 void *private;
197 };
198
199 /**
200 * struct dma_chan_dev - relate sysfs device node to backing channel device
201 * @chan - driver channel device
202 * @device - sysfs device
203 * @dev_id - parent dma_device dev_id
204 * @idr_ref - reference count to gate release of dma_device dev_id
205 */
206 struct dma_chan_dev {
207 struct dma_chan *chan;
208 struct device device;
209 int dev_id;
210 atomic_t *idr_ref;
211 };
212
213 /**
214 * enum dma_slave_buswidth - defines bus with of the DMA slave
215 * device, source or target buses
216 */
217 enum dma_slave_buswidth {
218 DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
219 DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
220 DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
221 DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
222 DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
223 };
224
225 /**
226 * struct dma_slave_config - dma slave channel runtime config
227 * @direction: whether the data shall go in or out on this slave
228 * channel, right now. DMA_TO_DEVICE and DMA_FROM_DEVICE are
229 * legal values, DMA_BIDIRECTIONAL is not acceptable since we
230 * need to differentiate source and target addresses.
231 * @src_addr: this is the physical address where DMA slave data
232 * should be read (RX), if the source is memory this argument is
233 * ignored.
234 * @dst_addr: this is the physical address where DMA slave data
235 * should be written (TX), if the source is memory this argument
236 * is ignored.
237 * @src_addr_width: this is the width in bytes of the source (RX)
238 * register where DMA data shall be read. If the source
239 * is memory this may be ignored depending on architecture.
240 * Legal values: 1, 2, 4, 8.
241 * @dst_addr_width: same as src_addr_width but for destination
242 * target (TX) mutatis mutandis.
243 * @src_maxburst: the maximum number of words (note: words, as in
244 * units of the src_addr_width member, not bytes) that can be sent
245 * in one burst to the device. Typically something like half the
246 * FIFO depth on I/O peripherals so you don't overflow it. This
247 * may or may not be applicable on memory sources.
248 * @dst_maxburst: same as src_maxburst but for destination target
249 * mutatis mutandis.
250 *
251 * This struct is passed in as configuration data to a DMA engine
252 * in order to set up a certain channel for DMA transport at runtime.
253 * The DMA device/engine has to provide support for an additional
254 * command in the channel config interface, DMA_SLAVE_CONFIG
255 * and this struct will then be passed in as an argument to the
256 * DMA engine device_control() function.
257 *
258 * The rationale for adding configuration information to this struct
259 * is as follows: if it is likely that most DMA slave controllers in
260 * the world will support the configuration option, then make it
261 * generic. If not: if it is fixed so that it be sent in static from
262 * the platform data, then prefer to do that. Else, if it is neither
263 * fixed at runtime, nor generic enough (such as bus mastership on
264 * some CPU family and whatnot) then create a custom slave config
265 * struct and pass that, then make this config a member of that
266 * struct, if applicable.
267 */
268 struct dma_slave_config {
269 enum dma_data_direction direction;
270 dma_addr_t src_addr;
271 dma_addr_t dst_addr;
272 enum dma_slave_buswidth src_addr_width;
273 enum dma_slave_buswidth dst_addr_width;
274 u32 src_maxburst;
275 u32 dst_maxburst;
276 };
277
278 static inline const char *dma_chan_name(struct dma_chan *chan)
279 {
280 return dev_name(&chan->dev->device);
281 }
282
283 void dma_chan_cleanup(struct kref *kref);
284
285 /**
286 * typedef dma_filter_fn - callback filter for dma_request_channel
287 * @chan: channel to be reviewed
288 * @filter_param: opaque parameter passed through dma_request_channel
289 *
290 * When this optional parameter is specified in a call to dma_request_channel a
291 * suitable channel is passed to this routine for further dispositioning before
292 * being returned. Where 'suitable' indicates a non-busy channel that
293 * satisfies the given capability mask. It returns 'true' to indicate that the
294 * channel is suitable.
295 */
296 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
297
298 typedef void (*dma_async_tx_callback)(void *dma_async_param);
299 /**
300 * struct dma_async_tx_descriptor - async transaction descriptor
301 * ---dma generic offload fields---
302 * @cookie: tracking cookie for this transaction, set to -EBUSY if
303 * this tx is sitting on a dependency list
304 * @flags: flags to augment operation preparation, control completion, and
305 * communicate status
306 * @phys: physical address of the descriptor
307 * @chan: target channel for this operation
308 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
309 * @callback: routine to call after this operation is complete
310 * @callback_param: general parameter to pass to the callback routine
311 * ---async_tx api specific fields---
312 * @next: at completion submit this descriptor
313 * @parent: pointer to the next level up in the dependency chain
314 * @lock: protect the parent and next pointers
315 */
316 struct dma_async_tx_descriptor {
317 dma_cookie_t cookie;
318 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
319 dma_addr_t phys;
320 struct dma_chan *chan;
321 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
322 dma_async_tx_callback callback;
323 void *callback_param;
324 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
325 struct dma_async_tx_descriptor *next;
326 struct dma_async_tx_descriptor *parent;
327 spinlock_t lock;
328 #endif
329 };
330
331 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
332 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
333 {
334 }
335 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
336 {
337 }
338 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
339 {
340 BUG();
341 }
342 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
343 {
344 }
345 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
346 {
347 }
348 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
349 {
350 return NULL;
351 }
352 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
353 {
354 return NULL;
355 }
356
357 #else
358 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
359 {
360 spin_lock_bh(&txd->lock);
361 }
362 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
363 {
364 spin_unlock_bh(&txd->lock);
365 }
366 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
367 {
368 txd->next = next;
369 next->parent = txd;
370 }
371 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
372 {
373 txd->parent = NULL;
374 }
375 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
376 {
377 txd->next = NULL;
378 }
379 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
380 {
381 return txd->parent;
382 }
383 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
384 {
385 return txd->next;
386 }
387 #endif
388
389 /**
390 * struct dma_tx_state - filled in to report the status of
391 * a transfer.
392 * @last: last completed DMA cookie
393 * @used: last issued DMA cookie (i.e. the one in progress)
394 * @residue: the remaining number of bytes left to transmit
395 * on the selected transfer for states DMA_IN_PROGRESS and
396 * DMA_PAUSED if this is implemented in the driver, else 0
397 */
398 struct dma_tx_state {
399 dma_cookie_t last;
400 dma_cookie_t used;
401 u32 residue;
402 };
403
404 /**
405 * struct dma_device - info on the entity supplying DMA services
406 * @chancnt: how many DMA channels are supported
407 * @privatecnt: how many DMA channels are requested by dma_request_channel
408 * @channels: the list of struct dma_chan
409 * @global_node: list_head for global dma_device_list
410 * @cap_mask: one or more dma_capability flags
411 * @max_xor: maximum number of xor sources, 0 if no capability
412 * @max_pq: maximum number of PQ sources and PQ-continue capability
413 * @copy_align: alignment shift for memcpy operations
414 * @xor_align: alignment shift for xor operations
415 * @pq_align: alignment shift for pq operations
416 * @fill_align: alignment shift for memset operations
417 * @dev_id: unique device ID
418 * @dev: struct device reference for dma mapping api
419 * @device_alloc_chan_resources: allocate resources and return the
420 * number of allocated descriptors
421 * @device_free_chan_resources: release DMA channel's resources
422 * @device_prep_dma_memcpy: prepares a memcpy operation
423 * @device_prep_dma_xor: prepares a xor operation
424 * @device_prep_dma_xor_val: prepares a xor validation operation
425 * @device_prep_dma_pq: prepares a pq operation
426 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
427 * @device_prep_dma_memset: prepares a memset operation
428 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
429 * @device_prep_slave_sg: prepares a slave dma operation
430 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
431 * The function takes a buffer of size buf_len. The callback function will
432 * be called after period_len bytes have been transferred.
433 * @device_control: manipulate all pending operations on a channel, returns
434 * zero or error code
435 * @device_tx_status: poll for transaction completion, the optional
436 * txstate parameter can be supplied with a pointer to get a
437 * struct with auxilary transfer status information, otherwise the call
438 * will just return a simple status code
439 * @device_issue_pending: push pending transactions to hardware
440 */
441 struct dma_device {
442
443 unsigned int chancnt;
444 unsigned int privatecnt;
445 struct list_head channels;
446 struct list_head global_node;
447 dma_cap_mask_t cap_mask;
448 unsigned short max_xor;
449 unsigned short max_pq;
450 u8 copy_align;
451 u8 xor_align;
452 u8 pq_align;
453 u8 fill_align;
454 #define DMA_HAS_PQ_CONTINUE (1 << 15)
455
456 int dev_id;
457 struct device *dev;
458
459 int (*device_alloc_chan_resources)(struct dma_chan *chan);
460 void (*device_free_chan_resources)(struct dma_chan *chan);
461
462 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
463 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
464 size_t len, unsigned long flags);
465 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
466 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
467 unsigned int src_cnt, size_t len, unsigned long flags);
468 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
469 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
470 size_t len, enum sum_check_flags *result, unsigned long flags);
471 struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
472 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
473 unsigned int src_cnt, const unsigned char *scf,
474 size_t len, unsigned long flags);
475 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
476 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
477 unsigned int src_cnt, const unsigned char *scf, size_t len,
478 enum sum_check_flags *pqres, unsigned long flags);
479 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
480 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
481 unsigned long flags);
482 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
483 struct dma_chan *chan, unsigned long flags);
484 struct dma_async_tx_descriptor *(*device_prep_dma_sg)(
485 struct dma_chan *chan,
486 struct scatterlist *dst_sg, unsigned int dst_nents,
487 struct scatterlist *src_sg, unsigned int src_nents,
488 unsigned long flags);
489
490 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
491 struct dma_chan *chan, struct scatterlist *sgl,
492 unsigned int sg_len, enum dma_data_direction direction,
493 unsigned long flags);
494 struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
495 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
496 size_t period_len, enum dma_data_direction direction);
497 int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
498 unsigned long arg);
499
500 enum dma_status (*device_tx_status)(struct dma_chan *chan,
501 dma_cookie_t cookie,
502 struct dma_tx_state *txstate);
503 void (*device_issue_pending)(struct dma_chan *chan);
504 };
505
506 static inline int dmaengine_device_control(struct dma_chan *chan,
507 enum dma_ctrl_cmd cmd,
508 unsigned long arg)
509 {
510 return chan->device->device_control(chan, cmd, arg);
511 }
512
513 static inline int dmaengine_slave_config(struct dma_chan *chan,
514 struct dma_slave_config *config)
515 {
516 return dmaengine_device_control(chan, DMA_SLAVE_CONFIG,
517 (unsigned long)config);
518 }
519
520 static inline int dmaengine_terminate_all(struct dma_chan *chan)
521 {
522 return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
523 }
524
525 static inline int dmaengine_pause(struct dma_chan *chan)
526 {
527 return dmaengine_device_control(chan, DMA_PAUSE, 0);
528 }
529
530 static inline int dmaengine_resume(struct dma_chan *chan)
531 {
532 return dmaengine_device_control(chan, DMA_RESUME, 0);
533 }
534
535 static inline int dmaengine_submit(struct dma_async_tx_descriptor *desc)
536 {
537 return desc->tx_submit(desc);
538 }
539
540 static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len)
541 {
542 size_t mask;
543
544 if (!align)
545 return true;
546 mask = (1 << align) - 1;
547 if (mask & (off1 | off2 | len))
548 return false;
549 return true;
550 }
551
552 static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
553 size_t off2, size_t len)
554 {
555 return dmaengine_check_align(dev->copy_align, off1, off2, len);
556 }
557
558 static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
559 size_t off2, size_t len)
560 {
561 return dmaengine_check_align(dev->xor_align, off1, off2, len);
562 }
563
564 static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
565 size_t off2, size_t len)
566 {
567 return dmaengine_check_align(dev->pq_align, off1, off2, len);
568 }
569
570 static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
571 size_t off2, size_t len)
572 {
573 return dmaengine_check_align(dev->fill_align, off1, off2, len);
574 }
575
576 static inline void
577 dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
578 {
579 dma->max_pq = maxpq;
580 if (has_pq_continue)
581 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
582 }
583
584 static inline bool dmaf_continue(enum dma_ctrl_flags flags)
585 {
586 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
587 }
588
589 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
590 {
591 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
592
593 return (flags & mask) == mask;
594 }
595
596 static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
597 {
598 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
599 }
600
601 static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
602 {
603 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
604 }
605
606 /* dma_maxpq - reduce maxpq in the face of continued operations
607 * @dma - dma device with PQ capability
608 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
609 *
610 * When an engine does not support native continuation we need 3 extra
611 * source slots to reuse P and Q with the following coefficients:
612 * 1/ {00} * P : remove P from Q', but use it as a source for P'
613 * 2/ {01} * Q : use Q to continue Q' calculation
614 * 3/ {00} * Q : subtract Q from P' to cancel (2)
615 *
616 * In the case where P is disabled we only need 1 extra source:
617 * 1/ {01} * Q : use Q to continue Q' calculation
618 */
619 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
620 {
621 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
622 return dma_dev_to_maxpq(dma);
623 else if (dmaf_p_disabled_continue(flags))
624 return dma_dev_to_maxpq(dma) - 1;
625 else if (dmaf_continue(flags))
626 return dma_dev_to_maxpq(dma) - 3;
627 BUG();
628 }
629
630 /* --- public DMA engine API --- */
631
632 #ifdef CONFIG_DMA_ENGINE
633 void dmaengine_get(void);
634 void dmaengine_put(void);
635 #else
636 static inline void dmaengine_get(void)
637 {
638 }
639 static inline void dmaengine_put(void)
640 {
641 }
642 #endif
643
644 #ifdef CONFIG_NET_DMA
645 #define net_dmaengine_get() dmaengine_get()
646 #define net_dmaengine_put() dmaengine_put()
647 #else
648 static inline void net_dmaengine_get(void)
649 {
650 }
651 static inline void net_dmaengine_put(void)
652 {
653 }
654 #endif
655
656 #ifdef CONFIG_ASYNC_TX_DMA
657 #define async_dmaengine_get() dmaengine_get()
658 #define async_dmaengine_put() dmaengine_put()
659 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
660 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
661 #else
662 #define async_dma_find_channel(type) dma_find_channel(type)
663 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
664 #else
665 static inline void async_dmaengine_get(void)
666 {
667 }
668 static inline void async_dmaengine_put(void)
669 {
670 }
671 static inline struct dma_chan *
672 async_dma_find_channel(enum dma_transaction_type type)
673 {
674 return NULL;
675 }
676 #endif /* CONFIG_ASYNC_TX_DMA */
677
678 dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
679 void *dest, void *src, size_t len);
680 dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
681 struct page *page, unsigned int offset, void *kdata, size_t len);
682 dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
683 struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
684 unsigned int src_off, size_t len);
685 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
686 struct dma_chan *chan);
687
688 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
689 {
690 tx->flags |= DMA_CTRL_ACK;
691 }
692
693 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
694 {
695 tx->flags &= ~DMA_CTRL_ACK;
696 }
697
698 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
699 {
700 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
701 }
702
703 #define first_dma_cap(mask) __first_dma_cap(&(mask))
704 static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
705 {
706 return min_t(int, DMA_TX_TYPE_END,
707 find_first_bit(srcp->bits, DMA_TX_TYPE_END));
708 }
709
710 #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
711 static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
712 {
713 return min_t(int, DMA_TX_TYPE_END,
714 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
715 }
716
717 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
718 static inline void
719 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
720 {
721 set_bit(tx_type, dstp->bits);
722 }
723
724 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
725 static inline void
726 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
727 {
728 clear_bit(tx_type, dstp->bits);
729 }
730
731 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
732 static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
733 {
734 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
735 }
736
737 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
738 static inline int
739 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
740 {
741 return test_bit(tx_type, srcp->bits);
742 }
743
744 #define for_each_dma_cap_mask(cap, mask) \
745 for ((cap) = first_dma_cap(mask); \
746 (cap) < DMA_TX_TYPE_END; \
747 (cap) = next_dma_cap((cap), (mask)))
748
749 /**
750 * dma_async_issue_pending - flush pending transactions to HW
751 * @chan: target DMA channel
752 *
753 * This allows drivers to push copies to HW in batches,
754 * reducing MMIO writes where possible.
755 */
756 static inline void dma_async_issue_pending(struct dma_chan *chan)
757 {
758 chan->device->device_issue_pending(chan);
759 }
760
761 #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
762
763 /**
764 * dma_async_is_tx_complete - poll for transaction completion
765 * @chan: DMA channel
766 * @cookie: transaction identifier to check status of
767 * @last: returns last completed cookie, can be NULL
768 * @used: returns last issued cookie, can be NULL
769 *
770 * If @last and @used are passed in, upon return they reflect the driver
771 * internal state and can be used with dma_async_is_complete() to check
772 * the status of multiple cookies without re-checking hardware state.
773 */
774 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
775 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
776 {
777 struct dma_tx_state state;
778 enum dma_status status;
779
780 status = chan->device->device_tx_status(chan, cookie, &state);
781 if (last)
782 *last = state.last;
783 if (used)
784 *used = state.used;
785 return status;
786 }
787
788 #define dma_async_memcpy_complete(chan, cookie, last, used)\
789 dma_async_is_tx_complete(chan, cookie, last, used)
790
791 /**
792 * dma_async_is_complete - test a cookie against chan state
793 * @cookie: transaction identifier to test status of
794 * @last_complete: last know completed transaction
795 * @last_used: last cookie value handed out
796 *
797 * dma_async_is_complete() is used in dma_async_memcpy_complete()
798 * the test logic is separated for lightweight testing of multiple cookies
799 */
800 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
801 dma_cookie_t last_complete, dma_cookie_t last_used)
802 {
803 if (last_complete <= last_used) {
804 if ((cookie <= last_complete) || (cookie > last_used))
805 return DMA_SUCCESS;
806 } else {
807 if ((cookie <= last_complete) && (cookie > last_used))
808 return DMA_SUCCESS;
809 }
810 return DMA_IN_PROGRESS;
811 }
812
813 static inline void
814 dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
815 {
816 if (st) {
817 st->last = last;
818 st->used = used;
819 st->residue = residue;
820 }
821 }
822
823 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
824 #ifdef CONFIG_DMA_ENGINE
825 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
826 void dma_issue_pending_all(void);
827 struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
828 void dma_release_channel(struct dma_chan *chan);
829 #else
830 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
831 {
832 return DMA_SUCCESS;
833 }
834 static inline void dma_issue_pending_all(void)
835 {
836 }
837 static inline struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask,
838 dma_filter_fn fn, void *fn_param)
839 {
840 return NULL;
841 }
842 static inline void dma_release_channel(struct dma_chan *chan)
843 {
844 }
845 #endif
846
847 /* --- DMA device --- */
848
849 int dma_async_device_register(struct dma_device *device);
850 void dma_async_device_unregister(struct dma_device *device);
851 void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
852 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
853 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
854
855 /* --- Helper iov-locking functions --- */
856
857 struct dma_page_list {
858 char __user *base_address;
859 int nr_pages;
860 struct page **pages;
861 };
862
863 struct dma_pinned_list {
864 int nr_iovecs;
865 struct dma_page_list page_list[0];
866 };
867
868 struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
869 void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
870
871 dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
872 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
873 dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
874 struct dma_pinned_list *pinned_list, struct page *page,
875 unsigned int offset, size_t len);
876
877 #endif /* DMAENGINE_H */