include/linux/apm-exynos.h

   1 /* arch/arm64/mach-exynos/include/mach/apm-exynos.h
   2  *
   3  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   4  *                                                http://www.samsung.com
   5  *
   6  * APM register definitions
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __ASM_ARCH_REGS_APM_H
  14 #define __ASM_ARCH_REGS_APM_H __FILE__
  15
  16 #include <linux/regmap.h>
  17 #include <linux/types.h>
  18 #include <linux/file.h>
  19 #include <linux/fs.h>
  20
  21 /* Margin related variables */
  22 #define MARGIN_0MV                              (0)
  23 #define MARGIN_6_25MV                           (1)
  24 #define MARGIN_12_5MV                           (2)
  25 #define MARGIN_18_75MV                          (3)
  26 #define MARGIN_25MV                             (4)
  27 #define MARGIN_31_25MV                          (5)
  28 #define MARGIN_37_5MV                           (6)
  29 #define MARGIN_43_75MV                          (7)
  30 #define MARGIN_50MV                             (8)
  31 #define MARGIN_56_25MV                          (9)
  32 #define MARGIN_62_5MV                           (0xA)
  33 #define MARGIN_68_75MV                          (0xB)
  34 #define MARGIN_75MV                             (0xC)
  35 #define MARGIN_81_25MV                          (0xD)
  36 #define MARGIN_87_5MV                           (0xE)
  37 #define MARGIN_93_75MV                          (0xF)
  38
  39 /* PERIOD related variables */
  40 #define PERIOD_1MS                              (0)
  41 #define PERIOD_5MS                              (1)
  42
  43 /* APM Protocol related variables */
  44 /* Notifier variables */
  45 #define APM_READY                               (0x0001)
  46 #define APM_SLEEP                               (0x0002)
  47 #define APM_TIMEOUT                             (0x0003)
  48 #define CL_ENABLE                               (0x0004)
  49 #define CL_DISABLE                              (0x0005)
  50
  51 /* Shift variables */
  52 #define CL_DVFS_SHIFT                           (29)
  53 #define COMMAND_SHIFT                           (27)
  54 #define PM_SECTION_SHIFT                        (26)
  55 #define MASK_SHIFT                              (25)
  56 #define INIT_MODE_SHIFT                         (22)
  57 #define ASV_MODE_SHIFT                          (21)
  58 #define CL_ALL_STOP_SHIFT                       (30)
  59 #define CL_ALL_START_SHIFT                      (31)
  60 #define MULTI_BYTE_SHIFT                        (16)
  61 #define CL_DOMAIN_SHIFT                         (14)
  62
  63 #define MULTI_BYTE_CNT_SHIFT                    (16)
  64 #define ATLAS_SHIFT                             (0)
  65 #define APOLLO_SHIFT                            (4)
  66 #define G3D_SHIFT                               (8)
  67 #define MIF_SHIFT                               (12)
  68 #define PERIOD_SHIFT                            (16)
  69 #define BYTE_SHIFT                              (8)
  70 #define BYTE_MASK                               (0xFF)
  71 #define WRITE_MODE                              (0)
  72 #define READ_MODE                               (1)
  73 #define NONE                                    (2)
  74 #define TX_INTERRUPT_ENABLE                     (1)
  75 #define MASK                                    (1)
  76 #define BYTE_4                                  (4)
  77 #define INIT_SET                                (1)
  78 #define ASV_SET                                 (1)
  79 #define DEBUG_COUNT                             (10)
  80
  81 /* Mask variables */
  82 #define CL_DVFS_MASK                            (1)
  83 #define COMMAND_MASK                            (0x3)
  84 #define MULTI_BYTE_MASK                         (0xF)
  85 #define CL_DVFS                                 (CL_DVFS_MASK << CL_DVFS_SHIFT)
  86 #define CL_DVFS_OFF                             (0)
  87 #define COMMAND                                 (COMMAND_MASK << COMMAND_SHIFT)
  88 #define MULTI_BYTE                              (MULTI_BYTE_MASK << MULTI_BYTE_SHIFT)
  89
  90 /* Error variable */
  91 #define APM_RET_SUCESS                          (0xa)
  92 #define APM_GPIO_ERR                            (0xFFFFFFFF)
  93 #define PMIC_NO_ACK_ERR                         (0xEEEEEEEE)
  94 #define ERR_TIMEOUT                             (1)
  95 #define ERR_RETRY                               (2)
  96 #define ERR_OUT                                 (3)
  97 #define RETRY_ERR                               (-0xFF)
  98
  99 /* apm related variables */
 100 #define MSG_LEN                                 (5)
 101 #define G3D_LV_OFFSET                           (0)
 102 #define MBOX_LEN                                (4)
 103 #define TIMEOUT                                 (500)           /* timeout 500 msec */
 104 #define TX                                      (0)
 105 #define RX                                      (1)
 106 #define HSI2C_MODE                              (0)
 107 #define APM_MODE                                (1)
 108 #define APM_TIMOUT                              (2)
 109
 110 #define CL_ON                                   (1)
 111 #define CL_OFF                                  (0)
 112
 113 #define APM_OFF                                 (0)
 114 #define APM_ON                                  (1)
 115 #define APM_WFI_TIMEOUT                         (2)
 116
 117 #define EXYNOS_PMU_CORTEXM3_APM_CONFIGURATION                           (0x2500)
 118 #define EXYNOS_PMU_CORTEXM3_APM_STATUS                                  (0x2504)
 119 #define EXYNOS_PMU_CORTEXM3_APM_OPTION                                  (0x2508)
 120 #define EXYNOS_PMU_CORTEXM3_APM_DURATION0                               (0x2510)
 121 #define EXYNOS_PMU_CORTEXM3_APM_DURATION1                               (0x2514)
 122 #define EXYNOS_PMU_CORTEXM3_APM_DURATION2                               (0x2518)
 123 #define EXYNOS_PMU_CORTEXM3_APM_DURATION3                               (0x251C)
 124
 125 /* CORTEX M3 */
 126 #define ENABLE_APM                      (0x1 << 15)
 127 #define APM_STATUS_MASK                 (0x1)
 128 #define STANDBYWFI                      (28)
 129 #define STANDBYWFI_MASK                 (0x1)
 130 #define APM_LOCAL_PWR_CFG_RUN           (0x1 << 0)
 131 #define APM_LOCAL_PWR_CFG_RESET         (~(0x1 << 0))
 132
 133 struct apm_ops {
 134         int (*apm_update_bits) (unsigned int type, unsigned int reg,
 135                                         unsigned int mask, unsigned int value);
 136         int (*apm_write) (unsigned int type, unsigned int reg, unsigned int value);
 137         int (*apm_bulk_write) (unsigned int type, unsigned char reg,
 138                                         unsigned char *buf, unsigned int count);
 139         int (*apm_read) (unsigned int type, unsigned int reg, unsigned int *val);
 140         int (*apm_bulk_read) (unsigned int type, unsigned char reg,
 141                                 unsigned char *buf, unsigned int count);
 142 };
 143
 144 struct cl_ops {
 145         void (*apm_reset) (void);
 146         void (*apm_power_up) (void);
 147         void (*apm_power_down) (void);
 148         int (*cl_dvfs_setup) (unsigned int atlas_cl_limit, unsigned int apollo_cl_limit,
 149                                         unsigned int g3d_cl_limit, unsigned int mif_cl_limit, unsigned int cl_period);
 150         int (*cl_dvfs_start) (unsigned int cl_domain);
 151         int (*cl_dvfs_stop) (unsigned int cl_domain, unsigned int level);
 152         int (*cl_dvfs_enable) (void);
 153         int (*cl_dvfs_disable) (void);
 154         int (*g3d_power_on) (void);
 155         int (*g3d_power_down) (void);
 156         int (*enter_wfi) (void);
 157 };
 158
 159 struct debug_data {
 160         u32 buf[DEBUG_COUNT][6];
 161         s64 time[DEBUG_COUNT];
 162         char* name[DEBUG_COUNT];
 163         unsigned int cnt;
 164 #ifdef CONFIG_EXYNOS_APM_VOLTAGE_DEBUG
 165         u32 vol[DEBUG_COUNT][4];
 166         u32 atl_value;
 167         u32 apo_value;
 168         u32 g3d_value;
 169         u32 mif_value;
 170 #endif
 171 };
 172
 173 struct cl_init_data {
 174         u32 atlas_margin;
 175         u32 apollo_margin;
 176         u32 g3d_margin;
 177         u32 mif_margin;
 178         u32 period;
 179         u32 cl_status;
 180         u32 apm_status;
 181 };
 182
 183 extern void cl_dvfs_lock(void);
 184 extern void cl_dvfs_unlock(void);
 185 extern int cm3_status_open(struct inode *inode, struct file *file);
 186 extern struct apm_ops exynos_apm_function_ops;
 187
 188 extern int register_apm_notifier(struct notifier_block *nb);
 189 extern int unregister_apm_notifier(struct notifier_block *nb);
 190 extern int apm_notifier_call_chain(unsigned long val);
 191 extern void exynos_apm_reset_release(void);
 192 extern void exynos_apm_power_up(void);
 193 extern void exynos_apm_power_down(void);
 194 extern int exynos_cl_dvfs_setup(unsigned int atlas_cl_limit, unsigned int apollo_cl_limit, unsigned int g3d_cl_limit,
 195                                                                         unsigned int mif_cl_limit, unsigned int cl_period);
 196 extern int exynos_cl_dvfs_start(unsigned int cl_domain);
 197 extern int exynos_cl_dvfs_stop(unsigned int cl_domain, unsigned int level);
 198 extern int exynos_cl_dvfs_mode_enable(void);
 199 extern int exynos_cl_dvfs_mode_disable(void);
 200 extern int exynos_g3d_power_on_noti_apm(void);
 201 extern int exynos_g3d_power_down_noti_apm(void);
 202 extern int exynos_apm_enter_wfi(void);
 203 extern int exynos_apm_update_bits(unsigned int type, unsigned int reg, unsigned int mask, unsigned int value);
 204 extern int exynos_apm_write(unsigned int type, unsigned int address, unsigned int value);
 205 extern int exynos_apm_bulk_write(unsigned int type, unsigned char reg, unsigned char *buf, unsigned int count);
 206 extern int exynos_apm_read(unsigned int type, unsigned int reg, unsigned int *val);
 207 extern int exynos_apm_bulk_read(unsigned int type, unsigned char reg, unsigned char *buf, unsigned int count);
 208
 209 #define exynos7890_cl_dvfs_start(a)             exynos7420_cl_dvfs_start(a)
 210 #define exynos7890_cl_dvfs_stop(a, b)           exynos7420_cl_dvfs_stop(a, b)
 211 #define exynos7890_cl_dvfs_mode_enable()        exynos7420_cl_dvfs_mode_enable()
 212 #define exynos7890_cl_dvfs_mode_disable()       exynos7420_cl_dvfs_mode_disable()
 213 #define exynos7890_g3d_power_on_noti_apm()      exynos7420_g3d_power_on_noti_apm()
 214 #define exynos7890_g3d_power_down_noti_apm()    exynos7420_g3d_power_down_noti_apm()
 215 #define exynos7890_apm_enter_wfi()              exynos7420_apm_enter_wfi()
 216 #define exynos7890_apm_update_bits(a, b, c, d)  exynos7420_apm_update_bits(a, b, c, d)
 217 #define exynos7890_apm_write(a, b, c)           exynos7420_apm_write(a, b, c)
 218 #define exynos7890_apm_bulk_write(a, b, c, d)   exynos7420_apm_bulk_write(a, b, c, d)
 219 #define exynos7890_apm_read(a, b, c)            exynos7420_apm_read(a, b, c)
 220 #define exynos7890_apm_bulk_read(a, b, c, d)    exynos7420_apm_bulk_read(a, b, c, d)
 221
 222 unsigned int exynos_cortexm3_pmu_read(unsigned int offset);
 223 void exynos_cortexm3_pmu_write(unsigned int val, unsigned int offset);
 224 unsigned int exynos_mailbox_reg_read(unsigned int offset);
 225 void exynos_mailbox_reg_write(unsigned int val, unsigned int offset);
 226 #endif