include/asm-powerpc/ppc_asm.h

   1 /*
   2  * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
   3  */
   4 #ifndef _ASM_POWERPC_PPC_ASM_H
   5 #define _ASM_POWERPC_PPC_ASM_H
   6
   7 #include <linux/stringify.h>
   8 #include <linux/config.h>
   9
  10 #ifdef __ASSEMBLY__
  11
  12 /*
  13  * Macros for storing registers into and loading registers from
  14  * exception frames.
  15  */
  16 #ifdef __powerpc64__
  17 #define SAVE_GPR(n, base)       std     n,GPR0+8*(n)(base)
  18 #define REST_GPR(n, base)       ld      n,GPR0+8*(n)(base)
  19 #define SAVE_NVGPRS(base)       SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
  20 #define REST_NVGPRS(base)       REST_8GPRS(14, base); REST_10GPRS(22, base)
  21 #else
  22 #define SAVE_GPR(n, base)       stw     n,GPR0+4*(n)(base)
  23 #define REST_GPR(n, base)       lwz     n,GPR0+4*(n)(base)
  24 #define SAVE_NVGPRS(base)       SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
  25                                 SAVE_10GPRS(22, base)
  26 #define REST_NVGPRS(base)       REST_GPR(13, base); REST_8GPRS(14, base); \
  27                                 REST_10GPRS(22, base)
  28 #endif
  29
  30
  31 #define SAVE_2GPRS(n, base)     SAVE_GPR(n, base); SAVE_GPR(n+1, base)
  32 #define SAVE_4GPRS(n, base)     SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
  33 #define SAVE_8GPRS(n, base)     SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
  34 #define SAVE_10GPRS(n, base)    SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
  35 #define REST_2GPRS(n, base)     REST_GPR(n, base); REST_GPR(n+1, base)
  36 #define REST_4GPRS(n, base)     REST_2GPRS(n, base); REST_2GPRS(n+2, base)
  37 #define REST_8GPRS(n, base)     REST_4GPRS(n, base); REST_4GPRS(n+4, base)
  38 #define REST_10GPRS(n, base)    REST_8GPRS(n, base); REST_2GPRS(n+8, base)
  39
  40 #define SAVE_FPR(n, base)       stfd    n,THREAD_FPR0+8*(n)(base)
  41 #define SAVE_2FPRS(n, base)     SAVE_FPR(n, base); SAVE_FPR(n+1, base)
  42 #define SAVE_4FPRS(n, base)     SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
  43 #define SAVE_8FPRS(n, base)     SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
  44 #define SAVE_16FPRS(n, base)    SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
  45 #define SAVE_32FPRS(n, base)    SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
  46 #define REST_FPR(n, base)       lfd     n,THREAD_FPR0+8*(n)(base)
  47 #define REST_2FPRS(n, base)     REST_FPR(n, base); REST_FPR(n+1, base)
  48 #define REST_4FPRS(n, base)     REST_2FPRS(n, base); REST_2FPRS(n+2, base)
  49 #define REST_8FPRS(n, base)     REST_4FPRS(n, base); REST_4FPRS(n+4, base)
  50 #define REST_16FPRS(n, base)    REST_8FPRS(n, base); REST_8FPRS(n+8, base)
  51 #define REST_32FPRS(n, base)    REST_16FPRS(n, base); REST_16FPRS(n+16, base)
  52
  53 #define SAVE_VR(n,b,base)       li b,THREAD_VR0+(16*(n));  stvx n,b,base
  54 #define SAVE_2VRS(n,b,base)     SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
  55 #define SAVE_4VRS(n,b,base)     SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
  56 #define SAVE_8VRS(n,b,base)     SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
  57 #define SAVE_16VRS(n,b,base)    SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
  58 #define SAVE_32VRS(n,b,base)    SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
  59 #define REST_VR(n,b,base)       li b,THREAD_VR0+(16*(n)); lvx n,b,base
  60 #define REST_2VRS(n,b,base)     REST_VR(n,b,base); REST_VR(n+1,b,base)
  61 #define REST_4VRS(n,b,base)     REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
  62 #define REST_8VRS(n,b,base)     REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
  63 #define REST_16VRS(n,b,base)    REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
  64 #define REST_32VRS(n,b,base)    REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
  65
  66 #define SAVE_EVR(n,s,base)      evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
  67 #define SAVE_2EVRS(n,s,base)    SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
  68 #define SAVE_4EVRS(n,s,base)    SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
  69 #define SAVE_8EVRS(n,s,base)    SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
  70 #define SAVE_16EVRS(n,s,base)   SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
  71 #define SAVE_32EVRS(n,s,base)   SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
  72 #define REST_EVR(n,s,base)      lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
  73 #define REST_2EVRS(n,s,base)    REST_EVR(n,s,base); REST_EVR(n+1,s,base)
  74 #define REST_4EVRS(n,s,base)    REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
  75 #define REST_8EVRS(n,s,base)    REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
  76 #define REST_16EVRS(n,s,base)   REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
  77 #define REST_32EVRS(n,s,base)   REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
  78
  79 /* Macros to adjust thread priority for hardware multithreading */
  80 #define HMT_VERY_LOW    or      31,31,31        # very low priority
  81 #define HMT_LOW         or      1,1,1
  82 #define HMT_MEDIUM_LOW  or      6,6,6           # medium low priority
  83 #define HMT_MEDIUM      or      2,2,2
  84 #define HMT_MEDIUM_HIGH or      5,5,5           # medium high priority
  85 #define HMT_HIGH        or      3,3,3
  86
  87 /* handle instructions that older assemblers may not know */
  88 #define RFCI            .long 0x4c000066        /* rfci instruction */
  89 #define RFDI            .long 0x4c00004e        /* rfdi instruction */
  90 #define RFMCI           .long 0x4c00004c        /* rfmci instruction */
  91
  92 #ifdef CONFIG_PPC64
  93
  94 #define XGLUE(a,b) a##b
  95 #define GLUE(a,b) XGLUE(a,b)
  96
  97 #define _GLOBAL(name) \
  98         .section ".text"; \
  99         .align 2 ; \
 100         .globl name; \
 101         .globl GLUE(.,name); \
 102         .section ".opd","aw"; \
 103 name: \
 104         .quad GLUE(.,name); \
 105         .quad .TOC.@tocbase; \
 106         .quad 0; \
 107         .previous; \
 108         .type GLUE(.,name),@function; \
 109 GLUE(.,name):
 110
 111 #define _KPROBE(name) \
 112         .section ".kprobes.text","a"; \
 113         .align 2 ; \
 114         .globl name; \
 115         .globl GLUE(.,name); \
 116         .section ".opd","aw"; \
 117 name: \
 118         .quad GLUE(.,name); \
 119         .quad .TOC.@tocbase; \
 120         .quad 0; \
 121         .previous; \
 122         .type GLUE(.,name),@function; \
 123 GLUE(.,name):
 124
 125 #define _STATIC(name) \
 126         .section ".text"; \
 127         .align 2 ; \
 128         .section ".opd","aw"; \
 129 name: \
 130         .quad GLUE(.,name); \
 131         .quad .TOC.@tocbase; \
 132         .quad 0; \
 133         .previous; \
 134         .type GLUE(.,name),@function; \
 135 GLUE(.,name):
 136
 137 #else /* 32-bit */
 138
 139 #define _GLOBAL(n)      \
 140         .text;          \
 141         .stabs __stringify(n:F-1),N_FUN,0,0,n;\
 142         .globl n;       \
 143 n:
 144
 145 #define _KPROBE(n)      \
 146         .section ".kprobes.text","a";   \
 147         .globl  n;      \
 148 n:
 149
 150 #endif
 151
 152 /*
 153  * LOADADDR( rn, name )
 154  *   loads the address of 'name' into 'rn'
 155  *
 156  * LOADBASE( rn, name )
 157  *   loads the address (less the low 16 bits) of 'name' into 'rn'
 158  *   suitable for base+disp addressing
 159  */
 160 #ifdef __powerpc64__
 161 #define LOADADDR(rn,name) \
 162         lis     rn,name##@highest;      \
 163         ori     rn,rn,name##@higher;    \
 164         rldicr  rn,rn,32,31;            \
 165         oris    rn,rn,name##@h;         \
 166         ori     rn,rn,name##@l
 167
 168 #define LOADBASE(rn,name)               \
 169         .section .toc,"aw";             \
 170 1:      .tc     name[TC],name;          \
 171         .previous;                      \
 172         ld      rn,1b@toc(r2)
 173
 174 #define OFF(name)       0
 175
 176 #define SET_REG_TO_CONST(reg, value)                    \
 177         lis     reg,(((value)>>48)&0xFFFF);             \
 178         ori     reg,reg,(((value)>>32)&0xFFFF);         \
 179         rldicr  reg,reg,32,31;                          \
 180         oris    reg,reg,(((value)>>16)&0xFFFF);         \
 181         ori     reg,reg,((value)&0xFFFF);
 182
 183 #define SET_REG_TO_LABEL(reg, label)                    \
 184         lis     reg,(label)@highest;                    \
 185         ori     reg,reg,(label)@higher;                 \
 186         rldicr  reg,reg,32,31;                          \
 187         oris    reg,reg,(label)@h;                      \
 188         ori     reg,reg,(label)@l;
 189
 190 /* operations for longs and pointers */
 191 #define LDL     ld
 192 #define STL     std
 193 #define CMPI    cmpdi
 194
 195 #else /* 32-bit */
 196 #define LOADADDR(rn,name) \
 197         lis     rn,name@ha;     \
 198         addi    rn,rn,name@l
 199
 200 #define LOADBASE(rn,name)       \
 201         lis     rn,name@ha
 202
 203 #define OFF(name)       name@l
 204
 205 /* operations for longs and pointers */
 206 #define LDL     lwz
 207 #define STL     stw
 208 #define CMPI    cmpwi
 209
 210 #endif
 211
 212 /* various errata or part fixups */
 213 #ifdef CONFIG_PPC601_SYNC_FIX
 214 #define SYNC                            \
 215 BEGIN_FTR_SECTION                       \
 216         sync;                           \
 217         isync;                          \
 218 END_FTR_SECTION_IFSET(CPU_FTR_601)
 219 #define SYNC_601                        \
 220 BEGIN_FTR_SECTION                       \
 221         sync;                           \
 222 END_FTR_SECTION_IFSET(CPU_FTR_601)
 223 #define ISYNC_601                       \
 224 BEGIN_FTR_SECTION                       \
 225         isync;                          \
 226 END_FTR_SECTION_IFSET(CPU_FTR_601)
 227 #else
 228 #define SYNC
 229 #define SYNC_601
 230 #define ISYNC_601
 231 #endif
 232
 233
 234 #ifndef CONFIG_SMP
 235 #define TLBSYNC
 236 #else /* CONFIG_SMP */
 237 /* tlbsync is not implemented on 601 */
 238 #define TLBSYNC                         \
 239 BEGIN_FTR_SECTION                       \
 240         tlbsync;                        \
 241         sync;                           \
 242 END_FTR_SECTION_IFCLR(CPU_FTR_601)
 243 #endif
 244
 245
 246 /*
 247  * This instruction is not implemented on the PPC 603 or 601; however, on
 248  * the 403GCX and 405GP tlbia IS defined and tlbie is not.
 249  * All of these instructions exist in the 8xx, they have magical powers,
 250  * and they must be used.
 251  */
 252
 253 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
 254 #define tlbia                                   \
 255         li      r4,1024;                        \
 256         mtctr   r4;                             \
 257         lis     r4,KERNELBASE@h;                \
 258 0:      tlbie   r4;                             \
 259         addi    r4,r4,0x1000;                   \
 260         bdnz    0b
 261 #endif
 262
 263
 264 #ifdef CONFIG_IBM405_ERR77
 265 #define PPC405_ERR77(ra,rb)     dcbt    ra, rb;
 266 #define PPC405_ERR77_SYNC       sync;
 267 #else
 268 #define PPC405_ERR77(ra,rb)
 269 #define PPC405_ERR77_SYNC
 270 #endif
 271
 272
 273 #ifdef CONFIG_IBM440EP_ERR42
 274 #define PPC440EP_ERR42 isync
 275 #else
 276 #define PPC440EP_ERR42
 277 #endif
 278
 279
 280 #if defined(CONFIG_BOOKE)
 281 #define tophys(rd,rs)                           \
 282         addis   rd,rs,0
 283
 284 #define tovirt(rd,rs)                           \
 285         addis   rd,rs,0
 286
 287 #elif defined(CONFIG_PPC64)
 288 /* PPPBBB - DRENG  If KERNELBASE is always 0xC0...,
 289  * Then we can easily do this with one asm insn. -Peter
 290  */
 291 #define tophys(rd,rs)                           \
 292         lis     rd,((KERNELBASE>>48)&0xFFFF);   \
 293         rldicr  rd,rd,32,31;                    \
 294         sub     rd,rs,rd
 295
 296 #define tovirt(rd,rs)                           \
 297         lis     rd,((KERNELBASE>>48)&0xFFFF);   \
 298         rldicr  rd,rd,32,31;                    \
 299         add     rd,rs,rd
 300 #else
 301 /*
 302  * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
 303  * physical base address of RAM at compile time.
 304  */
 305 #define tophys(rd,rs)                           \
 306 0:      addis   rd,rs,-KERNELBASE@h;            \
 307         .section ".vtop_fixup","aw";            \
 308         .align  1;                              \
 309         .long   0b;                             \
 310         .previous
 311
 312 #define tovirt(rd,rs)                           \
 313 0:      addis   rd,rs,KERNELBASE@h;             \
 314         .section ".ptov_fixup","aw";            \
 315         .align  1;                              \
 316         .long   0b;                             \
 317         .previous
 318 #endif
 319
 320 #ifdef CONFIG_PPC64
 321 #define RFI             rfid
 322 #define MTMSRD(r)       mtmsrd  r
 323
 324 #else
 325 #define FIX_SRR1(ra, rb)
 326 #ifndef CONFIG_40x
 327 #define RFI             rfi
 328 #else
 329 #define RFI             rfi; b .        /* Prevent prefetch past rfi */
 330 #endif
 331 #define MTMSRD(r)       mtmsr   r
 332 #define CLR_TOP32(r)
 333 #endif
 334
 335 /* The boring bits... */
 336
 337 /* Condition Register Bit Fields */
 338
 339 #define cr0     0
 340 #define cr1     1
 341 #define cr2     2
 342 #define cr3     3
 343 #define cr4     4
 344 #define cr5     5
 345 #define cr6     6
 346 #define cr7     7
 347
 348
 349 /* General Purpose Registers (GPRs) */
 350
 351 #define r0      0
 352 #define r1      1
 353 #define r2      2
 354 #define r3      3
 355 #define r4      4
 356 #define r5      5
 357 #define r6      6
 358 #define r7      7
 359 #define r8      8
 360 #define r9      9
 361 #define r10     10
 362 #define r11     11
 363 #define r12     12
 364 #define r13     13
 365 #define r14     14
 366 #define r15     15
 367 #define r16     16
 368 #define r17     17
 369 #define r18     18
 370 #define r19     19
 371 #define r20     20
 372 #define r21     21
 373 #define r22     22
 374 #define r23     23
 375 #define r24     24
 376 #define r25     25
 377 #define r26     26
 378 #define r27     27
 379 #define r28     28
 380 #define r29     29
 381 #define r30     30
 382 #define r31     31
 383
 384
 385 /* Floating Point Registers (FPRs) */
 386
 387 #define fr0     0
 388 #define fr1     1
 389 #define fr2     2
 390 #define fr3     3
 391 #define fr4     4
 392 #define fr5     5
 393 #define fr6     6
 394 #define fr7     7
 395 #define fr8     8
 396 #define fr9     9
 397 #define fr10    10
 398 #define fr11    11
 399 #define fr12    12
 400 #define fr13    13
 401 #define fr14    14
 402 #define fr15    15
 403 #define fr16    16
 404 #define fr17    17
 405 #define fr18    18
 406 #define fr19    19
 407 #define fr20    20
 408 #define fr21    21
 409 #define fr22    22
 410 #define fr23    23
 411 #define fr24    24
 412 #define fr25    25
 413 #define fr26    26
 414 #define fr27    27
 415 #define fr28    28
 416 #define fr29    29
 417 #define fr30    30
 418 #define fr31    31
 419
 420 /* AltiVec Registers (VPRs) */
 421
 422 #define vr0     0
 423 #define vr1     1
 424 #define vr2     2
 425 #define vr3     3
 426 #define vr4     4
 427 #define vr5     5
 428 #define vr6     6
 429 #define vr7     7
 430 #define vr8     8
 431 #define vr9     9
 432 #define vr10    10
 433 #define vr11    11
 434 #define vr12    12
 435 #define vr13    13
 436 #define vr14    14
 437 #define vr15    15
 438 #define vr16    16
 439 #define vr17    17
 440 #define vr18    18
 441 #define vr19    19
 442 #define vr20    20
 443 #define vr21    21
 444 #define vr22    22
 445 #define vr23    23
 446 #define vr24    24
 447 #define vr25    25
 448 #define vr26    26
 449 #define vr27    27
 450 #define vr28    28
 451 #define vr29    29
 452 #define vr30    30
 453 #define vr31    31
 454
 455 /* SPE Registers (EVPRs) */
 456
 457 #define evr0    0
 458 #define evr1    1
 459 #define evr2    2
 460 #define evr3    3
 461 #define evr4    4
 462 #define evr5    5
 463 #define evr6    6
 464 #define evr7    7
 465 #define evr8    8
 466 #define evr9    9
 467 #define evr10   10
 468 #define evr11   11
 469 #define evr12   12
 470 #define evr13   13
 471 #define evr14   14
 472 #define evr15   15
 473 #define evr16   16
 474 #define evr17   17
 475 #define evr18   18
 476 #define evr19   19
 477 #define evr20   20
 478 #define evr21   21
 479 #define evr22   22
 480 #define evr23   23
 481 #define evr24   24
 482 #define evr25   25
 483 #define evr26   26
 484 #define evr27   27
 485 #define evr28   28
 486 #define evr29   29
 487 #define evr30   30
 488 #define evr31   31
 489
 490 /* some stab codes */
 491 #define N_FUN   36
 492 #define N_RSYM  64
 493 #define N_SLINE 68
 494 #define N_SO    100
 495
 496 #define ASM_CONST(x) x
 497 #else
 498   #define __ASM_CONST(x) x##UL
 499   #define ASM_CONST(x) __ASM_CONST(x)
 500 #endif /*  __ASSEMBLY__ */
 501
 502 #endif /* _ASM_POWERPC_PPC_ASM_H */