include/asm-powerpc/pci.h

   1 #ifndef __ASM_POWERPC_PCI_H
   2 #define __ASM_POWERPC_PCI_H
   3 #ifdef __KERNEL__
   4
   5 /*
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/types.h>
  13 #include <linux/slab.h>
  14 #include <linux/string.h>
  15 #include <linux/dma-mapping.h>
  16
  17 #include <asm/machdep.h>
  18 #include <asm/scatterlist.h>
  19 #include <asm/io.h>
  20 #include <asm/prom.h>
  21 #include <asm/pci-bridge.h>
  22
  23 #include <asm-generic/pci-dma-compat.h>
  24
  25 #define PCIBIOS_MIN_IO          0x1000
  26 #define PCIBIOS_MIN_MEM         0x10000000
  27
  28 struct pci_dev;
  29
  30 /* Values for the `which' argument to sys_pciconfig_iobase syscall.  */
  31 #define IOBASE_BRIDGE_NUMBER    0
  32 #define IOBASE_MEMORY           1
  33 #define IOBASE_IO               2
  34 #define IOBASE_ISA_IO           3
  35 #define IOBASE_ISA_MEM          4
  36
  37 /*
  38  * Set this to 1 if you want the kernel to re-assign all PCI
  39  * bus numbers
  40  */
  41 extern int pci_assign_all_buses;
  42 #define pcibios_assign_all_busses()     (pci_assign_all_buses)
  43
  44 #define pcibios_scan_all_fns(a, b)      0
  45
  46 static inline void pcibios_set_master(struct pci_dev *dev)
  47 {
  48         /* No special bus mastering setup handling */
  49 }
  50
  51 static inline void pcibios_penalize_isa_irq(int irq, int active)
  52 {
  53         /* We don't do dynamic PCI IRQ allocation */
  54 }
  55
  56 #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
  57 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
  58 {
  59         if (ppc_md.pci_get_legacy_ide_irq)
  60                 return ppc_md.pci_get_legacy_ide_irq(dev, channel);
  61         return channel ? 15 : 14;
  62 }
  63
  64 #ifdef CONFIG_PPC64
  65
  66 /*
  67  * We want to avoid touching the cacheline size or MWI bit.
  68  * pSeries firmware sets the cacheline size (which is not the cpu cacheline
  69  * size in all cases) and hardware treats MWI the same as memory write.
  70  */
  71 #define PCI_DISABLE_MWI
  72
  73 #ifdef CONFIG_PCI
  74 extern void set_pci_dma_ops(struct dma_mapping_ops *dma_ops);
  75 extern struct dma_mapping_ops *get_pci_dma_ops(void);
  76
  77 /* For DAC DMA, we currently don't support it by default, but
  78  * we let 64-bit platforms override this.
  79  */
  80 static inline int pci_dac_dma_supported(struct pci_dev *hwdev,u64 mask)
  81 {
  82         struct dma_mapping_ops *d = get_pci_dma_ops();
  83
  84         if (d && d->dac_dma_supported)
  85                 return d->dac_dma_supported(&hwdev->dev, mask);
  86         return 0;
  87 }
  88
  89 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
  90                                         enum pci_dma_burst_strategy *strat,
  91                                         unsigned long *strategy_parameter)
  92 {
  93         unsigned long cacheline_size;
  94         u8 byte;
  95
  96         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
  97         if (byte == 0)
  98                 cacheline_size = 1024;
  99         else
 100                 cacheline_size = (int) byte * 4;
 101
 102         *strat = PCI_DMA_BURST_MULTIPLE;
 103         *strategy_parameter = cacheline_size;
 104 }
 105 #else   /* CONFIG_PCI */
 106 #define set_pci_dma_ops(d)
 107 #define get_pci_dma_ops()       NULL
 108 #endif
 109
 110 /* Decide whether to display the domain number in /proc */
 111 extern int pci_proc_domain(struct pci_bus *bus);
 112
 113 #else /* 32-bit */
 114
 115 #ifdef CONFIG_PCI
 116 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 117                                         enum pci_dma_burst_strategy *strat,
 118                                         unsigned long *strategy_parameter)
 119 {
 120         *strat = PCI_DMA_BURST_INFINITY;
 121         *strategy_parameter = ~0UL;
 122 }
 123 #endif
 124
 125 /*
 126  * At present there are very few 32-bit PPC machines that can have
 127  * memory above the 4GB point, and we don't support that.
 128  */
 129 #define pci_dac_dma_supported(pci_dev, mask)    (0)
 130
 131 /* Set the name of the bus as it appears in /proc/bus/pci */
 132 static inline int pci_proc_domain(struct pci_bus *bus)
 133 {
 134         return 0;
 135 }
 136
 137 #endif /* CONFIG_PPC64 */
 138
 139 extern int pci_domain_nr(struct pci_bus *bus);
 140
 141 struct vm_area_struct;
 142 /* Map a range of PCI memory or I/O space for a device into user space */
 143 int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
 144                         enum pci_mmap_state mmap_state, int write_combine);
 145
 146 /* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
 147 #define HAVE_PCI_MMAP   1
 148
 149 #if defined(CONFIG_PPC64) || defined(CONFIG_NOT_COHERENT_CACHE)
 150 /*
 151  * For 64-bit kernels, pci_unmap_{single,page} is not a nop.
 152  * For 32-bit non-coherent kernels, pci_dma_sync_single_for_cpu() and
 153  * so on are not nops.
 154  * and thus...
 155  */
 156 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
 157         dma_addr_t ADDR_NAME;
 158 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         \
 159         __u32 LEN_NAME;
 160 #define pci_unmap_addr(PTR, ADDR_NAME)                  \
 161         ((PTR)->ADDR_NAME)
 162 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)         \
 163         (((PTR)->ADDR_NAME) = (VAL))
 164 #define pci_unmap_len(PTR, LEN_NAME)                    \
 165         ((PTR)->LEN_NAME)
 166 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
 167         (((PTR)->LEN_NAME) = (VAL))
 168
 169 #else /* 32-bit && coherent */
 170
 171 /* pci_unmap_{page,single} is a nop so... */
 172 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
 173 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
 174 #define pci_unmap_addr(PTR, ADDR_NAME)          (0)
 175 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
 176 #define pci_unmap_len(PTR, LEN_NAME)            (0)
 177 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)   do { } while (0)
 178
 179 #endif /* CONFIG_PPC64 || CONFIG_NOT_COHERENT_CACHE */
 180
 181 #ifdef CONFIG_PPC64
 182
 183 /* The PCI address space does not equal the physical memory address
 184  * space (we have an IOMMU).  The IDE and SCSI device layers use
 185  * this boolean for bounce buffer decisions.
 186  */
 187 #define PCI_DMA_BUS_IS_PHYS     (0)
 188
 189 #else /* 32-bit */
 190
 191 /* The PCI address space does equal the physical memory
 192  * address space (no IOMMU).  The IDE and SCSI device layers use
 193  * this boolean for bounce buffer decisions.
 194  */
 195 #define PCI_DMA_BUS_IS_PHYS     (1)
 196
 197 #endif /* CONFIG_PPC64 */
 198
 199 extern void pcibios_resource_to_bus(struct pci_dev *dev,
 200                         struct pci_bus_region *region,
 201                         struct resource *res);
 202
 203 extern void pcibios_bus_to_resource(struct pci_dev *dev,
 204                         struct resource *res,
 205                         struct pci_bus_region *region);
 206
 207 static inline struct resource *pcibios_select_root(struct pci_dev *pdev,
 208                         struct resource *res)
 209 {
 210         struct resource *root = NULL;
 211
 212         if (res->flags & IORESOURCE_IO)
 213                 root = &ioport_resource;
 214         if (res->flags & IORESOURCE_MEM)
 215                 root = &iomem_resource;
 216
 217         return root;
 218 }
 219
 220 extern void pcibios_fixup_device_resources(struct pci_dev *dev,
 221                         struct pci_bus *bus);
 222
 223 extern void pcibios_setup_new_device(struct pci_dev *dev);
 224
 225 extern void pcibios_claim_one_bus(struct pci_bus *b);
 226
 227 extern struct pci_controller *init_phb_dynamic(struct device_node *dn);
 228
 229 extern struct pci_dev *of_create_pci_dev(struct device_node *node,
 230                                         struct pci_bus *bus, int devfn);
 231
 232 extern void of_scan_pci_bridge(struct device_node *node,
 233                                 struct pci_dev *dev);
 234
 235 extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);
 236
 237 extern int pci_read_irq_line(struct pci_dev *dev);
 238
 239 extern void pcibios_add_platform_entries(struct pci_dev *dev);
 240
 241 struct file;
 242 extern pgprot_t pci_phys_mem_access_prot(struct file *file,
 243                                          unsigned long pfn,
 244                                          unsigned long size,
 245                                          pgprot_t prot);
 246
 247 #define HAVE_ARCH_PCI_RESOURCE_TO_USER
 248 extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
 249                                  const struct resource *rsrc,
 250                                  resource_size_t *start, resource_size_t *end);
 251
 252 #endif  /* __KERNEL__ */
 253 #endif /* __ASM_POWERPC_PCI_H */