include/asm-powerpc/immap_qe.h

   1 /*
   2  * include/asm-powerpc/immap_qe.h
   3  *
   4  * QUICC Engine (QE) Internal Memory Map.
   5  * The Internal Memory Map for devices with QE on them. This
   6  * is the superset of all QE devices (8360, etc.).
   7
   8  * Copyright (C) 2006. Freescale Semicondutor, Inc. All rights reserved.
   9  *
  10  * Authors:     Shlomi Gridish <gridish@freescale.com>
  11  *              Li Yang <leoli@freescale.com>
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18 #ifndef _ASM_POWERPC_IMMAP_QE_H
  19 #define _ASM_POWERPC_IMMAP_QE_H
  20 #ifdef __KERNEL__
  21
  22 #include <linux/kernel.h>
  23
  24 #define QE_IMMAP_SIZE   (1024 * 1024)   /* 1MB from 1MB+IMMR */
  25
  26 /* QE I-RAM */
  27 struct qe_iram {
  28         __be32  iadd;           /* I-RAM Address Register */
  29         __be32  idata;          /* I-RAM Data Register */
  30         u8      res0[0x78];
  31 } __attribute__ ((packed));
  32
  33 /* QE Interrupt Controller */
  34 struct qe_ic_regs {
  35         __be32  qicr;
  36         __be32  qivec;
  37         __be32  qripnr;
  38         __be32  qipnr;
  39         __be32  qipxcc;
  40         __be32  qipycc;
  41         __be32  qipwcc;
  42         __be32  qipzcc;
  43         __be32  qimr;
  44         __be32  qrimr;
  45         __be32  qicnr;
  46         u8      res0[0x4];
  47         __be32  qiprta;
  48         __be32  qiprtb;
  49         u8      res1[0x4];
  50         __be32  qricr;
  51         u8      res2[0x20];
  52         __be32  qhivec;
  53         u8      res3[0x1C];
  54 } __attribute__ ((packed));
  55
  56 /* Communications Processor */
  57 struct cp_qe {
  58         __be32  cecr;           /* QE command register */
  59         __be32  ceccr;          /* QE controller configuration register */
  60         __be32  cecdr;          /* QE command data register */
  61         u8      res0[0xA];
  62         __be16  ceter;          /* QE timer event register */
  63         u8      res1[0x2];
  64         __be16  cetmr;          /* QE timers mask register */
  65         __be32  cetscr;         /* QE time-stamp timer control register */
  66         __be32  cetsr1;         /* QE time-stamp register 1 */
  67         __be32  cetsr2;         /* QE time-stamp register 2 */
  68         u8      res2[0x8];
  69         __be32  cevter;         /* QE virtual tasks event register */
  70         __be32  cevtmr;         /* QE virtual tasks mask register */
  71         __be16  cercr;          /* QE RAM control register */
  72         u8      res3[0x2];
  73         u8      res4[0x24];
  74         __be16  ceexe1;         /* QE external request 1 event register */
  75         u8      res5[0x2];
  76         __be16  ceexm1;         /* QE external request 1 mask register */
  77         u8      res6[0x2];
  78         __be16  ceexe2;         /* QE external request 2 event register */
  79         u8      res7[0x2];
  80         __be16  ceexm2;         /* QE external request 2 mask register */
  81         u8      res8[0x2];
  82         __be16  ceexe3;         /* QE external request 3 event register */
  83         u8      res9[0x2];
  84         __be16  ceexm3;         /* QE external request 3 mask register */
  85         u8      res10[0x2];
  86         __be16  ceexe4;         /* QE external request 4 event register */
  87         u8      res11[0x2];
  88         __be16  ceexm4;         /* QE external request 4 mask register */
  89         u8      res12[0x2];
  90         u8      res13[0x280];
  91 } __attribute__ ((packed));
  92
  93 /* QE Multiplexer */
  94 struct qe_mux {
  95         __be32  cmxgcr;         /* CMX general clock route register */
  96         __be32  cmxsi1cr_l;     /* CMX SI1 clock route low register */
  97         __be32  cmxsi1cr_h;     /* CMX SI1 clock route high register */
  98         __be32  cmxsi1syr;      /* CMX SI1 SYNC route register */
  99         __be32  cmxucr1;        /* CMX UCC1, UCC3 clock route register */
 100         __be32  cmxucr2;        /* CMX UCC5, UCC7 clock route register */
 101         __be32  cmxucr3;        /* CMX UCC2, UCC4 clock route register */
 102         __be32  cmxucr4;        /* CMX UCC6, UCC8 clock route register */
 103         __be32  cmxupcr;        /* CMX UPC clock route register */
 104         u8      res0[0x1C];
 105 } __attribute__ ((packed));
 106
 107 /* QE Timers */
 108 struct qe_timers {
 109         u8      gtcfr1;         /* Timer 1 and Timer 2 global config register*/
 110         u8      res0[0x3];
 111         u8      gtcfr2;         /* Timer 3 and timer 4 global config register*/
 112         u8      res1[0xB];
 113         __be16  gtmdr1;         /* Timer 1 mode register */
 114         __be16  gtmdr2;         /* Timer 2 mode register */
 115         __be16  gtrfr1;         /* Timer 1 reference register */
 116         __be16  gtrfr2;         /* Timer 2 reference register */
 117         __be16  gtcpr1;         /* Timer 1 capture register */
 118         __be16  gtcpr2;         /* Timer 2 capture register */
 119         __be16  gtcnr1;         /* Timer 1 counter */
 120         __be16  gtcnr2;         /* Timer 2 counter */
 121         __be16  gtmdr3;         /* Timer 3 mode register */
 122         __be16  gtmdr4;         /* Timer 4 mode register */
 123         __be16  gtrfr3;         /* Timer 3 reference register */
 124         __be16  gtrfr4;         /* Timer 4 reference register */
 125         __be16  gtcpr3;         /* Timer 3 capture register */
 126         __be16  gtcpr4;         /* Timer 4 capture register */
 127         __be16  gtcnr3;         /* Timer 3 counter */
 128         __be16  gtcnr4;         /* Timer 4 counter */
 129         __be16  gtevr1;         /* Timer 1 event register */
 130         __be16  gtevr2;         /* Timer 2 event register */
 131         __be16  gtevr3;         /* Timer 3 event register */
 132         __be16  gtevr4;         /* Timer 4 event register */
 133         __be16  gtps;           /* Timer 1 prescale register */
 134         u8 res2[0x46];
 135 } __attribute__ ((packed));
 136
 137 /* BRG */
 138 struct qe_brg {
 139         __be32  brgc1;          /* BRG1 configuration register */
 140         __be32  brgc2;          /* BRG2 configuration register */
 141         __be32  brgc3;          /* BRG3 configuration register */
 142         __be32  brgc4;          /* BRG4 configuration register */
 143         __be32  brgc5;          /* BRG5 configuration register */
 144         __be32  brgc6;          /* BRG6 configuration register */
 145         __be32  brgc7;          /* BRG7 configuration register */
 146         __be32  brgc8;          /* BRG8 configuration register */
 147         __be32  brgc9;          /* BRG9 configuration register */
 148         __be32  brgc10;         /* BRG10 configuration register */
 149         __be32  brgc11;         /* BRG11 configuration register */
 150         __be32  brgc12;         /* BRG12 configuration register */
 151         __be32  brgc13;         /* BRG13 configuration register */
 152         __be32  brgc14;         /* BRG14 configuration register */
 153         __be32  brgc15;         /* BRG15 configuration register */
 154         __be32  brgc16;         /* BRG16 configuration register */
 155         u8      res0[0x40];
 156 } __attribute__ ((packed));
 157
 158 /* SPI */
 159 struct spi {
 160         u8      res0[0x20];
 161         __be32  spmode;         /* SPI mode register */
 162         u8      res1[0x2];
 163         u8      spie;           /* SPI event register */
 164         u8      res2[0x1];
 165         u8      res3[0x2];
 166         u8      spim;           /* SPI mask register */
 167         u8      res4[0x1];
 168         u8      res5[0x1];
 169         u8      spcom;          /* SPI command register */
 170         u8      res6[0x2];
 171         __be32  spitd;          /* SPI transmit data register (cpu mode) */
 172         __be32  spird;          /* SPI receive data register (cpu mode) */
 173         u8      res7[0x8];
 174 } __attribute__ ((packed));
 175
 176 /* SI */
 177 struct si1 {
 178         __be16  siamr1;         /* SI1 TDMA mode register */
 179         __be16  sibmr1;         /* SI1 TDMB mode register */
 180         __be16  sicmr1;         /* SI1 TDMC mode register */
 181         __be16  sidmr1;         /* SI1 TDMD mode register */
 182         u8      siglmr1_h;      /* SI1 global mode register high */
 183         u8      res0[0x1];
 184         u8      sicmdr1_h;      /* SI1 command register high */
 185         u8      res2[0x1];
 186         u8      sistr1_h;       /* SI1 status register high */
 187         u8      res3[0x1];
 188         __be16  sirsr1_h;       /* SI1 RAM shadow address register high */
 189         u8      sitarc1;        /* SI1 RAM counter Tx TDMA */
 190         u8      sitbrc1;        /* SI1 RAM counter Tx TDMB */
 191         u8      sitcrc1;        /* SI1 RAM counter Tx TDMC */
 192         u8      sitdrc1;        /* SI1 RAM counter Tx TDMD */
 193         u8      sirarc1;        /* SI1 RAM counter Rx TDMA */
 194         u8      sirbrc1;        /* SI1 RAM counter Rx TDMB */
 195         u8      sircrc1;        /* SI1 RAM counter Rx TDMC */
 196         u8      sirdrc1;        /* SI1 RAM counter Rx TDMD */
 197         u8      res4[0x8];
 198         __be16  siemr1;         /* SI1 TDME mode register 16 bits */
 199         __be16  sifmr1;         /* SI1 TDMF mode register 16 bits */
 200         __be16  sigmr1;         /* SI1 TDMG mode register 16 bits */
 201         __be16  sihmr1;         /* SI1 TDMH mode register 16 bits */
 202         u8      siglmg1_l;      /* SI1 global mode register low 8 bits */
 203         u8      res5[0x1];
 204         u8      sicmdr1_l;      /* SI1 command register low 8 bits */
 205         u8      res6[0x1];
 206         u8      sistr1_l;       /* SI1 status register low 8 bits */
 207         u8      res7[0x1];
 208         __be16  sirsr1_l;       /* SI1 RAM shadow address register low 16 bits*/
 209         u8      siterc1;        /* SI1 RAM counter Tx TDME 8 bits */
 210         u8      sitfrc1;        /* SI1 RAM counter Tx TDMF 8 bits */
 211         u8      sitgrc1;        /* SI1 RAM counter Tx TDMG 8 bits */
 212         u8      sithrc1;        /* SI1 RAM counter Tx TDMH 8 bits */
 213         u8      sirerc1;        /* SI1 RAM counter Rx TDME 8 bits */
 214         u8      sirfrc1;        /* SI1 RAM counter Rx TDMF 8 bits */
 215         u8      sirgrc1;        /* SI1 RAM counter Rx TDMG 8 bits */
 216         u8      sirhrc1;        /* SI1 RAM counter Rx TDMH 8 bits */
 217         u8      res8[0x8];
 218         __be32  siml1;          /* SI1 multiframe limit register */
 219         u8      siedm1;         /* SI1 extended diagnostic mode register */
 220         u8      res9[0xBB];
 221 } __attribute__ ((packed));
 222
 223 /* SI Routing Tables */
 224 struct sir {
 225         u8      tx[0x400];
 226         u8      rx[0x400];
 227         u8      res0[0x800];
 228 } __attribute__ ((packed));
 229
 230 /* USB Controller */
 231 struct usb_ctlr {
 232         u8      usb_usmod;
 233         u8      usb_usadr;
 234         u8      usb_uscom;
 235         u8      res1[1];
 236         __be16  usb_usep1;
 237         __be16  usb_usep2;
 238         __be16  usb_usep3;
 239         __be16  usb_usep4;
 240         u8      res2[4];
 241         __be16  usb_usber;
 242         u8      res3[2];
 243         __be16  usb_usbmr;
 244         u8      res4[1];
 245         u8      usb_usbs;
 246         __be16  usb_ussft;
 247         u8      res5[2];
 248         __be16  usb_usfrn;
 249         u8      res6[0x22];
 250 } __attribute__ ((packed));
 251
 252 /* MCC */
 253 struct mcc {
 254         __be32  mcce;           /* MCC event register */
 255         __be32  mccm;           /* MCC mask register */
 256         __be32  mccf;           /* MCC configuration register */
 257         __be32  merl;           /* MCC emergency request level register */
 258         u8      res0[0xF0];
 259 } __attribute__ ((packed));
 260
 261 /* QE UCC Slow */
 262 struct ucc_slow {
 263         __be32  gumr_l;         /* UCCx general mode register (low) */
 264         __be32  gumr_h;         /* UCCx general mode register (high) */
 265         __be16  upsmr;          /* UCCx protocol-specific mode register */
 266         u8      res0[0x2];
 267         __be16  utodr;          /* UCCx transmit on demand register */
 268         __be16  udsr;           /* UCCx data synchronization register */
 269         __be16  ucce;           /* UCCx event register */
 270         u8      res1[0x2];
 271         __be16  uccm;           /* UCCx mask register */
 272         u8      res2[0x1];
 273         u8      uccs;           /* UCCx status register */
 274         u8      res3[0x24];
 275         __be16  utpt;
 276         u8      guemr;          /* UCC general extended mode register */
 277         u8      res4[0x200 - 0x091];
 278 } __attribute__ ((packed));
 279
 280 /* QE UCC Fast */
 281 struct ucc_fast {
 282         __be32  gumr;           /* UCCx general mode register */
 283         __be32  upsmr;          /* UCCx protocol-specific mode register */
 284         __be16  utodr;          /* UCCx transmit on demand register */
 285         u8      res0[0x2];
 286         __be16  udsr;           /* UCCx data synchronization register */
 287         u8      res1[0x2];
 288         __be32  ucce;           /* UCCx event register */
 289         __be32  uccm;           /* UCCx mask register */
 290         u8      uccs;           /* UCCx status register */
 291         u8      res2[0x7];
 292         __be32  urfb;           /* UCC receive FIFO base */
 293         __be16  urfs;           /* UCC receive FIFO size */
 294         u8      res3[0x2];
 295         __be16  urfet;          /* UCC receive FIFO emergency threshold */
 296         __be16  urfset;         /* UCC receive FIFO special emergency
 297                                    threshold */
 298         __be32  utfb;           /* UCC transmit FIFO base */
 299         __be16  utfs;           /* UCC transmit FIFO size */
 300         u8      res4[0x2];
 301         __be16  utfet;          /* UCC transmit FIFO emergency threshold */
 302         u8      res5[0x2];
 303         __be16  utftt;          /* UCC transmit FIFO transmit threshold */
 304         u8      res6[0x2];
 305         __be16  utpt;           /* UCC transmit polling timer */
 306         u8      res7[0x2];
 307         __be32  urtry;          /* UCC retry counter register */
 308         u8      res8[0x4C];
 309         u8      guemr;          /* UCC general extended mode register */
 310         u8      res9[0x100 - 0x091];
 311 } __attribute__ ((packed));
 312
 313 /* QE UCC */
 314 struct ucc_common {
 315         u8      res1[0x90];
 316         u8      guemr;
 317         u8      res2[0x200 - 0x091];
 318 } __attribute__ ((packed));
 319
 320 struct ucc {
 321         union {
 322                 struct  ucc_slow slow;
 323                 struct  ucc_fast fast;
 324                 struct  ucc_common common;
 325         };
 326 } __attribute__ ((packed));
 327
 328 /* MultiPHY UTOPIA POS Controllers (UPC) */
 329 struct upc {
 330         __be32  upgcr;          /* UTOPIA/POS general configuration register */
 331         __be32  uplpa;          /* UTOPIA/POS last PHY address */
 332         __be32  uphec;          /* ATM HEC register */
 333         __be32  upuc;           /* UTOPIA/POS UCC configuration */
 334         __be32  updc1;          /* UTOPIA/POS device 1 configuration */
 335         __be32  updc2;          /* UTOPIA/POS device 2 configuration */
 336         __be32  updc3;          /* UTOPIA/POS device 3 configuration */
 337         __be32  updc4;          /* UTOPIA/POS device 4 configuration */
 338         __be32  upstpa;         /* UTOPIA/POS STPA threshold */
 339         u8      res0[0xC];
 340         __be32  updrs1_h;       /* UTOPIA/POS device 1 rate select */
 341         __be32  updrs1_l;       /* UTOPIA/POS device 1 rate select */
 342         __be32  updrs2_h;       /* UTOPIA/POS device 2 rate select */
 343         __be32  updrs2_l;       /* UTOPIA/POS device 2 rate select */
 344         __be32  updrs3_h;       /* UTOPIA/POS device 3 rate select */
 345         __be32  updrs3_l;       /* UTOPIA/POS device 3 rate select */
 346         __be32  updrs4_h;       /* UTOPIA/POS device 4 rate select */
 347         __be32  updrs4_l;       /* UTOPIA/POS device 4 rate select */
 348         __be32  updrp1;         /* UTOPIA/POS device 1 receive priority low */
 349         __be32  updrp2;         /* UTOPIA/POS device 2 receive priority low */
 350         __be32  updrp3;         /* UTOPIA/POS device 3 receive priority low */
 351         __be32  updrp4;         /* UTOPIA/POS device 4 receive priority low */
 352         __be32  upde1;          /* UTOPIA/POS device 1 event */
 353         __be32  upde2;          /* UTOPIA/POS device 2 event */
 354         __be32  upde3;          /* UTOPIA/POS device 3 event */
 355         __be32  upde4;          /* UTOPIA/POS device 4 event */
 356         __be16  uprp1;
 357         __be16  uprp2;
 358         __be16  uprp3;
 359         __be16  uprp4;
 360         u8      res1[0x8];
 361         __be16  uptirr1_0;      /* Device 1 transmit internal rate 0 */
 362         __be16  uptirr1_1;      /* Device 1 transmit internal rate 1 */
 363         __be16  uptirr1_2;      /* Device 1 transmit internal rate 2 */
 364         __be16  uptirr1_3;      /* Device 1 transmit internal rate 3 */
 365         __be16  uptirr2_0;      /* Device 2 transmit internal rate 0 */
 366         __be16  uptirr2_1;      /* Device 2 transmit internal rate 1 */
 367         __be16  uptirr2_2;      /* Device 2 transmit internal rate 2 */
 368         __be16  uptirr2_3;      /* Device 2 transmit internal rate 3 */
 369         __be16  uptirr3_0;      /* Device 3 transmit internal rate 0 */
 370         __be16  uptirr3_1;      /* Device 3 transmit internal rate 1 */
 371         __be16  uptirr3_2;      /* Device 3 transmit internal rate 2 */
 372         __be16  uptirr3_3;      /* Device 3 transmit internal rate 3 */
 373         __be16  uptirr4_0;      /* Device 4 transmit internal rate 0 */
 374         __be16  uptirr4_1;      /* Device 4 transmit internal rate 1 */
 375         __be16  uptirr4_2;      /* Device 4 transmit internal rate 2 */
 376         __be16  uptirr4_3;      /* Device 4 transmit internal rate 3 */
 377         __be32  uper1;          /* Device 1 port enable register */
 378         __be32  uper2;          /* Device 2 port enable register */
 379         __be32  uper3;          /* Device 3 port enable register */
 380         __be32  uper4;          /* Device 4 port enable register */
 381         u8      res2[0x150];
 382 } __attribute__ ((packed));
 383
 384 /* SDMA */
 385 struct sdma {
 386         __be32  sdsr;           /* Serial DMA status register */
 387         __be32  sdmr;           /* Serial DMA mode register */
 388         __be32  sdtr1;          /* SDMA system bus threshold register */
 389         __be32  sdtr2;          /* SDMA secondary bus threshold register */
 390         __be32  sdhy1;          /* SDMA system bus hysteresis register */
 391         __be32  sdhy2;          /* SDMA secondary bus hysteresis register */
 392         __be32  sdta1;          /* SDMA system bus address register */
 393         __be32  sdta2;          /* SDMA secondary bus address register */
 394         __be32  sdtm1;          /* SDMA system bus MSNUM register */
 395         __be32  sdtm2;          /* SDMA secondary bus MSNUM register */
 396         u8      res0[0x10];
 397         __be32  sdaqr;          /* SDMA address bus qualify register */
 398         __be32  sdaqmr;         /* SDMA address bus qualify mask register */
 399         u8      res1[0x4];
 400         __be32  sdebcr;         /* SDMA CAM entries base register */
 401         u8      res2[0x38];
 402 } __attribute__ ((packed));
 403
 404 /* Debug Space */
 405 struct dbg {
 406         __be32  bpdcr;          /* Breakpoint debug command register */
 407         __be32  bpdsr;          /* Breakpoint debug status register */
 408         __be32  bpdmr;          /* Breakpoint debug mask register */
 409         __be32  bprmrr0;        /* Breakpoint request mode risc register 0 */
 410         __be32  bprmrr1;        /* Breakpoint request mode risc register 1 */
 411         u8      res0[0x8];
 412         __be32  bprmtr0;        /* Breakpoint request mode trb register 0 */
 413         __be32  bprmtr1;        /* Breakpoint request mode trb register 1 */
 414         u8      res1[0x8];
 415         __be32  bprmir;         /* Breakpoint request mode immediate register */
 416         __be32  bprmsr;         /* Breakpoint request mode serial register */
 417         __be32  bpemr;          /* Breakpoint exit mode register */
 418         u8      res2[0x48];
 419 } __attribute__ ((packed));
 420
 421 /* RISC Special Registers (Trap and Breakpoint) */
 422 struct rsp {
 423         u8      fixme[0x100];
 424 } __attribute__ ((packed));
 425
 426 struct qe_immap {
 427         struct qe_iram          iram;           /* I-RAM */
 428         struct qe_ic_regs       ic;             /* Interrupt Controller */
 429         struct cp_qe            cp;             /* Communications Processor */
 430         struct qe_mux           qmx;            /* QE Multiplexer */
 431         struct qe_timers        qet;            /* QE Timers */
 432         struct spi              spi[0x2];       /* spi */
 433         struct mcc              mcc;            /* mcc */
 434         struct qe_brg           brg;            /* brg */
 435         struct usb_ctlr         usb;            /* USB */
 436         struct si1              si1;            /* SI */
 437         u8                      res11[0x800];
 438         struct sir              sir;            /* SI Routing Tables */
 439         struct ucc              ucc1;           /* ucc1 */
 440         struct ucc              ucc3;           /* ucc3 */
 441         struct ucc              ucc5;           /* ucc5 */
 442         struct ucc              ucc7;           /* ucc7 */
 443         u8                      res12[0x600];
 444         struct upc              upc1;           /* MultiPHY UTOPIA POS Ctrlr 1*/
 445         struct ucc              ucc2;           /* ucc2 */
 446         struct ucc              ucc4;           /* ucc4 */
 447         struct ucc              ucc6;           /* ucc6 */
 448         struct ucc              ucc8;           /* ucc8 */
 449         u8                      res13[0x600];
 450         struct upc              upc2;           /* MultiPHY UTOPIA POS Ctrlr 2*/
 451         struct sdma             sdma;           /* SDMA */
 452         struct dbg              dbg;            /* Debug Space */
 453         struct rsp              rsp[0x2];       /* RISC Special Registers
 454                                                    (Trap and Breakpoint) */
 455         u8                      res14[0x300];
 456         u8                      res15[0x3A00];
 457         u8                      res16[0x8000];  /* 0x108000 - 0x110000 */
 458         u8                      muram[0xC000];  /* 0x110000 - 0x11C000
 459                                                    Multi-user RAM */
 460         u8                      res17[0x24000]; /* 0x11C000 - 0x140000 */
 461         u8                      res18[0xC0000]; /* 0x140000 - 0x200000 */
 462 } __attribute__ ((packed));
 463
 464 extern struct qe_immap *qe_immr;
 465 extern phys_addr_t get_qe_base(void);
 466
 467 static inline unsigned long immrbar_virt_to_phys(volatile void * address)
 468 {
 469         if ( ((u32)address >= (u32)qe_immr) &&
 470                         ((u32)address < ((u32)qe_immr + QE_IMMAP_SIZE)) )
 471                 return (unsigned long)(address - (u32)qe_immr +
 472                                 (u32)get_qe_base());
 473         return (unsigned long)virt_to_phys(address);
 474 }
 475
 476 #endif /* __KERNEL__ */
 477 #endif /* _ASM_POWERPC_IMMAP_QE_H */